TEXAS INSTRUMENTS TSB43AA82A, TSB43AA82AI Technical data

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Data Manua

April 2004 MSDS 1394

SLLS512E

IMPORTANT NOTICE

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Contents

Section Title Page

1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Description 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Functions 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 DMA/Bulky Data Interface 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.2 Microcontroller/Microprocessor Signals 1−5. . . . . . . . . . . . . . . .

1.4.3 Physical Layer 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.4 Test Interface 1−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.5 Power Supplies 1−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.6 Miscellaneous 1−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Assignments for TSB43AA82A 1−8. . . . . . . . . . . . . . . . . . . . . . . .

1.5.1 144-Terminal PGE Package 1−8. . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.2 176-Terminal GGW Package 1−9. . . . . . . . . . . . . . . . . . . . . . . . .

2 Architecture 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Host I/F 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 DMA I/F (Bulky Data I/F) 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Configuration Register (CFR) 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Fast ORB Exchanger (FOX) 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Auto Response (AR) 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Transaction/Timer Manager (TrMgr) 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Packet Distributor 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Packetizer 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Configuration ROM 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Link Core 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 PHY (and PHY Interface) 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 FIFOs 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 Example System Block Diagrams 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.1 Asynchronous Mode With Separate Microcontroller

and DMA Bus 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.2 SCSI Mode With Shared Microcontroller and DMA Bus 2−5. .

3 Configuration Register (CFR) 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Addressing 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Data Bit/Byte Order 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Write/Read Access 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 CFR Definitions 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.1 Version/Revision Register at 00h 3−6. . . . . . . . . . . . . . . . . . . . .

iii

3.4.2 Miscellaneous Register at 04h 3−7. . . . . . . . . . . . . . . . . . . . . . . .

3.4.3 Control Register at 08h 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.4 Interrupt/Interrupt Mask Registers at 0Ch/10h 3−9. . . . . . . . . .

3.4.5 Cycle Timer Register at 14h 3−10. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.6 Diagnostics Register at 18h 3−10. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.7 Reserved at 1Ch 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.8 PHY Access Register at 20h 3−11. . . . . . . . . . . . . . . . . . . . . . . . .

3.4.9 Bus Reset Register at 24h 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.10 Time Limit Register at 28h 3−12. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.11 ATF Status Register at 2Ch 3−12. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.12 ARF Status Register at 30h 3−13. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.13 MTQ Status Register at 34h 3−13. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.14 MRF Status Register at 38h 3−14. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.15 CTQ Status Register at 3Ch 3−14. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.16 CRF Status Register at 40h 3−15. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.17 ORB Fetch Control Register at 44h 3−16. . . . . . . . . . . . . . . . . . .

3.4.18 Management Agent Register at 48h 3−17. . . . . . . . . . . . . . . . . . .

3.4.19 Command Agent Register at 4Ch 3−17. . . . . . . . . . . . . . . . . . . . .

3.4.20 Agent Control Register at 50h 3−17. . . . . . . . . . . . . . . . . . . . . . . .

3.4.21 ORB Pointer Register 1 at 54h 3−18. . . . . . . . . . . . . . . . . . . . . . .

3.4.22 ORB Pointer Register 2 at 58h 3−18. . . . . . . . . . . . . . . . . . . . . . .

3.4.23 Agent Status Register at 5Ch 3−19. . . . . . . . . . . . . . . . . . . . . . . . .

3.4.24 Transaction Timer Control Register at 60h 3−20. . . . . . . . . . . . .

3.4.25 Transaction Timer Status Registers at 64h, 68h, 6Ch 3−21. . . .

3.4.26 Write-First, Write-Continue, and Write-Update Registers

at 70h, 74h, 78h 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.27 Reserved at 7Ch 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.28 ARF, MRF, and CRF Data Read Registers

at 80h, 84h, 88h 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.29 Configuration ROM Control Register at 8Ch 3−23. . . . . . . . . . . .

3.4.30 DMA Control Register at 90h 3−23. . . . . . . . . . . . . . . . . . . . . . . . .

3.4.31 Bulky Interface Control Register at 94h 3−25. . . . . . . . . . . . . . . .

3.4.32 DTF/DRF and DTF/DRF Page Table Size Register

at 98h 3−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.33 DTF/DRF Available Register at 9Ch 3−26. . . . . . . . . . . . . . . . . . .

3.4.34 DTF/DRF Acknowledge Register at A0h 3−26. . . . . . . . . . . . . . .

3.4.35 DTF First and Continue Register at A4h 3−27. . . . . . . . . . . . . . .

3.4.36 DTF Update Register at A8h 3−27. . . . . . . . . . . . . . . . . . . . . . . . .

3.4.37 DRF Data Read Register at ACh 3−27. . . . . . . . . . . . . . . . . . . . . .

3.4.38 DTF Control Registers at B0h, B4h, B8h, and BCh 3−27. . . . . .

3.4.39 DRF Control Registers at C0h, C4h, C8h, and CCh

(DRPktz at 90h = 0)—Direct 3−29. . . . . . . . . . . . . . . . . . . . . . . . .

3.4.40 DRF Control Registers at C0h, C4h, C8h, and CCh

(DRPktz at 90h = 1)—Packetizer 3−30. . . . . . . . . . . . . . . . . . . . .

3.4.41 DRF Header Registers at D0h, D4h, D8h, and DCh 3−31. . . . .

3.4.42 DRF Trailer Register at E0h 3−32. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.43 DTF/DRF Page Count Register at E4h 3−32. . . . . . . . . . . . . . . .

3.4.44 DTx Write Request Header Registers at E8h, ECh, F0h,

and F4h (DhdSel at 90h = 00b) 3−33. . . . . . . . . . . . . . . . . . . . . .

3.4.45 DTF Packetizer Status Registers at E8h, ECh, F0h, and

F4h (DhdSel at 90h = 01b) 3−34. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.46 DRx Read Request Header Registers at E8h, ECh, F0h,

and F4h (DhdSel at 90h = 10b) 3−35. . . . . . . . . . . . . . . . . . . . . .

3.4.47 DRx Packetizer Status Registers at E8h, ECh, F0h, and

F4h (DhdSel at 90h = 11b) 3−36. . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.48 Log/ROM Control Register at F8h 3−38. . . . . . . . . . . . . . . . . . . . .

3.4.49 Log ROM Data Register at FCh 3−39. . . . . . . . . . . . . . . . . . . . . . .

4 Asynchronous Command FIFOs 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Sizes of Asynchronous Command FIFOs (total 378 quadlets) 4−1. . . . .

4.1.1 MTQ/MRF 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 CTQ/CRF 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.3 ATF/ARF 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Asynchronous Command Transmit and Receive Data Formats 4−2. . . .

4.2.1 tLabel/tCode Management for Packet Transmission 4−2. . . . .

4.2.2 Reserved tLabel 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.3 Exception to the Rule 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Asynchronous Transmit FIFO (ATF) 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 Generic Quadlet and Block Transmit 4−3. . . . . . . . . . . . . . . . . .

4.3.2 PHY Packet Common Format 4−4. . . . . . . . . . . . . . . . . . . . . . . .

4.4 Asynchronous Receive FIFO (ARF) 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1 Generic Quadlet and Block Receive 4−7. . . . . . . . . . . . . . . . . . .

4.5 Management and Command FIFOs (MTQ/CTQ and MRF/CRF) 4−9. . .

4.5.1 MTQ/CTQ Format 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.2 MRF/CRF Short Format 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.3 MRF/CRF Long Format 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 ConfigROM and LOG FIFOs (Total 126 Quadlets) 5−1. . . . . . . . . . . . . . . . . . . .

5.1 Setting the ConfigROM and LOG FIFO Size 5−1. . . . . . . . . . . . . . . . . . . .

5.2 Configuration ROM Setup 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Transaction LOG 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Transaction Timer/Manager (TrMgr) 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Confirm Transaction End 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Confirm End State 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Confirm Status of Ongoing Transaction 6−1. . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Abort Transaction 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Fast ORB Exchanger (FOX) 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Command ORB Auto-Fetch Agent 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.1 Internal Agent Operation for Initiator 7−1. . . . . . . . . . . . . . . . . . .

7.1.2 Internal Agent Transaction for Write Request

From Initiator 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.3 Internal Agent Transaction for Read Request

From Initiator 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.4 Controlling Command ORB Fetch Request 7−3. . . . . . . . . . . . .

7.1.5 Agent Behavior to DOORBELL Register Write 7−3. . . . . . . . . .

7.2 Management Transactions 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 Typical ORB Management ORB Fetch

Command Operation 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.2 Login 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.3 Logout 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 SBP-2 Linked Command ORBs 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1 Typical Command ORB Fetch Command Operation 7−7. . . . .

7.3.2 SBP-2/Linked Command ORB Procedure 7−7. . . . . . . . . . . . . .

8 BD FIFOs (Total 1182 Quadlets) 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Setting the BD FIFO Size 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1.1 DTF 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1.2 DRF 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 DTF/DRF Packet Format 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.1 DRF Packet Format 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.2 DTF Packet Format 8−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Status Block Setup 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 DMA Operation 8−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.1 Packet Transmission by DTF 8−4. . . . . . . . . . . . . . . . . . . . . . . . .

8.4.2 Packet Receipt With DRF 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.3 Reading DRF Through the CFR 8−7. . . . . . . . . . . . . . . . . . . . . .

8.4.4 Reading DRF Through the Bulky Interface 8−8. . . . . . . . . . . . .

9 DMA Interface 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 Mode Setting 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1.1 Setting Active Signal 9−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 Synchronous Mode (Modes A, D, and G) 9−2. . . . . . . . . . . . . . . . . . . . . . .

9.2.1 Request Transmission (Memory → TSB43AA82A)

(Modes A, D, and G) 9−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2.2 Receiving Transmission (TSB43AA82A → Memory)

(Modes A, D, and G) 9−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2.3 Timing Values (Modes A, D, and G) 9−4. . . . . . . . . . . . . . . . . . .

9.3 Asynchronous SCSI Mode (Modes E and H) 9−5. . . . . . . . . . . . . . . . . . . .

9.3.1 Request Transmission (Memory → TSB43AA82A)

(Modes E and H) 9−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.2 Receiving Transmission (TSB43AA82A → Memory)

(Modes E and H) 9−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.3 Timing Values (Modes E and H) 9−6. . . . . . . . . . . . . . . . . . . . . .

9.4 Asynchronous Handshake Mode (Modes B, C, and F) 9−11. . . . . . . . . . . .

9.4.1 Request Transmission (Memory → TSB43AA82A)

(Modes B, C, and F) 9−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.2 Receiving Transmission (TSB43AA82A → Memory)

(Modes B, C, and F) 9−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.3 Timing Values (Modes B, C, and F) 9−11. . . . . . . . . . . . . . . . . . .

9.5 ATAPI Mode (Mode G and Burst = 1) 9−14. . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6 Endianness 9−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.7 Clearing the DMA Interface Data 9−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.8 Resetting the DMA Interface 9−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.9 Suspending the BDIO Output 9−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Host Interface 10−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 Parallel Mode Specification 10−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 Multiplex Mode Specification 10−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 PHY 11−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 Description 11−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 PHY Internal Registers 11−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3 Power-Class Programming 11−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Application Information 12−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 PHY Port Cable Connection 12−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 Crystal Selection 12−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3 Bus Reset 12−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.4 Low-Power Mode 12−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5 Power Down and Initialization 12−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.6 Power-Supply Sequence 12−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 Packet Processing With CSR Addressing 13−1. . . . . . . . . . . . . . . . . . . . . . . . . .

13.1 Ack and Response Packet for Request Packet—CFR ErrResp and

StErPkt at 08h 13−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.1 RAM ROM 13−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.2 ARF ROM 13−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.3 Outside of Configuration ROM 13−2. . . . . . . . . . . . . . . . . . . . . . . .

13.1.4 Other 13−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 Electrical Characteristics 14−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.1 Absolute Maximum Ratings Over Free-Air Temperature Range 14−1. . . .

14.2 Recommended Operating Conditions 14−1. . . . . . . . . . . . . . . . . . . . . . . . . .

14.3 Electrical Characteristics Over Recommended Ranges of

Operating Conditions 14−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.3.1 Device 14−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.3.2 Driver 14−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.3.3 Receiver 14−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.4 Switching Characteristics 14−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15 Mechanical Data 15−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

List of Illustrations

Figure Title Page

2−1 Functional Block Architecture 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Automatically Creating an SBP-2 Compliant Request for a

Block Packet 3−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Generic Transmit Format of Packet With Quadlet Data 4−3. . . . . . . . . . . . . . . . .

4−2 Generic Transmit Format of Packet With Block Data 4−3. . . . . . . . . . . . . . . . . . .

4−3 PHY Packet Format 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 Link-On Packet 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 PING Packet 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Remote Access Packet 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Remote Command Packet 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 Resume Packet 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−9 Generic Receive Format of Packet With Quadlet Data 4−7. . . . . . . . . . . . . . . . .

4−10 Generic Receive Format of Packet With Block Data 4−8. . . . . . . . . . . . . . . . . .

4−11 MTQ/CTQ Transmission Block Read Packet Format 4−9. . . . . . . . . . . . . . . . . .

4−12 MRF/CRF Receive Short Format (ORB) 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−13 MRF/CRF Receive Long Format (ORB) 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 Example ConfigROM Base Structure (Reference SBP-2 Draft) 5−1. . . . . . . . . .

5−2 ConfigROM Setup 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1 Command Agent Registers 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−2 Typical Login Process 7−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−3 Typical Management ORB Transaction 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−4 Logout Process 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−5 Typical Link Fetch 7−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−6 SUSPENDED and DOORBELL Request by Dummy ORB 7−9. . . . . . . . . . . . . .

7−7 UNSOLICITED_STATUS_ENABLE 7−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−1 DRF Block-Receive Packet Format 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−2 DTF Packet Format With Block Data 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−3 Status Block Format 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1 Synchronous Mode 9−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−2 SCSI Handshake Mode 9−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−3 SCSI Burst Mode Write (1) 9−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−4 SCSI Burst Mode Write (2) 9−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−5 SCSI Burst Mode Write (3) 9−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

9−6 SCSI Burst Mode Write (4) 9−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−7 Asynchronous Mode 9−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−8 Asynchronous Handshake Mode Write 9−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−9 Asynchronous Handshake Mode Read 9−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−10 Asynchronous Burst Mode Write 9−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−11 Asynchronous Burst Mode Read 9−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−12 ATAPI Initiate (Read) 9−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−13 ATAPI Read 9−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−14 ATAPI Terminate (Read) 9−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−15 ATAPI Initiate (Write) 9−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−16 ATAPI Write 9−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−17 ATAPI Terminate (Write) 9−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−1 Parallel Mode Read/Write Cycle 10−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−2 Multiplex (MUX) Mode Read/Write Cycle 10−3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−1 TP Cable Connections 12−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−2 Nonisolated Outer Shield Termination for 6-Pin Connector 12−2. . . . . . . . . . . .

12−3 Nonisolated Outer Shield Termination for 4-Pin Connector 12−2. . . . . . . . . . . .

12−4 Load Capacitance for the TSB43AA82A PHY Portion 12−3. . . . . . . . . . . . . . . . .

12−5 Recommended Crystal and Capacitor Layout 12−3. . . . . . . . . . . . . . . . . . . . . . . .

12−6 Initialization Sequence 12−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−7 Power-Up Sequence 12−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−8 Power-Down Sequence 12−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2−1 Address/Data 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 CFR Map 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 DTFCtl: DTF Packetizer Transmit Control 3−28. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 DRFCtl: DRF Packetizer Transmit Control 3−30. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Block-Transmit Format Descriptions 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 PHY Packet Format Descriptions 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 Link-On Packet Descriptions 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 PING Packet Descriptions 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 Remote Access Packet Descriptions 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Remote Command Packet Descriptions 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Resume Packet Descriptions 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 Generic Receive Format Descriptions 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−9 Block-Transmit Format Descriptions 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−10 MRF/CRF Format Descriptions 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 FIFO/Timer and Status Bit Combinations 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1 Agent Transaction for Initiator Write Request 7−2. . . . . . . . . . . . . . . . . . . . . . . . .

7−2 Command Agent Response—Successful Write 7−2. . . . . . . . . . . . . . . . . . . . . . .

7−3 Command Agent Error Response 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−4 Agent Transaction for Read Request From Initiator 7−3. . . . . . . . . . . . . . . . . . . .

7−5 Doorbell Special Functions 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−1 DRF Block-Receive Format Descriptions 8−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−2 Block-Transmit Format Descriptions 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−3 Status-Block Format Descriptions 8−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1 Modes of the Bulky Data Interface 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−2 Synchronous Mode 9−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−3 SCSI Handshake Mode 9−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−4 SCSI Burst Mode Write (1) 9−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−5 SCSI Burst Mode Write (2) 9−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−6 SCSI Burst Mode Write (3) 9−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−7 SCSI Burst Mode Write (4) 9−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−8 Asynchronous Mode 9−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−9 Asynchronous Handshake Mode Write and Read 9−12. . . . . . . . . . . . . . . . . . . . .

9−10 Asynchronous Burst Mode Write and Read 9−13. . . . . . . . . . . . . . . . . . . . . . . . . .

9−11 ATAPI Mode 9−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−1 Parallel Mode Read/Write Cycle 10−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−2 Multiplex Mode Read/Write Cycle 10−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−1 Base Register Configuration 11−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−2 Base Register Field Descriptions 11−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−3 Page-0 (Port Status) Register Configuration 11−5. . . . . . . . . . . . . . . . . . . . . . . . .

11−4 Page-0 (Port Status) Register Field Descriptions 11−5. . . . . . . . . . . . . . . . . . . . .

11−5 Page-1 (Vendor ID) Register Configuration 11−6. . . . . . . . . . . . . . . . . . . . . . . . . .

11−6 Page 1 (Vendor ID) Register Field Descriptions 11−6. . . . . . . . . . . . . . . . . . . . . .

11−7 Page-7 (Vendor-Dependent) Register Configuration 11−6. . . . . . . . . . . . . . . . . .

11−8 Page-7 (Vendor-Dependent) Register Field Descriptions 11−7. . . . . . . . . . . . . .

11−9 Power-Class Descriptions 11−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−1 Reset Timing 12−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Introduction

1.1 Features

• IEEE 1394a-2000 Compliant

• Single 3.3-V Supply

• Internal 1.8-V Circuit to Reduce Power Consumption

• Integrated 400-Mbps Two-Port Physical Layer (PHY)

• Internal Voltage Regulator

• IEEE 1394 Related Functions:

− Automated Read Response for ConfigROM Register Access

− Automated Single Retry Protocol and Split Transaction Control

• SBP-2 Related Functions:

− Supports Four Initiators by Automated Transactions and More Can Be Supported Through Firmware.

− Automated Management ORB Fetching

− Automated Linked Command ORB Fetching

− Automated PageTable Fetching

− Automated Status Block Transmit

• Ability to Support Direct Print Protocol (DPP) Mode

• Data Transfers:

− Auto Address Increment of Direct/Indirect Addressing on Data Transfer (Packetizer)

− Automated Header Insert/Strip for DMA Data Transfers

− 8-/16-Bit Asynchronous and Synchronous DMA I/F With Handshake and Burst Mode

− Supports ATAPI (Ultra-DMA) Mode and SCSI Mode

− 8-/16-Bit Data/Address Multiplex Microcontroller and 8-/16-Bit Separated Data/Address Bus

− Three FIFO Configurations That Support High Performance for the DMA and for Command Exchanges Asynchronous Command FIFO: 1512 Bytes

Config ROM/LOG FIFO: 504 Bytes DMA FIFO: 4728 Bytes

1−1

1.2 Description

The TSB43AA82A is a high performance 1394 integrated PHY and link layer controller. It is compliant with the IEEE 1394-1995 and IEEE 1394a-2000 specifications and supports asynchronous transfers.

TSB43AA82A has a generic 16-/8-bit host bus interface. It supports parallel or multiplexed connections to the microcontroller (MCU) at rates up to 40 MHz.

The TSB43AA82A offers large data transfers with three mutually independent FIFOs: 1) the asynchronous command FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504 bytes.

The features of the TSB43AA82A support the serial bus protocol 2 (SBP-2). It handles up to four initiators with the SBP-2 transaction/timer manager. This SBP-2 transaction engine supports fully automated operation request block (ORB) fetches and fully automated memory page table fetches for both read and write transactions. Automated responses to other node requests are provided; this includes responding to another node’s read request to the Config ROM and issuing ack_busy_X for a single retry. Various control registers enable the user to program IEEE 1394 asynchronous transaction settings. The user can program the number of retries and the split transaction time-out value by setting the time limit register in the CFR.

The TSB43AA82A also supports the direct print protocol (DPP). The asynchronous receive FIFO (ARF) in the TSB43AA82A is large enough to satisfy the connection register area, the DRF receiving FIFO can be used as the segment data unit (SDU) register to fulfill the large data transfer.

This document is not intended to serve as a tutorial on IEEE 1394; users are referred to IEEE Std 1394-1995 and IEEE 1394a-2000 (see Note 1).

IEEE Std 1394-1995, IEEE Standard for a High Performance Serial Bus

IEEE Std 1394a−2000, IEEE Standard for a High Performance Serial Bus − Amendment 1

1−2

1.3 Terminal Assignments

AGN5

AVD5 FILTER0 FILTER1

VDPLL VSPLL

VSS

PWTST

TEST0 TEST1 TEST2 TEST3

VSS TEST4 TEST5

PWTST

TEST6

VDD3V

TEST7

LPS

VSS

PWRCLS0 PWRCLS1

PWRCLS2

CNA

PLLON

LINKON

CONTEND

VSS

PWTST

CPS

PHYTESTM

VDD3V

144-TERMINAL PGE PACKAGE

(TOP VIEW)

TPA2P

TPBIAS2

AVD4

TPA2N

105

106

107

108 109 110

111 112 113 114 115

116 117

118 119 120

121 122

123 124

125 126

127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

1234567891011121314151617181920212223242526272829303132333435

AGN4

103

104

TPB2N

TPB2P

102

AVD3

101

100

TPBIAS1

AGN3

TPA1P

TPA1N

AVD2

AGN2

TPB1N

TPB1P

AVD1

AGN1

VSS

XRESETP

PWTST

XCS

XRESETL

VSS

ALE

XWR

PWTST

XRD

VDD3V

XWAIT

DA15

VSS

DA14

DA13

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

DA12 DA11

VDD3V DA10 DA9 VSS VDD3V DA8 DA7 PWTST DA6 DA5 DA4 VSS DA3 DA2 DA1 DA0 XINT BDIO15 VDD3V VSS BDIO14 BDIO13 BDIO12 PWTST BDIO11 BDIO10 BDIO9 VSS BDIO8 BDACK BDIO7

BDIO6 VDD3V BDIO5

VSS

MODE0

MODE1

M8M16

MODE2

BDICLK

BDITRIS

MUXMODE

BDOCLKDIS

VSS

VDD3V

BDIF0

ATACK

BDOCLK

BDIF2

BDIF1

PWTST

VSS

BDOF0

BDOF1

BDOF2

VDD3V

BDIEN/BDWR(SCSI)

BDOEN/BDRD(SCSI)

BDOAVAIL/BDRW(SCSI)

BDIBUSY/BDREQ(SCSI)

VSS

BDIO1

BDIO0

BDIO2

PWTST

BDIO3

VDD3V

VSS

BDIO4

1−3

1.4 Terminal Functions

I/O

DESCRIPTION

1.4.1 DMA/Bulky Data Interface

TERMINAL

NAME PGE NO. GGW NO.

ATACK 13 G1 O ATAPI acknowledge BDACK 41 T4 I DMA acknowledge BDIBUSY/

BDREQ(SCSI) BDICLK 8 E1 I DMA input clock. BDICLK must be provided when bulky data

BDIEN/ BDWR(SCSI)

BDIF[2:0] 17, 16, 14 J1, H2, H1 I/O DMA input flag. Indicates order of the input data on stream. BDIO[15:0] 53, 50, 49, 48, 46,

37, 36, 34, 30, 29, 28

BDITRIS 7 E2 I BDIO 3-state set. When BDITRIS is set high, BDIBUSY, BDOAVAIL,

BDOAVAIL/ BDRW(SCSI)

BDOCLK 12 G2 O DMA clock output based on the 49.152-MHz PHY clock BDOCLKDIS 9 F3 I BDOCLK clock output disable. Tie high to disable BDOCLK BDOEN/

BDRD(SCSI) BDOF[2:0] 21, 20, 18 K3, K2, J3 O DMA output flag. Indicates order of the output data on stream.

NOTES: 1. Any frequency up to 40 MHz can be used. The maximum frequency is not required to match the transfer speed frequency.

2. When in synchronous mode, BDICLK is required. The BDICLK input is ignored when in asynchronous mode.

3. BDORst/BDIRst (94h) activates BDIBUSY, BDOAVAIL, and ATACK.

22 L1 O DMA input busy

interface is in synchronous mode. See Notes 1 and 2.

23 L2 I DMA input enable

45, 44, 42, 40, 39,

25 M1 O BDOAVAIL is the DMA output available. In SCSI mode, BDRW is

26 M2 I DMA output enable

MODE

Asynchronous BDOCLK

Synchronous BDICLK

T8, U7, T7, R7, R6, U5, T5, U4, R4, U3, U2, T1, R1, N3, N2,

CLOCK

I/O DMA data

and ATACK are initially 3-state. See Note 3.

DMARW(90h bit0). It indicates the current state (read or write) of the bulky interface.

1−4

1.4.2 Microcontroller/Microprocessor Signals

I/O

DESCRIPTION

I/O

DESCRIPTION

TERMINAL

NAME PGE NO. GGW NO.

ALE 82 M15 I Address latch enable. Ignored when not DA mux mode

DA[15:0] 76, 74, 73, 72, 71,

69, 68, 65, 64, 62,

61, 60, 58, 57, 56, 55

M8M16 5 D1 I Bit width select. M8M16 determines the width of the data bus. The

MUXMODE 6 E3 I Mode selects. MUXMODE determines if the data and address lines are

XCS 84 M17 I Chip select XINT 54 U9 O Interrupt XRD 78 P17 I Read cycle enable XWAIT 77 P16 O Wait XWR 81 N17 I Write cycle enable

P15, R16, T17, U16, T15, R14, U14, R12,

T12, R11, T11, U11,

T10, U10, T9, R9

(MUXMODE = 1).

I/O I/O lines used for address and data. See Table 2−1 for more

information on the use of address and data lines.

terminal is tied high for 16 bit mode. See Table 2−1 for more information on the use of address and data lines.

parallel or multiplexed. The terminal is tied high for data address multiplex mode. See Table 2−1 for more information on the use of address and data lines.

1.4.3 Physical Layer

TERMINAL

NAME PGE NO. GGW NO.

CNA 135 C6 O Cable not active output. If no bias is detected from the cable, the CNA signal is

CONTEND 139 A4 I Contend. Tie high for bus manager capability. CPS 142 A3 I Cable power supply . This terminal is normally connected to cable power through

FILTER0 FILTER1

LINKON 138 C5 O Link-on. The link-on output is activated if the LLC is inactive (LPS inactive or PD

LPS 130 A7 I Link power status. The signal indicates that the link is powered up and ready for

PD 136 A5 I Power-down input. When PD is asserted, the device is in a power down mode.

PWRCLS[2:0] 134, 133, 132 B6, A6, C7 I Power class inputs. See 1394a-2000 for more information. On hardware reset,

R0 R1

111 112

100

A15 A14

F17 F16

set high. The CNA output is not valid during power-up reset. CNA is valid during power-down mode, when PD is high.

a 400-kΩ resistor. This circuit drives an internal comparator that is used to detect the presence of cable power.

I PLL filter. These terminals are connected to an external capacitor to form a

lag-lead filter required for stable operation of the internal frequency multiplier PLL running off the crystal oscillator. A 0.1-µF ±10% capacitor is the only external component required to complete this filter.

active). The signal indicates that the PHY has detected a link-on packet addressed to this node, or has detected a resume event on a suspended port. The signal remains asserted until the LPS signal is asserted by the link in response.

transactions. When this mode is deasserted, the device can be put into a low power mode.

The device is asynchronously reset during this mode, so a device reset must be provided after PD is deasserted. See Section 12 for more details.

these inputs set the default value on the power class indicated during self-ID. Programming is done by tying terminals high or low.

Current setting resistor terminals. These terminals are connected to an external resistance to set the internal operating currents and cable driver output currents.

—

A resistance of 6.34 kΩ ±1.0% is required to meet the IEEE Std 1394-1995 output voltage limits.

1−5

1.4.3 Physical Layer (continued)

I/O

DESCRIPTION

TPA1N

9596G17

I/O

Twisted-pair cable-A differential signal terminals. Board traces from each pair of

positive and negative differential signal terminals must match and be kept as

TPA2N

106

C17

I/O

TPB1N

9192J17

I/O

Twisted-pair cable-B differential signal terminals. Board traces from each pair of

positive and negative differential signal terminals must match and be kept as

TPB2N

102

E17

I/O

116

A12

—

nant fundamental mode crystal. The optimum values for the external shunt ca-

I/O

DESCRIPTION

TERMINAL

NAME PGE NO. GGW NO.

TPA1N TPA1P

TPA2N TPA2P

TPB1N TPB1P

TPB2N TPB2P

TPBIAS1 TPBIAS2

106 107

102 103

108

115

G17 G16

C17 C16

J17 J16

E17 E16

G15

B17

A13

1.4.4 Test Interface

TERMINAL

NAME PGE NO. GGW NO.

TEST[7:0] 129, 127, 125,

124, 122, 121,

120, 119

C8, A8, C9,

A9, C10, A10,

A11, B11

I/O Twisted-pair cable-A differential signal terminals. Board traces from each pair of

positive and negative differential signal terminals must match and be kept as short as possible to the external load resistors and to the cable connector.

I/O

I/O Twisted-pair cable-B differential signal terminals. Board traces from each pair of

positive and negative differential signal terminals must match and be kept as short as possible to the external load resistors and to the cable connector.

I/O

O Twisted pair bias output. This provides the 1.86-V nominal bias voltage needed

for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. Each of these terminals, except for an unused port, must be decoupled with a 1.0-µF capacitor to ground. For the unused port, this terminal can be left unconnected.

Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel reso-

pacitors are dependent on the specifications of the crystal used.

I/O Test data lines. The test data lines are used in manufacturing test and is tied low in

normal/operational mode.

1−6

1.4.5 Power Supplies

DESCRIPTION

TERMINAL

NAME PGE NO. GGW NO.

AGN[5:1] 109, 104, 98, 93, 90 A16, D17, G14, H17,

AVD[5:1] 110, 105, 101, 94, 89 B15, D16, F15, H16,

PWTST 15, 31, 47, 63, 80, 87,

118, 126, 141

VDD3V 10, 24, 33, 38, 52, 66,

70, 79, 128, 144

VDPLL 113 C13 PLL power supply. A combination of high-frequency decoupling capacitors

VSPLL 114 B13 PLL ground. These terminals must be tied together to the low-impedance

VSS 3, 11, 19, 27, 35, 43,

51, 59, 67, 75, 83, 88,

117, 123, 131, 140

B9, C4, C11, H3, L17,

P3, R8, T3, U13, U15

B4, B7, B10, D3, D11,

G3, K1, K17, M3, M16,

K16

K15

N16, P1, U6, U12

A2, B8, F2, L3, N15,

R2, R5, R10, R13,

R17, U8

Analog ground. These terminals must be tied together to the low-impedance circuit board ground plane.

Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1-µF and

0.001-µF capacitors. These supply terminals are separated from PWTST, VDD3V, and VDPLL internal to the device to provide noise isolation.

1.8-V Vdd power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1-uF and

0.001-uF capacitors. These supply terminals are separated from VDD3V, AVD, and VDPLL internal to the device to provide noise isolation (this voltage is not supplied when the internal regulator is enabled.)

3.3-V V terminal is suggested, such as paralleled 0.1-uF and 0.001-µF capacitors. These supply terminals are separated from PWTST, AVD, and VDPLL internal to the device to provide noise isolation.

near each terminal is suggested, such as paralleled 0.1-µF and 0.001-µF capacitors. These supply terminals are separated from PWTST, VDD3V, and AVD internal to the device to provide noise isolation.

circuit board ground plane. Digital ground. These terminals must be tied together to the low-impedance

circuit board ground plane.

A combination of high frequency decoupling capacitors near each

dd.

1.4.6 Miscellaneous

TERMINAL

NAME PGE

EN 32 P2 I/O/

MODE[2:0] 4, 2, 1 D2,

PHYTESTM 143 B3 I Test mode. This input terminal is used in manufacturing tests. Tie high during normal/operational

PLLON 137 B5 I PLL enable. This signal forces the internal phase-locked loop (PLL) on when it is asserted, even

XRESETL 85 L15 I Link reset. Reset for link block XRESETP 86 L16 I PHY reset. Reset for PHY block

NO.

GGW

NO.

C1, B1

I/O DESCRIPTION

Internal 1.8-V regulator enable. This terminal enables the internal 1.8-V regulator. Tie low during

Hi-Z

normal/operational mode.

I Chip mode select. MODE[2:0] = 000 is the normal/operational mode. All other modes are for test

purposes and are not described in this data sheet.

mode.

during ultralow−power mode and power-down mode. If this signal is deasserted, the PLL operates only during regular device operation.

1−7

1.5 Terminal Assignments for TSB43AA82A

1.5.1 144-Terminal PGE Package

TERM.

NO.

1 MODE0 I 37 BDIO5 I/O 73 DA13 I/O 109 AGN5 2 MODE1 I 38 VDD3V 74 DA14 I/O 110 AVD5 3 VSS 39 BDIO6 I/O 75 VSS 111 FILTER0 I 4 MODE2 I 40 BDIO7 I/O 76 DA15 I/O 112 FILTER1 I 5 M8M16 I 41 BDACK I 77 XWAIT O 113 VDPLL 6 MUXMODE I 42 BDIO8 I/O 78 XRD I 114 VSPLL 7 BDITRIS I 43 VSS 79 VDD3V 115 XI I 8 BDICLK I 44 BDIO9 I/O 80 PWTST 116 XO

9 BDOCLKDIS I 45 BDIO10 I/O 81 XWR I 117 VSS 10 VDD3V 46 BDIO11 I/O 82 ALE I 118 PWTST 11 VSS 47 PWTST 83 VSS 119 TEST0 I/O 12 BDOCLK O 48 BDIO12 I/O 84 XCS I 120 TEST1 I/O 13 ATACK O 49 BDIO13 I/O 85 XRESETL I 121 TEST2 I/O 14 BDIF0 I 50 BDIO14 I/O 86 XRESETP I 122 TEST3 I/O 15 PWTST 51 VSS 87 PWTST 123 VSS 16 BDIF1 I 52 VDD3V 88 VSS 124 TEST4 I/O 17 BDIF2 I 53 BDIO15 I/O 89 AVD1 125 TEST5 I/O 18 BDOF0 O 54 XINT O 90 AGN1 126 PWTST 19 VSS 55 DA0 I/O 91 TPB1N I/O 127 TEST6 I/O 20 BDOF1 O 56 DA1 I/O 92 TPB1P I/O 128 VDD3V 21 BDOF2 O 57 DA2 I/O 93 AGN2 129 TEST7 I/O 22 BDIBUSY O 58 DA3 I/O 94 AVD2 130 LPS I 23 BDIEN I 59 VSS 95 TPA1N I/O 131 VSS 24 VDD3V 60 DA4 I/O 96 TPA1P I/O 132 PWRCLS0 I 25 BDOAVAIL O 61 DA5 I/O 97 TPBIAS1 O 133 PWRCLS1 I 26 BDOEN I 62 DA6 I/O 98 AGN3 134 PWRCLS2 I 27 VSS 63 PWTST 99 R0 I/O 135 CNA O 28 BDIO0 I/O 64 DA7 I/O 100 R1 I/O 136 PD I 29 BDIO1 I/O 65 DA8 I/O 101 AVD3 137 PLLON I 30 BDIO2 I/O 66 VDD3V 102 TPB2N I/O 138 LINKON O 31 PWTST 67 VSS 103 TPB2P I/O 139 CONTEND I 32 EN I 68 DA9 I/O 104 AGN4 140 VSS 33 VDD3V 69 DA10 I/O 105 AVD4 141 PWTST 34 BDIO3 I/O 70 VDD3V I 106 TPA2N I/O 142 CPS I 35 VSS 71 DA11 I/O 107 TPA2P I/O 143 PHYTESTM I 36 BDIO4 I/O 72 DA12 I/O 108 TPBIAS2 O 144 VDD3V

SIGNAL

NAME

I/O

TERM.

NO.

SIGNAL

NAME

I/O

TERM.

NO.

SIGNAL

NAME

I/O

TERM.

NO.

SIGNAL

NAME

I/O

1−8

1.5.2 176-Terminal GGW Package

TERM.

NO.

A2 VDD3V C17 TPA2N I/O J14 NC R2 VSS A3 CPS I D1 M8M16 I J15 NC R4 BDIO7 I/O A4 CONTEND I D2 MODE2 I J16 TPB1P I/O R5 VSS A5 PD I D3 VSS J17 TPB1N I/O R6 BDIO11 I/O A6 PWRCLS1 I D7 NC K1 VSS R7 BDIO12 I/O A7 LPS I D8 NC K2 BDOF1 O R8 VDD3V A8 TEST6 I/O D9 NC K3 BDOF2 O R9 DA0 I/O

A9 TEST4 I/O D10 NC K4 NC R10 VSS A10 TEST2 I/O D11 VSS K14 NC R11 DA6 I/O A11 TEST1 I/O D15 NC K15 AVD1 R12 DA8 I/O A12 X0 D16 AVD4 K16 AGN1 R13 VSS A13 X1 I D17 AGN4 K17 VSS R14 DA10 I/O A14 FILTER1 I E1 BDICLK I L1 BDIBUSY O R16 DA14 I/O A15 FILTER0 I E2 BDITRIS I L2 BDIEN I R17 VSS A16 AGN5 E3 MUXMODE I L3 VDD3V T1 BDIO4 I/O

B1 MODE0 I E15 NC L4 NC T3 VDD3V

B3 PHYTESTM I E16 TPB2P I/O L14 NC T4 BDACK I

B4 VSS E17 TPB2N I/O L15 XRESETL I T5 BDIO9 I/O

B5 PLLON I F1 NC L16 XRESETP I T6 NC

B6 PWRCLS2 I F2 VDD3V L17 PWTST T7 BDIO13 I/O

B7 VSS F3 BDOCLKDIS I M1 BDOAVAIL O T8 BDIO15 I/O

B8 VDD3V F15 AVD3 M2 BDOEN I T9 DA1 I/O

B9 PWTST F16 R1 I/O M3 VSS T10 DA3 I/O B10 VSS F17 R0 I/O M15 ALE B11 TEST0 I/O G1 ATACK O M16 VSS T12 DA7 I/O B12 NC G2 BDOCLK O M17 XCS I T13 NC B13 VSPLL G3 VSS N1 BDIO0 I/O T14 NC B14 NC G4 NC N2 BDIO1 I/O T15 DA11 I/O B15 AVD5 G14 AGN3 N3 BDIO2 I/O T17 DA13 I/O B17 TPBIAS2 O G15 TPBIAS1 O N15 VDD3V U2 BDIO5 I/O

C1 MODE1 I G16 TPA1P I/O N16 PWTST U3 BDIO6 I/O

C2 NC G17 TPA1N I/O N17 XWR I U4 BDIO8 I/O

C4 PWTST H1 BDIF0 I/O P1 PWTST U5 BDIO10 I/O

C5 LINKON O H2 BDIF1 I/O P2 EN I U6 PWTST

C6 CNA O H3 PWTST P3 VDD3V U7 BDIO14 I/O

C7 PWRCLS0 I H4 NC P7 NC U8 VSS

C8 TEST7 I/O H14 NC P8 NC U9 XINT O

C9 TEST5 I/O H15 NC P9 NC U10 DA2 I/O C10 TEST3 I/O H16 AVD2 P10 NC U11 DA4 I/O C11 PWTST H17 AGN2 P11 NC U12 PWTST C12 NC J1 BDIF2 I/O P15 DA15 I/O U13 VDD3V C13 VDPLL J2 NC P16 XWAIT O U14 DA9 I/O C14 NC J3 BDOF0 O P17 XRD I U15 VDD3V C16 TPA2P I/O J4 NC R1 BDIO3 I/O U16 DA12 I/O

SIGNAL

NAME

I/O

TERM.

NO.

SIGNAL

NAME

I/O

TERM.

NO.

SIGNAL

NAME

I/O

TERM.

NO.

T11 DA5 I/O

SIGNAL

NAME

I/O

1−9

1−10

2 Architecture

The iSphynx II functional block architecture is shown in Figure 2-1.

Configuration Register (CFR)

8/16

Host

I/F

Configuration

ROM

Asynchronous

Command FIFO

ATF

MTQ

CTQ

ARF

MRF

CRF

BDFIFO

Auto

Response

(AR)

Transaction

Timer/Manager

(TrMgr)

Fast ORB Exchanger (FOX)

MOAF_AGENT

COAF_AGENT

LOG

Link

Core

(1394a)

Port

8/16

DMA

(Bulky

Data)

I/F

DTF

DRF

Packetizer

Packet

Distributor

Figure 2−1. Functional Block Architecture

Port

2−1

2.1 Host I/F

The host (microcontroller) interface is the interface between the microcontroller, the CFR, the asynchronous command FIFOs, and the ConfigROM. The host bus interface consists of an 8-bit data bus and an 8-/16-bit address bus. The TSB43AA82A is interrupt driven to reduce polling. This interface has endian programmable access, and allows the microcontroller easy access to the CFR. See Section 10 for more details.

Table 2−1. Address/Data

M8M16 MUXMODE Data Address

0 (8-bit) 0 (parallel) DA[15:8] DA[7:0]

1(MUX) DA[7:0] DA[7:0]

1 (16-bit) 0 (parallel) DA[15:0] BDIO[15:8]

1(MUX) DA[15:0] DA[7:0]

2.2 DMA I/F (Bulky Data I/F)

The DMA bulky interface provides a data transfer interface for high-speed peripherals. It is the interface between an external host DMA and the DMA FIFO (BDFIFO). The interface provides up to 160-Mbps sustained data rates. The bulky data interface supports several modes such as 8-bit or 16-bit parallel width and asynchronous/synchronous modes. See Section 9 for more details.

2.3 Configuration Register (CFR)

The configuration register (CFR) is the internal register for controlling and managing the TSB43AA82A operation. It provides most of the control bits and host controller monitor. The CFR is discussed in detail in Section 3.

2.4 Fast ORB Exchanger (FOX)

The fast ORB exchanger or FOX module supports management ORB and command block ORB transactions. In the SBP-2 protocol, the target has to read ORB packets from initiators. When requested by the initiator , the FOX module automatically reads the management ORB and command block ORB. Linked command-block ORBs are automatically fetched one by one and the hardware supports up to four agents. The management ORB and the command-block ORB each have two FIFO modules for transmit and receive. See Section 7 for more details.

• MOAF_AGENT: Management ORB auto-fetch agent. Controls fetch/state for management ORB.

• COAF_AGENT: Command-block ORB auto-fetch agent. Fetches command block ORBs and manages

command block agent registers.

2.5 Auto Response (AR)

The auto response (AR) module provides the auto packet response service for incoming request packets. The AR services configuration ROM read requests, agent-state read requests, and unexpected packets.

2.6 Transaction/Timer Manager (TrMgr)

The transaction/timer manager module provides transaction control service for transmit priority between control packets and data packets. Any cable packet transmit request is sent in the order the request is received. This module also manages split transactions and controls busy retry. See Section 6 for more details.

2−2

2.7 Packet Distributor

The packet distributor module provides the packet routing service for each FIFO module. In SBP-2 mode, all request and response packets are properly routed to the correct FIFO, and sent to corresponding initiators. In direct print protocol (DPP) mode, the packet distributor filters a request packet by its address and then saves it into the correct receive FIFO.

2.8 Packetizer

The packetizer module provides packetization for a transmit packet. The data stream from the DMA FIFO is split into small packets that meet the SBP-2 requirements. A read or write request header is attached to each packet with a correctly incremented destination address. The transaction/timer manager provides busy retry and split transaction timer control if required. The packetizer also provides auto-page table fetch service. The internal auto-fetch module sends a read request to the present page address, and the DMA automatically sends data to the requested address set by the Page Table Element. At the end of packetizer , if the DMA function has successfully completed, the DMA automatically sends a status block packet.

2.9 Configuration ROM

The ConfigROM provides the configuration ROM required by the IEEE 1212 standard2. The ConfigROM module supports the auto response service for a ConfigROM read request and records the transaction history. The host controller can load ConfigROM data during node initialization. Once initialized, the ConfigROM is accessible by peer node read requests. See Section 5 for more details.

2.10 Link Core

The link core provides link layer service such as correctly formatted IEEE 1394-19953 and IEEE 1394a-2000 asynchronous transmit and receive packets. It also generates and inspects the 32-bit cyclic redundancy check (CRC). This link core does not support isochronous service.

2.11 PHY (and PHY Interface)

The TSB43AA82A has an integrated 400-Mbps two-port physical layer. The PHYsical (PHY) interface provides PHY-level service to the link layer service. See Section 11 for more details.

2.12 FIFOs

The TSB43AA82A has three FIFO types, asynchronous command FIFOs, configuration ROM FIFOs and DMA FIFOs. These FIFO types have maximum sizes of 378 quadlets, 126 quadlets, and 1182 quadlets respectively. Except for the MTQ and MRF, the FIFO sizes are adjustable. The sum of all the FIFOs in a type must not exceed the maximum size. See Section 4 for more information on the asynchronous command FIFOs, Section 5 for more information on ConfigROM/LOG FIFOs, and Section 8 for more information on BDFIFOs.

IEEE Std 1212-1991, IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses

IEEE Std 1394-1995, IEEE Standard for a High Performance Serial Bus

IEEE Std 1394a-2000, IEEE Standard for a High Performance Serial Bus - Amendment 1

2−3

Asynchronous command FIFOs (total 378 quadlets)

MTQ: MRF: CTQ: CRF: ATF: ARF:

Management ORB transmit FIFO Management ORB receive FIFO Command block ORB transmit FIFO Command block ORB receive FIFO Asynchronous packet transmit FIFO Asynchronous packet receive FIFO

3 quadlets (fixed) 15 quadlets (fixed) Adjustable Adjustable Adjustable Adjustable

ConfigROM/LOG FIFOs (total 126 quadlets)

Autoresponse ConfigROM area Page table buffer for DTF Page table buffer for DRF Status block buffer for DTF Status block buffer for DRF Log data area

Adjustable Adjustable Adjustable Adjustable Adjustable Adjustable

DMA FIFOs (BDFIFO) (total 1182 quadlets)

DTF: DRF:

Data transmit FIFO Data receive/fetch FIFO

Adjustable Adjustable

2.13 Example System Block Diagrams

2.13.1 Asynchronous Mode With Separate Microcontroller and DMA Bus

In this system, the CPU has no DMA capabilities. At the host I/F of the TSB43AA82A is a CPU with no DMA capabilities. At the DMA I/F of the TSB43AA82A is a DMA controller to control the data in and out of the TSB43AA82A.

CPU

Memory

DMA Controller

ADDR

Data 8 or 16

ADDR

XWR

XRD

1394

TSB43AA82A

1394

BDIO BDIEN BDOEN

2−4

2.13.2 SCSI Mode With Shared Microcontroller and DMA Bus

In this system, the host I/F and the DMA I/F of the TSB43AA82A share the same data and control buses. The CPU has DMA capabilities and the address decode is used to determine which I/F is addressed by the CPU.

CPU

ADDR

Data

Address

Decode

XCS

ADDR

XWR

XRD

BDACK BDIO BDWR BDRD

TSB43AA82A

1394

2−5

2−6

3 Configuration Register (CFR)

The CFR contains the registers that dictate the basic operation of the TSB43AA82A. A CFR map is shown in Table 3-1. These registers default to 0 and are unaffected by a bus reset unless otherwise specified.

3.1 Addressing

The CFR is addressed in bytes. The address terminal order is described below:

Address[7:0] = (DA7, DA6, DA5, DA4, DA3 , DA2, DA1, DA0)

3.2 Data Bit/Byte Order

MSB LSB

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303

Byte0 Byte1 Byte2 Byte3

Doublet0 Doublet1

Quadlet

3−1

00h

04h

Version/ Revision

Miscellaneous

Table 3−1. CFR Map

LPS

LKON

101112131415161718192021222324252627282930

Version Revision

Ping_Timer

Root

ATAck

AckErr

AckVld

08h Control

0Ch Interrupt

Interrupt

10h

Mask

Cycle

14h

Timer

18h Diagnostics

1Ch Reserved

PHY

20h

Access 24h Bus Reset BusNumber NodeNum BRFErr_Code NodeSum CFRContID 28h Time Limit SplitTimeOut RetryInterval RtryLmt ORBTimer

2Ch ATF Status

IDVal

RxSld

Int

PhInt

Int

PhInt

Seconds_Count Cycle_Count Cycle_Offset

ACKTardy

WrPy

RdPy

ATFFul

ATFAFl

Bsy0

RSIsel

Breset

BudgEn

ATFAEm

TrEn

ACArbOn

Endslf

Phypkt

CmdSlf

Endslf

Phypkt

CmdSlf

RegRW

PhyRgAd PhyRgData PhyRxAd PhyRxData

ATFEmp

AgRdy0

AgntStWr

BDIFcntEN

SntRj

PhRRx

SntRj

PhRRx

AgRdy1

AgRdy2

RstTr

IFAcc

HdrErr

IFAcc

HdrErr

AgRdy3

TCErr

CySec

TCErr

CySec

StErpkt

SplTrEn

ErrResp

Cyst

DRHUpdate

Cyst

DRHUpdate

MAAckconf

RetryEn

Ackpnd

MAAckConf

FaGap

TxRdy

CyDne

FaGap

TxRdy

CyDne

Budget_Counter

ATFClr

CyMas

CyLst

CyPnd

CyLst

CyPnd

DMclr

CyTmrEn

CyArbF

RxUnexp

ATFEnd

Prio_Budget

RUEsel

ARFRxd

MOREnd

ARFRxd

MOREnd

ATF_Size

DTFEnd

COREnd

DTFEnd

COREnd

TxExpr

DRFEnd

TxExpr

DRFEnd

AgntWr

30h ARF Status

MTQ 34h

Status

MRF 38h

Status

CTQ

3Ch

Status

40h CRF Status

3−2

ARFFul

ARFAFl

MTQFul

MTQAFl

MRFFul

MRFAFl

CTQFul

CTQAFl

CRFFul

CRFAFl

ARFEmp

ARFAEm

MTQEmp

MTQAEmp

MRFEmp

MRFAEm

CTQAEm

CTQEmp

CRFEmp

CRFAEm 2

ARFThere

ARFCD

MRFThere

MRFCD

CTQ1Av

CRFThere

CRFCD

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ARFClr

MTQClr

MRFClr

CTQClr

CRFClr

ARF_Size

CTQ_Size

CRF_Size

Table 3−1. CRF Map (Continued)

Retry_Counter

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ORB Fetch

44h

Control

Manage-

48h

ment Agent Command

4Ch

Agent Agent

50h

Control

ORB

54h

Pointer 1 ORB

58h

Pointer 2 Agent

5Ch

Status

Transaction Timer

60h

Control Transac-

tion Timer

64h

Status 1 Transac-

tion Timer

68h

Status 2 Transac-

tion Timer

6Ch

Status 3

70h Write-First Write_First

Write-

74h

Continue Write-

78h

Update

7Ch Reserved

ARF Data

80h

Read MRF Data

84h

Read CRF Data

88h

Read Configura-

tion ROM

8Ch

Control

MAgtVld

MAgtBsy

AgtNmb

State0

DTTxEd

DRTxEd

tCode Spd tLabel

MShtFmt

DrBll0

UnStEn0

ATTxEd

MTTxEd

MORB_Prior

Rst0

Dead0

DrBClr0

USEClr0

CTTxEd

ARTxEd

Destination_ID Destination_offset_hi

CORB_Size

Management_Agent_offset

WrNdId

AgntVld

USTIEn

ORB_destination_offset_lo

State1

DTErr

DRErr

AR_CSR_Size CSR_Size

DrBll1

ATErr

Dead1

UnStEn1

CTErr

MTErr

Destination_offset_lo

RdNdID

Rst1

DrBClr1

USEClr1

ARErr

Write_Continue

Write_Update

ARFRead

MRFRead

CRFRead

CAg0Vld

CAg1Vld

CAg2Vld

CAg3Vld

Agent_base_offset

DrBll2

State2

DTRtry

ATRtry

DRRtry

UnStEn2

MTRtry

DrBSnp

DrBFtEn

CnxFtEn

CShtFmt

CAg0Rdy

CAg1Rdy

CAg2Rdy

Agent_NodeID

ORB_destination_offset_hi

Rst2

Dead2

CTRtry

DrBClr2

USEClr2

ARRtry

SplitTrTimer

State3

TimrNo

DrBll3

CORB_Prior

CAg3Rdy

Rst3

Dead3

UnStEn3

HldTr

TxAbrt

DrBClr3

USEClr3

RlsTr

90h

DMA Control

DRPage-

DTFEn

DRFEn

DMARW

DTPktz

DRPktz

DTSpDis

DRSpDis 6

DhdSel

LongBlk

QuadSend

RconfSnglpkt

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QuadBndry

FetchSiz

AutoPg

CheckPg

DTPageFetchSiz

Dackpnd

Drespcm

DTHdls

Dpause

DRHStr

DRStPS

DTDSel

DRDSel

DTFClr

DRFCLr

3−3

94h

BDIMode

DTF Page

DRF Page

98h

Bulky

Interface

Control

DTF/DRF

and DTF/

DRF Page

Table Size

Table 3−1. CRF Map (Continued)

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BDIDelay

BLECtl

BOAvCtl

BIEnC

BOEnCtl

AutoPad

MTRBufSiz

DTFPTBufSiz DTF_Size DRFPTBufSiz DRF_Size

MTTBufSiz

BlBsyCtl

ATAckCtl

BDAckCtl

Burst

BDOMode

RcvPad

BDORst

BDIRst

BDOTris

9Ch

A0h

A4h

A8h

ACh

B0h

B4h

B8h

BCh

C0h

DTF/DRF

Available

DTF/DRF

Acknowl-

edge

DTF First

and

Continue

DTF

Update

DRF Data

Read

DTF

Control 0

DTF

Control 1

DTF

Control 2

DTF

Control 3

DRF

Control 0

(direct)

DTFEmpty

DTFCTL0

DTFCTL1

DTFClr/DTFst

DRFBldEn

DRFSldEn

DRFAdrEn

DTFNotify

DTFNdldval

DTF_destination_ID

DTFAvail

DRxAck

DRAE

DTF Max

Payload

DTF Spd

BDOAvail

DRFEmpty

DRAV

DTF_First&Continue

DTF_Update

DRFRead

Size

PgTblEn

DTF_BlockCount/DTF_BlockSize

DTF_destination_offset_lo

DTF_BlockSize/DTF_BlockCount

DRFThere

DTxAck

DTAE

DTF_destination_offset_hi

DTAVal

3−4

C0h

C4h

C8h

DRF

Control 0

(packetiz-

er)

DRF

Control 1

(direct)

DRF

Control 1

(packetiz-

er)

DRF

Control 2

DRFCTL0

DRFCTL1

DRFClr/DRFst

DRFNotify

DRFNdIdVal

DRF_destination_ID

DRFSpd

DRF Max

Payload

DRF_BlockCount/DRF_BlockSize

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Size

PgTblEn

DRF_destination_Width

DRF_BlockSize/DRF_BlockCount

DRF_destination_offset_hi

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