Texas Instruments TSB41LV06PZP Datasheet

D

Fully Supports Provisions of IEEE
1394–1995 Standard for High Performance
Serial Bus† and the P1394a Supplement
(Draft 2.0)

D

Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed concatenation, Arbitration
Acceleration, Fly-by Concatenation, Port
Disable/Suspend/Resume

D

Provides Six P1394a Fully Compliant Cable
Ports at 100/200/400 Megabits per Second
(Mbits/s)

D

Cable Ports Monitor Line Conditions for
Active Connection to Remote Node

D

Power-Down Features to Conserve Energy
in Battery Powered Applications include:
Automatic Device Power-Down during
Suspend, Device Power-Down Pin, Link
Interface Disable via LPS, and Inactive
Ports Powered Down

D

Logic Performs System Initialization and
Arbitration Functions

D

Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding

D

Incoming Data Resynchronized to Local
Clock

description

TSB41LV06

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

D

Single 3.3 V Supply Operation

D

Interface to Link Layer Controller Supports
Low Cost TI Bus-Holder Isolation and
Optional Annex J Electrical Isolation

D

Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz

D

Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at

49.152 MHz

D

Interoperable with Link-Layer Controllers
Using 3.3-V and 5-V Supplies

D

Interoperable with Other Physical Layers
(PHY) Using 3.3-V and 5-V Supplies

D

Node Power Class Information Signaling
for System Power Management

D

Cable Power Presence Monitoring

D

Separate Cable Bias (TPBIAS) for Each Port

D

Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Bit and P1394a Features

D

Fully Interoperable with FIreWire and
i.LINK Implementation of IEEE Std 1394

D

Low Cost, High Performance 100 Pin TQFP
(PZP) Thermally Enhanced Package

The TSB41L V06 provides the digital and analog transceiver functions needed to implement a six-port node in
a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41L V06 is designed to interface
with a Link Layer Controller (LLC), such as the TSB12LV22, TSB12LV21, TSB12LV31, TSB12LV41, or
TSB12LV01.

The TSB41LV06 requires only an external 24.576 MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates
the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock
signals used to control transmission of the outbound encoded Strobe and Data information. A 49.152 MHz clock
signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization
of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation
FireWire is a trademark of Apple Computers Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

description (continued)

The TSB41L V06 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal
is tied high, the LLC interface outputs behave normally . When the ISO terminal is tied low, internal differentiating
logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer
galvanic isolation barrier as described in IEEE 1394a section 5.9.4. T o operate with TI Bus Holder isolation the
ISO

on the PHY terminal must be tied HIGH.

Data bits to be transmitted through the cable ports are received from the LLC on two, four or eight parallel paths
(depending on the requested transmission speed) and are latched internally in the TSB41LV06 in
synchronization with the 49.152 MHz system clock. These bits are combined serially , encoded, and transmitted
at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed, respectively) as the
outbound data-strobe information stream. During transmission, the encoded data information is transmitted
differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the
TPA cable pair(s).

During packet reception the TP A and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded
strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover
the receive clock signal and the serial data bits. The serial data bits are split into two, four or eight bit parallel
streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock
and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected)
cable ports.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the
remotely supplied twisted-pair bias voltage.

The TSB41L V06 provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. The PHY
contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver,
indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter
capacitor of 1 µF.

The line drivers in the TSB41L V06 operate in a high-impedance current mode, and are designed to work with
external 110 Ω line-termination resistor networks in order to match the 1 10-Ω cable impedance. One network
is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω
resistors. The midpoint of the pair of resistors that is directly connected to the twisted pair A terminals is
connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly
connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with
recommended values of 5 kΩ and 220 pF. The values of the external line termination resistors are designed
to meet the standard specifications when connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal
operating currents. This current setting resistor has a value of 6.3-kΩ ±0.5%. This may be accomplished by
placing a 6.34-kΩ ±0.5% resistor in parallel with a 1-MΩ resistor.

When the power supply of the TSB41L V06 is 0 V while the twisted-pair cables are connected, the TSB41L V06
transmitter and receiver circuitry will present a high impedance to the cable and will not load the TPBIAS voltage
at the other end of the cable.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB41LV06

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

When the TSB41LV06 is used with one or more of the ports not brought out to a connector, the twisted–pair
terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and
TPB– terminals should be tied together and then pulled to ground, or the TPB+ and TPB– terminals should be
connected to the suggested termination network. The TP A+ and TPA– and TPBIAS terminals of an unused port
may be left unconnected. The TPBias terminal should be connected to a 1-µF capacitor to ground or left floating.

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, the TESTM terminal should be connected to VDD, SE should be tied to ground through a 1-kΩ resistor,
while SM should be connected directly to ground.

Four package terminals are used as inputs to set the default value for four configuration status bits in the self–ID
packet, and are hardwired high or low as a function of the equipment design. The PC0–PC2 terminals are used
to indicate the default power-class status for the node (the need for power from the cable or the ability to supply
power to the cable). See T able 9 for power-class encoding. The C/LKON terminal is used as an input to indicate
that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM).

The PHY supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism
allows pairs of directly–connected ports to be placed into a low power conservation state while maintaining a
port–to–port connection between 1394 bus segments. While in a low–power state, a port is unable to transmit
or receive data transaction packets. However, a port in a low power state is capable of detecting connection
status changes and detecting incoming TPBias. When all six ports of the TSB41L V06 are suspended all circuits
except the bandgap reference generator and bias detection circuits are powered down resulting in significant
power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use
of suspend/resume is recommended for new designs.

The port transmitter and receiver circuitry is disabled during power-down (when the PD input terminal is
asserted high), during reset (when the RESET
to the port, or when controlled by the internal arbitration logic. The TPBIAS is disabled during power–down,
during reset, or when the port is disabled as commanded by the LLC.

The CNA (cable-not-active) terminal provides a high output when all twisted-pair cable ports are disconnected,
and can be used along with LPS to determine when to power–down the TSB41LV06. The CNA output is not
debounced. In a PD terminal initiated power down, the CNA detection circuitry remains enabled.

The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node.
The LPS signal from the LLC indicates to the PHY that the LLC is powered up and active. During LLC
power-down mode, as indicated by the LPS input being low for more than 2.6 µs, the TSB41L V06 deactivates
the PHY-LLC interface to save power . The TSB41LV06 will continue the necessary repeater function required
for network operation during this low power state.

If the PHY receives a link-on packet from another node, the C/LKON terminal is activated to output a
square-wave signal. The LLC recognizes this signal, reactivates any powered-down portions of the LLC, and
notifies the PHY of its power-on status via the LPS terminal. The PHY confirms notification by deactivating the
square-wave signal on the C/LKON terminal, and then enables the PHY-link interface.

input terminal is asserted low), when no active cable is connected

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

functional block diagram

CPS

LPS

ISO

CNA

SYSCLK

LREQ

CTL0
CTL1

D0
D1
D2
D3
D4
D5
D6
D7

PC0
PC1
PC2

C/LKON

R0
R1

TPBIAS0
TPBIAS1
TPBIAS2
TPBIAS3
TPBIAS4
TPBIAS5

Link

Interface

I/O

Received

Data

Decoder/

Retimer

Arbitration

and

Control State

Machine

Logic

Bias Voltage

AND

Current

Generator

Cable Port 0

Cable Port 1

Cable Port 2

Cable Port 3

Cable Port 4

Cable Port 5

TPA0+
TPA0–

TPB0+
TPB0–

TPA1+
TPA1–

TPB1+
TPB1–

TPA2+
TPA2–

TPB2+
TPB2–

TPA3+
TPA3–

TPB3+
TPB3–

TPA4+
TPA4–

TPB4+
TPB4–

TPA5+
TPA5–

TPB5+
TPB5–

PD

RESET

4

Transmit

Data

Encoder

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Crystal Oscillator,

PLL System,

and Clock
Generator

XI
XO
FILTER0
FILTER1

TSB41LV06

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

PZP PACKAGE

(TOP VIEW)

DGND
DGND

LREQ
DV

DD

SYSCLK

DGND

CTL0
CTL1

DV

DD

D0
D1

V

DD_5V

DV

DD

D2
D3
D4
D5
D6
D7

DGND

CNA

DV

DD

PD

LPS

DGND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DD

DGND

RESETXIPLLGND

DV

XO

97

98

99

100

29

28

27

26

96

30

PLLGND

94

95

32

31

DD

PLLV

93

33

FIL TER1

FIL TER0

91

92

35

34

TPBIAS5

TPA5+

AGND

88

89

90

TSB41LV06

38

37

36

TP A5–

87

39

TPB5+

TPB5–

85

86

41

40

R1R0AGND

84

42

83

43

82

44

AGND

81

45

DDAVDDAVDDAVDD

AV

77

78

79

80

49

48

47

46

AGND

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

AGND
TPBIAS4
TPA4+
TPA4–
TPB4+
TPB4–
AV

DD

TPBIAS3
TPA3+
TPA3–
TPB3+
TPB3–

AV

DD

TPBIAS2
TPA2+
TP A2–
TPB2+
TPB2–

AV

DD

TPBIAS1
TPA1+
TPA1–
TPB1+
TPB1–
AGND

DGND

C/LKON

PC0

CPS

DDDVDD

DGND

DV

TPB0–

TPB0+

TPA0–

TPA0+

ISO

PC1

PC2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SE

TESTM

TPBIAS0

SM

DDAVDD

AV

AGND

AGND

AGND

AGND

AGND

5

TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

Terminal Functions

TERMINAL

NAME NO.

AGND 46, 47, 48, 49, 50,

AV

DD

C/LKON 27 CMOS I/O Bus manager contender programming input and link-on output. On hardware

CNA 21 CMOS O Cable not active output. This pin is asserted high when there are no ports

CPS 32 CMOS I Cable power status input. This pin is normally connected to cable power through

CTL0
CTL1

D0 – D7 10, 11, 14, 15, 16,

DGND 1, 2, 6, 20, 25, 26,

DV

DD

FILTER0
FILTER1

ISO 31 CMOS I Link interface isolation control input. This pin controls the operation of output

51, 75, 76, 81, 82,

90

44, 45, 57, 63, 69,

77, 78, 79, 80

7
8

17, 18, 19

33, 100

4, 9, 13, 22, 34,

35, 99

91
92

TYPE I/O DESCRIPTION

Supply – Analog circuit ground pins. These pins should be tied together to the low

Supply – Analog circuit power pins. A combination of high frequency decoupling

CMOS

5 V tol

CMOS

5 V tol

Supply – Digital circuit ground pins. These pins should be tied together to the low

Supply – Digital circuit power pins. A combination of high frequency decoupling capacitors

CMOS I/O PLL filter pins. These pins are connected to an external capacitance to form a

impedance circuit board ground plane.

capacitors near each pin are suggested, such as paralleled 0.1 µF and 0.001 µF.
Lower frequency 10 µF filtering capacitors are also recommended. These supply
pins are separated from PLLVDD and DVDD internal to the device to provide noise
isolation. They should be tied at a low impedance point on the circuit board.

reset, this pin is used to set the default value of the contender status indicated
during self-ID. Programming is done by tying the pin through a 10 kΩ resistor to a
high (contender) or low (not contender). The resistor allows the link-on output to
override the input.

Following hardware reset, this pin is the link-on output, which is used to notify the
LLC to power-up and become active. The link-on output is a square-wave signal
with a period of approximately 163 ns (8 SYSCLK cycles) when active. The
link-on output is deasserted low when the LPS input pin is active.

receiving incoming bias voltage.

a 400-kΩ resistor. This circuit drives an internal comparator that is used to detect
the presence of cable power.

I/O Control I/Os. These bidirectional signals control communication between the

TSB41L V06 and the LLC. Bus holders are built into these terminals.

I/O Data I/O’s. These are bidirectional data signals between the TSB41L V06 and the

LLC. Bus Holders are built into these terminals.

impedance circuit board ground plane.

near each pin are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower
frequency 10 µF filtering capacitors are also recommended. These supply pins
are separated from PLLVDD and AVDD internal to the device to provide noise
isolation. They should be tied at a low impedance point on the circuit board.

lag-lead filter required for stable operation of the internal frequency multiplier PLL
running off of the crystal oscillator . A 0.1 µF ±10% capacitor is the only external
component required to complete this filter.

differentiation logic on the CTL and D pins. If an optional isolation barrier of the
type described in Annex J of IEEE Std 1394-1995 is implemented between the
TSB41L V06 and LLC, the ISO
logic. If no isolation barrier is implemented (direct connection), or TI bus holder
Isolation is implemented, the ISO
differentiation logic. For additional information refer to TI application note

Bus Galvanic Isolation

pin should be tied low to enable the differentiation

pin should be tied high to disable the

Serial

, SLLA011.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB41LV06

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

Terminal Functions (Continued)

TERMINAL

NAME NO.

LPS 24 CMOS

LREQ 3 CMOS

PC0
PC1
PC2

PD 23 CMOS

PLLGND 94, 95 Supply – PLL circuit ground pins. These pins should be tied together to the low impedance

PLLV

DD

RESET 98 CMOS I Logic reset input. Asserting this pin low resets the internal logic. An internal

R0
R1

SE 42 CMOS I T est control input. This input is used in manufacturing test of the TSB41LV06. For

SM 43 CMOS I Test control input. This input is used in manufacturing test of the TSB41L V06. For

SYSCLK 5 CMOS O System clock output. Provides a 49.152 MHz clock signal, synchronized with

TESTM 41 CMOS I T est control input. This input is used in manufacturing test of the TSB41LV06. For

TPA0+
TPA1+
TPA2+
TPA3+
TPA4+
TPA5+

28
29
30

93 Supply – PLL circuit power pins. A combination of high frequency decoupling capacitors

83
84

39
55
61
67
73
88

TYPE I/O DESCRIPTION

5 V tol

5 V tol

CMOS I Power class programming inputs. On hardware reset, these inputs set the default

5 V tol

Bias – Current setting resistor pins. These pins are connected to an external resistance

Cable I/O Twisted-pair cable A differential signal pins. Board traces from each pair of

I Link power status input. This pin is used to monitor the power status of the LLC,

and is connected to either the VDD supplying the link layer controller through a
1kΩ resistor, or to a pulsed output which is active when the LLC is powered. The
pulsed output is useful when using an isolation barrier. If this input is low for more
than 2.6 µs, the LLC is considered powered-down. If this input is high for more
than 20 ns, the LLC is considered powered-up. If the LLC is powered-down, the
PHY-LLC interface is disabled, and the TSB41LV06 will perform only the basic
repeater functions required for network initialization and operation. Bus holder is
built into this terminal.

I LLC request input. The LLC uses this input to initiate a service request to the

TSB41L V06. Bus Holder is built into this terminal.

value of the power–class indicated during self-ID. Programmed is done by tying
the pins high or low. Refer to Table 9 for encoding.

I Power-down input. A high on this pin turns off all internal circuitry except the

cable-active monitor circuits, which control the CNA output. Bus Holder is built
into this terminal.

circuit board ground plane.

near each pin are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower
frequency 10 µF filtering capacitors are also recommended. These supply pins
are separated from DVDD and AVDD internal to the device to provide noise
isolation. They should be tied at a low impedance point on the circuit board.

pull–up resistor to VDD is provided so only an external delay capacitor in parallel
with a resistor is required for proper power-up operation (see
the

applications information section

input, and may also be driven by an open-drain type driver.

to set the internal operating currents and cable driver output currents. A
resistance of 6.30 kΩ ±0.5% is required to meet the IEEE Std 1394-1995 output
voltage limits.

normal use this pin should be tied to GND through a 1-kΩ resistor.

normal use this pin should be tied to GND.

data transfers, to the LLC.

normal use this pin should be tied to VDD.

positive and negative differential signal pins should be kept matched and as short
as possible to the external load resistors and to the cable connector.

). This input is otherwise a standard logic

power–up reset

in

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

Terminal Functions (Continued)

TERMINAL

NAME NO.

TPA0–
TPA1–
TPA2–
TPA3–
TPA4–
TPA5–

TPB0+
TPB1+
TPB2+
TPB3+
TPB4+
TPB5+

TPB0–
TPB1–
TPB2–
TPB3–
TPB4–
TPB5–

TPBIAS0
TPBIAS1
TPBIAS2
TPBIAS3
TPBIAS4
TPBIAS5

V

DD_5V

XI
XO

TYPE I/O DESCRIPTION

38
54
60
66
72
87

37
53
59
65
71
86

36
52
58
64
70
85

40
56
62
68
74
89

12 Supply – 5–V VDD pin. This pin should be connected to the LLC VDD supply when a 5–V

96
97

Cable I/O Twisted-pair cable A differential signal pins. Board traces from each pair of

Cable I/O Twisted-pair cable B differential signal pins. Board traces from each pair of

Cable I/O Twisted-pair cable B differential signal pins. Board traces from each pair of

Cable I/O Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed

Crystal – Crystal oscillator inputs. These pins connect to a 24.576 MHz parallel resonant

positive and negative differential signal pins should be kept matched and as short
as possible to the external load resistors and to the cable connector.

positive and negative differential signal pins should be kept matched and as short
as possible to the external load resistors and to the cable connector.

positive and negative differential signal pins should be kept matched and as short
as possible to the external load resistors and to the cable connector.

for proper operation of the twisted–pair cable drivers and receivers, and for
signaling to the remote nodes that there is an active cable connection. Each of
these pins must be decoupled with a 1.0 µF capacitor to ground.

LLC is used, and should be connected to the PHY DVDD when a 3–V LLC is used.
A combination of high frequency decoupling capacitors near this pin is
suggested, such as paralleled 0.1 µF and 0.001 µF . When this pin is tied to a 5–V
supply, all pin Bus Holders are disabled, regardless of the state of the ISO
When this pin is tied to a 3–V supply, Bus Holders are enabled when the ISO
high.

fundamental mode crystal. The optimum values for the external shunt capacitors
are dependent on the specifications of the crystal used

the applications information section).

(see crystal selection in

pin.

pin is

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
5V tolerant I/O supply voltage range, VDD_
5V tolerant input voltage range, VI_
Output voltage range at any output, V

(see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

I

5V

5V

O

–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to V

–0.5 V to VDD + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD_5V

†

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (see Note 2) HBM: 2 kV, MM: 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free air temperature,TA 0
Storage temperature range, T

stg

_

C to 70_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.

8

2. HBM is Human Body Model, MM is Machine Model.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Suppl

oltage, V

High level in ut voltage, V

IH

Low level in ut voltage, V

IL

R

l

°C

Differential input voltage, V

mV

Common-mode input voltage, V

V

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

DISSIPATION RATING TABLE

PACKAGE

‡

PZP

§

PZP

†

This is the inverse of the traditional junction-to-ambient thermal resistance (R

‡

1 oz. trace and copper pad with solder.

§

1 oz. trace and copper pad without solder.

NOTE: For more information, refer to TI application note

TI literature number SLMA002.

TA ≤ 25_C

POWER RATING

4.48 W 56.02 mW/°C 1.96 W

2.28 W 35.44 mW/°C 0.685 W

recommended operating conditions

PARAMETER MIN TYP

pp

y v

-

-

Output current, I
Maximum junction temperature TJ (see

values listed in therma

θJA

characteristics table)

Power-up reset time, t

Receive input jitter

Receive input skew

†

All typical values are at VDD = 3.3 V and TA = 25°

‡

For a node that does not source power, see Section 4.2.2.2 in IEEE 1394a.

DD

p

p

O

p

p

ID

IC

pu

Source power node 3 3.3 3.6 V
Nonsource power node 2.7
Case 1 (Bus Holder): ISO=VDD, V

Case 2 (5V Tol): ISO
LPS, PD, LREQ, CTL0, CTL1, D0–D7

C/LKON, PC0, PC1, PC2, ISO 0.7×V
RESET 0.6×V
Case 1 (Bus Holder): ISO=VDD, V

Case 2 (5V Tol): ISO
LPS, PD, LREQ, CTL0, CTL1, D0–D7

C/LKON, PC0, PC1, PC2, ISO 0.2 ×V
RESET 0.3×V
TPBIAS outputs –5.6 1.3 mA

R

= 17.85°C/W, TA=70°C 99

θJA

R

=28.22°C/W, TA=70°C 116

θJA
Cable inputs, during data reception 118 260
Cable inputs, during arbitration 168 265
TPB cable inputs, Source power node 0.4706 2.515
TPB cable inputs, Nonsource power node 0.4706 2.015
RESET input 2 ms
TPA, TPB cable inputs, S100 operation ±1.08
TPA, TPB cable inputs, S200 operation ±0.5
TPA, TPB cable inputs, S400 operation ±0.315
Between TPA and TPB cable inputs, S100 operation ±0.8
Between TPA and TPB cable inputs, S200 operation ±0.55
Between TPA and TPB cable inputs, S400 operation ±0.5

C.

DERATING FACTOR

ABOVE TA = 25_C

=VDD, V

=VDD, V

†

PowerPAD Thermally Enhanced Package

= V

DD_5V

DD_5V

DD_5V

= 5V

DD_5V

= 5 V

= V

DD

DD

TA = 70_C

POWER RATING

).

θJA

2.6 V

‡

DD
DD

TSB41LV06

SLLS289 – JANAURY1999

†

MAX UNIT

3 3.6

V
V

1.2 V

DD
DD

V
V

°

‡

ns

ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

TSB41LV06

ZIDDifferential impedance

Driver disabled

ZICCommon mode impedance

Driver disabled

Speed signal threshold

g

mV

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted)

driver

PARAMETER TEST CONDITION MIN TYP MAX UNIT

V
I
I
I

V
†
‡

receiver

V

V

V

V

V

V

Differential output voltage 56 Ω load, See Figure 1 172 265 mV

OD

Driver difference current, TP A+, TPA–, TPB+, TPB– Driver enabled, speed signaling off –1.05

DIFF

Common mode speed signaling current, TPB+, TPB– S200 speed signaling enabled –4.84

SP

Common mode speed signaling current, TPB+, TPB– S400 speed signaling enabled –12.4

SP

Off state differential voltage Drivers disabled, See Figure 1 20 mV

OFF
Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.
Limits defined as absolute limit of each of TPB+ and TPB– driver currents.

PARAMETER TEST CONDITION MIN TYP MAX UNIT

p

p

TH–R

TH–CB

TH+

TH–

TH–SP200

TH–SP400

Receiver input threshold voltage Drivers disabled –30 30 mV
Cable bias detect threshold, TPBx cable inputs Driver disabled 0.6 1 V
Positive arbitration comparator threshold

voltage
Negative arbitration comparator threshold

voltage

p

Driver disabled 89 168 mV

Driver disabled –168 –89 mV
TPBIAS-TPA common mode voltage,

drivers disabled

†
‡
‡

10 14 kΩ

20 kΩ

49 131

314 396

†

1.05
–2.53‡mA
–8.10‡mA

4 pF

24 pF

mA

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IDDSupply current

mA

V

0 V to V

mA

I

Pullup current, RESET input

A

V

V

V

V

TSB41LV06

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted) (continued)

device

PARAMETER TEST CONDITION MIN TYP MAX UNIT

pp

I

CC–PD

V

TH

V

OH

V

OL

I

BH+

I

BH–

I

I

I

OZ

IRST

IT+

IT–

V

O

†

Measured at cable power side of resistor.

‡

This parameter applicable only when ISO

NOTES: 3. Repeat (receive on port0, transmit on ports 1 through 5, full ISO payload of 84 µs, S400, data value of CCCCCCCCh), VDD = 3.3 V

Supply current – sleep power mode VCC = 3.3 V, TA = 25°C 7 mA
Power status threshold, CPS input

High-level output voltage

Low-level output voltage

Positive peak bus holder current
(D0 – D7, CTL0, CTL1, LREQ, LPS, PD)

Negative peak bus holder current
(D0 – D7, CTL0, CTL1, LREQ, LPS, PD)

Input current, LREQ, LPS, PD, TESTM, SE,
SM, PC0–PC2 inputs

Off-state output current, CTL0, CTL1,
D0–D7, C/LKON I/Os

p

Positive input threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs

Positive input threshold voltage, LPS inputs
Negative input threshold voltage, LREQ,

CTL0, CTL1, D0–D7 inputs
Negative input threshold voltage, LPS inputs
TPBIAS output voltage At rated IO current 1.665 2.015 V

TA = 25°C

4. Idle (receive cycle start on port0, xmt cycle start on ports 1 through 5), VDD = 3.3 V, TA = 25°C.

p

†

‡

‡

low.

See Note 3 273
See Note 4 166

= V

†

DD_5V

DD_5V

,

DD
DD

DD_5V

DD_5V

DD_5V

DD_5V

,

= V

,
= V

= V

DD

= VDD,

= V

DD

= VDD,

DD

DD

4.7 7.5 V

2.8

VDD–0.4

0.4

0.05 1

–1 –0.05

VDD/2+0.3 VDD/2+0.9

V

+1

ref

VDD/2–0.9 VDD/2–0.3

V

+0.2

ref

µ

400 KΩ resistor
VDD = 2.7 V, IOH = –4 mA 2.2
VDD = 3 V to 3.6 V,

IOH = –4 mA
Annex J; IOH = –9 mA

ISO

= 0 V, V
IOL = 4 mA 0.4
Annex J; IOH = 9 mA

ISO

= 0 V, V

ISO = 3.6 V, VDD = 3.6 V,

=

I

V

DD_5V

ISO = 0 V, VDD 3.6 V 5 µA

VO= VDD or 0 V ±5 µA
VI = 1.5 V –80 –40 –20

VI = 0 V –90 –45 –22
ISO = 0 V ,V
ISO = 0 V, V

V

= VDD × 0.42

ref

ISO = 0 V,V
ISO = 0 V, V

V

= VDD × 0.42

ref

V

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

TSB41LV06

gy

°C/W

gy

°C/W

IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

SLLS289 – JANAURY1999

thermal characteristics

PARAMETER TEST CONDITION

R

R

R

R

†

Usage of thermally enhanced PowerPad PZP package is assumed in all three test conditions.

Junction-to-free-air thermal resistance

θJA

Junction-to-case-thermal resistance

θJC

Junction-to-free-air thermal resistance

θJA

Junction-to-case-thermal resistance

θJC

Board mounted, No air flow,
High conductivity TI recommended test board,
Chip soldered or greased to thermal land with 1 oz.
copper

Board mounted, No air flow,
High conductivity TI recommended test board with
thermal land but no solder or grease thermal
connection to thermal land with 1 oz. copper

switching characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Jitter, transmit Between TPA and TPB ±0.15 ns

Skew, transmit Between TPA and TPB ±0.10 ns
trTP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns
tfTP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns
tsuSetup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK 50% to 50% See Figure 2 5 ns
thHold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK 50% to 50% See Figure 2 2 ns
tdDelay time, SYSCLK to CTL0, CTL1, D0–D7 50% to 50% See Figure 3 2 11 ns

†

MIN TYP MAX UNIT

17.85

0.12

28.22

0.12

°

°

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265