Texas Instruments TSB41LV04APFP Datasheet

Fully Supports Provisions of IEEE 1394-1995 Standard for High-Performance Serial Bus† and the P1394a Supplement

Fully Interoperable with FireWireTM and i.LINKTM Implementation of IEEE Std 1394

Fully Compliant With OpenHCI Requirements

Provides Four P1394a Fully-Compliant Cable Ports at 100/200/400 Megabits per Second (Mbits/s)

Full P1394a Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume

Extended Resume Signaling for Compatibility With Legacy DV Devices

Power-Down Features to Conserve Energy in Battery-Powered Applications Include: Automatic Device Power-Down during Suspend, Device Power-Down Terminal, Link Interface Disable Via LPS, and Inactive Ports Powered-Down

Ultra Low-Power Sleep Mode

Node Power Class Information Signaling for System Power Management

Cable Power Presence Monitoring

Cable Ports Monitor Line Conditions for Active Connection to Remote Node

description

TSB41LV04A

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz

Interface to Link-Layer Controller Supports Low-Cost TITMBus-Holder Isolation and Optional Annex J Electrical Isolation

Interoperable With Link-Layer Controllers Using 3.3-V and 5-V Supplies

Interoperable With Other Physical Layers (PHYs) Using 3.3-V and 5-V Supplies

Low-Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at

49.152 MHz

Incoming Data Resynchronized to Local Clock

Logic Performs System Initialization and Arbitration Functions

Encode and Decode Functions Included for Data-Strobe Bit Level Encoding

Separate Cable Bias (TPBIAS) for Each Port

Single 3.3-V Supply Operation

Low-Cost High-Performance 80-Pin TQFP (PFP) Thermally Enhanced Package

The TSB41L V04A provides the digital and analog transceiver functions needed to implement a four-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV04A is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12L V01A.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Corporation FireWire is a trademark of Apple Computers Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TSB41LV04A IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

description (continued)

The TSB41LV04A requires only an external 24.576 MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.

The TSB41L V04A supports an optional isolation barrier between itself and its LLC. When the ISO is tied high, the LLC interface outputs behave normally . When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the P1394a Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO terminal on the PHY must be high.

Data bits to be transmitted through the cable ports are received from the LLC on two, four or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41LV04A in synchronization with the 49.152 MHz system clock. These bits are combined serially , encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).

During packet reception the TP A and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two, four, or eight bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage.

input terminal

During packet reception the TP A and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two, four, or eight bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports.

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TSB41LV04A

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

description (continued)

The TSB41L V04A provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains four independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver , indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1.0 µF.

The line drivers in the TSB41L V04A operate in a high-impedance current mode, and are designed to work with external 1 12-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the external line termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.3-kΩ ±1%. This may be accomplished by placing a 6.34-kΩ ±1% resistor in parallel with a 1-MΩ resistor.

When the power supply of the TSB41L V04A is off while the twisted-pair cables are connected, the TSB41L V04A transmitter and receiver circuitry will present a high impedance to the cable and will not load the TPBIAS voltage at the other end of the cable.

When the TSB41LV04A is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB– terminals should be tied together and then pulled to ground, or the TPB+ and TPB– terminals should be connected to the suggested termination network. The TP A+ and TPA– and TPBIAS terminals of an unused port may be left unconnected. The TPBIAS terminal should be connected to a 1 µF capacitor to ground or left floating.

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to V while SM should be connected directly to ground.

Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are hardwired high or low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See T able 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM).

The TSB41LV04A supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low power conservation state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all four ports of the TSB41L V04A are suspended all circuits except the bandgap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use of suspend/resume is recommended for new designs.

The port transmitter and receiver circuitry is disabled during power-down (when the PD input terminal is asserted high), during reset (when the RESET to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power-down, during reset, or when the port is disabled as commanded by the LLC.

input terminal is asserted low), when no active cable is connected

, SE should be tied to ground through a 1-kΩ resistor,

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TSB41LV04A IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

description (continued)

The CNA (cable-not-active) output terminal is asserted high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended), and can be used along with LPS to determine when to power-down the TSB41L V04A. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET

The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICA TION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).

The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41L V04A detects that LPS is inactive, it will place the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41L V04A will continue the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY will initialize the interface and return it to normal operation.

terminal so as to force a reset of the TSB41LV04A internal logic.

When the PHY-LLC interface is in the low-power disabled state, the TSB41LV04A will automatically enter a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41LV04A disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the

low-power sleep

enable bit cleared. The TSB41L V04A will exit the low-power mode when the LPS input is asserted high or when a port event occurs, which requires that the TSB41L V04A become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a non-disabled port, etc.). The SYSCLK output will become active (and the PHY -LLC interface will be initialized and become operative) within 7.3 ms after LPS is asserted high when the TSB41LV04A is in the low-power mode.

The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163 ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists, which would otherwise cause C/LKON to be active.

mode) is attained when all ports are either disconnected, or disabled with the port’s interrupt

ultra

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functional block diagram

TSB41LV04A

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

CPS

LPS

ISO

CNA

SYSCLK

LREQ

CTL0 CTL1

D0 D1 D2 D3 D4 D5 D6 D7

PC0 PC1 PC2

C/LKON

R0 R1

Link

Interface

I/O

Received

Data

Decoder/

Retimer

Arbitration

and

Control State

Machine

Logic

Cable Port 0

Cable Port 1

Cable Port 2

Cable Port 3

TPA0+ TPA0–

TPB0+ TPB0–

TPA1+ TPA1–

TPB1+ TPB1–

TPA2+ TPA2–

TPB2+ TPB2–

TPA3+ TPA3–

TPB3+ TPB3–

TPBIAS0 TPBIAS1 TPBIAS2 TPBIAS3

RESET

Bias

Voltage

and

Current

Generator

Transmit

Data

Encoder

Crystal Oscillator,

PLL System,

and Clock Generator

XI XO FILTER0 FILTER1

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TSB41LV04A

TYPE

I/O

DESCRIPTION

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

PFP PACKAGE

(TOP VIEW)

AGND

AGND AGND

R0 R1

AGND FILTER0 FILTER1

PLLV

PLLGND PLLGND

RESET

DGND

AGND

TPBIAS3

59 58 57 56 5560 54

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

TP A3+

TP A3–

5678

TPB3+

TPB3–

TPBIAS2

TP A2+

52 51 5053

TSB41LV04A

10 11 12 13

TPA2–

TPB2+

TPB2–

49 48

AGND

TPBIAS1

47 46 45 44

14 15 16 17

TPA1+

TPB+

TPA1–

43 42 41

18 19 20

AGND

TPB1–

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

AGND AGND SM SE TESTM TPBIAS0 TPA0+ TPA0– TPB0+ TPB0– DV

DGND CPS ISO PC2 PC1 PC0 C/LKON DGND

TERMINAL

NAME NO.

AGND 39, 40, 41, 48,

60, 61, 66, 67,

47, 54, 62, 63,

64, 65

CNA

DGND

LPS

DGND

LREQ

SYSCLK

CTL0

DGND

CTL1

V5V

Terminal Functions

Supply – Analog circuit ground terminals. These terminals should be tied together to the low

Supply – Analog circuit power terminals. A combination of high frequency decoupling capacitors near

impedance circuit board ground plane.

each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from DVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board.

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TYPE

I/O

DESCRIPTION

TSB41LV04A

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

Terminal Functions (Continued)

TERMINAL

NAME NO.

C/LKON 22 CMOS I/O Bus manager contender programming input and link-on output. On hardware reset, this

CNA 17 CMOS O Cable not active output. This terminal is asserted high when there are no ports receiving

CPS 27 CMOS I Cable power status input. This terminal is normally connected to cable power through a

CTL0 CTL1

D0 – D7 7, 8, 10, 11, 12,

DGND 3, 16, 20, 21,

FILTER0 FILTER1

ISO 26 CMOS I Link interface isolation control input. This terminal controls the operation of output

4 5

13, 14, 15

28, 80

6, 29, 30, 79 Supply – Digital circuit power terminals. A combination of high frequency decoupling capacitors near

71 72

CMOS

5 V tol

CMOS

5 V tol

Supply – Digital circuit ground terminals. These terminals should be tied together to the low

CMOS I/O PLL filter terminals. These terminals are connected to an external capacitance to form a

terminal is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. However, it is recommended that this terminal should be programmed low , and that the contender status be set via the C register bit.

If the TSB41LV04A is used with an LLC that has a dedicated terminal for monitoring LKON and also setting the contender status, then a 10-kΩ series resistor should be placed on the LKON line between the PHY and LLC to prevent bus contention.

Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power-up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during Hardware Reset when it is high impedance.

The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and when:

a) the PHY receives a link-on PHY packet addressed to this node, b) the PEI (port-event interrupt) register bit is 1, or c) any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt),

or STOI (state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1.

Once activated, the link-on output will continue active until the LLC becomes active (both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the link-on output would otherwise be active because one of the interrupt bits is set (i.e., the link-on output is active due solely to the reception of a link-on PHY packet).

NOTE: If an interrupt condition exists, which would otherwise cause the link-on output to be activated if the LLC were inactive, the link-on output will be activated when the LLC subsequently becomes inactive.

incoming bias voltage.

400-kΩ resistor. This circuit drives an internal comparator that is used to detect the presence of cable power.

I/O Control I/Os. These bidirectional signals control communication between the TSB41LV04A

and the LLC. Bus holders are built into these terminals.

I/O Data I/Os. These are bidirectional data signals between the TSB41L V04A and the LLC. Bus

holders are built into these terminals.

impedance circuit board ground plane.

each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board.

lag-lead filter required for stable operation of the internal frequency multiplier PLL running off of the crystal oscillator. A 0.1-µF ±10% capacitor is the only external component required to complete this filter.

differentiation logic on the CTL and D terminals. If an optional Annex J type isolation barrier is implemented between the TSB41LV04A and LLC, the ISO terminal should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the ISO differentiation logic. For additional information refer to TI application note

Galvanic Isolation

, SLLA011.

terminal should be tied high to disable the

Serial Bus

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TSB41LV04A

TYPE

I/O

DESCRIPTION

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

Terminal Functions (Continued)

TERMINAL

NAME NO.

LPS 19 CMOS

LREQ 1 CMOS

PC0 PC1 PC2

PD 18 CMOS

PLLGND 74, 75 Supply – PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit

PLLV

R0 R1

RESET 78 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to

SE 37 CMOS I T est control input. This input is used in manufacturing test of the TSB41L V04A. For normal use this

SM 38 CMOS I Test control input. This input is used in manufacturing test of the TSB41L V04A. For normal use this

SYSCLK 2 CMOS O System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the

TESTM 36 CMOS I T est control input. This input is used in manufacturing test of the TSB41L V04A. For normal use this

23 24 25

73 Supply – PLL circuit power terminals. A combination of high frequency decoupling capacitors near each

68 69

5 V tol

CMOS I Power class programming inputs. On hardware reset, these inputs set the default value of the

5 V tol

Bias – Current setting resistor terminals. These terminals are connected to an external resistance to set

I Link power status input. This terminal is used to monitor the active/power status of the link layer

controller and to control the state of the PHY -LLC interface. This terminal should be connected to either the VDD supplying the LLC through a 10 kΩ resistor, or to a pulsed output, which is active when the LLC is powered. A pulsed signal should be used when an isolation barrier exists between the LLC and PHY (see Figure 8).

The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128 SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns in order to be guaranteed to be observed as high by the PHY.

When the TSB41LV04A detects that LPS is inactive, it will place the PHY-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset.

The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0.

I LLC request input. The LLC uses this input to initiate a service request to the TSB41LV04A. Bus

holder is built into this terminal.

power-class indicated during self-ID. Programmed is done by tying the terminals high or low. Refer to Table 9 for encoding.

I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active

monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal pulldown on the RESET terminal so as to force a reset of the internal control logic

board ground plane.

terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from DVDD and AV internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board.

the internal operating currents and cable driver output currents. A resistance of 6.30 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage limits.

VDD is provided so only an external delay capacitor in parallel with a resistor is required for proper power-up operation (see terminal also incorporates an internal pulldown, which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver.

terminal should be tied to GND through a 1-kΩ pulldown resistor.

terminal should be tied to GND.

LLC.

terminal should be tied to VDD.

power-up reset

in the

applications information section

). The RESET

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPE

I/O

DESCRIPTION

negative differential signal terminals should be kept matched and as short as possible to the

TSB41LV04A

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

Terminal Functions (Continued)

TERMINAL

NAME NO.

TPA0+ TPA1+ TPA2+ TPA3+

TPA0– TPA1– TPA2– TPA3–

TPB0+ TPB1+ TPB2+ TPB3+

TPB0– TPB1– TPB2– TPB3–

TPBIAS0 TPBIAS1 TPBIAS2 TPBIAS3

VDD5V 9 Supply – 5-V VDD terminal. This terminal should be connected to the LLC VDD supply when a 5-V LLC is

XI XO

34 45 52 58

33 44 51 57

32 43 50 56

31 42 49 55

35 46 53 59

76 77

Cable I/O

Twisted-pair cable A differential signal terminals. Board traces from each pair of positive and

Cable I/O

Cable I/O T wisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper operation

Crystal – Crystal oscillator inputs. These terminals connect to a 24.576 MHz parallel resonant fundamental

external load resistors and to the cable connector.

Twisted-pair cable B differential signal terminals. Board traces from each pair of positive and external load resistors and to the cable connector.

of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. Each of these terminals, except for an unused port, must be decoupled with a 1-µF capacitor to ground. For the unused port, this terminal can be left unconnected.

used, and should be connected to the PHY DVDD when a 3-V LLC is used. A combination of high frequency decoupling capacitors near this terminal is suggested, such as paralleled 0.1 µF and

0.001 µF . When this terminal is tied to a 5-V supply, all terminal bus holders are disabled, regardless of the state of the ISO when the ISO

mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used

terminal. When this terminal is tied to a 3-V supply, bus holders are enabled

terminal is high.

(see crystal selection in the applications information section).

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TSB41LV04A IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V 5-V tolerant I/O supply voltage range, V 5-V tolerant input voltage range, V Output voltage range at any output, V

Electrostatic discharge (see Note 2) HBM: 2 kV, MM: 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free air temperature,T Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.

2. HBM is Human Body Model, MM is Machine Model.

PACKAGE

PFP PFP PFP

†

This is the inverse of the traditional junction-to-ambient thermal resistance (R

‡

1 oz. trace and copper pad with solder.

1 oz. trace and copper pad without solder.

Standard JEDEC High-K board

NOTE: For more information, refer to TI application note

TI literature number SLMA002.

(see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5V –0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(5V)

stg

DISSIPATION RATING TABLE

TA ≤ 25_C

POWER RATING

‡

§ ¶

5.05 W 50.5 mW/°C 2.79 W

3.05 W 30.5 mW/°C 1.68 W

2.01 W 20.1 mW/°C 1.11 W

DERATING FACTOR

ABOVE TA = 25_C

PowerPAD Thermally Enhanced Package

†

TA = 70_C

POWER RATING

θJA

–0.5 V to VDD5V + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to VDD + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C to 70_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Suppl

oltage, V

High level in ut voltage, V

Low level in ut voltage, V

Maximum junction tem erature T

(see

Differential input voltage, V

Common-mode input voltage, V

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

recommended operating conditions

PARAMETER MIN TYP

y v

Output current, I

values listed in thermal

θJA

characteristics table)

Power-up reset time, t

Receive input jitter

Receive input skew

†

All typical values are at VDD = 3.3 V and TA = 25°C.

‡

For a node that does not source power, see Section 4.2.2.2 in IEEE 1394a.

Source power node 3 3.3 3.6 V Nonsource power node 2.7 Case 1 (Bus Holder): ISO=VDD, V

Case 2 (5V Tol): ISO LREQ, CTL0, CTL1, D0–D7

C/LKON, PC0, PC1, PC2, ISO, PD 0.7×V RESET 0.6×V Case 1 (Bus Holder): ISO=VDD, V

Case 2 (5V Tol): ISO LREQ, CTL0, CTL1, D0–D7

C/LKON, PC0, PC1, PC2, ISO, PD 0.2×V RESET 0.3×V TPBIAS outputs –5.6 1.3 mA R

= 17.85°C/W, TA=70°C 86.45

θJA

=28.22°C/W, TA=70°C 96

θJA

=49.17°C/W, TA=70°C 115.3

θJA

Cable inputs, during data reception 118 260 Cable inputs, during arbitration 168 265 TPB cable inputs, Source power node 0.4706 2.515 TPB cable inputs, Nonsource power node 0.4706 2.015 RESET input 2 ms TPA, TPB cable inputs, S100 operation ±1.08 TPA, TPB cable inputs, S200 operation ±0.5 TPA, TPB cable inputs, S400 operation ±0.315 Between TPA and TPB cable inputs, S100 operation ±0.8 Between TPA and TPB cable inputs, S200 operation ±0.55 Between TPA and TPB cable inputs, S400 operation ±0.5

=VDD, V

DD_5V

= 5V

= 5 V

= V

TSB41LV04A

SLLS379 – OCTOBER 1999

†

MAX UNIT

‡

2.6 V

DD DD

3 3.6

1.2 V

DD DD

‡

V V

°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB41LV04A

Common mode speed signaling current, TPB

TPB

ZIDDifferential impedance

Driver disabled

ZICCommon mode impedance

Driver disabled

Speed signal threshold

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

driver

PARAMETER TEST CONDITION MIN TYP MAX UNIT

DIFF

SP200

SP400

OFF

†

Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.

‡

Limits defined as absolute limit of each of TPB+ and TPB– driver currents.

receiver

TH–R

TH–CB

TH+

TH–

TH–SP200

TH–SP400

Differential output voltage 56 Ω load, See Figure 1 172 265 mV Driver difference current, TP A+, TPA–, TPB+, TPB– Driver enabled, speed signaling off –1.05

Off state differential voltage Drivers disabled, See Figure 1 20 mV

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Receiver input threshold voltage Drivers disabled –30 30 mV Cable bias detect threshold, TPBx cable inputs Driver disabled 0.6 1 V Positive arbitration comparator threshold

voltage Negative arbitration comparator threshold

voltage

S200 speed signaling enabled –4.84

–

S400 speed signaling enabled –12.4

Driver disabled 89 168 mV

Driver disabled –168 –89 mV TPBIAS-TPA common mode voltage,

drivers disabled

† ‡ ‡

10 14 kΩ

20 kΩ

49 131

314 396

1.05 –2.53 –8.10

†

‡ ‡

4 pF

24 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

High-level output voltage, CTL0, CTL1

TSB41LV04A

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued)

device

PARAMETER TEST CONDITION MIN TYP MAX UNIT

See Note 3 205

CC–ULP

OH-AJ

OL-AJ

BH+

BH–

IRST

SE-PU

IT+

IT–

†

Measured at cable power side of resistor.

‡

This parameter applicable only when ISO

NOTES: 3. Transmit Max Packet (4 ports transmitting maximum size isochronous packets – 4096 bytes, sent on every isochronous internal,

Supply current

Supply current – ultra low power mode

Power status threshold, CPS input

D0–D7, DNA, C/LKON, SYSCLK outputs

Low-level output voltage, CTL0, CTL1, D0–D7, DNA, C/LKON, SYSCLK outputs

High-level Annex J output voltage, CTL0, CTL1, D0–D7, DNA, C/LKON, SYSCLK outputs

Low-level Annex J output voltage, CTL0, CTL1, D0–D7, DNA, C/LKON, SYSCLK outputs

Positive peak bus holder current (D0 – D7, CTL0, CTL1, LREQ)

Negative peak bus holder current (D0 – D7, CTL0, CTL1, LREQ, LPS, PD)

Input current, LREQ, LPS, PD, TESTM, SE, SM, PC0–PC2 inputs

Off-state output current, CTL0, CTL1, D0–D7, C/LKON I/Os

Pullup current, RESET input VI = 1.5 V or 0 V –90 –20 µA Pullup current, SE input VI = 1.5 V or 0 V –50 –5 µA Positive input threshold voltage, LREQ,

CTL0, CTL1, D0–D7 inputs Positive input threshold voltage, LPS

inputs Negative input threshold voltage, LREQ,

CTL0, CTL1, D0–D7 inputs Negative input threshold voltage, LPS

inputs TPBIAS output voltage At rated IO current 1.665 2.015 V

S400, data value of 0xCCC CCCCh), VDD = 3.3 V, TA = 25°C.

4. Repeat Typical Packet (1 port receiving DV packets on every isochronous interval, 3 ports repeating the packet S100), VDD = 3.3 V, TA = 25°C.

5. Idle (4 ports transmitting cycle starts), VDD = 3.3 V, TA = 25°C.

†

‡

low.

See Note 4 See Note 5 125 VCC = 3.3 V, TA = 25°C,

Ports disabled, PD = 0 V, LPS = 0 V

= V

†

DD_5V

DD DD

DD_5V

= VDD,

= V

= VDD,

= V

= VDD,

4.7 7.5 V

2.8

VDD–0.4 V

0.05 1

–1 –0.05

VDD/2+0.3 VDD/2+0.9

VDD/2–0.9 VDD/2–0.3

+0.2

ref

400-kΩ resistor VDD = 2.7 V, IOH = –4 mA 2.2

VDD = 3 V to 3.6 V, IOH = –4 mA

IOL = 4 mA 0.4 V Annex J; IOH = –9 mA

ISO

= 0 V, V

VDD ≥ 3 V Annex J; IOL = 9 mA

ISO

= 0 V, V

VDD ≥ 3 V

ISO = 3.6 V, VDD = 3.6 V,

= 0 V to

DD_5V

ISO = 0 V, VDD 3.6 V 1 µA

VO= VDD or 0 V ±5 µA

ISO = 0 V ,V ISO = 0 V, V

= VDD × 0.42

ref

ISO = 0 V,V ISO = 0 V, V

= VDD × 0.42

ref

151

150 µA

0.4 V

ref

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB41LV04A

°C/W

High conductivity JEDEC test board with 1 oz

°C/W

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

thermal characteristics

PARAMETER TEST CONDITION

R R

†

Usage of thermally enhanced PowerPad PFP package is assumed in all three test conditions.

Junction-to-free-air thermal resistance

θJA

Junction-to-case-thermal resistance

θJC

Junction-to-free-air thermal resistance

θJA

Junction-to-case-thermal resistance

θJC

Junction-to-free-air thermal resistance

θJA

Junction-to-case-thermal resistance

θJC

Board mounted, No air flow, High conductivity TI recommended test board, Chip soldered or greased to thermal land with 1 oz. copper

Board mounted, No air flow, High conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land with 1 oz. copper

Board mounted, No air flow,

copper

switching characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Jitter, transmit Between TPA and TPB ±0.15 ns

Skew, transmit Between TPA and TPB ±0.10 ns trTP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns tfTP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns tsuSetup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK 50% to 50% See Figure 2 5 ns thHold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK 50% to 50% See Figure 2 2 ns tdDelay time, SYSCLK to CTL0, CTL1, D0–D7 50% to 50% See Figure 3 2 11 ns

†

MIN TYP MAX UNIT

19.8

0.17

32.8

0.17

49.8

3.6

PARAMETER MEASUREMENT INFORMATION

TPAx+

TPBx+

56 Ω

TPAx– TPBx–

Figure 1. Test Load Diagram

SYSCLK

Dx, CTLx, LREQ

Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB41LV04A

IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

SLLS379 – OCTOBER 1999

PARAMETER MEASUREMENT INFORMATION

SYSCLK

Dx, CTLx

Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms

APPLICATION INFORMATION

internal register configuration

There are 16 accessible internal registers in the TSB41L V04A. The configuration of the registers at addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0 through 7h, is currently selected. The selected page is set in base register 7h.

The configuration of the base registers is shown in T able 1 and corresponding field descriptions given in T able 2. The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as reserved or Rsvd in the register configuration tables below) is read as 0, but is subject to future usage. All registers in pages 2 through 6 are reserved.

Table 1. Base Register Configuration

ADDRESS BIT POSITION

0 1 2 3 4 5 6 7 0000 Physical ID R CPS 0001 RHB IBR Gap_Count 0010 Extended (111b) Rsvd Num_Ports (0101b) 0011 PHY_Speed (010b) Rsvd Delay (0000b) 0100 L C Jitter (000b) Pwr_Class 0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC 0110 Reserved 0111 Page_Select Rsvd Port_Select

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+ 34 hidden pages

Texas Instruments TSB41LV04APFP Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual