Texas Instruments TSB41LV02APAP Datasheet

D

Fully Supports Provisions of IEEE
1394-1995 Standard for High-Performance
Serial Bus† and the P1394a Supplement

D

Fully Interoperable With FireWire and
i.LINK Implementation of IEEE Std 1394

D

Fully Compliant With OpenHCI
Requirements

D

Provides Two P1394a Fully Compliant
Cable Ports at 100/200/400 Megabits per
Second (Mbits/s)

D

Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-By Concatenation, Port
Disable/Suspend/Resume

D

Extended Resume Signaling for
Compatibility With Legacy DV Devices

D

Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Pin, Link
Interface Disable via LPS, and Inactive
Ports Powered Down

D

Ultra Low-Power Sleep Mode

D

Node Power Class Information Signaling
for System Power Management

D

Cable Power Presence Monitoring

D

Cable Ports Monitor Line Conditions for
Active Connection to Remote Node

description

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

D

Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Control Bit and P1394a Features

D

Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz

D

Interface to Link Layer Controller Supports
Low Cost TI Bus-holder Isolation and
Optional Annex J Electrical Isolation

D

Interoperable With Link-Layer Controllers
Using 3.3-V and 5-V Supplies

D

Interoperable With Other Physical Layers
(PHYs) Using 3.3-V and 5-V Supplies

D

Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at

49.152 MHz

D

Incoming Data Resynchronized to Local
Clock

D

Logic Performs System Initialization and
Arbitration Functions

D

Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding

D

Separate Cable Bias (TPBIAS) for Each Port

D

Single 3.3-V Supply Operation

D

Meets Intel Mobile Power Guideline 2000

D

Low Cost High Performance 64 Pin TQFP
(PAP) Thermally Enhanced Package

The TSB41L V02A provides the digital and analog transceiver functions needed to implement a two-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV02A is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,
TSB12LV41, TSB12LV42, or TSB12L V01A.

The TSB41LV02A requires only an external 24.576 MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates
the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock
signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock
signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization
of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation.
FireWire is a trademark of Apple Computer, Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

TSB41LV02A
IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

description (continued)

The TSB41L V02A supports an optional isolation barrier between itself and its LLC. When the ISO input terminal
is tied high, the LLC interface outputs behave normally . When the ISO terminal is tied low, internal differentiating
logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer
galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in P1394a Supplement (section

5.9.4) (hereafter referred to as Annex J type isolation). T o operate with TI bus holder isolation, the ISO
on the PHY must be high.

Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths
(depending on the requested transmission speed) and are latched internally in the TSB41LV02A in
synchronization with the 49.152 MHz system clock. These bits are combined serially , encoded, and transmitted
at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the
outbound data-strobe information stream. During transmission, the encoded data information is transmitted
differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the
TPA cable pair(s).

During packet reception the TP A and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded
strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover
the receive clock signal and the serial data bits. The serial data bits are split into two, four, or eight bit parallel
streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock,
and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected)
cable ports.

terminal

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the
remotely supplied twisted-pair bias voltage.

The TSB41L V02A provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. The PHY
contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver,
indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter
capacitor of 1.0 µF.

The line drivers in the TSB41L V02A operate in a high-impedance current mode, and are designed to work with
external 1 12-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network
is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω
resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is
connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly
connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with
recommended values of 5 kΩ and 220 pF. The values of the external line termination resistors are designed
to meet the standard specifications when connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal
operating currents. This current setting resistor has a value of 6.3 kΩ ±1%. This may be accomplished by placing
a 6.34-kΩ ±1% resistor in parallel with a 1-MΩ resistor.

When the power supply of the TSB41LV02A is 0 V while the twisted-pair cables are connected, the
TSB41L V02A transmitter and receiver circuitry will present a high impedance to the cable and will not load the
TPBIAS voltage at the other end of the cable.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

description (continued)

When the TSB41LV02A is used with one or more of the ports not brought out to a connector, the twisted-pair
terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and
TPB– terminals should be tied together and then pulled to ground, or the TPB+ and TPB– terminals should be
connected to the suggested termination network. The TP A+ and TPA– and TPBIAS terminals of an unused port
may be left unconnected. The TPBIAS terminal should be connected to a 1-µF capacitor to ground or left
floating.

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, the TESTM terminal should be connected to V
while SM should be connected directly to ground.

Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID
packet, and are hardwired high or low as a function of the equipment design. The PC0–PC2 terminals are used
to indicate the default power-class status for the node (the need for power from the cable or the ability to supply
power to the cable). See T able 9 for power-class encoding. The C/LKON terminal is used as an input to indicate
that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM).

The TSB41LV02A supports suspend/resume as defined in the IEEE P1394a specification. The suspend
mechanism allows pairs of directly-connected ports to be placed into a low-power conservation state
(suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended
state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state
is capable of detecting connection status changes and detecting incoming TPBias. When both ports of the
TSB41LV02A are suspended, all circuits except the bandgap reference generator and bias detection circuits
are powered down, resulting in significant power savings. For additional details of suspend/resume operation
refer to the P1394a specification. The use of suspend/resume is recommended for new designs.

, SE should be tied to ground through a 1-kΩ resistor,

DD

The port transmitter and receiver circuitry is disabled during power-down (when the PD input terminal is
asserted high), during reset (when the RESET
to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power-down,
during reset, or when the port is disabled as commanded by the LLC.

The CNA (cable-not-active) output terminal is asserted high when there are no twisted-pair cable ports receiving
incoming bias (i.e., they are either disconnected or suspended), and can be used along with LPS to determine
when to power-down the TSB41L V02A. The CNA output is not debounced. When the PD terminal is asserted
high, the CNA detection circuitry is enabled (regardless of the previous state ports) and a pulldown is activated
on the RESET

The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node.
The LPS signal from the LLC used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application
Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable,
and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input
regardless of the state of the LCtrl bit).

The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise.
When the TSB41LV02A detects that the LPS is inactive, it will place the PHY-LLC interface into a low-power
reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored;
however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC
interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC
interface is also held in the disabled state during hardware reset. The TSB41L V02A will continue the necessary
repeater functions required for normal network operation regardless of the state of the PHY-LLC interface.
When the interface is in the reset or disabled state and the LPS is again observed active, the PHY will initialize
and return it to normal operation.

terminal so as to force a reset of the TSB41LV02A internal logic.

input terminal is asserted low), when no active cable is connected

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TSB41LV02A
IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

description (continued)

When the PHY-LLC interface is in the low-power disabled state, the TSB41LV02A will automatically enter a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41LV02A disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the ports (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the

low-power sleep

enable bit cleared. The TSB41L V02A will exit the low-power mode when the LPS input is asserted high or when
a port event occurs which requires that the TSB41L V02A to become active in order to respond to the event or
to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output will
become active (and the PHY -LLC interface will be initialized and become operative) within 7.3 ms after LPS is
asserted high when the TSB41LV02A is in the low-power mode.

The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described previously , or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY
packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts
the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which would
otherwise cause C/LKON to be active.

mode) is attained when all ports are either disconnected or disabled with the port’s interrupt

ultra

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

CPS
LPS

ISO

CNA

SYSCLK

LREQ

CTL0
CTL1

D0
D1
D2
D3
D4
D5
D6
D7

Link

Interface

I/O

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

Received Data

Decoder/Retimer

TPA0+
TPA0–

Arbitration

and Control

State Machine

Logic

Cable Port 0

TPB0+
TPB0–

PC0
PC1
PC2

C/LK0N

R0
R1

TPBIAS0
TPBIAS1

PD

RESET

Bias Voltage

and

Current Generator

Transmit

Data

Encoder

Cable Port 1

Crystal Oscillator,

PLL System,

and

Clock Generator

TPA1+
TPA1–

TPB1+
TPB1–

XI
XO

FILTER0

FILTER1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TSB41LV02A
IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

pin assignments

PAP PACKAGE

(TOP VIEW)

LREQ

SYSCLK

CNA
CTL0
CTL1

D0
D1
D2
D3
D4
D5
D6
D7

PD

LPS

VDD_5V

DD

DGND

DGND

DV

63 62 61 60 5964 58

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19

DGND

DGND

20

C/LKON

DD

XOXIPLLGND

DV

21 22 23 24

PC1

PC2

ISO

PC0

DD

FILTER1

PLLV

DD

DVDDDV

FILTER0

53 52

TESTM

PLLGND

56 55 5457

25 26 27 28 29

CPS

AVDDAV

RESET

51 50 49

30 31 32

SE

SM

DD

AGND

DD

AVDDAV

AGND

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

AGND

AGND
TPBIAS1
TP A1+
TP A1–
TPB1+
TPB1–
AV

DD

R1
R0
AGND
TPBIAS0
TP A0+
TP A0–
TPB0+
TPB0–
AGND

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPE

I/O

DESCRIPTION

TERMINAL

NAME NO.

32, 33,

AGND

AV

DD

C/LKON 19 CMOS I/O

CNA 3 CMOS O

CPS 24 CMOS I
CTL0

CTL1

D0 – D7

DGND

DV

DD

FILTER0
FILTER1

ISO 23 CMOS I

39, 48,

49, 50

30, 31,
42, 51,

52

4
5

6, 7, 8, 9,

10, 11,

12, 13

17, 18,

63, 64

25, 26
61, 62

54
55

Supply

Supply

CMOS

5 V tol

CMOS

5 V tol

Supply

Supply

CMOS I/O

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

Terminal Functions

Analog circuit ground pins. These pins should be tied together to the low impedance circuit board
ground plane.

Analog circuit power pins. A combination of high frequency decoupling capacitors near each pin is
suggested, such as paralleled 0.1 µF and 0.001 µF . Lower frequency 10 µF filtering capacitors are
also recommended. These supply pins are separated from PLLVDD and DVDD internal to the device
to provide noise isolation. They should be tied at a low impedance point on the circuit board.

Bus manager contender programming input and link-on output. On hardware reset, this pin is used
to set the default value of the contender status indicated during self-ID. Programming is done by
tying the pin through a 10-kΩ resistor to a high (contender) or low (not contender). The resistor
allows the link-on output to override the input.

Following hardware reset, this pin is the link-on output, which is used to notify the LLC to power-up
and become active. The link-on output is a square-wave signal with a period of approximately 163 ns
(8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during Hardware
Reset when it is high impedance.

The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit is cleared) and when:

• The PHY receives a link-on PHY packet addressed to this node,

• The PEI (port-event interrupt) register bit is 1, or

• Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or

STOI (state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt
enable) register bit is also 1.

Once activated the link-on output will continue active until the LLC becomes active (both LPS active
and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the
link-on output would otherwise be active because one of the interrupt bits is set (i.e., the link-on
output is active due solely to the reception of a link-on PHY packet.

Note: If an interrupt condition exists which would otherwise cause the link-on output to be activated if
the LLC were inactive, the link-on output will be activated when the LLC subsequently becomes
inactive.

Cable not active output. This pin is asserted high when there are no ports receiving incoming bias
voltage.

Cable power status input. This pin is normally connected to cable power through a 400 kΩ resistor.
This circuit drives an internal comparator that is used to detect the presence of cable power.

Control I/Os. These bidirectional signals control communication between the TSB41L V02A and the

I/O

LLC. Bus holders are built into these terminals.
Data I/Os. These are bidirectional data signals between the TSB41LV02A and the LLC. Bus holders

I/O

are built into these terminals.
Digital circuit ground pins. These pins should be tied together to the low impedance circuit board

ground plane.
Digital circuit power pins. A combination of high frequency decoupling capacitors near each pin is

suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are
also recommended. These supply pins are separated from PLLVDD and AVDD internal to the device
to provide noise isolation. They should be tied at a low impedance point on the circuit board.

PLL filter pins. These pins are connected to an external capacitance to form a lag-lead filter required
for stable operation of the internal frequency multiplier PLL running off of the crystal oscillator. A

0.1 µF ±10% capacitor is the only external component required to complete this filter .
Link interface isolation control input. This pin controls the operation of output differentiation logic on

the CTL and D pins. If an optional Annex J type isolation barrier is implemented between the
TSB41LV02A and LLC, the ISO
isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the
ISO

pin should be tied high to disable the differentiation logic. For additional information refer to TI

application note

Serial Bus Galvanic Isolation

pin should be tied low to enable the differentiation logic. If no

, SLLA011.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TSB41LV02A

TYPE

I/O

DESCRIPTION

diff

ible to th

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

Terminal Functions (Continued)

TERMINAL

NAME NO.

Link power status input. This pin is used to monitor the active/power status of the link-layer controller,
and to control the state of the PHY -LLC interface. This pin should be connected to either the V
supplying the LLC through a 1-kΩ resistor, or to a pulsed output which is active when the LLC is
powered. A pulsed signal should be used when an isolation barrier exists between the LLC and the
PHY .

The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128
SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating

LPS 15

LREQ 1
PC0

PC1
PC2

PD 14

PLLGND 57, 58 Supply

PLLV

DD

R0
R1

RESET 53 CMOS I

SE 28 CMOS I

SM 29 CMOS I

SYSCLK 2 CMOS O

TESTM 27 CMOS I
TPA0+

TPA1+
TPA0–

TPA1–

20
21
22

56 Supply

40
41

37
46

36
45

CMOS
5 V tol

CMOS
5 V tol

CMOS I

CMOS
5 V tol

Bias

Cable I/O

Cable I/O

signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns in order to be
ensured to be observed as high by the PHY.

I

When the TSB41LV02A detects that LPS is inactive, it will place the PHY-LLC interface into a
low-power reset state. In the reset state, the CTL and D outputs are held in the logic low state and the
LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for
more than 26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled
state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.

The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1,
and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0.

LLC request input. The LLC uses this input to initiate a service request to the TSB41LV02A. Bus

I

holder is built into this terminal.
Power class programming inputs. On hardware reset, these inputs set the default value of the

power-class indicated during self-ID. Programming is done by tying these pins high or low. Refer to
Table 9 for encoding.

Power-down input. A high on this pin turns off all internal circuitry except the cable-active monitor
circuits, which control the CNA output. Asserting the PD input high also activates an internal

I

pull-down on the RESET
PLL circuit ground pins. These pins should be tied together to the low impedance circuit board

ground plane.
PLL circuit power pins. A combination of high frequency decoupling capacitors near each pin are

suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are
also recommended. These supply pins are separated from DVDD and AVDD internal to the device to
provide noise isolation. They should be tied at a low impedance point on the circuit board.

Current setting resistor pins. These pins are connected to an external resistance to set the internal
operating currents and cable driver output currents. A resistance of 6.30 kΩ ±1% is required to meet
the IEEE Std 1394-1995 output voltage limits.

Logic reset input. Asserting this pin low resets the internal logic. An internal pullup resistor to VDD is
provided so only an external delay capacitor is required for proper power-up operation (see

power-up reset

incorporates an internal pulldown which is activated when the PD input is asserted high. This input is
otherwise a standard logic input, and may also be driven by an open-drain type driver.

T est control input. This input is used in manufacturing test of the TSB41L V02A. For normal use this
pin should be tied to GND through a 1 kΩ resistor.

T est control input. This input is used in manufacturing test of the TSB41L V02A. For normal use this
pin should be tied to GND.

System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the
LLC.

T est control input. This input is used in manufacturing test of the TSB41L V02A. For normal use this
pin should be tied to VDD.

Twisted-pair cable A differential signal pins. Board traces from each pair of positive and negative

erential signal pins should be kept matched and as short as poss

and to the cable connector.

in the APPLICATIONS INFORMATION section). The RESET terminal also

terminal so as to force a reset of the internal control logic.

p

p

DD

p

e external load resistors

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPE

I/O

DESCRIPTION

diff

ible to th

TERMINAL

NAME NO.

TPB0+
TPB1+

TPB0–
TPB1–

TPBIAS0
TPBIAS1

XI
XO

V

DD_5V

35
44

34
43

38
47

59
60

16 Supply

Cable I/O

Cable I/O

Cable I/O

Crystal

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

Terminal Functions (Continued)

Twisted-pair cable B differential signal pins. Board traces from each pair of positive and negative

erential signal pins should be kept matched and as short as poss

and to the cable connector.

Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper operation
of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an
active cable connection. Each of these pins, except for an unused port, must be decoupled with a
1 µF capacitor to ground. For the unused port, this pin can be left unconnected.

Crystal oscillator inputs. These pins connect to a 24.576 MHz parallel resonant fundamental mode
crystal. The optimum values for the external shunt capacitors are dependent on the specifications of
the crystal used (see

5-V VDD pin. This pin should be connected to the LLC VDD supply when a 5-V LLC is used, and
should be connected to the PHY DVDD when a 3-V LLC is used. A combination of high frequency
decoupling capacitors near this pin is suggested, such as paralleled 0.1 µF and 0.001 µF . When this
pin is tied to a 5-V supply, all pin bus holders are disabled, regardless of the state of the ISO
When this pin is tied to a 3-V supply, bus holders are enabled when the ISO

p

crystal selection

p

in the APPLICATIONS INFORMATION section).

p

e external load resistors

pin is high.

pin.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VDD (see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.5 V to VDD+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-V tolerant I/O supply voltage range, V
5-V tolerant input voltage range, V

I-5V

–0.5 V to V

–0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD-5V

DD-5V

+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range at any output, VO –0.5 V to VDD+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (see Note 2) HBM:4 kV, MM:200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free air temperature, T
Storage temperature range, T

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.

2. HBM is Human body model, MM is machine model.

DISSIPATION RATING TABLE

PACKAGE

§

PAP

¶

PAP

#

PAP

‡

This is the inverse of the traditional junction-to-ambient thermal resistance (R

§

1 oz. trace and copper pad with solder

¶

1 oz. trace and copper pad without solder

#

Standard JEDEC High-K board. For more information, refer to TI application note

Thermally Enhanced Package,

TA ≤ 25°C

POWER RATING

3.98 W 39.8 mW/°C 2.19 W

1.76 W 17.6 mW/°C 0.97 W

1.62 W 16.2 mW/°C 0.89 W

TI literature number SLMA002.

DERATING FACTOR

ABOVE TA = 25°C

‡

POWER RATING

TA = 70°C

).

θJA

PowerPAD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

TSB41LV02A

Suppl

oltage, V

V

Case1 (bus holder): ISO = V

DD

Case1 (bus holder): ISO = V

DD

Maximum junction tem erature, T

J

Differential input voltage, V

mV

Common-mode input voltage, V

V

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

recommended operating conditions

pp

y v

High-level input voltage, V

Low-level input voltage, V

Output current, I

(see R

θJA

characteristics table)

Power-up reset time, t

Receive input jitter

Receive input skew

†

All typical values are at VDD = 3.3 V and TA = 25°C.

‡

For a node that does not source power; see Section 4.2.2.2 in IEEE P1394a.

DD

IH

IL

O

p

values listed in thermal

p

p

ID

pu

IC

Source power node 3 3.3 3.6
Non-source power node 2.7

=

V

= V

DD-5V

Case 2 (5 V tolerance): ISO
V

DD-5V

V

DD-5V

Case 2 (5 V tolerance): ISO
V

DD-5V

TPBIAS outputs –5.6 1.3 mA
R

θJA

R

θJA

R

θJA

Cable inputs, during data reception 118 260
Cable inputs, during arbitration 168 265
TPB cable inputs, Source power node 0.4706 2.515
TPB cable inputs, nonsource power node 0.4706 2.015
RESET input 2 ms
TPA, TPB cable inputs, S100 operation ±1.08
TPA, TPB cable inputs, S200 operation ±0.5
TPA, TPB cable inputs, S400 operation ±0.315
Between TPA and TPB cable inputs, S100 operation ±0.8
Between TPA and TPB cable inputs, S200 operation ±0.55
Between TPA and TPB cable inputs, S400 operation ±0.5

DD

= 5 V

= V

DD

= 5 V

= 25.15°C/W, TA = 70°C 92.4
= 56.78°C/W, TA = 70°C 120.7
= 61.63°C/W, TA = 70°C 125

= VDD,

=

= VDD,

,

,

MIN TYP

‡

LREQ, CTL0,
CTL1, D0–D7

C/LKON,
PC0, PC1,
PC2, ISO

RESET 0.6V
LREQ, CTL0,

CTL1, D0–D7
C/LKON,

PC0, PC1,
PC2, ISO

RESET 0.3V

, PD

, PD

2.6 V

0.7V

DD

DD

†

3 3.6

0.2V

MAX UNIT

V

V

1.2 V

DD

DD

V

V

°C

‡

ns

ns

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ZIDDifferential impedance

Drivers disabled

ZICCommon-mode impedance

Drivers disabled

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)
driver

PARAMETER TEST CONDITION MIN TYP MAX UNIT

V

Differential output voltage 56 Ω, See Figure 1 172 265 mV

OD

Driver difference current, TP A+, TPA–, TPB+, TPB– Drivers enabled, speed signaling off –1.05
Common-mode speed signaling current, TPB+, TPB– S200 speed signaling enabled –4.84
Common-mode speed signaling current, TPB+, TPB– S400 speed signaling enabled –12.4
Off state differential voltage Drivers disabled, See Figure 1 20 mV

†

Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.

‡

Limits defined as absolute limit of each of TPB+ and TPB– driver currents.

receiver

PARAMETER TEST CONDITION MIN TYP MAX UNIT

p

p

V

TH-R

V

TH-CB

V

TH+

V

TH–

V

TH–SP200

V

TH–SP400

Receiver input threshold voltage Drivers disabled –30 30 mV
Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1.0 V

Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV
Negative arbitration comparator threshold voltage Drivers disabled –168 –89 mV

Speed signal threshold

Speed signal threshold

TPBIAS–TPA common mode
voltage, drivers disabled

TPBIAS–TPA common mode
voltage, drivers disabled

†
‡
‡

10 14 kΩ

20 kΩ

49 131 mV

314 396 mV

1.05
–2.53
–8.10

†
‡
‡

4 pF

24 pF

mA
mA
mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

TSB41LV02A

V

OH

(CTL0, CTL1, D0–D7, CNA, C/LKON

V

g

V

V

V

V

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

(continued)

device

PARAMETER TEST CONDITION MIN TYP MAX UNIT

See Note 3 108

I

DD

I

DD(ULP)

V

TH

V

OL

I

BH+

I

BH–

I

I

I

OZ

I

IRST

I

SE-PU

+

IT

–

IT

V

O

†

Measured at cable power side of resistor.

‡

This parameter applicable only when ISO

NOTES: 3. Transmit max packet (all ports transmit, max size isochronous packet – 4096 bytes, sent at every isochronous interval, S400, data

Supply current

Supply current – ultra low power mode

Power status threshold, CPS input

High-level output voltage

–

SYSCLK outputs)

Low-level output voltage
(CTL0, CTL1, D0–D7, CNA, C/LKON,
SYSCLK outputs)

Positive peak bus holder current
(D0–D7, CTL0, CTL1, LREQ)

Negative peak bus holder current
(D0–D7, CTL0, CTL1, LREQ)

Input current (LREQ, LPS, PD, TESTM,
SM, PC0–PC2 inputs)

Off-state output current (CTL0, CTL1.
D0–D7, C/LKON I/Os)

Pullup current (RESET input) VI = 1.5 V or VI = 0 V –90 –20 µA
Pullup current (SE input) VI = 1.5 V or VI = 0 V –50 –5 µA
Positive input threshold voltage

(LREQ, CTL0, CTL1, D0–D7 inputs)
Positive input threshold voltage

(LPS inputs)
Negative input threshold voltage

(LREQ, CTL0, CTL1, D0–D7 inputs)
Negative input threshold voltage

(LPS inputs)
TPBIAS output voltage At rated IO current 1.665 2.015 V

value of CCCCCCCCh, VDD = 3.3 V, TA = 25°C)

4. Repeat typical packet (receive on one port, transmit DV packets on other port, sent at every isochronous interval, S100, VDD = 3.3
V, TA = 25°C)

5. idle (receive cycle start on one port, transmit cycle start on other port), VDD = 3.3 V, TA = 25°C

†

low.

See Note 4
See Note 5 70
VDD = 3.3 V, TA = 25°C,

Ports disabled, PD = 0 V ,
LPS = 0 V

400-kΩ resistor
VDD = 2.7 V, IOH = 4 mA 2.2
VDD = 3 V to 3.6 V, IOH = 4 mA 2.8

,

Annex J: IO = –9 mA, ISO
V

DD-5V

IOL = 4 mA 0.4
Annex J: IOL = 9 mA, ISO

V

DD-5V

ISO = 3.6 V, VDD = 3.6 V,
VI = 0 V to VDD,V

ISO = 3.6 V, VDD = 3.6 V,
VI = 0 V to VDD,V

ISO = 0 V, VDD = 3.6 V 5 µA

VO= VDD or 0 V ±5 µA

V

‡

‡

DD-5V

V

DD-5V

V

= VDD × 0.42

ref

V

DD-5V

V

DD-5V

V

= VDD × 0.42

ref

†

DD-5

DD-5

= 0 V,

= 0 V,

= V

= V

= VDD,VDD ≥ 3 V

= VDD,VDD ≥ 3 V

= VDD, ISO = 0 V
= VDD, ISO = 0 V,

= VDD, ISO = 0 V
= VDD, ISO = 0 V,

4.7 7.5 V

VDD–0.4

DD

DD

VDD/2+0.3 V VDD/2+0.9

VDD/2–0.9 V VDD/2–0.3

0.05 1 mA

–1 –0.05 mA

V

+0.2 V

ref

80

150 µA

V

ref

0.4

+1

mA

V

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended test board, chi soldered or greased to

°C/W

°C/W
°C/W

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

(continued)

thermal characteristics

PARAMETER TEST CONDITION

R

Junction-to-free-air thermal resistance

θJA

R

Junction-to-case-thermal resistance

θJC

R

Junction-to-free-air thermal resistance

θJA

R

Junction-to-case-thermal resistance

θJC

R

Junction-to-free-air thermal resistance

θJA

R

Junction-to-case-thermal resistance

θJC

†

Use of the thermally-enhanced PowerPAD PAP package is assumed in all three test conditions.

Board mounted, no air flow, high conductivity TI

thermal land with 1 oz. copper
Board mounted, no air flow, high conductivity TI

recommended test board with thermal land but no solder
or grease thermal connection to thermal land with 1 oz.
copper

Board mounted, no air flow , JEDEC test board with 1 oz.
copper

switching characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Jitter, transmit Between TPA and TPB ±0.15 ns
Skew, transmit Between TPA and TPB ±0.10 ns

t

TP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns

r

t

TP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns

f

t

Setup time, CTL0, CTL1, D1–D7, LREQ to SYSCLK 50% to 50%, See Figure 2 5 ns

su

t

Hold time, CTL0, CTL1, D1–D7, LREQ after SYSCLK 50% to 50%, See Figure 2 2 ns

h

t

Delay time, SYSCLK to CTL0, CTL1, D1–D7 50% to 50%, See Figure 3 2 11 ns

d

†

p

MIN TYP MAX UNIT

25.2

1.2

56.8

1.2

61.6

1.2

°

°

°

PARAMETER MEASUREMENT INFORMATION

TPAx+

TPBx+

56 Ω

TPAx–
TPBx–

Figure 1. Test Load Diagram

SYSCLK

t

su

Dx, CTLx, LREQ

Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

t

h

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13

TSB41LV02A

Address

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

PARAMETER MEASUREMENT INFORMATION

SYSCLK

t

d

Dx, CTLx

Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms

APPLICATION INFORMATION

internal register configuration

There are 16 accessible internal registers in the TSB41L V02A. The configuration of the registers at addresses
0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the
paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected.
The selected page is set in base register 7h.

The configuration of the base registers is shown in Table 1, and corresponding field descriptions are given in
Table 2. The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables)
is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

Table 1. Base Register Configuration

BIT POSITION

0 1 2 3 4 5 6 7

0000 Physical ID R CPS
0001 RHB IBR Gap_Count
0010 Extended (’b111) Rsvd Num_Ports (’b0010)

0011 PHY_Speed (’b010) Rsvd Delay (’b0000)
0100 LCtrl C Jitter (’b000) Pwr_Class
0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC

0110 Reserved

0111 Page_Select Rsvd Port_Select

14

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TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MA Y 2000

APPLICATION INFORMATION

Table 2. Base Register Field Descriptions

FIELD SIZE TYPE DESCRIPTION

Physical ID 6 R This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid

R 1 R Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during

CPS 1 R Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to

RHB 1 R/W Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit is

IBR 1 R/W Initiate bus reset. This bit instructs the PHY to initiate a long (166 µs) bus reset at the next opportunity. Any

Gap_Count 6 R/W Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times. The

Extended 3 R Extended register definition. For the TSB41LV02A, this field is ’b11 1, indicating that the extended register set is

Num_Ports 4 R Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41LV02A this

PHY_Speed 3 R PHY speed capability. For the TSB41LV02A PHY this field is ’b010, indicating S400 speed capability.
Delay 4 R PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY, expressed as

LCtrl 1 R/W Link-active status control. This bit is used to control active status of the LLC as indicated during self-ID. The

C 1 R/W Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager.

Jitter 3 R PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater data

Pwr_Class 3 R/W Node power class. This field indicates this node power consumption and source characteristics and is

RPIE 1 R/W Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set whenever

ISBR 1 R/W Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 µs) arbitrated bus

after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer.

tree-ID if this node becomes root.

serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable power voltage has
dropped below its threshold for ensured reliable operation.

reset to 0 by a hardware reset, and is unaffected by a bus reset.

receive or transmit operation in progress when this bit is set will complete before the bus reset is initiated. The
IBR bit is reset to 0 after a hardware reset or a bus reset.

gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet.
The gap count is reset to 3Fh by hardware reset or after two consecutive bus resets without an intervening write
to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet).

implemented.

field is 2.

144+(delay ×20) ns. For the TSB41LV02A this field is 0.

logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC is
considered active only if both the LPS input is active and the LCtrl bit is set.

The LCtrl bit provides a software controllable means to indicate the LLC active/status in lieu of using the LPS
input.

The LCtrl bit is set to 1 by a hardware reset and is unaffected by a bus reset.
NOTE: The state of the PHY -LLC interface is controlled solely by the LPS input, regardless of the state of the

LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received
packets and status information will continue to be presented on the interface, and any requests indicated on the
LREQ input will be processed, even if the LCtrl bit is cleared to 0.

This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to the state specified by the C/LKON
input terminal by a hardware reset and is unaffected by a bus reset.

delay, expressed as (Jitter+1) × 20 ns. For the TSB41LV02A, this field is 0.

replicated in the pwr field (bits 21–23) of the self-ID packet. This field is reset to the state specified by the
PC0–PC2 input terminals upon a hardware reset, and is unaffected by a bus reset. See Table 9.

resume operations begin on any port. This bit also enables the C/LKON output signal to be activated whenever
the LLC is inactive and any of the CTOI, CPSI, or STOI interrupt bits are set. This bit is reset to 0 by hardware
reset and is unaffected by bus reset.

reset at the next opportunity. This bit is reset to 0 by a bus reset.
NOTE: Legacy IEEE Std 1394-1995 compliant PHYs can not perform short bus resets. Therefore, initiation of a

short bus reset in a network that contains such a legacy device results in a long bus reset being performed.

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15