Texas Instruments TSB41LV01PAP, TSB41LV01GQER, TSB41LV01GQE Datasheet

TSB41LV01

IEEE 1394A ONE-PORT CABLE

TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus† and the P1394a Supplement

Fully Interoperable With FireWire and i.LINK Implementation of IEEE Std 1394

Fully Compliant With OpenHCI Requirements

Provides One P1394a Fully Compliant Cable Port at 100/200/400 Megabits per Second (Mbits/s)

Full P1394a Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-by Concatenation, Port Disable/Suspend/Resume

Extended Resume Signaling for Compatibility With Legacy DV Devices

Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power-Down During Suspend, Device Power-Down Pin, Link Interface Disable via LPS, and Inactive Port Powered-Down

Ultra Low-Power Sleep Mode

Node Power Class Information Signaling for System Power Management

Cable Power Presence Monitoring

Cable Port Monitors Line Conditions for Active Connection to Remote Node

Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz

Interface to Link Layer Controller Supports Low Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation

Interoperable With Link-Layer Controllers Using 3.3 V and 5 V Supplies

Interoperable With Other Physical Layers (Phys) Using 3.3 V and 5 V Supplies

Low Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at

49.152 MHz

Incoming Data Resynchronized to Local Clock

Logic Performs System Initialization and Arbitration Functions

Encode and Decode Functions Included for Data-Strobe Bit Level Encoding

Single 3.3 Volt Supply Operation

Meets Intel Mobile Power Guideline 2000

Low Cost High Performance 64 Pin TQFP (PAP) Thermally Enhanced Package

description

The TSB41L V01 provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based IEEE 1394 network. The cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41L V01 is designed to interface with a link layer controller (LLC), such as the TSB12L V22, TSB12L V21, TSB12L V23, TSB12L V31, TSB12LV41, TSB12LV42 or TSB12LV01A.

The TSB41LV01 requires only an external 24.576 MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

FireWire is a trademark of Apple Computer, Incorporated. i.LINK is a trademark of SONY. TI is a trademark of Texas Instruments Incorporated.

TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The TSB41L V01 supports an optional isolation barrier between itself and its LLC. When the /ISO input terminal is tied high, the LLC interface outputs behave normally . When the /ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the P1394a Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). T o operate with TI Bus holder isolation the /ISO terminal on the Phy must be high.

Data bits to be transmitted through the cable port are received from the LLC on two, four or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41LV01 in synchronization with the 49.152 MHz system clock. These bits are combined serially , encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).

During packet reception the TP A and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two, four or eight bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage.

The TSB41L V01 provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF.

The line drivers in the TSB41L V01 operate in a high-impedance current mode, and are designed to work with external 1 12-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the external line termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.3-kΩ ±0.5%. This may be accomplished by placing a 6.34-kΩ ±0.5% resistor in parallel with a 1-MΩ resistor.

When the power supply of the TSB41L V01 is 0 V while the twisted-pair cables are connected, the TSB41L V01 transmitter and receiver circuitry will present a high impedance to the cable and will not load the TPBIAS voltage at the other end of the cable.

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to V

, SE should be tied to ground through a 1-kΩ resistor,

while SM should be connected directly to ground.

TSB41LV01

IEEE 1394A ONE-PORT CABLE

TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are hardwired high or low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See T able 1 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM).

The TSB41LV01 supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low power conservation state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When the port of the TSB41LV01 is suspended all circuits except the bandgap reference generator and bias detection circuits are powered down, resulting in significant power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use of suspend/resume is recommended for new designs.

The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET

input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power-down, during reset, or when the port is disabled as commanded by the LLC.

The CNA (cable-not-active) output terminal is asserted high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended), and can be used along with LPS to determine when to powerdown the TSB41L V01. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET

terminal so as to force a reset of the TSB41LV01 internal logic.

The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see T able 4 and Table 5 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the Phy-LLC interface (the state of the Phy-LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).

The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41LV01 detects that LPS is inactive, it will place the Phy-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the Phy-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The Phy-LLC interface is also held in the disabled state during hardware reset. The TSB41L V01 will continue the necessary repeater functions required for normal network operation regardless of the state of the Phy-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the Phy will initialize the interface and return it to normal operation.

When the Phy-LLC interface in the low-power disabled state, the TSB41LV01 will automatically enter a low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41LV01 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the

ultra

low-power sleep

mode) is attained when the port is either disconnected, or disabled with the port’s interrupt enable bit cleared. The TSB41L V01 will exit the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41LV01 become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a non-disabled port, etc.). The SYSCLK output will become active (and the Phy-LLC interface will be initialized and become operative) within 7.3 ms after LPS is asserted high when the TSB41LV01 is in the low-power mode.

TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The Phy uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163 ns period. The Phy activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on Phy packet addressed to this node is received, or conditionally when a Phy interrupt occurs. The Phy deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The Phy also deasserts the C/LKON output when a bus-reset occurs unless a Phy interrupt condition exists which would otherwise cause C/LKON to be active.

TSB41LV01

IEEE 1394A ONE-PORT CABLE

TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

XI XO FILTER0 FILTER1

CPS

Link

Interface

I/O

LPS

ISO

CNA

SYSCLK

LREQ

CTL0 CTL1

D0 D1 D2 D3 D4 D5 D6 D7

Received

Data

Decoder/

Retimer

Arbitration

and

Control State

Machine

Logic

PC0 PC1 PC2

C/LKON

Bias

Voltage

and

Current

Generator

R0 R1

TPBIAS

Transmit

Data

Encoder

RESET

Crystal Oscillator,

PLL System,

and Clock Generator

TPA+ TPA–

TPB+ TPB–

Cable Port 0

TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pin assignments

17 18

AGND NC NC NC NC NC AV

R1 R0 AGND TPBIAS TPA+ TPA– TPB+ TPB– AGND

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

LREQ

SYSCLK

CNA CTL0 CTL1

D0 D1 D2 D3 D4 D5 D6 D7

LPS

21 22 23 24

AGND

FILTER0

63 62 61 60 5964 58

XOXIPLLGND

PLLGND

TESTM

C/KLON

PC0

PC1

PC2

ISO

CPS

56 55 5457

25 26 27 28 29

53 52

DGND

51 50 49

30 31 32

AGND

FILTER1

AGND

DGND

RESET

TSB41LV01

DVDDDV

AVDDAV

PLLV

DVDDDV

PAP PACKAGE

(TOP VIEW)

TSB41LV01

IEEE 1394A ONE-PORT CABLE

TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 32, 33, 39,

48, 49, 50

– Analog circuit ground pins. These pins should be tied together to the low impedance circuit board ground

plane.

30, 31, 42,

51, 52

– Analog circuit power pins. A combination of high frequency decoupling capacitors near each pin is

suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are also recommended. These supply pins are separated from PLL VDD and DVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board.

C/LKON 19 I/O Bus manager contender programming input and link-on output. On hardware reset, this pin is used to set

the default value of the contender status indicated during self-ID. Programming is done by tying the pin through a 10 kΩ resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. However, it is recommended that this pin should be programmed low, and that the contender status be set via the C register bit.

If the TSB41LV01 is used with an LLC that has a dedicated pin for monitoring LKON and also setting the contender status, then a 1-kΩ series resistor should be placed on the LKON line between the Phy and LLC to prevent bus contention.

Following hardware reset, this pin is the Link-On output, which is used to notify the LLC to power-up and become active. The Link-On output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The Link-On output is otherwise driven low , except during Hardware Reset when it is high impedance.

The Link-On output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and when: a) the Phy receives a link-on Phy packet addressed to this node, b) the PEI (port-event interrupt) register bit is 1, or c) any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI

(state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1.

Once activated, the Link-On output will continue active until the LLC becomes active (both LPS active and the LCtrl bit set). The Phy also deasserts the Link-On output when a bus-reset occurs unless the Link-On output would otherwise be active because one of the interrupt bits is set (i.e., the Link-On output is active due solely to the reception of a link-on Phy packet).

NOTE: If an interrupt condition exists which would otherwise cause the Link-On output to be activated if the

LLC were inactive, the Link-On output will be activated when the LLC subsequently becomes inactive. CNA 3 O Cable Not Active output. This pin is asserted high when the port is not receiving incoming bias voltage. CPS 24 I Cable Power Status input. This pin is normally connected to cable power through a 400 kΩ resistor. This

circuit drives an internal comparator that is used to detect the presence of cable power. CTL0

CTL1

4 5

I/O Control I/Os. These bidirectional signals control communication between the TSB41L V01 and the LLC. Bus

holders are built into these terminals. D0 – D7 6, 7, 8, 9,

10, 11, 12,

I/O Data I/Os. These are bidirectional data signals between the TSB41L V01 and the LLC. Bus holders are built

into these terminals.

DGND 17, 18, 63,64– Digital circuit ground pins. These pins should be tied together to the low impedance circuit board ground

plane. DV

25, 26, 61,62– Digital circuit power pins. A combination of high frequency decoupling capacitors near each pin are

suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are also

recommended. These supply pins are separated from PLL VDD and AVDD internal to the device to provide

noise isolation. They should be tied at a low impedance point on the circuit board. FILTER0

FILTER1

54 55

I/O PLL filter pins. These pins are connected to an external capacitance to form a lag-lead filter required for

stable operation of the internal frequency multiplier PLL running off of the crystal oscillator. A 0.1 µF ±10%

capacitor is the only external component required to complete this filter.

TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

ISO 23 I Link interface isolation control input. This pin controls the operation of output differentiation logic on the CTL

and D pins. If an optional Annex J type isolation barrier is implemented between the TSB41LV01 and LLC, the ISO

pin should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct

connection), or TI bus holder isolation is implemented, the ISO

pin should be tied high to disable the

differentiation logic. For additional information refer to TI application note

Serial Bus Galvanic Isolation

SLLA011.

LPS 15 I Link power status input. This pin is used to monitor the active/power status of the link layer controller and

to control the state of the Phy-LLC interface. This pin should be connected to either the VDD supplying the LLC through a 10 kΩ resistor, or to a pulsed output which is active when the LLC is powered. A pulsed signal should be used when an isolation barrier exists between the LLC and Phy. (See Figure 1).

The LPS input is considered inactive if it is sampled low by the Phy for more than 2.6 µs (128 SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating signal with a low time less than

2.6 µs). The LPS input must be high for at least 21 ns in order to be guaranteed to be observed as high by the Phy.

When the TSB41L V01 detects that LPS is inactive, it will place the Phy-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs (1280 SYSCLK cycles), the Phy-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The Phy-LLC interface is placed into the disabled state upon hardware reset.

The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0.

LREQ 1 I LLC Request input. The LLC uses this input to initiate a service request to the TSB41LV01. Bus holder is

built into this terminal.

PC0 PC1 PC2

20 21 22

I Power class programming inputs. On hardware reset, these inputs set the default value of the power class

indicated during self-ID. Programming is done by tying these pins high or low. Refer to Table 2 for encoding.

PD 14 I Power-down input. A high on this pin turns off all internal circuitry except the cable-active monitor circuits,

which controls the CNA output. Asserting the PD input high also activates an internal pull-down on the RESET

terminal so as to force a reset of the internal control logic. PLLGND 57, 58 – PLL circuit ground pins. These pins should be tied together to the low impedance circuit board ground plane. PLLV

56 – PLL circuit power pins. A combination of high frequency decoupling capacitors near each pin are suggested,

such as paralleled 0.1 µF and 0.001 µF . Lower frequency 10 µF filtering capacitors are also recommended. These supply pins are separated from DVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board.

R0 R1

40 41

– Current setting resistor pins. These pins are connected to an external resistance to set the internal operating

currents and cable driver output currents. A resistance of 6.30 kΩ ±0.5% is required to meet the IEEE Std 1394-1995 output voltage limits.

RESET 53 I Logic reset input. Asserting this pin low resets the internal logic. An internal pull-up resistor to VDD is provided

so only an external delay capacitor is required for proper power-up operation (see

power-up reset

in the

APPLICATION INFORMA TION section). The RESET

terminal also incorporates an internal pull-down which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver.

SE 28 I T est control input. This input is used in manufacturing test of the TSB41L V01. For normal use this pin should

be tied to GND through a 1-kΩ pulldown resistor.

SM 29 I T est control input. This input is used in manufacturing test of the TSB41L V01. For normal use this pin should

be tied to GND.

SYSCLK 2 O System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the LLC.

TSB41LV01

IEEE 1394A ONE-PORT CABLE

TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

TPA+ 37 I/O

Twisted-pair cable A dif ferential signal pins. Board traces from each pair of positive and negative differential

TPA– 36 I/O

signal ins should be ke t matched and as short as ossible to the external load resistors and to the cable

connector.

TPB+ 35 I/O

Twisted-pair cable B dif ferential signal pins. Board traces from each pair of positive and negative differential

TPB– 34 I/O

signal ins should be ke t matched and as short as ossible to the external load resistors and to the cable

connector.

TPBIAS 38 I/O T wisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper operation of the

twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. This pin must be decoupled with a 1.0 µF capacitor to ground.

TESTM 27 I T est control input. This input is used in manufacturing test of the TSB41LV01. For normal use this pin should

be tied to VDD.

XI XO

59 60

– Crystal oscillator inputs. These pins connect to a 24.576 MHz parallel resonant fundamental mode crystal.

The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see

crystal selection

in the APPLICATIONS INFORMATION section).

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, V

(see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.5 V to VDD+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-V-tolerant I/O supply voltage range, V

DD_5V

–0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-V-tolerant input voltage range, V

I-5V

–0.5 V to V

DD_5V

+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range at any output, VO –0.5 V to VDD+0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (see Note 2) HBM:2 kV, MM:200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free air temperature, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.

2. HBM is Human Body Model, MM is Machine Model.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 70°C

POWER RATING

PAP

3.98 W 39.8 mW/°C 2.19 W

PAP

1.76 W 17.6 mW/°C 0.97 W

PAP

1.62 W 16.2 mW/°C 0.89 W

‡

This is the inverse of the traditional junction-to-ambient thermal resistance (R

θJA

1 oz. trace and copper pad with solder.

1 oz. trace and copper pad without solder.

Standard JEDEC high-K board

For more information, refer to TI application note

PowerPAD Thermally Enhanced Package,

TI literature number SLMA002.

TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

PARAMETER MIN TYP

†

MAX UNIT

Source power node 3 3.3 3.6

Suppl

y v

oltage, V

Nonsource power node 2.7

‡

3 3.6

Case 1 (Bus holder): ISO=VDD, V

DD_5V=VDD

Case 2 (5V Tol): ISO

=VDD, V

DD_5V

=5V

LREQ, CTL0, CTL1, D0–D7

2.6

High level in ut voltage, V

C/LKON, PC0, PC1, PC2, ISO, PD 0.7×V

RESET 0.6×V

Case 1 (Bus holder): ISO=VDD, V

DD_5V=VDD

Case 2 (5V Tol): ISO

=VDD, V

DD_5V

=5V

LREQ, CTL0, CTL1, D0–D7

1.2

Low level in ut voltage, V

C/LKON, PC0, PC1, PC2, ISO, PD 0.2×V

RESET 0.3×V

Output current, I

TPBIAS outputs –5.6 1.3 mA

θJA

=25.2_C/W, TA=70°C 92.4

Maximum junction tem erature, T

(see R

θJA

values listed in thermal

θJA

=56.8_C/W, TA=70°C 120.7

°C

characteristics table)

θJA

=61.6_C/W, TA=70°C 125

Cable inputs, during data reception 118 260

Differential input voltage, V

Cable inputs, during arbitration 168 265

TPB cable inputs, source power node 0.4706 2.515

Common-mode input voltage, V

TPB cable inputs, non-source power node 0.4706 2.015

‡

Power-up reset time, t

RESET input 2 ms TPA, TPB cable inputs, S100 operation ±1.08

Receive input jitter

TPA, TPB cable inputs, S200 operation ±0.5

ns TPA, TPB cable inputs, S400 operation ±0.315 Between TPA and TPB cable inputs, S100 operation ±0.8

Receive input skew

Between TPA and TPB cable inputs, S200 operation ±0.55

ns Between TPA and TPB cable inputs, S400 operation ±0.5

†

All typical values are at VDD = 3.3 V and T

= 25°C.

‡

For a node that does not source power; see Section 4.2.2.2 in IEEE P1394A.

TSB41LV01

IEEE 1394A ONE-PORT CABLE

TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

driver

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Differential output voltage 56 Ω, See Figure 1 172 265 mV

DIFF

Driver difference current, TP A+, TPA–, TPB+, TPB–

Drivers enabled, Speed signaling off –1.05

†

1.05

†

SP200

Common mode speed signaling current, TPB+, TPB–

S200 speed signaling enabled –4.84

‡

–2.53‡mA

SP400

Common mode speed signaling current, TPB+, TPB–

S400 speed signaling enabled –12.4

‡

–8.10‡mA

OFF

Off state differential voltage Drivers disabled, See Figure 1 20 mV

†

Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.

‡

Limits defined as absolute limit of each of TPB+ and TPB– driver currents.

receiver

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

10 14 kΩ

ZIDDifferential impedance

4 pF

20 kΩ

ZICCommon mode impedance

24 pF

TH–R

Receiver input threshold voltage

Dri

vers disable

–30 30 mV

TH–CB

Cable bias detect threshold, TPB cable inputs 0.6 1 V

TH+

Positive arbitration comparator threshold voltage 89 168 mV

TH–

Negative arbitration comparator threshold voltage –168 –89 mV

TH–SP200

Speed signal threshold

TPBIAS–TPA common mode

49 131 mV

TH–SP400

Speed signal threshold

voltage, drivers disabled

314 396 mV

TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued)

device

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

See Note 3 69

Supply current

See Note 4

See Note 5 49

DD–ULP

Supply current – ultra-low power mode

VDD = 3.3 V, Port disabled,

TA = 25°C, PD=0V , LPS=0V

150 µA

Power status threshold, CPS input

†

400-kΩ resistor

†

4.7 7.5 V

High-level output voltage,

VDD=2.7 V , IOH = –4 mA 2.2

CTL0, CTL1, D0–D7, CNA

C/LKON, SYSCLK outputs

VDD=3 to 3.6 V ,

IOH = –4 mA 2.8

Low-level output voltage, CTL0, CTL1, D0–D7, CNA, C/LKON, SYSCLK outputs

IOL = 4 mA 0.4 V

OH–AJ

High-level Annex J output voltage, CTL0, CTL1, D0–D7, C/LKON, SYSCLK outputs

Annex J: IOH= –9 mA, ISO

= 0V, V

DD_5V

= V

VDD ≥ 3 V

VDD–0.4 V

OL–AJ

Low-level Annex J output voltage, CTL0, CTL1, D0–D7, CLKON

SYSCLK outputs

Annex J: IOL= 9 mA, ISO

= 0V, V

DD_5V

= VDD,

VDD ≥ 3 V

0.4 V

BH+

Positive peak bus holder current, D0–D7, CTL0–CTL1, LREQ

ISO = 3.6 V, VI = 0 V to VDD,

VDD = 3.6 V, V

DD_5V

= V

0.05 1 mA

BH–

Negative peak bus holder current, D0–D7, CTL0–CTL1, LREQ

ISO = 3.6 V, VI = 0 V to VDD,

VDD = 3.6 V, V

DD_5V

= V

–1 –0.05 mA

Input current, LREQ, LPS, PD, TESTM, SM, PC0–PC2 inputs

ISO=0 V , VDD = 3.6 V 5 µA

Off-state output current, CTL0, CTL1, D0–D7, C/LKON I/Os

VO= VDD or 0 V ±5 µA

IRST

Pullup current, RESET input VI=1.5 V or 0 V –90 –20 µA

SE–PU

Pullup current, SE input VI=1.5 V or 0 V –50 –5 µA Positive input threshold voltage,

LREQ, CTL0, CTL1, D0–D7 inputs

‡

DD_5V=VDD

, ISO= 0 V VDD/2+0.3 VDD/2+0.9

Positive input threshold voltage, LPS inputs

DD_5V=VDD

ref

= VDD×0.42

ISO= 0 V V

ref

Negative input threshold voltage, LREQ, CTL0, CTL1, D0–D7 inputs

‡

ISO= 0 V, V

DD_5V=VDD

VDD/2–0.9 VDD/2–0.3

–

Negative input threshold voltage, LPS inputs

ISO= 0 V, V

ref

= VDD×0.42

DD_5V=VDD

ref

+0.2

TPBIAS output voltage At rated IO current 1.665 2.015 V

†

This parameter applicable only when ISO

low.

‡

Measured at cable power side of resistor.

NOTES: 3. Transmit max packet (1 port transmitting max size isochronous packet – 4096 bytes, sent on every isochronous interval, s400, data

value of 0xCCCCCCCCh), V

= 3.3 V, TA = 25°C

4. Repeat typical packet (1 port receiving DV packets on every isochronous interval, S100), V

= 3.3 V, TA = 25°C

5. Idle (1 port transmitting cycle starts), V

= 3.3 V, TA = 25°C

TSB41LV01

IEEE 1394A ONE-PORT CABLE

TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued)

thermal characteristics

PARAMETER TEST CONDITIONS

†

MIN TYP MAX UNIT

RθJA Junction-to-free-air thermal resistance

Board mounted, no air flow, high conductivity TI

25.15

RθJC Junction-to-case-thermal resistance

recommended test board, chip soldered or greased to thermal land with 1 oz. copper

1.2

°C/W

RθJA Junction-to-free-air thermal resistance

Board mounted, no air flow, high conductivity TI recommended test board with thermal land, but no

56.78

RθJC Junction-to-case-thermal resistance

solder or grease thermal connection to thermal land with 1 oz. copper

1.2

°C/W

RθJA Junction-to-free-air thermal resistance

Board mounted, no air flow, high conductivity JEDEC

61.63 °C/W

RθJC Junction-to-free-air thermal resistance

,,g y

test board with 1 oz. copper

1.2 °C/W

†

Usage of thermally enhanced PowerPad PAP package is assumed in all three test conditions.

switching characteristics

driver

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Jitter, transmit Between TPA and TPB ±0.15 ns Skew, transmit Between TPA and TPB ±0.10 ns

TP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns

TP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns

Setup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK 50% to 50%, See Figure 2 5 ns

Hold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK 50% to 50%, See Figure 2 2 ns

Delay time, SYSCLK to CTL0, CTL1, D0–D7 50% to 50%, See Figure 3 2 11 ns

TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

TPAx+ TPBx+

TPAx–

TPBx–

56 Ω

Figure 1. Test Load Diagram

SYSCLK

Dx, CTLx, LREQ

Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

SYSCLK

Dx, CTLx

Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms

TSB41LV01

IEEE 1394A ONE-PORT CABLE

TRANSCEIVER/ARBITER

SLLS365 – AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

internal register configuration

There are 16 accessible internal registers in the TSB41LV01. The configuration of the registers at addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8 through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently selected. The selected page is set in base register 7.

The configuration of the base registers is shown in Table 1, and corresponding field descriptions given in Table 5. The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the register configuration tables below) is read as 0, but is subject to future usage. All registers in pages 2 through 6 are reserved.

Table 1. Base Register Configuration

BIT POSITION

ADDRESS

0 1 2 3 4 5 6 7

0000 Physical ID R CPS 0001 RHB IBR Gap_Count 0010 Extended (‘b111) Rsvd Num_Ports (‘b0010) 0011 PHY_Speed (‘b010)

Rsvd Delay (‘b0000)

0100 LCtrl C Jitter (‘b000) Pwr_Class 0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC 0110 Reserved 0111 Page_Select Rsvd Port_Select

Table 2. Base Register Field Descriptions

FIELD SIZE TYPE DESCRIPTION

Physical ID 6 Rd This field contains the physical address ID of this node determined during self-ID. The physical-ID is

invalid after a bus-reset until self-ID has completed as indicated by an unsolicited register-0 status transfer.

1 Rd Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus-reset, and is set to

1 during tree-ID if this node becomes root.

CPS 1 Rd Cable-power-status. This bit indicates the state of the CPS input pin. The CPS pin is normally tied to

serial bus cable power through a 400 kΩ resistor. A 0 in this bit indicates that the cable power voltage has dropped below its threshold for guaranteed reliable operation.

RHB 1 Rd/Wr Root-holdoff bit. This bit instructs the Phy to attempt to become root after the next bus-reset. The RHB

bit is reset to 0 by hardware reset and is unaffected by bus-reset.

IBR 1 Rd/Wr Initiate bus-reset. This bit instructs the Phy to initiate a long (166 µs) bus-reset at the next opportunity.

Any receive or transmit operation in progress when this bit is set will complete before the bus-reset is initiated. The IBR bit is reset to 0 by hardware reset or bus-reset.

Gap_Count 6 Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay

times. The gap count may be set either by a write to this register or by reception or transmission of a PHY_CONFIG packet. The gap count is set to 3Fh by hardware reset or after two consecutive bus-resets without an intervening write to the gap count register (either by a write to the Phy register or by a PHY_CONFIG packet).

Extended 3 Rd Extended register definition. For the TSB41L V01 this field is ‘b1 11, indicating that the extended register

set is implemented.

Num_Ports 4 Rd Number of ports. This field indicates the number of ports implemented in the Phy. For the TSB41LV01

this field is 1.

+ 34 hidden pages