TEXAS INSTRUMENTS TRF7960, TRF7961 Technical data

TRF7960 TRF7961

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SLOU186F–AUGUST 2006–REVISED AUGUST 2010

MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFID

ANALOG FRONT END AND DATA-FRAMING READER SYSTEM

Check for Samples: TRF7960, TRF7961

1 Introduction

1.1 Features

• Completely Integrated Protocol Handling • Parallel 8-Bit or Serial 4-Pin SPI Interface With

• Separate Internal High-PSRR Power Supplies

for Analog, Digital, and PA Sections Provide • Ultra-Small 32-Pin QFN Package Noise Isolation for Superior Read Range and (5 mm × 5 mm) Reliability

• Dual Receiver Inputs With AM and PM Demodulation to Minimize Communication Holes

• Receiver AM and PM RSSI

• Reader-to-Reader Anti-Collision

• High Integration Reduces Total BOM and Board

Area

– Single External 13.56-MHz Crystal Oscillator – MCU-Selectable Clock-Frequency Output of

RF, RF/2, or RF/4

– Adjustable 20-mA, High-PSRR LDO for

Powering External MCU

• Easy to Use With High Flexibility – Auto-Configured Default Modes for Each

Supported ISO Protocol

– 12 User-Programmable Registers – Selectable Receiver Gain and AGC – Programmable Output Power

(100 mW or 200 mW)

– Adjustable ASK Modulation Range

(8% to 30%)

– Built-In Receiver Band-Pass Filter With

User-Selectable Corner Frequencies

• Wide Operating Voltage Range of 2.7 V to 5.5 V

• Ultra-Low-Power Modes – Power Down < 1 μA – Standby 120 μA – Active (Rx only) 10 mA

MCU Using 12-Byte FIFO

• Available Tools – Reference Design/EVM With Development

Software

– Source Code Available for MSP430

1.2 APPLICATIONS

• Secure Access Control

• Product Authentication

– Printer Ink Cartridges – Blood Glucose Monitors

• Contactless Payment Systems

• Medical Systems

1.3 Description

The TRF7960/61 is an integrated analog front end and data-framing system for a 13.56-MHz RFID reader system. Built-in programming options make it suitable for a wide range of applications for proximity and vicinity RFID systems.

The reader is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Tag-it is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

TRF7960 TRF7961

SLOU186F–AUGUST 2006–REVISED AUGUST 2010

Table 1-1. PRODUCT SELECTION TABLE

PROTOCOLS

DEVICE ISO14443A/B

106 kbps 212 kbps 424 kbps 848 kbps

TRF7960 √ √ √ √ √ √ TRF7961 √ √

ISO15693

ISO18000-3

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1 Introduction .............................................. 1

1.1 Features .............................................. 1

1.2 APPLICATIONS ...................................... 1

1.3 Description ........................................... 1

2 Description (continued) ................................ 4

3 Physical Characteristics ............................... 5

3.1 Terminal Functions ................................... 5

3.2 PACKAGING/ORDERING INFORMATION .......... 6

4 ELECTRICAL SPECIFICATIONS ..................... 7

4.1 ABSOLUTE MAXIMUM RATINGS .................. 7

4.2 DISSIPATION RATINGS TABLE .................... 7

4.3 RECOMMENDED OPERATING CONDITIONS ..... 7

SLOU186F–AUGUST 2006–REVISED AUGUST 2010

4.4 ELECTRICAL CHARACTERISTICS ................. 8

4.5 Application Schematic for the TRF796x EVM

(Parallel Mode) ....................................... 9

4.6 Application Schematic for the TRF796x EVM (SPI

Mode) ............................................... 10

5 System Description ................................... 11

5.1 Power Supplies ..................................... 11

5.2 Receiver – Analog Section ......................... 17

5.3 Register Descriptions ............................... 24

5.4 Direct Commands From MCU to Reader ........... 34

5.5 Reader Communication Interface .................. 36

5.6 Parallel Interface Communication .................. 38

5.7 Serial Interface Communication .................... 40

5.8 External Power Amplifier Application ............... 44

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8(Parallel)

3(SPI)

Z – Matching

Circuit

Tx_Out

Rx_IN1

Rx_IN2

VDD_X

VDD_I/O

SYS_CLK

DATA_CLK

VDD

TRF796x MSP430

Xtal

13.56MHz

IRQ

XtalIn

XtalOut

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2 Description (continued)

A parallel or serial interface can be implemented for communication between the MCU and reader. Transmit and receive functions use internal encoders and decoders with a 12-byte FIFO register. For direct transmit or receive functions, the encoders / decoders can be bypassed so the MCU can process the data in real time. The transmitter has selectable output power levels of 100 mW (20 dBm) or 200 mW (23 dBm) into a 50-Ω load (5 -V supply) and is capable of ASK or OOK modulation. Integrated voltage regulators ensure power-supply noise rejection for the complete reader system.

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Figure 2-1. Typical Application

Data transmission comprises low-level encoding for ISO15693, modified Miller for ISO14443-A, high-bit-rate systems for ISO14443 and Tag-it coding systems. Included with the data encoding is automatic generation of SOF, EOF, CRC, and / or parity bits.

The receiver system enables AM and PM demodulation using a dual-input architecture. The receiver also includes an automatic gain control option and selectable gain. Also included is a selectable bandwidth to cover a broad range of input sub-carrier signal options. The received signal strength for AM and PM modulation is accessible via the RSSI register. The receiver output is a digitized sub-carrier signal among a selectable protocol and bit rate as outlined in Table 5-11. A selected decoder delivers bit stream and a data clock as outputs.

The receiver system also includes a framing system. This system performs CRC and / or parity check, removes the EOF and SOF settings, and organizes the data in bytes. Framed data is then accessible to the MCU via a 12-byte FIFO register and MCU interface. The framing supports ISO14443 and ISO15693 protocols.

The TRF7960/61 supports data communication levels from 1.8 V to 5.5 V for the MCU I/O interface, while also providing a data synchronization clock. An auxiliary 20-mA regulator (pin 32) is available for additional system circuits.

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3 Physical Characteristics

3.1 Terminal Functions

SLOU186F–AUGUST 2006–REVISED AUGUST 2010

Figure 3-1. TRF796x Pin Assignments (Top View)

Table 3-1. Terminal Functions

TERMINAL

NAME NO.

VDD_A 1 OUT Internal regulated supply (2.7 V – 3.4 V) for analog circuitry VIN 2 SUP External supply input to chip (2.7 V – 5.5 V) VDD_RF 3 OUT Internal regulated supply (2.7 V – 5 V), normally connected to VDD_PA (pin 4) VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3) TX_OUT 5 OUT RF output (selectable output power, 100 mW at 8 Ω or 200 mW at 4 Ω, with VDD = 5 V) VSS_RF 6 SUP Negative supply for PA; normally connected to circuit ground VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground RX_IN1 8 INP RX input, used for AM reception RX_IN2 9 INP RX input, used for PM reception VSS 10 SUP Chip substrate ground BAND_GAP 11 OUT Band-gap voltage (1.6 V); internal analog voltage reference; must be ac-bypassed to ground.

ASK/OOK 12 BID

IRQ 13 OUT Interrupt request MOD 14 INP Direct mode, external modulation input VSS_A 15 SUP Negative supply for internal analog circuits; normally connected to circuit ground

VDD_I/O 16 SUP I/O_0 17 BID I/O pin for parallel communication

I/O_1 18 BID I/O pin for parallel communication I/O_2 19 BID I/O pin for parallel communication I/O_3 20 BID I/O pin for parallel communication I/O_4 21 BID I/O pin for parallel communication

TYPE

(1)

Also can be configured to provide the received analog signal output (ANA_OUT) Direct mode, selection between ASK and OOK modulation (0 = ASK, 1 = OOK)

Supply for I/O communications (1.8 V – 5.5 V). Should be connected to VIN for 5-V communication, VDD_X for 3.3-V communication, or any other voltage from 1.8 V to 5.5 V.

DESCRIPTION

(1) SUP = Supply, INP = Input, BID = Bi-directional, OUT = Output

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Table 3-1. Terminal Functions (continued)

TERMINAL

NAME NO.

I/O_5 22 BID Strobe out clock for serial communication

I/O_6 23 BID MISO for serial communication (SPI)

I/O_7 24 BID

EN2 25 INP active during power down to support the MCU. Pin can also be used for pulse wake-up from

DATA_CLK 26 INP Clock input for MCU communication (parallel and serial)

SYS_CLK 27 OUT

EN 28 INP Chip enable input (If EN = 0, then chip is in power-down mode). VSS_D 29 SUP Negative supply for internal digital circuits; normally connected to circuit ground OSC_OUT 30 OUT Crystal oscillator output OSC_IN 31 INP Crystal oscillator input VDD_X 32 OUT Internally regulated supply (2.7 V – 3.4 V) for external circuitry (MCU) Thermal Pad Connected to circuit ground

TYPE

(1)

I/O pin for parallel communication

Data clock output in direct mode I/O pin for parallel communication

Serial bit data output in direct mode 1 or sub-carrier signal in direct mode 0 I/O pin for parallel communication. MOSI for serial communication (SPI) Pulse enable and selection of power down mode. If EN2 is connected to VIN, then VDD_X is

power-down mode.

Clock for MCU (3.39 / 6.78 / 13.56 MHz) at EN = 1 and EN2 = don't care If EN = 0 and EN2 = 1, then system clock is set to 60 kHz

DESCRIPTION

3.2 PACKAGING/ORDERING INFORMATION

PACKAGED DEVICES PACKAGE TYPE

TRF7960RHBT Tape and reel 250 TRF7960RHBR Tape and reel 3000 TRF7961RHBT Tape and reel 250 TRF7961RHBR Tape and reel 3000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package .

RHB-32

(1)

(2)

TRANSPORT MEDIA QUANTITY

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4 ELECTRICAL SPECIFICATIONS

4.1 ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VIN Supply voltage 6 V I

stg

(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may

(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

Output current 150 mA Continuous power dissipation See Dissipation Ratings Table Maximum junction temperature, any condition Maximum junction temperature, continuous operation, long-term reliability Storage temperature range –55 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C

HBM (human body model) 2 kV

ESDS rating CDM (charged device model) 500

MM (machine model) 200

cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified are not implied.

result in reduced reliability and/or lifetime of the device.

(2)

(1)

VALUE UNIT

140 °C

(2)

125 °C

4.2 DISSIPATION RATINGS TABLE

PACKAGE

RHB (32) 31 36.4 2.7 W 1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB. (2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.

Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability.

(°C/W) (°C/W)

(1)

TA≤ 25°C TA= 85°C

POWER RATING

(2)

4.3 RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

VIN Supply voltage 2.7 5 5.5 V T

Operating virtual junction temperature range –40 125 °C Operating ambient temperature range –40 25 110 °C

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4.4 ELECTRICAL CHARACTERISTICS

over temperature range VS= 5 V (unless otherwise noted)

TYP

–40°C 110°C

10 16 mA MAX

70 mA MAX

1.4 MIN

1.7 MAX

1.4 MIN

2.5 MAX

3.1 MIN

3.8 MAX 4 MIN

5.2 MAX

3.1 MIN

3.8 MAX

5 MIN

20 MAX

30 MIN

120 MAX

PD2

STBY

ON1

ON2

ON3

PARAMETER CONDITIONS

Supply current in power-down mode All systems disabled, including supply-voltage regulators 1 10 μA MAX Supply current in power-down mode 2 120 300 μA MAX

Supply current in standby mode 1.5 4 mA MAX

The reference voltage generator and the VDD_X remain active to support external circuitry.

Oscillator running, supply-voltage regulators in low-consumption mode

Supply current without antenna driver Oscillator, regulators, Rx and AGC, are all active. Tx is current off.

Supply current with antenna driver Oscillator, regulators, Rx, AGC, and Tx are all active. current Pout = 100 mW.

Supply current with antenna driver Oscillator, regulators, Rx, AGC, and Tx are all active. current Pout = 200 mW.

25°C TO UNIT

120 mA MAX

BG Band Gap voltage Internal analog reference voltage 1.6 V

POR

DD_A

DD_RF

DD_X

PSRR

RFOUT

RFIN

SENS

SET_PD

SET_STBY

REC

SYS_CLK

CLK

MAX

OUT

SYS_CLK

Power on reset voltage (POR) 2 V

Regulated supply for analog circuitry 3.5 V

Regulated supply for RF circuitry Regulator set for 5-V system with 250-mV difference. 4.6 V

Regulated supply for external circuitry 3.4 V

Rejection of external supply noise on the supply VDD_RF regulator

PA driver output resistance

The difference between the external supply and the regulated voltage is higher than 250 mV. Measured at 26 20 dB MIN 212 kHz.

Half-power mode 8 12 Ω MAX

Full- power mode 4 6 Ω MAX RX_IN1 and RX_IN2 input resistance 10 kΩ Maximum input voltage At RX_IN1 and RX_IN2 inputs 3.5 V

Input sensitivity

SUB-CARRIER

= 424 kHz 1.2 2.5 mV

= 848 kHz 1.2 3 mV Set up time after power down 10 20 ms MAX Set up time after standby mode 30 100 μs MAX Recovery time after modulation

(ISO14443)

Modulation signal: sine, 424-kHz, 10-mVpp 60 μs MAX

SYS_CLK frequency In PD2 mode EN = 0 and EN2 = 1 60 kHz Maximum CLK frequency 2 MHz TYP

Input logic low 0.2 0.2 VDD_I/O MAX Input logic high 0.8 VDD_I/O MIN Output resistance I/O_0 to I/O_7 low_io = H for VDD_I/O < 2.7 V 400 800 Ω MAX Output resistance SYS_CLK low_io = H for VDD_I/O< 2.7 V 200 400 Ω MAX

PP PP

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MIN/ MAX

MAX MAX MAX

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Test Port

Ext AntPort

TRF796x

RHB-32

234

9 10 11 12 13 14 15 16

29 28

ThermalPad

VDD_X

OSC_IN

OSC_OUT

VSS_D

SYS_CLK

DATA_CLK

EN2

VDD_I/O

VSS_A

MOD

IRQ

ASK/OOK

BANDGAP

VSS

RX2_PM

RX1_AM

VDD_A

VSS_RX

VSS_RF

TX_OUT

VDD_PA

VDD_RF

VIN

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

1000pF

1500pF

680pF

220pF

VSWR

Adj

Phase

Adj

330nH

150nH

Freq Adj

100pF

27pF

2.2uF

10nF

2.2uF

0Ohms

27pF

13.56MHz

VSWR

Adj

DVcc

D/AVss

XIN

1K

ReaderPwrEnable(GPIO)

InterruptCapableGPIO

MSP430

(Family)

4.7uF

10V

0.1uF

1K

CLK(GPIO)

PX.7

PX.6

PX.5

PX.4

PX.3

PX.2

PX.1

PX.0

Vcc

100

0.1uF

2.2uF

10nF

10K

10pF

Harmonic

Suppression

C2´

Xtal C

C1+C

Antenna

Circuit

Ant “Q”

Adj

R “cal”

open/short/load

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4.5 Application Schematic for the TRF796x EVM (Parallel Mode)

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TestPort

Ext AntPort

TRF796x

RHB-32

234

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

ThermalPad

VDD_X

OSC_IN

OSC_OUT

VSS_D

SYS_CL

DATA_CLK

EN2

VDD_I/O

VSS_A

MOD

IRQ

ASK/

BANDGAP

VSS

RX2_PM

RX1_AM

VDD_A

VSS_RX

VSS_RF

TX_OUT

VDD_PA

VDD_RF

VIN

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

1000pF

1500pF

680pF

220pF

VSWR

Adj

Phase

Adj

330nH

150nH

Freq

Adj

100pF

27pF

2.2

Fµ

10nF

2.2

Fµ

2.2

Fµ

2.2

Fµ

0Ohms

27pF

13.56MHz

VSWR

Adj

Vcc

DVcc

D/AVss

MISO

MOSI

XIN

10K

1K

CLK(GPIO)

SlaveSelect(GPIO)

ReaderPwrEnable(GPIO)

InterruptCapableGPIO

MSP430(Family)

4.7

10V

0.1

Fµ

1K

100

0.1

Fµ

2.2

Fµ

10nF

10pF

Harmonic

Suppression

10K

C2´

Xtal C

C1+C

Antenna

Circuit

Ant “Q”

Adj

R “cal”

open/short/load

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4.6 Application Schematic for the TRF796x EVM (SPI Mode)

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5 System Description

5.1 Power Supplies

The positive supply pin, VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. The positive supply input sources three internal regulators with output voltages V capacitors for supply noise filtering. These regulators provide enhanced PSRR for the RFID reader system.

The regulators are not independent and have common control bits for output voltage setting. The regulators can be configured to operate in either automatic or manual mode. The automatic regulator mode setting ensures an optimal compromise between regulator PSRR and highest possible supply voltage for RF output power. Whereas, the manual mode allows the user to manually configure the regulator settings.

DD_RF

DD_A

The regulator V be set for either 5-V or 3-V operation. When configured for the 5-V operation, the output voltage can be set from 4.3 V to 5 V in 100-mV steps. The current sourcing capability for 5-V operation is 150 mA maximum over the adjusted output voltage range.

When configured for 3-V operation, the output can be set from 2.7 V to 3.4 V, also in 100-mV steps. The current sourcing capability for 3-V operation is 100 mA maximum over the adjusted output voltage range.

Regulator V setting is divided in two ranges. When configured for 5-V operation, the output voltage is fixed at 3.5 V.

SLOU186F–AUGUST 2006–REVISED AUGUST 2010

, V

DD_RF

(pin 3) is used to source the RF output stage. The voltage regulator can

DD_RF

(pin 1) supplies voltage to analog circuits within the reader chip. The voltage

DD_A

and V

that use external bypass

DD_X

When configured for 3-V operation, the output can be set from 2.7 V to 3.4 V in 100-mV steps. Note that when configured, both V (their settings are not independent).

DD_X

Regulator V

(pin 32) can be used to source the digital I/O of the reader chip together with

DD_X

other external system components. When configured for 5-V operation, the output voltage is fixed at 3.4 V.

When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. The total current sourcing capability of the V adjusted output range. Note that when configured, both V configured together (their settings are not independent).

DD_PA

The V

pin (pin 4) is the positive supply pin for the RF output stage and is externally

DD_PA

connected to the regulator output V

5.1.1 Negative Supply Connections

The negative supply connections are all externally connected together (to GND). The substrate connection is VSS(pin 10), the analog negative supply is V the RF output stage negative supply is V V

SS_RX

(pin 7).

5.1.2 Digital I/O Interface

To allow compatible I/O signal levels, the TRF7960/61 has a separate supply input V an input voltage range of 1.8 V to 5.5 V. This pin is used to supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, V V

to ensure that the I/O signal levels of the MCU are the same as the internal logic levels of the

DD_X

reader.

and V

DD_A

(pin 3).

DD_RF

(pin 15), the logic negative supply is V

SS_A

(pin 6), and the negative supply for the RF receiver input is

SS_TX

regulators are configured together

DD_X

regulator is 20 mA maximum over the

DD_X

DD_A

and V

is connected directly to

DD_I/O

regulators are

DD_X

SS_D

DD_I/O

(pin 29),

(pin 16), with

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5.1.3 Supply Regulator Configuration

The supply regulators can be automatically or manually configured by the control bits. The available options are shown in Table 5-1 through Table 5-4. Table 5-1 shows a 5-V system and the manual-mode regulator settings. Table 5-2 shows manual mode for selection of a 3-V system. Table 5-3 and Table 5-4 show the automatic-mode gain settings for 5-V and 3-V systems.

The automatic mode is the default configuration. In automatic mode, the regulators are automatically set every time the system is activated by asserting the EN input HIGH. The internal regulators are also automatically reconfigured every time the automatic regulator selection bit is set HIGH (on the rising edge).

The user can re-run the automatic mode setting from a state in which the automatic setting bit is already high by changing the automatic setting bit from high to low to high. The regulator-configuration algorithm adjusts the regulator outputs 250 mV below the VINlevel, but not higher than 5 V for V V

, and 3.4 V for V

DD_A

maintaining an adequate PSRR (power supply rejection ratio). As an example, the user can improve the PSRR if there is a noisy supply voltage from V V

regulator as shown for automatic regulator settings in Table 5-3 and Table 5-4.

DD_X

Table 5-1. Supply-Regulator Setting – Manual – 5-V System

Byte Option Bits Setting in Control Register Action

Address

00 1 5-V system 0B 0 Manual regulator setting 0B 0 1 1 1 V 0B 0 1 1 0 V 0B 0 1 0 1 V 0B 0 1 0 0 V 0B 0 0 1 1 V 0B 0 0 1 0 V 0B 0 0 0 1 V 0B 0 0 0 0 V

B7 B6 B5 B4 B3 B2 B1 B0

. This ensures the highest possible supply voltage for the RF output stage while

DD_X

by increasing the target voltage difference across the

DD_X

= 5 V, V

DD_RF

= 4.9 V, V

DD_RF

= 4.8 V, V

DD_RF

= 4.7 V, V

DD_RF

= 4.6 V, V

DD_RF

= 4.5 V, V

DD_RF

= 4.4 V, V

DD_RF

= 4.3 V, V

DD_RF

= 3.5 V, and V

DD_A

DD_A DD_A DD_A DD_A DD_A DD_A DD_A

= 3.5 V, and V = 3.5 V, and V = 3.5 V, and V = 3.5 V, and V = 3.5 V, and V = 3.5 V, and V = 3.5 V, and V

DD_X

DD_X DD_X DD_X DD_X DD_X DD_X DD_X

DD_RF

= 3.4 V

= 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V

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, 3.5 V for

Table 5-2. Supply-Regulator Setting – Manual – 3-V System

Byte Option Bits Setting in Control Register Action

Address

00 0 3V system 0B 0 Manual regulator setting 0B 0 1 1 1 V 0B 0 1 1 0 V 0B 0 1 0 1 V 0B 0 1 0 0 V 0B 0 0 1 1 V 0B 0 0 1 0 V 0B 0 0 0 1 V 0B 0 0 0 0 V

B7 B6 B5 B4 B3 B2 B1 B0

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DD_RF DD_RF DD_RF

F = 3.1 V, V

DD_R DD_RF DD_RF DD_RF DD_RF

= 3.4 V, V = 3.3 V, V = 3.2 V, V

= 3.0 V, V = 2.9 V, V = 2.8 V, V = 2.7 V, V

DD_A DD_A DD_A

DD_A DD_A DD_A DD_A DD_A

, and V , and V , and V

, and V , and V , and V , and V , and V

DD_X DD_X DD_X

DD_X DD_X DD_X DD_X DD_X

= 3.4 V = 3.3 V = 3.2 V

= 3.1 V = 3.0 V = 2.9 V = 2.8 V = 2.7 V

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Table 5-3. Supply-Regulator Setting – Automatic – 5-V System

Byte Option Bits Setting in Control Register Action

Address

00 1 5-V system 0B 1 x 1 1 Automatic regulator setting ≉ 250-mV difference 0B 1 x 1 0 Automatic regulator setting ≉ 350-mV difference 0B 1 x 0 0 Automatic regulator setting ≉ 400-mV difference

(1) X are don't cares

B7 B6 B5 B4 B3 B2

(1)

B1 B0

Table 5-4. Supply-Regulator Setting – Automatic – 3-V System

Byte Option Bits Setting in Control Register Action

Address

00 0 3-V system 0B 1 x 1 1 Automatic regulator setting ≉ 250-mV difference 0B 1 x 1 0 Automatic regulator setting ≉ 350-mV difference 0B 1 x 0 0 Automatic regulator setting ≉ 400-mV difference

(1) X are don't cares

B7 B6 B5 B4 B3 B2

(1)

B1 B0

5.1.4 Power Modes

The chip has seven power states, which are controlled by two input pins (EN and EN2) and three bits in the chip status control register (00h).

The main reader enable input is EN (which has a threshold level of 1 V minimum). Any input signal level from 1.8 V to VINcan be used. When EN is set high, all of the reader regulators are enabled, together with the 13.56-MHz oscillator, while the SYS_CLK (output clock for external micro controller) is made available.

The auxiliary-enable input EN2 has two functions. A direct connection from EN2 to VINensures availability of the regulated supply (V

) and an auxiliary clock signal (60 kHz) on the SYS_CLK output (same for

DD_X

the case EN = 0). This mode is intended for systems in which the MCU controlling the reader is also being supplied by the reader supply regulator (V

) and the MCU clock is supplied by the SYS_CLK output of

DD_X

the reader. This allows the MCU supply and clock to be available during power-down. A second function of the EN2 input is to enable start-up of the reader system from complete power down

(EN = 0, EN2 = 0). In this case the EN input is being controlled by the MCU or other system device that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has a 1-V threshold level) starts the reader supply system and 13.56-MHz oscillator (identical to condition EN = 1). This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high by the MCU (or other system device), the reader stays active. If the EN input is not set high within 100 μs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete power-down mode. This option can be used to wake the reader system from complete power down by using a push-button switch or by sending a single pulse.

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After the reader EN line is high, the other power modes are selected by control bits. The power mode options and functions are listed in Table 5-5.

Table 5-5. Power Modes

Byte Option Bits Setting in Chip Status Control Register EN EN2 Functionality Current

Address

B7 B6 B5 B4 B3 B2 B1 B0

STBY RFON RF PWR REC ON

00 0 0 Complete power down <1 μA 00 0 1 VDD_X available 120 μA

SYS_CLK auxiliary frequency 60 kHz is ON

00 1 x x x 1 x All supply regulators active and in low power 1.5 mA

mode

13.56-MHz oscillator ON SYS_CLK clock available

00 0 0 x 0 1 x All supply regulators active 3.5 mA

13.56-MHz oscillator ON SYS_CLK clock available

00 0 0 x 1 1 x All supply regulators active 10 mA

13.56-MHz oscillator ON SYS_CLK clock available Receiver active

00 0 1 1 x 1 x All supply regulators active 70 mA

13.56-MHz oscillator ON (at 5 V) SYS_CLK clock available Receiver active Transmitter active – half-power mode

00 0 1 0 x 1 x All supply regulators active 120 mA

13.56-MHz oscillator running (at 5 V) SYS_CLK clock available Receiver active Transmitter active – full-power mode

During reader inactivity, the TRF7960/61 can be placed in power down-mode (EN = 0). The power down can be complete (EN = 0, EN2 = 0) with no function running, or partial (EN = 0, EN2 = 1) where the regulated supply (V

) and auxiliary clock 60 kHz (SYS_CLK) are available to the MCU or other system

DD_X

device. When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1), the supply regulators are

activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the selected frequency derived from the crystal oscillator. At this point, the reader is ready to communicate and perform the required tasks. The control system (MCU) can then write appropriate bits to the chip status control register (address 00) and select the operation mode.

The STANDBY mode (bit 7 = 1 of register 00) is the active mode with the lowest current consumption. The reader is capable of recovering from this mode to full operation in 100 μs.

The active mode with RF section disabled (bit 5 = 0 and bit 1 = 0 of register 00) is the next active mode with low power consumption. The reader is capable of recovering from this mode to full operation in 25 μs.

The active mode with only the RF receiver section active (bit 1 = 1 of register 00) can be used to measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollision is implemented.

The active mode with the entire RF section active (bit 5 = 1 of register 00) is the normal mode used for transmit and receive operations.

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C001

C002

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5.1.5 Timing Diagrams

SLOU186F–AUGUST 2006–REVISED AUGUST 2010

CHIP POWER UP TO CLOCK START

Figure 5-1. Power Up [VIN(Blue) to Crystal Start (Red)]

CHIP ENABLE TO CLOCK START

Figure 5-2. EN2 Low and EN High (Blue) to Start of System Clock (Red)

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CHIP ENABLE TO CLOCK START

Figure 5-3. EN2 High and EN Low (Blue) to Start of System Clock (Red)

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