Texas Instruments TPS77127DGKR, TPS77127DGK, TPS77118DGKR, TPS77118DGK, TPS77101DGKR Datasheet

TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT

TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000

D

Open Drain Power-On Reset With 220-ms
Delay (TPS771xx)

D

Open Drain Power-Good (PG) Status
Output (TPS772xx)

D

150-mA Low-Dropout Voltage Regulator

D

Available in 1.8-V, 2.7-V, 2.8-V, 3.3-V, Fixed
Output and Adjustable Versions

D

Dropout Voltage Typically 115 mV
at 150 mA (TPS77133, TPS77233)

D

Ultra Low 92-µA Quiescent Current (Typ)

D

8-Pin MSOP (DGK) Package

D

Low Noise (55 µV

) Without External

rms

Filter (Bypass) Capacitor (TPS77118,
TPS77218)

D

2% Tolerance Over Specified Conditions
for Fixed-Output Versions

D

Fast Transient Response

D

Thermal Shutdown Protection

description

The TPS771xx and TPS772xx are low dropout
regulators with integrated power-on reset and
power good (PG) function respectively. These
devices are capable of supplying 150 mA of output
current with a dropout of 115 mV (TPS77133,
TPS77233). Quiescent current is 92 µA at full load
dropping down to 1 µA when device is disabled.
These devices are optimized to be stable with a
wide range of output capacitors including low ESR
ceramic (10 µF) or low capacitance (1 µF)
tantalum capacitors. These devices have ex­tremely low noise output performance (55 µV
without using any added filter capacitors.
TPS771xx and TPS772xx are designed to have
fast transient response for larger load current
changes.

rms

TPS771xx

DGK PACKAGE

(TOP VIEW)

FB/SENSE

RESET

GND

FB/SENSE

GND

300

250

200

150

– Dropout Voltage – mV

100

DO

V

50

1
2

EN

PG
EN

3
4

TPS772xx

DGK PACKAGE

(TOP VIEW)

1
2
3
4

TPS77x33

DROPOUT VOLTAGE

vs

JUNCTION TEMPERATURE

8
7
6
5

8
7
6
5

IO = 150 mA

IO = 10 mA

OUT
OUT
IN
IN

OUT
OUT
IN
IN

IO = 0 A

)

0

–40 0 40 80

TJ – Junction Temperature – °C

120 140

The TPS771xx or TPS772xx is offered in 1.8-V, 2.7-V, 2.8-V and 3.3-V fixed-voltage versions and in an
adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line,
load, and temperature ranges. The TPS771xx and TPS772xx families are available in 8-pin MSOP (DGK)
packages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT

J

–40 C to 125 C

TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000

description (continued)

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 115 mV
at an output current of 150 mA for 3.3 volt option) and is directly proportional to the output current. Additionally ,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent
of output loading (typically 92 µA over the full range of output current, 0 mA to 150 mA). These two key
specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when the EN

pin is connected to a low-level input voltage. This LDO family also features
a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent
current to less than 1 µA at TJ = 25°C.

The TPS771xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS)
or reset output voltage. The RESET output of the TPS771xx initiates a reset in DSP, microcomputer or
microprocessor systems at power-up and in the event of an undervoltage condition. An internal comparator in
the TPS771xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated
output voltage. When OUT

reaches 95% of its regulated voltage, RESET will go to a high-impedance state after

a 220 ms delay . RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition)
of its regulated voltage.

For the TPS772xx, the power good terminal (PG) is an active high output, which can be used to implement a
power-on reset or a low-battery indicator. An internal comparator in the TPS772xx monitors the output voltage
of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82%
of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT
is above 82% of its regulated voltage.

AVAILABLE OPTIONS

OUTPUT

VOLTAGE

T

–

°

The TPS77101 and TPS77201 are programmable using an external resistor divider
(see application information). The DGK package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS77101DGKR).

°

(V)

TYP

3.3 TPS77133DGK TPS77233DGK

2.8 TPS77128DGK TPS77228DGK

2.7 TPS77127DGK TPS77227DGK

1.8 TPS77118DGK TPS77218DGK

Adjustable

1.5 V to 5.5 V

PACKAGED DEVICES

MSOP

(DGK)

TPS77101DGK TPS77201DGK

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT

TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000

V

I

0.1 µF

5
6

3

Figure 1. Typical Application Configuration (For Fixed Output Options)

functional block diagram—adjustable version

IN

EN

_
+

IN

IN

EN

GND

4

OUT
OUT

SENSE

PG or

RESET

7
8
1

2

V

PG or RESET

+

10 µF

O

PG or RESET

OUT

V

= 1.1834 V

ref

GND

+
_

220 ms Delay

(for TPS771xx Option)

R1

FB/SENSE

R2

External to the device

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT

I/O

DESCRIPTION

I/O

DESCRIPTION

TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000

functional block diagram—fixed-voltage version

IN

EN

PG or RESET

_

V

= 1.1834 V

ref

+

+
_

GND

220 ms Delay

(for TPS771xx Option)

R1

R2

OUT

SENSE

Terminal Functions (TPS771xx)

TERMINAL

NAME NO.

FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
RESET 2 O Reset output
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 I Input voltage
OUT 7, 8 O Regulated output voltage

Terminal Functions (TPS772xx)

TERMINAL

NAME NO.

FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
PG 2 O Power good
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 I Input voltage
OUT 7, 8 O Regulated output voltage

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT

TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

TPS771xx RESET timing diagram

V

I

†

V

res

SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000

V

res

t

V

O

Threshold

Voltage

RESET
Output

Output

Undefined

†

V

is the minimum input voltage for a valid RESET . The symbol V

res

for semiconductor symbology.

‡

VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) V
to V

is the hysteresis voltage.

IT+

V

IT+

‡

220 ms
Delay

V

IT+

‡

V

IT–

res

‡

‡

V

IT–

t

220 ms
Delay

Output
Undefined

t

is not currently listed within EIA or JEDEC standards

IT–

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT
TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT
150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000

TPS772xx PG timing diagram

V

I

†

V

res

V

res

t

V

O

Threshold

Voltage

PG

Output

Output

Undefined

†

V

is the minimum input voltage for a valid PG. The symbol V

res

semiconductor symbology .

‡

VIT –Trip voltage is typically 18% lower than the output voltage (82%VO) V
to V

is the hysteresis voltage.

IT+

‡

V

IT+

‡

V

IT–

V

IT+

is not currently listed within EIA or JEDEC standards for

res

‡

‡

V

IT–

t

Output
Undefined

t

IT–

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS77101, TPS77118, TPS77127, TPS77128, TPS77133 WITH RESET OUTPUT

TPS77201, TPS77218, TPS77227, TPS77228, TPS77233 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH INTEGRATED RESET OR PG

SLVS225A – FEBRUARY 2000 – REVISED MARCH 2000

absolute maximum ratings over operating junction temperature range

(unless otherwise noted)

Input voltage range‡, VI –0.3 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at EN –0.3 V to 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum RESET voltage (TPS771xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum PG voltage (TPS772xx) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See dissipation rating tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage, V

Operating virtual junction temperature range, TJ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

ESD rating, HBM 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

All voltage values are with respect to network terminal ground.

PACKAGE

DGK

(OUT, FB) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

DISSIPATION RATING TABLE – FREE-AIR TEMPERATURES

AIR FLOW

(CFM)

0 266.2 3.84 376 mW 3.76 mW/°C 207 mW 150 mW
150 255.2 3.92 392 mW 3.92 mW/°C 216 mW 157 mW
250 242.8 4.21 412 mW 4.12 mW/°C 227 mW 165 mW

θ

JA

(°C/W)

θ

JC

(°C/W)

TA < 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

Ĕ

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

recommended operating conditions

MIN MAX UNIT

Input voltage, V
Output voltage range, V
Output current, IO (see Note 1) 0 150 mA
Operating virtual junction temperature, TJ (see Note 1) –40 125 °C

§

To calculate the minimum input voltage for your maximum output current, use the following equation: V

NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the

§

I

O

I(min)

device operate under conditions beyond those specified in this table for extended periods of time.

= V

2.7 10 V

1.5 5.5 V

+ V

O(max)

DO(max load)

.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7