TEXAS INSTRUMENTS TPS65120, TPS65121, TPS65123, TPS65124 Technical data

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SWN

TPS65123

D1

L1

10

C1

2.2

V

IN

2.7 V to 5.5 V

V

GL

down to −18 V/2 mA

C3

100 nFR4

R3

SWP

FBL

VMAIN

FBM

C5

220 nF

R6

R5

V

MAIN

3.0 V to 5.3 V/25 mA

C4

1

BOOT

VGH

C2

100 nF

V

GH

up to 20 V/2 mA

PGND

AGND

FBH

RUN
EN

VIN

A

A

GATE

R2

R1

Fµ

µFµH

0.1

0.5

0.9

4.0

8.0

12.0

16.0

20.0

24.0

2.3

2.4

2.6

2.8

3.2

4.0

4.7

5.2

5.5

0

10

20

30

40

50

60

70

80

90

100

Core Converter Efficiency − %

VIN − Input Voltage − V

I

BOOT

− Load Current − mA

TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

SINGLE-INDUCTOR QUADRUPLE-OUTPUT

TFT LCD POWER SUPPLY

FEATURES

• Main Output, V

– Adjustable Voltage, 3.0 V to 5.6 V/25 mA
– Post-Regulated for Low Ripple (5mV
– ±0.8% Typical Accuracy

MAIN

)

PP

• Automatic or Programmable Power

Sequencing

• Complete 1 mm Component Profile Solution

• 2.5 V to 5.5 V Input Voltage Range

• Output Short Circuit Protected

– Efficiency up to 83% • 16-Pin QFN Package (3 × 3 × 0,9 mm)

• Positive Output, V

– Adjustable Voltage up to 20 V/2 mA
– ±3% Typical Accuracy

• Negative Output, V

– Adjustable Voltage down to -18 V/2 mA
– ±3% Typical Accuracy

• Auxiliary 1.8 V/3.3 V Linear Regulator

GH

APPLICATIONS

• Small Form Factor a-Si and LTPS TFT LCD

• Cell Phones, Smart Phones

GL

• PDAs, Pocket PCs

• Portable DVD

• Digital-Still Cameras, Camcorders

• Handheld Instruments

• Portable GPS

• Car Navigation Systems

DESCRIPTION

The TPS6512x DC-DC converter supplies all three voltages required by amorphous-silicon (a-Si) and
low-temperature poly-silicon (LTPS) TFT-LCD displays. The compact layout of the TPS6512x uses a single
inductor to generate independently-regulated positive and negative outputs. A free-running variable peak current
PWM control scheme time-multiplexes the inductor between outputs. This control architecture operates at a
pseudo-fixed-frequency to provide fast response to line and load transients while maintaining a relatively
constant switching frequency and high efficiency over a wide range of input and output voltages. Due to the high
switching frequency capability of the device, inexpensive and ultra-thin 8.2 or 10 µH inductors can be used.

The main output, V
auxiliary outputs generate a boosted output voltage, V

-18 V for the LCD gate drive. The device has internal current limiting for high reliability under fault conditions.
Additionally, the device offers a fixed output linear regulator for the LCD logic circuitry.

, is post-regulated to provide a low-ripple source drive voltage for the LCD display. The

MAIN

, up to 20 V, and a negative output voltage, V

GH

GL

, down to

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Figure 1. Typical Application Figure 2. Core Converter Efficiency

Copyright © 2004–2005, Texas Instruments Incorporated

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TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

A

-40 to 85°C

(1) The xyz package is available in tape and reel. Add R suffix (xyzR) to order quantities of TBD parts. Add T suffix (xyzT) to order

quantities of 250 parts.

INTEGRATED POWER SEQUENCING PACKAGE PART NUMBER

LINEAR REGULATOR MARKING

Fixed 3.3V output voltage Automatic Power-Up/Down 3 × 3 QFN-16 TPS65120RGT BKA
Fixed 1.8V output voltage Automatic Power-Up/Down 3 × 3 QFN-16 TPS65121RGT BKB

NO Automatic Power-Up/Down 3 × 3 QFN-16 TPS65123RGT BKC
NO Programmable 3 × 3 QFN-16 TPS65124RGT BKD

Power-Up/Down

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VIN -0.3 V to +6 V

Input voltage

Voltage

Input voltage at GATE, EN, RUN
Power dissipation Internally limited
Operating temperature range -40°C to 85°C
Maximum operating junction temperature, TJ(max) 135°C
Storage temperature range 65°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(2)

(2)

SWN VIN- 24 V to VIN+0.3 V
SWP - 0.3 V to +23 V
VGH - 0.3 V to +21 V
VMAIN, LDOIN, LDOOUT, ENVGL, ENVGH - 0.3 V to +6 V
BOOT - 0.3 V to +6.2 V

(2)

(1)

(1)

UNIT

-0.3 V to VIN+ 0.3 V

PACKAGE

DISSIPATION RATINGS

PACKAGE R

RGT 68°C/W 15mW/°C

(1) Maximum power dissipation is a function of TJ(max), θJAand TA. The maximum allowable power

dissipation at any allowable ambient temperature is PD= [TJ(max)-T

2

θ JA

DERATING FACTOR ABOVE TA= 25°C

(1)

]/ θJA.

A

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TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

ELECTRICAL CHARACTERISTICS

V

= 3.6 V, EN = RUN = VIN, L = 10 µH, TA= -40°C to 85°C, typical values are at TA= 25°C (unless otherwise noted)

IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CONVERTER STAGE

R

≥ 330 Ω at V

L_MAIN

R

≥ 12 k Ω at V

Input voltage for full load operation 2.7 5.5 V

V

IN

Minimum input voltage for start-up 2.5 V

f Switching frequency 4.0 MHz

P

GH

P

GL

Output power on V

Output power on V

GH

GL

L_VGH

R

≥ 12 k Ω at V

L_VGL

V

= GND, TA= -40°C to 85°C

LDOIN

R

≥ 660 Ω at V

L_MAIN

R

≥ 24 k Ω at V

L_VGH

R

≥ 24 k Ω at V

L_VGL

V

= GND, TA= -20°C to 85°C

LDOIN

R

= 250 Ω at V

L_MAIN

V

= ENVGH = ENVGL = GND

LDOIN

VIN≥ 2.7 V 35
VIN≥ 2.5 V 15
VIN≥ 2.7 V 35
VIN≥ 2.5 V 15
VIN≥ 2.5 V 60

P

TOT

Total output power on
V

+ V

BOOT

+ V

GH

GL

VIN≥ 2.7 V 120
VIN≥ 3 V 150
VIN≥ 4.5 V 250

η Power efficiency V

I

LIM

I

START-UP

P-MOS1 current limit 2.7 V ≤ VIN≤ 5.5 V 150 200 mA
P-MOS1 start-up current limit 2.7 V ≤ VIN≤ 5.5 V 65 mA

P-MOS1 switch on-resistance Ω

r

DS(ON)

N-MOS1 switch on-resistance Ω

P-MOS1 leakage current 0.01
N-MOS1 leakage current 0.01

N-MOS2 + P-MOS2 forward voltage drop 400 600 mV

N-MOS3 + D1 forward voltage drop 900 1100 mV

MAIN

= 15 V, V

GH

IGH= IGL= 100 µA, V

VIN= V
VIN= V
V

= V

BOOT

V

= V

BOOT

V

= 6 V, TA= 25°C µA

DS

V

= V

GS

I

= ID= 50 mA

BOOT

V

= V

GS

IGH= ID= 50 mA

BOOT

GL

= 3.6 V 2.5 4.3

GS

= 2.5 V 3.8 6.9

GS

= 3.7 V 1.9 3.5

GS

= 5 V 1.4 2.3

GS

= 5.5 V, V

BOOT

= 5.5 V, V

BOOT

V

= 5.0 V, I

CONVERTER SUPPLY CURRENT

Quiescent current into VIN I
Quiescent current into BOOT 30 60

I

Q

Quiescent current into VGH 0.1 1

I

SD

Shutdown current TA= 25°C 0.1 1 µA

= IGH= IGL= 0 mA, 140 170

MAIN

V

= +15 V, V

GH

V

MAIN

V

FBL

V

LDOIN

TA= 25°C

= 5 V, V

= -0.2 V, V

GL

FBH

= GND, EN = RUN = VIN,

BOOT

= 5 V,

MAIN

= 12 V,

GH

= -12 V,

GL

= 5 V,

MAIN

= 12 V,

GH

= -12 V,

GL

= 5 V

MAIN

= 20 mA,

= -10 V, 83%

= GND

LDOIN

= 2 V,

SWP

= 2 V,

SWP

= -15 V,

= V

= +1.5 V,

FBM

= 5.25 V,

mW

mW

mW

µA

3

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TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

ELECTRICAL CHARACTERISTICS (continued)

V

= 3.6 V, EN = RUN = VIN, L = 10 µH, TA= -40°C to 85°C, typical values are at TA= 25°C (unless otherwise noted)

IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

MAIN OUTPUT

V

MAIN

I

MAIN

V

FBM

I

FBM

I

SC_MAIN

R

DIS_VMAIN

VGH OUTPUT

V

GH

I

GH

V

FBH

I

FBH

R

DIS_VGH

VGL OUTPUT

V

GL

I

GL

V

FBL

I

FBL

Main output voltage range 3.0 5.6 V

V

≤ 5.3 V 25

Maximum main output current mA

Feedback regulation voltage

Feedback input bias current V
Load regulation I
Minimum dropout voltage I
Main output voltage ripple I
Short-circuit current limit V

MAIN

V

≥ 5.3 V 7.5

MAIN

2.7 V ≤ VIN≤ 5.5 V, 100 µA ≤ I
TA= -20°C to 50°C

≤ 25 mA,

MAIN

2.7 V ≤ VIN≤ 5.5 V,
0 mA ≤ I

FBM
MAIN
MAIN
MAIN

BOOT

≤ 25 mA

MAIN

= V

REF

= 0 to 25 mA, V

= 5 V 0.006 %/mA

MAIN

= 10 mA 130 mV
= 10 mA 5 mV

= 5.5 V 50 mA

Discharge resistor for power-down se­quence

V

output voltage range VIN+ 0.5 20 V

GH

Maximum DC output current 6 mA
V

precharge resistor 1 k Ω

GH

Feedback regulation voltage 2.7 V ≤ VIN≤ 5.5 V, 0 mA ≤ IGH≤ 2 mA 1.177 1.213 1.249 V
Feedback input bias current V
Load regulation IGH= 0 to 2 mA, V

= 0 V 0.01 0.1 µA

FBH

= 15 V -0.11 %/mA

GH

Line regulation VIN= 2.7 V to 5.5 V, IGH= 100 µA 0.01 %/V
V

output voltage ripple 20 mV

GH

200 µA load, V
C

= 220 nF, C

OUT

= 15 V,

GH

= 10 pF

FF

Discharge resistor for power-down se­quence

V

Output voltage range -18 -2.5 V

GL

Maximum DC output current 6 mA
Feedback regulation voltage 2.7 V ≤ VIN≤ 5.5 V, 0 mA ≤ IGL≤ 2 mA -0.036 0 0.036 V
Feedback input bias current V
Load regulation IGL= 0 to 2 mA, V

= 0 V 0.01 0.1 µA

FBL

= -15 V 0.13 %/mA

GL

Line regulation VIN= 2.7 V to 5.5 V, IGL= 100 µA 0.1 %/V
V

output voltage ripple 20 mV

GL

200 µA load, V
C

= 220 nF

OUT

= -15 V,

GL

1.203 1.213 1.223 V

1.195 1.213 1.231 V

0.01 0.1 µA

P-P

10 k Ω

10 k Ω

4

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TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

ELECTRICAL CHARACTERISTICS (continued)

V

= 3.6 V, EN = RUN = VIN, L = 10 µH, TA= -40°C to 85°C, typical values are at TA= 25°C (unless otherwise noted)

IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LINEAR REGULATOR STAGE - AUXILIARY OUTPUT

V

LDOIN

V

LDOOUT

I

LDOOUT

I

SC_LDO

I

Q_LDO

I

SD_LDO

GATE DRIVER

V

IH

V

IL

UNDERVOLTAGE LOCKOUT

V

UVLO

LOGIC SIGNALS EN, RUN, ENVGL, ENVGH

V

IH

V

IL

I

LKG

Input voltage range 2.5 5.8 V
Output voltage range 1.8 V
Maximum output current 20 mA

Short-circuit current limit V
Minimum dropout voltage I

Total accuracy ±3%
Load regulation I
Line regulation 0.013 %/V

Linear regulator quiescent current 11 20 µA

LDOOUT

2.5 V ≤ V
0 mA ≤ I

LDOOUT

V
to 5.5 V, I

V
TA= 25°C

= 0 V 50 mA

LDOOUT

= 10 mA 400 mV

≤ 5.5 V,

LDOIN

≤ 20 mA

LDOOUT

= 0 to 20 mA 0.006 %/mA

= V

LDOIN

LDOOUT

= V

LDOIN

LDOOUT

LDOOUT

+ 0.5 V (min 2.5 V)

= 20 mA

+ 0.4 V (min 2.5 V),

Linear regulator shutdown current GATE = VIN 0.2 1 µA

Gate output pull-down resistance V

< 500 mV 100 k Ω

GATE

Gate output pull-up resistance 100 k Ω
High level input voltage 1.4 V
Low level input voltage 0.4 V

Undervoltage lockout threshold VINfalling 2.15 2.3 V

High level input voltage 1.4 V
Low level input voltage 0.4 V

Logic input leakage current µA

ENVGL, ENVGH = VINor GND (TPS65124) 0.01 0.1
EN, RUN = V

IN

EN, RUN pin pull-down resistance EN, RUN ≤ 0.4 v 100 k Ω

0.01 0.1

V

LDOIN

-0.5

5

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1
2

3
4

12
11

10

9

5 6 7 8

131516

EN

RUN

ENVGL

ENVGH

FBL

FBM

AGND

VMAIN

PGND
BOOT
VGH
FBH

GATE

VIN

SWN

SWP

1
2
3
4

12
11

10

9

5 6

7

8

13141516

EN

RUN
AGND
AGND

FBL

FBM

AGND

VMAIN

PGND
BOOT
VGH
FBH

GATE

VIN

SWP

1
2
3
4

12
11

10

9

5 6

7

8

13141516

Exposed

Thermal Die*

EN

RUN

LDOIN

LDOOUT

FBL

FBM

AGND

VMAIN

PGND
BOOT
VGH
FBH

GATE

VIN

SWN

SWP

AGND

SWN

Exposed

Thermal Die*

AGND

14

Exposed

Thermal Die*

AGND

TPS65120/1/2

(TOP VIEW)

TPS65123

(TOP VIEW)

TPS65124

(TOP VIEW)

TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

PIN ASSIGNMENTS

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

VIN 15 I This is the input voltage pin of the device.

GATE 16 I/O section), or an active high control input. Pulling GATE above the 1.4 V logic-high level and RUN to a logic-low

RUN 2 I

EN 1 I floating. A simultaneous logic-high level on EN and RUN enables the converter and a logic-low shuts down

SWN 14 I/O Connect the inductor to this pin. This pin is connected to the source of the high-side MOSFET switch.
SWP 13 I/O Connect the inductor to this pin. This pin is connected to the drain of the low-side MOSFET switch.
PGND 12 O Power ground. Connect to AGND underneath the IC.
VGH 10 O Positive output

BOOT 11 O
VMAIN 8 I Main output

FBH 9 I Feedback pin for the positive output voltage divider. Regulates to 1.213 V nominal.
FBL 5 I
FBM 6 I Feedback pin for the main output voltage divider. Regulates to 1.213V nominal.
AGND 7, 3, 4

LDOIN 3 I (TPS65120/1/2). The low-dropout series-pass regulator (LDO) is enabled according to the GATE signal

LDOOUT 4 O Auxiliary linear regulator output (TPS65120/1/2).
ENVGL 3 I Enable pin for negative output (TPS65124). This pin should be terminated and not be left floating.
ENVGH 4 I Enable pin for positive output (TPS65124). This pin should be terminated and not be left floating.

I/O DESCRIPTION

This pin can either be the gate driver output to an external small P-Channel MOSFET (see application
level disables the integrated active power-down sequencing.

RUN controls the external P-Channel MOSFET. This pin must be terminated and not be left floating. Forcing
this pin to a logic-high level turns on the external MOSFET switch.

This is the enable pin of the multiple-output dc-to-dc converter. This pin must be terminated and not be left
the device.

Provides a bootstrapped supply for the rectifier MOSFET driver, enabling the gate of the MOSFET to be
driven above the output voltage.

Feedback pin for the negative output voltage divider. Regulates to 0 V nominal. Connect feedback resistor
divider between VGL and main output.

Analog ground. Connect to power ground (PGND) underneath IC. Pins 3 and 4 are only used for AGND in
TPS65123.

Auxiliary linear regulator input. If this pin is connected to GND, the voltage regulator is disabled
timing.

6

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Current Limit

Comparator

Undervoltage

Lockout

Bias Supply

VIN

SWP

LDOOUT

SWN

T

on

VGH

BOOT

PGND

VMAINLDO

BOOT

V

REF

R

V

REF

R

FBH

R

FBL

BOOT

FBM

AGND

Bandgap

V

REF

= 1.213V

Power Up/Down

Sequencer

Oscillator

S

Min Off Time

VMAIN

Control

Logic

EN

BOOT

BOOT

P−MOS1

P−MOS2

N−MOS1

N−MOS2

N−MOS3

D1

RUN

VMAIN

GATE

EN

100kR

Power Down Seq Off

Power Down Seq Off

R

DIS_VGH

R

DIS_VMAIN

EN

LDO

LDOIN

EN_LDOAUX

NOT PRESENT IN TPS65123

FUNCTIONAL BLOCK DIAGRAM - TPS65120/1/2/3

TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

7

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Current Limit

Comparator

Undervoltage

Lockout

Bias Supply

VIN

SWP

SWN

T

on

VGH

BOOT

PGND

VMAIN

BOOT

V

REF

R

V

REF

R

FBH

R

FBL

BOOT

FBM

AGND

Power Up/Down

Sequencer

Oscillator

S Min Off Time

VMAIN

Control

Logic

EN

BOOT

BOOT

P−MOS1

P−MOS2

N−MOS1

N−MOS2

N−MOS3

D1

RUN

VMAIN

GATE

EN

100kR

Power Down Seq Off

Power Down Seq Off

R

DIS_VGH

R

DIS_VMAIN

EN

ENVGH

ENVGL

Bandgap

V

REF

= 1.213V

LDO

TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

FUNCTIONAL BLOCK DIAGRAM - TPS65124

8

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PARAMETER MEASUREMENT INFORMATION

SWN

TPS65120

D1

L1
10

C1

F

V

IN

2.7 V to 5.5 V

V

GL

down to −18 V/2 mA

C3

220 nF

R4

R3

SWP

FBL

VMAIN

FBM

C5
220 nF

R6

R5

V

MAIN

3.0 V to 5.3 V/20 mA

C4

1

BOOT

VGH

C2

220 nF

V

GH

up to 20 V/2 mA

PGND

AGND

FBH

RUN

V

AUX

3.3 V/20 mA

EN

VIN

A

A

GATE

LDOIN

LDOOUT

C6
220 nF

R2

R1

List of Components:
U1 = TPS6512x
L1 = EPCOS SIMID1812-C
D1 = ZETEX ZUMD54C
CX = X5R/X7R

2.2  FH

TPS65120, TPS65121, TPS65123, TPS65124

SLVS531A – JUNE 2004 – REVISED MARCH 2005

η Core converter efficiency vs Load current 3

V

MAIN

V

, V

GH

V

GH

V

GL

f

s

I

Q

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

vs Input voltage 4

Main output efficiency vs Load current 5

vs Input voltage 6
Output ripple voltage 7
DC output voltage vs Load current 8
Load transient response 9

GL

Positive, negative output ripple voltage 10, 11
DC output voltage vs Load current 12
DC output voltage vs Load current 13
Switching frequency vs Load current 14
No load quiescent current vs Input voltage 15
Power-Up Sequencing (TPS65120) 16
Power-Down Sequencing (TPS65120) 17

9