TPS65100EVMĆ030
User’s G uide
February 2004 PMP Portable Power
SLVU101
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR S TATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 2.7 V to 5.8 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
125°C. The EVM is designed to operate properly with certain components above 125°C as
long as the input and output ranges are maintained. These components include but are not
limited to linear regulators, switching transistors, pass transistors, and current sense
resistors. These types of devices can be identified using the EVM schematic located in the
EVM User’s Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
About This Manual
How to Use This Manual
Preface
This users guide describes the characteristics, operation, and use of the
TPS65100EVM-030 evaluation module (EVM). This EVM contains Texas
Instruments TPS65100 triple output LCD supply IC with linear regulator
controller and VCOM buffer. This users guide includes EVM specifications,
test results, schematic diagram, bill of materials (BOM), and recommended
test setup.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 – Introduction
- Chapter 2 – EVM Operation
- Chapter 3 – Board Layout
- Chapter 4 – Bill of Materials and Schematic
Related Documentation From Texas Instruments
SLVS496 − TPS65100 data sheet
If you need Assistance
Contact your local TI sales representative.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademark
Powermite is a registered trademark of Microsemi Corporation.
iii
iv
Contents
1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Background 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Performance Specification Summary 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Modifications 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 EVM Operation 2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Input/Output Connect 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 J1−VIN 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 J2−GND 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 J3−VOUT1 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 J4−GND 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 J5−VCOM 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6 J6−GND 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.7 J7−VCOMIN 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.8 J8−VOUT4 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.9 J9−GND 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.10 J10−VOUT2 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.11 J11−GND 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.12 J12−VOUT3 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.13 J13−GND 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.14 JP2−Enable (EN) 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.15 JP3−Enable Regulator (ENR) 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.16 JP2 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Test Setup 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Test Results 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Board Layout 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Layout 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Bill of Materials and Schematic 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Bill of Materials for VIN = 3.3 V and VOUT1 = 10 V 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Bill of Materials for VIN = 5 V and VOUT1 = 13.5 V 4-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Schematic 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
Contents
2−1 TPS65100 VOUT1 Efficiency 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 TPS65100 Main Boost Converter Load Transient for V
2−3 TPS65100 Main Boost Converter Load Transient for V
3−1 Top Assembly Layer 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 Top Layer Routing 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Bottom Layer Routing 3-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 TPS65100EVM Schematic 4-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
= 3.3 V and V
I
= 5 V and V
I
= 10 V 2-4 . . . . . . . .
O
= 13.5 V 2-4 . . . . . . . .
O
1−1 Performance Specification Summary for V
1−2 Performance Specification Summary for V
4−1 Bill of Materials for VIN = 3.3 V and VOUT1 = 10 V 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Bill of Materials for V
= 5 V and VOUT1 = 13.5 V 4-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IN
= 3.3 V and VOUT1 = 10 V 1-2 . . . . . . . . . .
I
= 5 V and VOUT1 = 13.5 V 1-3 . . . . . . . . . . . . . . .
I
vi
Chapter 1
This chapter contains background information for the TPS65100EVM-030
evaluation module.
Topic Page
1.1 Background 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Performance Specification Summary 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Modifications 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction
1-1
Background
Specification
Specification
1.1 Background
The TPS65100EVM uses a TPS65100 multichannel output IC to provide three
LCD power rails, as well as a linear regulator controller to provide 3.3 V and
a VCOM buffer. The goal of the EVM is to facilitate evaluation of the
TPS65100.
1.2 Performance Specification Summary
Table 1−1 provides a summary of the TPS65100EVM performance
specifications. All specifications are given for an ambient temperature of 25°C.
Table 1−1.Typical Performance Specification Summary for VIN = 3.3 V and VOUT1 = 10 V,
T
= 25°C
A
1.3 Modifications
Voltage Range
(V)
Min Typ Max Min Typ Max
VIN 2.7 3.3 4.0 3000
VOUT1 9.85 10 10.15 0 300
VOUT2 −5.10 −5 −4.90 0 20
VOUT3 22.5 23 23.5 0 20
VOUT4 N/A
VCOM 4.92 5 5.07 0 650 peak
(2)
Current Range
(mA)
(1)
(1)
N/A
(1)
1) Maximum currents are determined by ambient conditions.
2) The linear regulator requires VIN ≥ 3.7 V for normal operation and should
be disabled using JP3.
The primary goal of this EVM is to facilitate user evaluation of the TPS65100.
To facilitate user customization of the EVM, the board was designed with
devices having 603 or larger footprints. So, a real implementation would likely
occupy less total board space.
Changing components can improve or degrade EVM performance. For
example, using an inductor with larger dc resistance for the main boost
converter will lower efficiency of the solution. In addition, using a BJT with
lower Beta or in a smaller package will limit the total output current that the
linear regulator can provide.
The main boost converter requires external compensation components (R7,
C11) for stability. This EVM has been optimized for an input voltage of 3.3 V.
If a dif ferent input voltage and/or a dif ferent output voltage is to be applied, the
main boost converter needs to be re-compensated in order to be stable over
the entire load and temperature range (see Table 1−2 and Table 4−2).
1-2
Modifications
Specification
Specification
Table 1−2.Typical Performance Specification Summary for VIN = 5 V and VOUT1 = 13.5V,
= 255C
T
A
Voltage Range
(V)
Min Typ Max Min Typ Max
VIN 4.0 5 5.8 2000
VOUT1 13.30 13.5 13.70 0 400
VOUT2 −7.11 −7 −6.86 0 20
VOUT3 22.5 23 23.5 0 20
VOUT4 3.2 3.3 3.4 0 500
VCOM 6.65 6.75 6.85 0 650 peak
1) Maximum currents are determined by ambient conditions.
Current Range
(mA)
(1)
(1)
(1)
(1)
Introduction
1-3
Modifications
(This page has been left blank intentionally.)
1-4
Chapter 2
This chapter describes how to properly test the TPS65100 using the
TPS65100EVM−030.
Topic Page
2.1 Input/Output Connect 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Test Setup 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Test Results 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EVM Operation
2-1
Input/Output Connect
2.1 Input/Output Connect
The EVM connection points are described in the following paragraphs.
2.1.1 J1−VIN
This is the positive connection to the input power supply. The leads to the input
supply should be twisted and kept as short as possible.
2.1.2 J2−GND
This is the return connection to the input power supply.
2.1.3 J3−VOUT1
This is the positive output for the main boost convertr of the device.
2.1.4 J4−GND
This is the return connection for the load on the main boost converter of the
device.
2.1.5 J5−VCOM
2.1.6 J6−GND
2.1.7 J7−VCOMIN
2.1.8 J8−VOUT4
2.1.9 J9−GND
2.1.10 J10−VOUT2
2.1.11 J11−GND
This is the positive output of the VCOM buffer.
This is the return connection for the load on the VCOM buffer.
This is the input connection for the VCOM buffer.
This is the output for the 3.3-V linear regulator.
This is the return connection for the load on the linear regulator.
This is the negative output for the inverting charge pump.
This the return connection for the load on the inverting charge pump.
2.1.12 J12−VOUT3
This is the positive output for the positive charge pump.
2.1.13 J13−GND
This the return connection for the load on the positive charge pump.
2-2
2.1.14 JP1 − Mode
This is the charge pump mode pin connector. In order for the charge pump to
operate as a voltage doubler, a jumper is installed to pull the mode pin to GND
and C16 is left unpopulated. In order for the charge pump to operate as a
voltage tripler, the jumper is removed and C16 is populated.
2.1.15 JP2−Enable (EN)
This is the enable pin for the main boost converter (VOUT1). The enable pin
is pulled up to Vin by an onboard pullup resistor. Placing a jumper across pins
2−3 of JP2 shorts the enable pin to GND; thereby disabling the device. Placing
a jumper across pins 1−2 of JP2 connects the enable pin to Vin and enables
the device.
2.1.16 JP3−Enable Regulator (ENR)
This is the enable pin the linear regulator (VOUT4). The enable pin is pulled
up to Vin by an onboard pullup resistor. Placing a jumper across pins 2−3 of
JP3 shorts the enable pin to GND; thereby disabling the device. Placing a
jumper across pins 1−2 of JP3 connects the enable pin to Vin and enables the
device.
Test Setup
2.2 Test Setup
The absolute maximum input voltage is 6 V. The TPS65100 is designed to
operate with a maximum input voltage of 5.8 V. Connect a power supply with
3.3 V output voltage and current limit set to at least 3 A. Short pins 1−2 on
jumpers JP2 and JP3 to enable both the main boost converter and linear
regulator. Connect a load not to exceed the maximum loads per Table 1−2 to
each output of the EVM.
EVM Operation
2-3
Test Results
2.3 Test Results
Below are the efficiency results using this EVM:
Figure 2−1.TPS65100 VOUT1 Efficiency Using the CDRH5D28−4R2 Inductor
90
85
VIN = 5 V,
VOUT1 = 13.5 V
80
75
Efficiency − %
70
65
60
0.05 0.15 0.25 0.35 0.45
Note: Choosing a different inductor could change the effieciency by ± 5%.
VIN = 3.3 V,
VOUT1 = 10 V
Io − Output Current − A
2-4
Test Results
Figure 2−2.TPS65100 Main Boost Converter Load Transient for VIN = 3.3V and VOUT = 10V
Figure 2−3.TPS65100 Main Boost Converter Load Transient for VIN = 5 V and VOUT = 13.5V
EVM Operation
2-5
Chapter 3
This chapter provides the TPS65100EVM−030 board layout and illustrations.
Topic Page
3.1 Layout 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Layout
3-1
Layout
3.1 Layout
Board layout is critical for all switch mode power supplies. Figures 3−1, 3−2,
and 3−3 show the board layout for the HPA030 PWB. The switching nodes with
high frequency noise are isolated from the noise sensitive feedback circuitry
and careful attention has been given to the routing of high frequency current
loops. Refer to the data sheet for more specific layout guidelines.
Figure 3−1.Top Assembly Layer
Figure 3−2.Top Layer Routing
3-2
Figure 3−3.Bottom Layer Routing
Layout
Board Layout
3-3
Layout
(This page has been left blank intentionally.)
3-4
Chapter 4
!
This chapter provides the TPS65100EVM-030 bill of materials and schematic.
Topic Page
4.1 Bill of Materials 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Schematic 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials and Schematic
4-1
Bill of Materials
4.1 Bill of Materials
Table 4−1.Bill of Materials for VIN = 3.3 V and VOUT1 = 10 V
Count Ref Des Description Size MFR Part Number
1 C1 Capacitor, ceramic, 22 µF, 16−V, X5R, 10% 1210 TDK C3225X5R1C226KT
0 C13 Capacitor, ceramic, xx µF, xx−V 603
1 C15 Capacitor, ceramic, 0.22 µF, 50−V, X7R, 10% 805 TDK C2012X5R1H224KT
1 C16 Capacitor, ceramic, 4.7 µF, 6.3−V, X5R, 10% 805 TDK C2012X5R0J475KT
1 C2 Capacitor, ceramic, 22 µF, 6.3−V, X5R, 10% 1206 TDK C3216X5R0J226KT
2 C3, C12 Capacitor, ceramic, 1.0 µF, 10−V, X5R, 10% 603 TDK C1608X5R1A105KT
0 C4 Capacitor, ceramic, xx µF, vv−V 1210
1 C5 Capacitor, ceramic, 6.8 pF, 50−V, C0G, 5% 603 AVX 06035A6R8CAT2A
2 C6, C11 Capacitor, ceramic, 1000 pF, 50−V, X7R, 10% 603 TDK C1608X7R1H102KT
5 C7−C10,
C14
1 D1 Diode, Schottky, 1A, 20 V 457−04 On Semi MBRM120
1 D2 Diode, Dual Schottky, 200−mA, 30−V SOT23 Zetex BAT54S
13 J1−J13 Header, 2−pin, 100 mil spacing, (36-pin strip) 0.100 × 2 Sullins PTC36SAAN
1 JP1 Header, 2−pin, 100 mil spacing, (36-pin strip) 0.100 × 2 Sullins PTC36SAAN
2 JP2, JP3 Header, 3−pin, 100 mil spacing, (36-pin strip) 0.100 × 3 Sullins PTC36SAAN
1 L1 Inductor, SM Toroid, 4.2 µH, 2.2−A, 31 mΩ 74480 Sumida CDRH5D28−4R2
1 Q1 Transistor, NPN general purpose amplifier, VCE
2 R1, R4 Resistor, chip, 511 kΩ, 1/16−W, 1% 603 Std Std
1 R2 Resistor, chip, 432 kΩ, 1/16−W, 1% 603 Std Std
2 R3, R6 Resistor, chip, 56.2 kΩ, 1/16−W, 1% 603 Std Std
1 R5 Resistor, chip, 1.00 MΩ, 1/16−W, 1% 603 Std Std
1 R7 Resistor, chip, 15.0 kΩ, 1/16−W, 1% 603 Std Std
1 R8 Resistor, chip, 150 kΩ, 1/16−W, 1% 603 Std Std
1 R9 Resistor, chip, 619 kΩ, 1/16−W, 1% 603 Std Std
1 U1 IC, (TFT) LCD supply HTSSOP 24 TI TPS65100PWP
1 — PCB, 2.45 In × 2.1 In × 0.062 In Any HPA030
3 — Shunt, 100 mil, black 0.100 3M 929950−00
Capacitor, ceramic, 0.22 µF, 25−V, X5R, 10% 603 TDK C1608X5R1E224KT
SOT223 Fairchild BCP68
20V, VCB 30V, VEB 5V, IC 1A
4-2
Bill of Materials
Table 4−2.Bill of Materials for VIN = 5 V and VOUT1 = 13.5 V
Count Ref Des Description Size MFR Part Number
1 C1 Capacitor, ceramic, 22 µF, 16−V, X5R, 10% 1210 TDK C3225X5R1C226KT
0 C13 Capacitor, ceramic, xx µF, xx−V 603
1 C15 Capacitor, ceramic, 0.22 µF, 50−V, X7R, 10% 805 TDK C2012X5R1H224KT
1 C16 Capacitor, ceramic, 4.7 µF, 6.3−V, X5R, 10% 805 TDK C2012X5R0J475KT
1 C2 Capacitor, ceramic, 22 µF, 6.3−V, X5R, 10% 1206 TDK C3216X5R0J226KT
2 C3, C12 Capacitor, ceramic, 1.0 µF, 10−V, X5R, 10% 603 TDK C1608X5R1A105KT
0 C4 Capacitor, ceramic, xx µF, vv−V 1210
1 C5 Capacitor, ceramic, 3.3 pF, 50−V, C0G, 5% 603 AVX 06035A6R8CAT2A
2 C6, C11 Capacitor, ceramic, 2200 pF, 50−V, X7R, 10% 603 TDK C1608X7R1H102KT
5 C7−C10,
C14
1 D1 Diode, Schottky, 1A, 20 V 457−04 On Semi MBRM120
1 D2 Diode, Dual Schottky, 200−mA, 30−V SOT23 Zetex BAT54S
13 J1−J13 Header, 2−pin, 100 mil spacing, (36-pin strip) 0.100 × 2 Sullins PTC36SAAN
1 JP1 Header, 2−pin, 100 mil spacing, (36-pin strip) 0.100 × 2 Sullins PTC36SAAN
2 JP2, JP3 Header, 3−pin, 100 mil spacing, (36-pin strip) 0.100 × 3 Sullins PTC36SAAN
1 L1 Inductor, SM Toroid, 4.2 µH, 2.2−A, 31 mΩ 74480 Sumida CDRH5D28−4R2
1 Q1 Transistor, NPN general purpose amplifier, VCE
2 R1, R4 Resistor, chip, 511 kΩ, 1/16−W, 1% 603 Std Std
1 R2 Resistor, chip, 825 kΩ, 1/16−W, 1% 603 Std Std
1 R3 Resistor, chip, 80.6 kΩ, 1/16−W, 1% 603 Std Std
1 R6 Resistor, chip, 56.2 kΩ, 1/16−W, 1% 603 Std Std
1 R5 Resistor, chip, 1.00 MΩ, 1/16−W, 1% 603 Std Std
1 R7 Resistor, chip, 4.32 kΩ, 1/16−W, 1% 603 Std Std
1 R8 Resistor, chip, 130 kΩ, 1/16−W, 1% 603 Std Std
1 R9 Resistor, chip, 750 kΩ, 1/16−W, 1% 603 Std Std
1 U1 IC, (TFT) LCD supply HTSSOP 24 TI TPS65100PWP
1 — PCB, 2.45 In × 2.1 In × 0.062 In Any HPA030
3 — Shunt, 100 mil, black 0.100 3M 929950−00
Capacitor, ceramic, 0.22 µF, 25−V, X5R, 10% 603 TDK C1608X5R1E224KT
SOT223 Fairchild BCP68
20V, VCB 30V, VEB 5V, IC 1A
Bill of Materials and Schematic
4-3
Schematic
4.2 Schematic
Figure 4−1.TPS65100EVM−030 Schematic for VIN = 3.3 V and VOUT1 = 10 V.
JP2
VIN
GND
EN
GND
VIN
VIN
1
JP3
VIN
ENR
1
GND
J8
VOUT4
1
1
3
2
2
VIN
VOUT4
2
BCP68
4
U1
J9
1
2
F
4.7 µ
C16
1
C13
F
µ
C12
1.0
23
24
EN
ENR
TPS65100PWP
FB1
FB4
1
2
VOUT2
1000 pF
C11
15 .0 kΩ
R7
21
22
COMP
BASE
3
4
J10
1
Ω
619 k
R9
150 KΩ
R8
20
FB2
VINSWSW
5
VOUT2
2
F
0.22 µ
C10
19
REF
678
C14
GND
F
0.22 µ
D2
F
0.22 µ
C7
18
PGND
J11
DRV
121
BAT54S
17
GND
2
F
0.22 µ
C8
16
C1−
PGND
9
15
C1+
C2−/MD
SUP
VCOM
101112
JP1
MODE
F
0.22 µ
C9
14
C2+
VCOMIN
GND
13
OUT3
FB3
J12
R5
PwrPad
1
1.00 MΩ
VOUT3
2
C15
GND
J13
1
2
F
0.22 µ
56.2 kΩ
R6
4-4
VOUT4
R2
C5
432 kΩ
6.8 pF
OPEN
C3
2
VCOM
VOUT1
VOUT1
F
1.0 µ
1
1211
J6
1
2
GND
1
J7
VCOMIN
C2 C4
2
VOUT1
511 kΩ
R4
C6
1000 pF
R1
511 kΩ
1
22 µ F
1
1
2
J4
J5
GND
MBRM120
L1 4.2 µ H
D1
R3
56.2 kΩ
C2
22 µ F
VIN
1
1
2
2
J1
J2
VIN
VOUT1
2
GND
1
J3
1
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