Texas Instruments TPS56302PWPR, TPS56302PWP Datasheet

TPS56302

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

2.8 V – 5.5 V Input Voltage Range

D

Programmable Dual Output Controller
Supports Popular DSP, FPGA and
Microcontroller Core and I/O Voltages
– Switching Regulator Controls I/O Voltage
– Low Dropout Controller Regulates Core

Voltage

D

Adjustable Slow-Start for Simultaneous
Powerup of Both Outputs

D

Power Good Output Monitors Both Outputs

D

Fast Ripple Regulator Reduces Bulk
Capacitance for Lower System Costs

D

±1.5% Reference V oltage Tolerance

D

Efficiencies Greater Than 90%

D

Overvoltage, Undervoltage, and Adjustable
Overcurrent Protection

D

Drives Logic Level N-Channel MOSFETs
Through Entire Input Voltage Range

D

Evaluation Module TPS56302EVM–163
Available

description

The high-performance TPS56302 synchronous-buck regulator provides two supply voltages to power the core
and I/O of digital signal processors. The TPS56302 is identical to the TPS56300 except that the reference
voltages of the LDO and switching regulator have been reversed. The switching regulator, using hysteretic
control with droop compensation, supports high current and efficiency for the I/O and other peripheral
components. The LDO controller, suitable for powering the core voltage, drives an external N-channel power
MOSFET and functions as an LDO regulator and as a power distribution switch.

typical design

+

+ +

U1
TPS56302PWP

CPC1
CPC2
VREFB
VHYST
DROOP
OCP
IOUT
SLOWST
VID0
VID1
BIAS
VLDODRV
VDRV
ANAGND

PwrPad

V

CC

DSP

V

CORE

V

I/O

Data

Data Bus

PERIPHERAL

V

I

(2.8 V – 5.5 V)

PWRGD

NGATE–LDO

VSEN–LDO

INHIBIT

IOUTLO

HISENSE

HIGHDR

VSEN–RR

LOSENSE/LOHIB

BOOT

BOOTLO

LOWDR

DRVGND

See Table 1
See Table 1

+

+

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VID0
VID1

SLOWST

VHYST
VREFB

VSEN–RR

ANAGND

BIAS

VLDODRV

CPC1

V

CC

CPC2

VDRV

DRVGND

DROOP
OCP
IOUT
PWRGD
VSEN–LDO
NGATE–LDO
INHIBIT
IOUTLO
HISENSE
LOSENSE/LOHIB
HIGHDR
BOOT
BOOTLO
LDWDR

PWP PowerPAD PACKAGE

(TOP VIEW)

Thermal

Pad

OUTPUTS

V

OUT

–LDO

V

OUT

–Switcher

TPS56302

1.3 V TO 2.5 V

1.3 V TO 3.3 V

TPS56300

1.3 V TO 3.3 V

1.3 V TO 2.5 V

AVAILABLE VID CODE RANGES

NOTE: See Table 1 for actual VID codes.

TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

T o promote better system reliability during power up, voltage sequencing and protection are controlled such that
the core and I/O power up together with the same slow-start voltage. At power down, the LDO and ripple
regulator are discharged towards ground for added protection. The TPS56302 also includes inhibit, slow-start,
and under-voltage lockout features to aide in controlling power sequencing. A tri-level voltage identification
definition (VID) sets both regulated voltages to any of 9 preset voltage pairs from 1.3 V to 3.3 V . Other voltages
are possible by implementing an external voltage divider. Strong MOSFET drivers, with a typical peak current
rating of 2-A sink and source are included on chip, which allows paralleling MOSFET s to be driven and allowing
higher current to be controlled. The high-side driver features a floating bootstrap driver with an internal bootstrap
synchronous rectifier. Many protection features are incorporated within the device to ensure better system
integrity . An open-drain output power good status circuit monitors both output voltages, and is pulled low if either
output falls below the threshold. An over current shutdown circuit protects the high-side power MOSFET against
short-to-ground faults, while over voltage protection turns off the output drivers and LDO controller if either
output exceeds its threshold. Under voltage protection turns off the high-side and low-side MOSFET drivers and
the LDO controller if either output is 25% below V

REF

. Lossless current-sensing is implemented by detecting
the drain-source voltage drop across the high-side power MOSFET while it is conducting. The TPS56302 is fully
compliant with TI DSP power requirements.

AVAILABLE OPTIONS

PACKAGES

T

J

TSSOP

†

(PWP)

EVALUATION MODULE

–40°C to 125°C TPS56302PWP TPS56302EVM–163 (SLVP163)

†

The PWP package is also available taped and reel. To order, add an R to the end of
the part number (e.g., TPS56302PWPR).

Table 1. Voltage Identification Code

¶#

VID TERMINALS

‡

56302 56300

VID1 VID0

V

REF–LDO

#

(VDC)

V

REF–RR

#

(VDC)

V

REF–RR

#

(VDC)

V

REF–LDO

#

(VDC)

0 0 1.30 1.50 1.30 1.50
0 1 1.50 1.80 1.50 1.80
0 2 1.30 1.80 1.30 1.80
1 0 1.80 3.30 1.80 3.30
1 1 1.30 1.30 1.30 1.30
1 2 2.50 3.30 2.50 3.30
2 0 1.30 2.50 1.30 2.50
2 1 1.50 3.30 1.50 3.30
2 2 1.80 2.50 1.80 2.50

‡

0 = ground (GND), 1 = floating(V

BIAS

/2), 2 = (V

BIAS

)

§

RR = Ripple Regulator, LDO = Low Drop-Out Regulator

¶

V

BIAS

/2 is internal, leave the VID pin floating. Adding an external 0.1-µF capacitor to ANAGND may be used

to avoid erroneous level.

#

External resistors may be used as a voltage divider (from V

OUT

to VSEN–xx to ground) to program output

voltages to other values.

TPS56302

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

CC

23

24

VLDODRV

NGATE–LDO

VSEN–LDO

RR_OVP

LDO_OVP

RR_UVP *

LDO_UVP *

SHUTDOWN

VID

2

1

VID0

VID1

VREF_LDO

VREF_RR

5

VREFB

Hysteresis

Setting

+

–

28

VHYST

6

VSEN–RR

Hysteresis

Comparator

Adaptive

Deadtime

15

18

16

14

17

VDRV

BOOT

HIGHDR

BOOTLO

LOWDR

DRVGND

22

11

INHIBIT

V

VDRV UVLO
V

3

SLOWST

SHUTDOWN

+

–

–

+

Delay

26202119

LOSENSE/

LOHIB

IOUTLO HISENSE

IOUT

HIGHDR

Ivrefb/5

Vbias

8

Bias

7

Reg.

VLDODRV

25

>0.93xVSEN–RR

>0.93xVSEN–LDO

4

DROOP

PWRGD

ANAGND

SHUTDOWN

27

125 mV

OCP

RS

Q

Fault

Latch

SHUTDOWN

INHIBIT

SLOWST

SLOWST

SHUTDOWN

SHUTDOWN

5 V

10

CPC1

9

12

CPC2

13

VDRV

VDRV

BOOT

–

+

E/A

Synchronous

FET

RR–Ripple Regulator

(see Table 1)

VDRV

* UVP is disabled during slowstart

CC

UVLO

TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

NO.

DESCRIPTION

VID0 1 Voltage Identification input 0. The VID pins are tri-level programming pins that set the output voltages for both

converters. The code pattern for setting the output voltage is located in table 1. The VID pins are internally pulled to
V

BIAS

/2, allowing floating voltage set to logic 1 (see Table 1).
VID1 2 Voltage Identification input 1 (see VID0 pin description and Table 1).
SLOWST 3 Slow-start (soft start). A capacitor from pin 3 to GND sets the slow-start time for V

OUT-RR

and V

OUT-LDO

. Both supplies

will ramp-up together while tracking the slow-start voltage.
VHYST 4 Hysteresis set pin. The hysteresis equals 2 × (VREFB – VHYST).
VREFB 5 Buffered ripple regulator reference voltage from VID network.
VSEN-RR 6 Ripple regulator voltage sense input. This pin is connected to the ripple regulator output. It is used to sense the ripple

regulator voltage for regulation, OVP , UVP , and power good functions.. It is recommended that an RC low pass filter be

connected at this pin to filter high frequency noise.
ANAGND 7 Analog ground
BIAS 8 Analog BIAS pin. Recommended that a 1-µF capacitor be connected to ANAGND.
VLDODRV 9 Output of charge pump generated through bootstrap diode. Approximately equal to VDRV + VIN – 300 mV . Used as

supply for LDO driver and bias regulator. Recommended that a 1-µF capacitor be connected to DR VGND.
CPC1 10 Connect one end of charge pump capacitor. Recommended that a 1-µF capacitor be connected from CPC1 to CPC2.
V

CC

11 3.3 V or 5 V supply (2.8 V – 5.5 V). It is recommended that a low ESR capacitor be connected directly from VCC to

DRVGND (bulk capacitors supplied at power stage input).
CPC2 12 Other end of charge pump capacitor from CPC1.
VDRV 13 Regulated output of internal charge pump. Supplies DRIVE charge for the low-side MOSFET driver (5 V).

Recommended that a 10-µF capacitor be connected to DRVGND.
DRVGND 14 Drive ground. Ground for FET drivers. Connect to source of low-side FET.
LOWDR 15 Low drive. Output drive to synchronous rectifier low-side FET.
BOOTLO 16 Bootstrap low. This pin connects to the junction of the high-side and low-side FETs.
BOOT 17 Bootstrap pin. Connect a 1-µF low ESR capacitor to BOOTLO to generate floating drive for the high-side FET driver.
HIGHDR 18 High drive. Output drive to high-side power switching FETs
LOSENSE/

LOHIB

19 Low sense/low-side inhibit. This pin is connected to the junction of the high and low-side FET s and is used in current

sensing and the anti-cross-conduction to eliminate shoot-through current.
HISENSE 20 High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs.
IOUTLO 21 Current sense low output. Voltage on this pin is the voltage on the LOSENSE pin when the high-side FETs are on.
INHIBIT 22 This pin inhibits the drive signals to the MOSFET drivers. The IC is in a low-current state if INHIBIT is grounded. It is

recommended that an external pullup resistor be connected to 5 V.
NGATE-LDO 23 Drives external N-channel power MOSFET to regulate LDO voltage to VREF-LDO.
VSEN–LDO 24 LDO voltage sense. This pin is connected to the LDO output. It is used to sense the LDO voltage for regulation, OVP,

UVP, and power good functions.
PWRGD 25 Power good. Power good signal goes high when output voltage is above 93% of V

REF

for both ripple regulator and

LDO. This is an open-drain output.
IOUT 26 Current signal output. Output voltage on this pin is proportional to the load current as measured across the high-side

FET s on-resistance. The voltage on this pin equals 2× RON×IOUT, where RON is the equivalent on-resistance of the

high-side FETs
OCP 27 Over current protection. Current limit trip point for ripple regulator is set with a resistor divider between the IOUT pin and

ANAGND. The trip point is typically 125 mV .
DROOP 28 Droop voltage. Voltage input used to set the amount of output voltage droop as a function of load current. The amount of

droop compensation is set with a resistor divider between the IOUT pin and ANAGND.

TPS56302

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range: VDRV –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to DRVGND (High-side Driver ON) –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to BOOTLO –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to HIGHDRV –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOTLO to DRVGND –0.5 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DRV to DRVGND –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BIAS to ANAGND –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INHIBIT –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DROOP –0.3 V to V

CC

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OCP –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VID0, VID1 (tri-level terminals) –0.3 V to V

BIAS

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . .

PWRGD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LOSENSE, LOHIB –0.5 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IOUTLO –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HISENSE –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VSEN–LDO –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VSEN–RR –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage difference between ANAGND and DRVGND ±300 mV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating junction temperature range, T

J

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.

DISSIPATION RATING TABLE

PWP

TA < 25°C DERATING FACTOR

‡

TA = 70°C TA = 85°C

PowerPAD mounted 3.58 W 0.0358 W/°C 1.96 W 1.43 W
PowerPAD unmounted 1.78 W 0.0178 W/°C 0.98 W 0.71 W

‡

Test Board Conditions:

1.. Thickness: 0.062”

2. 3”× 3”

3. 2 oz. Copper traces located on the top of the board (0.071 mm thick )

4. Copper areas located on the top and bottom of the PCB for soldering

5. Power and ground planes, 1 oz. Copper (0.036 mm thick)

6. Thermal vias, 0.33 mm diameter, 1.5 mm pitch

7. Thermal isolation of power plane

For more information, refer to TI technical brief SLMA002.

JUNCTION-CASE THERMAL RESISTANCE TABLE

Junction-case thermal resistance

0.72 °C/W

TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)

input

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

V

CC

Supply voltage range 2.8 5.5 V

I

CC

Quiescent current INHIBIT = 0 V, VCC = 5 V 15 mA

NOTE 2: Ensured by design, not production tested.

reference/voltage identification

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VID0–VID1 High-level input voltage (2) V

BIAS

– 0.3 V V

VID0–VID1 Mid-level floating voltage (1)

V

BIAS

2

*

1

V

BIAS

2

)

1

V

VID0–VID1 Low-level input voltage (0) 0.3 V

Input pull-to-mid resistance 36.5 73 95 kΩ

cumulative reference

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

V

REF

= 1.3 V, Hysteresis window = 30 mV ,

TJ = 25°C

–1.3% 0.25% 1.3%

Cumulative accuracy ripple regulator

V

REF

= 1.3 V, Hysteresis window = 30 mV ,

TJ = –40°C, See Note 2

–0.2%

V

REF

= full range, Hysteresis window = 30 mV,

Droop = 0, See Note 2

–1.5% 1.5%

Cumulative accuracy LDO

V

REF

= 1.3 V, IO = 0.1 A,
Closed Loop, Pass device = IRFZ24N,
TJ = 25°C, See Note 2

–2% 2%

y

V

REF

= full range, IO = 0.1 A, Closed Loop,
Pass device = IRFZ24N, See Note 2

–2.5% 2.5%

NOTE 2. Ensured by design, not production tested.

buffered reference

PARAMETER CONDITIONS MIN TYP MAX UNITS

p

I

REFB

=50 µA, Accuracy from V

REF

nominal

V

REF

–1.5%

V

REF

V

REF

+1.5%

VREFB output voltage

I

REFB

=50 µA, Accuracy from V

REF

nominal

TJ = –40°C, See Note 2

V

REF

–0.6%

V

VREFB load regulation 10 µA < I

REFB

< 500 µA 2 mV

NOTE 2. Ensured by design, not production tested.

hysteretic comparator(ripreg)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input bias current See Note 2 500 nA
Hysteresis accuracy

V

VREFB

– V

VHYST

= 15 mV,

Hysteresis window = 30 mV

–3.5 3.5 mV

Maximum hysteresis setting

V

VREFB

– V

VHYST

= 30 mV,

See Note 2

60 mV

Propagation delay time from VSENSE to HIGHDR or
LOWDR (excluding deadtime)

10 mV overdrive, 1.3 V <= V

REF

<= 3.3 V,

See Note 2

150 250 ns

Prefilter pole frequency See Note 2 5 MHz

NOTE 2. Ensured by design, not production tested.

TPS56302

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)

overvoltage protection

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

OVP ripple regulator trip point (RR) Upper threshold 112 115 120 %V

REF

Hysteresis (RR)

Upper threshold – lower threshold,
(see Note 2)

10 mV

Comparator propagation delay time (RR) V

overdrive

= 30 mV , See Note 2 1 µs

Deglitch time (includes comparator propagation delay time) (RR) V

overdrive

= 30 mV , See Note 2 2.25 11 µs

OVP LDO trip point (LDO) Upper threshold 112 115 120 % V

REF

Hysteresis (LDO)

Upper threshold – lower threshold,
(see Note 2)

10 mV

Comparator propagation delay time (LDO) V

overdrive

= 50 mV , See Note 2 1 µs

Deglitch time (includes comparator propagation delay time)
(LDO)

V

overdrive

= 50 mV , See Note 2 2.25 11 µs

NOTE 2. Ensured by design, not production tested.

undervoltage protection

PARAMETER CONDITIONS MIN TYP MAX UNITS

UVP ripple regulator trip point (RR) Lower threshold 70 75 80 % V

REF

Hysteresis (RR)

Upper threshold – lower threshold,

(see Note 2)

10 mV

Comparator propagation delay time (RR) V

overdrive

= 50 mV , See Note 2 1 µs

Deglitch time (includes comparator
propagation delay time) (RR)

V

overdrive

= 50 mV , See Note 2 0.1 1 ms

UVP LDO trip point (LDO) Lower threshold 70 75 80 % V

REF

Hysteresis (LDO)

Upper threshold – lower threshold,

(see Note 2)

10 mV

Comparator propagation delay time (LDO) V

overdrive

= 50 mV , See Note 2 1 µs

Deglitch time (includes comparator
propagation delay time) (LDO)

V

overdrive

= 50 mV , See Note 2 0.1 1 ms

NOTE 2. Ensured by design, not production tested.

inhibit comparator

PARAMETER CONDITIONS MIN TYP MAX UNITS

2.1 2.35

Start threshold

TJ = –40°C, See Note 2 2.1

V

Stop threshold 1.79 V

NOTE 2. Ensured by design, not production tested.

VDRV UVLO

PARAMETER CONDITIONS MIN TYP MAX UNITS

Start threshold See Note 2 4.9 V
Hysteresis See Note 2 0.3 0.35 V
Stop threshold See Note 2 4.4 V

NOTE 2. Ensured by design, not production tested.

TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)

slow-start

PARAMETER CONDITIONS MIN TYP MAX UNITS

Charge current

V

(S/S)

= 0.5 V,
Resistance from VREFB pin to ANAGND = 20 kΩ
VREFB = 1.3 V, Ichg = (I

VREFB

/5)

10.4 13 15.6 µA

Discharge current V

(S/S)

= 1.3 V 3 mA

Comparator input offset voltage 10 mV
Comparator input bias current See Note 2 10 100 nA
Hysteresis accuracy –7.5 7.5 mV
Comparator propagation delay Overdrive = 10 mV, See Note 2 560 1000 ns

NOTE 2. Ensured by design, not production tested.

VCC UVLO

PARAMETER CONDITIONS MIN TYP MAX UNITS

(see Note 2) 2.72 2.80

Start threshold

TJ = –40°C, See Note 2 2.71

V

Stop threshold (see Note 2) 2.48 V

NOTE 2. Ensured by design, not production tested.

power good

PARAMETER CONDITIONS MIN TYP MAX UNITS

Undervoltage trip point ripple regulator

VIN and VDRV above UVLO thresholds 90 93 95

gg

(VSENSE–RR)

TJ = –40°C, See Note 2 93

% V

REF

Undervoltage trip point LDO

VIN and VDRV above UVLO thresholds 90 93 95

g

(VSENSE–LDO)

TJ = –40°C, See Note 2 93

% V

REF

Output saturation voltage IO=5 mA 0.5 0.75 V
Leakage current V

PGD

= 4.5 V 1 µA

V

REF

= 1.3 V, 1.5 V, or 1.8 V 50 75 mV

Hysteresis

V

REF

= 2.5 V, or 3.3 V 100 125 mV

Comparator high–low transition time
(propagation delay only)

See Note 2 1 µs

Comparator low–high transition time
(propagation delay + deglitch)

See Note 2 0.2 1 2 ms

NOTE 2. Ensured by design, not production tested.

droop compensation

PARAMETER CONDITIONS MIN TYP MAX UNITS

Initial accuracy V

DROOP

= 50 mV 46 54 mV

overcurrent protection (RR)

PARAMETER CONDITIONS MIN TYP MAX UNITS

OCP trip point 118 130 142 mV
Input bias current 300 nA
Comparator propagation delay time V

overdrive

= 30 mV , See Note 2 1 µs

Deglitch time (includes comparator
propagation delay time)

V

overdrive

= 30 mV , See Note 2 2.25 11 µs

NOTE 2. Ensured by design, not production tested.

TPS56302

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)

high-side VDS sensing

PARAMETER CONDITIONS MIN TYP MAX UNITS

Gain 2 V/V
Initial accuracy

V

HISENSE

= 3.3 V, V

IOUTLO

= 3.2 V,

Differential input to Vds sensing amp = 100 mV

194 208 mV

Common-mode rejection ratio

V

HISENSE

=2.8 V to 5.5 V ,

V

HISENSE

– V

IOUTLO

=100 mV

69 75 dB

Sink current (IOUTLO) 2.8 V < V

IOUTLO

< 5.5 V 250 nA

Source current (IOUT)

V

IOUT

= 0.5 V, V

HISENSE

=3.3 V ,

V

IOUTLO

=2.8 V

500 µA

Sink current (IOUT)

V

IOUT

= 0.05 V , V

HISENSE

=3.35 V ,

V

IOUTLO

=3.3 V

50 µA

V

HISENSE

=5.5 V , R

IOUT

= 10 kΩ 0 1.75

Output voltage swing

V

HISENSE

=4.5 V , R

IOUT

= 10 kΩ 0 1.5

V

V

HISENSE

=3 V, R

IOUT

= 10 kΩ 0 0.75

LOSENSE high-level input voltage V

HISENSE

=2.8 V , See Note 2 1.77 V

LOSENSE low-level input voltage V

HISENSE

=2.8 V , See Note 2 1.49 V

LOSENSE high-level input voltage V

HISENSE

=4.5 V , See Note 2 2.85 V

LOSENSE low-level input voltage V

HISENSE

=4.5 V , See Note 2 2.4 V

LOSENSE high-level input voltage V

HISENSE

=5.5 V , See Note 2 3.80 V

LOSENSE low-level input voltage V

HISENSE

=5.5 V , See Note 2 3.2 V

V

HISENSE =

6 V, See Note 2 70 90

p

V

HISENSE =

4.5 V , See Note 2 80 100

Sample/hold resistance

V

HISENSE =

3.6 V , See Note 2 90 120

Ω

V

HISENSE =

2.8 V , See Note 2 120 180

V

HISENSE

= 2.55 V ,

V

IOUTLO

pulsed from 2.55 V to 2.45 V ,

100 ns rise and fall times, See Note 2

4

Response time (measured from 90% of

V

HISENSE

= 2.8 V,

V

IOUTLO

pulsed from 2.8 V to 2.7 V ,

100 ns rise and fall times, See Note 2

3.5

(

V

IOUTLO

to 90% of V

IOUT

)

V

HISENSE

= 4.5 V,

V

IOUTLO

pulsed from 4.5 V to 4.4 V ,

100 ns rise and fall times, See Note 2

3

µ

s

V

HISENSE

= 5.5 V,

V

IOUTLO

pulsed from 5.5 V to 5.9 V ,

100 ns rise and fall times, See Note 2

3

Short circuit protection rising edge delay LOSENSE grounded, See Note 2 300 500 ns
Sample/hold switch turnon/turnoff delay

2.8 V < V

HISENSE

< 5.5 V,

V

LOSENSE

= V

HISENSE

, See Note 2

30 100 ns

NOTE 2. Ensured by design, not production tested.

TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)

thermal shutdown

PARAMETER CONDITIONS MIN TYP MAX UNITS

Over temperature trip point See Note 2 145 °C
Hysteresis See Note 2 10 °C

NOTE 2. Ensured by design, not production tested.

synch charge pump regulator

PARAMETER CONDITIONS MIN TYP MAX UNITS

Internal oscillator frequency

2.8 V < VIN < 5.5 V, I

DRV

= 50 mA,

VDRV=5 V , See Note 2

200 300 400 kHz

Internal oscillator turnon threshold VCC above UVLO threshold, See Note 2 5.05 5.2 V
Internal oscillator turnon hysteresis VCC above UVLO threshold, See Note 2 20 mV

NOTE 2. Ensured by design, not production tested.

hysteretic comparator (charge pump)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Threshold VIN above UVLO threshold, See Note 2 5.05 5.2 V
Hysteresis VIN above UVLO threshold, See Note 2 20 mV

NOTE 2. Ensured by design, not production tested.

deadtime circuit

PARAMETER CONDITIONS MIN TYP MAX UNITS

LOSENSE/LOHIB high level input voltage V

HISENSE

=2.55 V – 5.5 V , See Note 2 2.4 V

LOSENSE/LOHIB low level input voltage V

HISENSE

=2.55 V – 5.5 V , See Note 2 1.33 V

LOWDR high level input voltage V

HISENSE

=2.55 V–5.5 V , See Note 2 3 V

LOWDR low level input voltage V

HISENSE

=2.55 V–5.5 V , See Note 2 1.7 V

Driver nonoverlap time

C

LOWDR

= 9 nF, 10% threshold on LOWDR,

VDRV=5 V

40 170 ns

NOTE 2. Ensured by design, not production tested.

TPS56302

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS289 – MARCH 2000

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)

output drivers (see Note 5)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Duty cycle < 2%, tpw < 100 us,
V

BOOT

– V

BOOTLO

= 4.5 V,

V

HIGHDR

= 4 V (sink), See Note 2 and Figure 15

0.7 2

p

Duty cycle < 2%, tpw < 100 us,
V

BOOT

– V

BOOTLO

= 4.5 V,

V

HIGHDR

= 0.5 V (source), See Note 2 and Figure 15

1.2 2

Peak output current

Duty cycle < 2%, tpw < 100 µs,
V

DRV

= 4.5 V, V

LOWDR

= 4 V (sink),

See Note 2 and Figure 15

1.3 2

A

Duty cycle < 2%, tpw < 100 us,
V

DRV

= 4.5 V, V

LOWDR

= 0.5 V (source),

See Note 2 and Figure 15

1.4 2

V

BOOT

– V

BOOTLO

= 4.5 V, V

HIGHDR

= 0.5 V,

See Note 2

5

Output resistance

V

BOOT

– V

BOOTLO

= 4.5 V, V

HIGHDR

= 4 V,

See Note 2

45

Ω

V

DRV

= 4.5 V, V

LOWDR

= 0.5 V , See Note 2 9

V

DRV

= 4.5 V, V

LOWDR

= 4 V, See Note 2 45

HIGHDR rise/fall time

CL = 3.3 nF, V

BOOT

= 4.5 V ,

V

BOOTLO

=grounded, See Note 2

60 ns

LOWDR rise/fall time CL = 3.3 nF, V

DRV

= 4.5 V , See Note 2 40 ns

INHIBIT grounded, VIN < UVLO, V

BOOT

=6 V ,

BOOTLO grounded

10 µA

High-side driver quiescent current

INHIBIT connected to +5 V , VIN > UVLO
f

(swx)

= 200 kHz, V

BOOT

= 5.5 V,

BOOTLO = 0, C

HIGHDR

= 50 pF,

See Note 2

2 mA

NOTES: 2. Ensured by design, not production tested.

5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the R

ds(on)

of the MOSFET transistor when

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

LDO N-channel output driver

PARAMETER CONDITIONS MIN TYP MAX UNITS

p

V

LDODRV

= 7.5 V, V

N–DRV

= 3 V (source),

V

IOSENSE

= 0.9 × V

LDOREF

, See Note 2

100 µA

Peak output current

V

LDODRV

= 7.5 V, V

N–DRV

=0 V (sink),

V

IOSENSE

= 1.1 × V

LDOREF

, See Note 2

1.5 mA

Open loop voltage gain
(V

NGATE–LDO

/ V

SENSE–LDO

)

7.5 V ≥ V

NGATE–LDO

≥ 0.5 V, VIN = 5.5 V,

See Note 2

3000

(70)

V/V

(dB)

Power supply ripple rejection

f = 1 kHz, CO=10 µF,

5.5 V ≥ VIN ≥ 2.55 V, TJ=125 °C,
See Note 2

60 dB

NOTE 2. Ensured by design, not production tested.