Texas Instruments TPS 54310 – Q 1 INSTALLATION INSTRUCTIONS

 

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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       

    !"

FEATURES

D Qualification in Accordance With AEC-Q100
D Qualified for Automotive Applications
D Customer-Specific Configuration Control Can

Be Supported Along With Major-Change
Approval

D 60-mΩ MOSFET Switches for High Efficiency

at 3-A Continuous Output Source or Sink
Current

D 0.9-V to 3.3-V Adjustable Output Voltage With

1% Accuracy

D Externally Compensated for Design Flexibility
D Fast Transient Response
D Wide PWM Frequency: Fixed 350 kHz,

550 kHz, or Adjustable 280 kHz to 700 kHz

D Load Protected by Peak Current Limit and

Thermal Shutdown

D Integrated Solution Reduces Board Area and

Total Cost

(1)

Contact Texas Instruments for details. Q100 qualification data
available on request.

(1)

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007



DESCRIPTION

As members of the SWIFT family of dc/dc regulators,
the TPS54310 low-input-voltage high-output-current
synchronous-buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high-performance,
voltage error amplifier that provides high performance
under transient conditions, an undervoltage-lockout
circuit to prevent start up until the input voltage reaches
3 V, an internally and externally set slow-start circuit to
limit in-rush currents, and a power good output useful
for processor/logic reset, fault signaling, and supply
sequencing.

The TPS54310 device is available in a thermally
enhanced 20-pin TSSOP (PWP) PowerPAD
package, which eliminates bulky heatsinks. Texas
Instruments provides evaluation modules and the
SWIFT designer software tool to aid in quickly achieving
high-performance power supply designs to meet
aggressive equipment development cycles.

APPLICATIONS

D Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs, and
Microprocessors

D Automotive Systems

− Navigation Units

− Entertainment Modules

− Satellite Radio

D Industrial High-Density Systems With Power

Distributed at 5 V or 3.3 V

ORDERING INFORMATION

PACKAGED DEVICES

T

J

−40°C to 125°C 0.9 V to 3.3 V TPS54310QPWPRQ1

(1)

The PWP package is taped and reeled as indicated by the R suffix to the device type (i.e., TPS54310QPWPRQ1). See the Application section
of the data sheet for PowerPAD drawing and layout information.

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and SWIFT are trademarks of T exas Instruments.

  #$%&'()*#&$ # +,''-$* ) &% .,/0#+)*#&$ 1)*-2 '&1,+*
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OUTPUT VOLTAGE

PLASTIC HTSSOP

Copyright  2007, Texas Instruments Incorporated

(PWP)

(1)



Input voltage range, V

Output voltage range, V

Source current, I

Sink current

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

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Simplified Schematic

Input Output

VIN

TPS54310

VBIAS

BOOT
PGND

COMP

VSENSE

AGND

PH

Compensation
Network

96

94

92

90

88

86

Efficiency − %

84

82

80

0 0.5 1 1.5 2 2.5 3

EFFICIENCY

LOAD CURRENT

TA = 25°C
VI = 5 V
VO = 3.3 V

Load Current − A

vs

ABSOLUTE MAXIMUM RATINGS

over operat i n g f ree-air temperature range unless otherwise noted

VIN, SS/ENA, FSEL −0.3 to 7 V
RT −0.3 to 6 V

I

VSENSE −0.3 to 4 V
BOOT −0.3 to 17 V
VBIAS, PWRGD, COMP −0.3 to 7 V

O

PH −0.6 to 10 V
PH Internally Limited

O

COMP, VBIAS 6 mA
PH 6 A

Sink current

COMP 6 mA
SS/ENA,PWRGD 10 mA

Voltage dif ferential AGND to PGND ±0.3 V
Continuous power dissipation
Operating virtual junction temperature range, T

Storage temperature, T

stg

J

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

(1)

TPS54310-Q1 UNIT

See Power Dissipation

Rating Table

−40 to 150 °C

−65 to 150 °C

2

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RECOMMENDED OPERATING CONDITIONS

Input voltage range, V
Operating junction temperature, T

I

J



SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

MIN NOM MAX UNIT

3 6 V

−40 125 °C

PACKAGE DISSIPATION RATINGS

PACKAGE

20-pin PWP with solder 26°C/W 3.85 W

20-pin PWP without solder 57.5°C/W 1.73 W 0.96 W 0.69 W

(1)

For more information on the PWP package, see the Texas Instruments technical brief (SLMA002).

(2)

Test board conditions:

1. 3” × 3”, 2 layers, Thickness: 0.062”

2. 1.5 oz copper traces located on the top of the PCB

3. 1.5 oz copper ground plane on the bottom of the PCB

4. Ten thermal vias (see the recommended land pattern in application section of this data sheet)

(3)

Maximum power dissipation may be limited by overcurrent protection.

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

(1) (2)

TA = 25°C

POWER RATING

(3)

TA = 70°C

POWER RATING

2.12 W 1.54 W

TA = 85°C

POWER RATING

3



V

V

Line regulation

(1) (3)

%/V

Load regulation

(1) (3)

%/A

Internally set free-running frequency range

kHz

Externally set free-running frequency range

kHz

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS

TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE, VIN

VIN input voltage range 3 6 V

fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase
pin open

Quiescent current

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO 2.95 3
Stop threshold voltage, UVLO 2.7 2.8
Hysteresis voltage, UVLO 0.16 V
Rising and falling edge deglitch, UVLO

BIAS VOLTAGE

O

CUMULATIVE REFERENCE

V

ref

REGULATION

OSCILLATOR

(1)
(2)
(3)
(4)

Output voltage, VBIAS I
Output current, VBIAS

Accuracy

Externally set free-running frequency range

High-level threshold voltage, FSEL 2.5 V
Low-level threshold voltage, FSEL 0.8 V
Pulse duration, FSEL
Frequency range, FSEL
Ramp valley
Ramp amplitude (peak-to-peak)
Minimum controllable on time
Maximum duty cycle

Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10.
To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1kΩ and
C ≤ 120 pF.

(1)

(1)

(2)

(1)

(1) (4)

(1)

(1)

(1)

(1)

fs = 550 kHz, FSEL ≥ 2.5 V, RT open, phase
pin open

Shutdown, SS/ENA = 0 V 1 1.4

= 0 2.7 2.8 2.95 V

(VBIAS)

0.882 0.891 0.900 V

IL = 1.5 A, fs = 350 kHz, TJ = 125°C 0.07
IL = 1.5 A, fs = 550 kHz, TJ = 125°C 0.07
IL = 0 A to 3 A, fs = 350 kHz, TJ = 125°C 0.03
IL = 0 A to 3 A, fs = 550 kHz, TJ = 125°C 0.03

FSEL ≤ 0.8 V, RT open 265 350 440
FSEL ≥ 2.5 V, RT open 415 550 680

(1)

(1)

252 280 308

663 700 762

330 700 kHz

90%

RT = 180 kΩ (1% resistor to AGND)
RT = 160 kΩ (1% resistor to AGND) 290 312 350
RT = 68 kΩ (1% resistor to AGND)

6.2 9.6

8.4 12.8

2.5 µs

50 ns

0.75 V
1 V

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mA

100 µA

kHz

200 ns

4

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Current limit trip point

A

r

Power MOSFET switches

m

ELECTRICAL CHARACTERISTICS (continued)

TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ERROR AMPLIFIER

Error amplifier open loop voltage gain 1-kΩ COMP to AGND
Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND
Error amplifier common-mode input voltage

range

I

IB

V

O

PWM COMPARATOR

SLOW-START/ENABLE

POWER GOOD

CURRENT LIMIT

THERMAL SHUTDOWN

OUTPUT POWER MOSFETS

DS(on)

(1)
(2)

Input bias current, VSENSE
Output voltage slew rate (symmetric),

(1)

COMP

PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
dead time)

Enable threshold voltage, SS/ENA 0.82 1.2 1.4 V
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA
Internal slow-start time
Charge current, SS/ENA SS/ENA = 0 V 2.5 5 8 µA
Discharge current, SS/ENA SS/ENA = 0.2 V , VI = 2.7 V 1.2 2.3 4 mA

Power good threshold voltage VSENSE falling 90 %V
Power good hysteresis voltage
Power good falling edge deglitch
Output saturation voltage, PWRGD I
Leakage current, PWRGD VI = 5.5 V 1 µA

Current limit leading edge blanking time 100 ns
Current limit total response time 200 ns

Thermal shutdown trip point
Thermal shutdown hysteresis

Specified by design
Matched MOSFETs, low side r

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

production tested, high side r

DS(on)

Powered by internal LDO
VSENSE = V

10-mV overdrive

= 2.5 mA 0.18 0.3 V

(sink)

VI = 3 V , output shorted
VI = 6 V , output shorted

IO = 3 A, VI = 6 V
IO = 3 A, VI = 3 V

(1)

ref

(1)

specified by design

DS(on)



SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

90 110 dB

(1)

(1)

(1)
(1)

(2)
(2)

3 5 MHz
0 VBIAS V

60 250 nA

1 1.4 V/µs

70 85 ns

0.03 V

2.5 µs

2.6 3.35 4.1 ms

3 %V

35 µs

4 6.5

4.5 7.5

135 150 165 °C

10 °C

59 88
85 136

ref
ref

Ω

5



PWP PACKAGE

DESCRIPTION

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

PIN ASSIGNMENTS

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(TOP VIEW)

AGND

VSENSE

COMP

PWRGD

BOOT

PH
PH
PH
PH
PH

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND

Terminal Functions

TERMINAL

NAME NO.

AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor, and

BOOT 5 Bootstrap input. A 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

COMP 3 Error amplifier output. Connect the compensation network from COMP to VSENSE.
PGND 11−13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the

PH 6−10 Phase input/output. Junction of the internal high and low-side power MOSFETs and output inductor.
PWRGD 4 Power good open drain output. High when VSENSE ≥ 90% V

RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency , fs.
SS/ENA 18 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor

FSEL 19 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select

VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

VIN 14−16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to the device

VSENSE 2 Error amplifier inverting input.

FSEL pin. Make PowerPAD connection to AGND.

high-side FET driver.

input and output supply returns and negative terminals of the input and output capacitors.

, otherwise PWRGD is low. Note that output is low when

SS/ENA is low or internal shutdown signal active.

input to externally set the start-up time.

between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.

quality, low ESR 0.1-µF to 1-µF ceramic capacitor.

package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.

ref

6

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FUNCTIONAL BLOCK DIAGRAM



SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

SS/ENA

VIN

Enable

Comparator

1.2 V
Hysteresis: 0.03

V

VIN UVLO

Comparator

VIN

2.95 V
Hysteresis: 0.16

V

Internal/External

VREF = 0.891 V

TPS54310

Slow-start

Reference

(Internal Slow-start Time = 3.35 ms

Falling

Edge

Deglitch

2.5 µs

Falling

and

Rising

Edge

Deglitch

2.5 µs

Thermal

Shutdown

150°C

+

−
Error

Amplifier

SS_DIS

PWM

Comparator

OSC

RTCOMPVSENSE

SHUTDOWN

Leading

Edge

Blanking

100 ns

RQ
S

Powergood

Comparator

VSENSE

0.90 V

ref

Hysteresis: 0.03 Vref

FSEL

AGND

VBIAS

ILIM

Comparator

SHUTDOWN

Adaptive Dead-Time

Control Logic

SHUTDOWN

and

VIN

VBIAS

Falling

Deglitch

REG

Edge

35 µs

30 mΩ

30 mΩ

VIN

BOOT

PH

PGND

PWRGD

L

OUT

C

3 − 6 V

O

V

O

ADDITIONAL 3-A SWIFT DEVICES

DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE

TPS54311 0.9 V TPS54313 1.5 V TPS54315 2.5 V
TPS54312 1.2 V TPS54314 1.8 V TPS54316 3.3 V

RELATED DC/DC PRODUCTS

D UCC3585—dc/dc controller
D PT5500 series—3-A plug-in modules
D TPS757XX—3-A low dropout regulator

7



Figure 1

Drain-Source On-State Resistance −

E

Figure 2

Drain-Source On-State Resistance −

E

Figure 3

INTERNALLY SET OSCILLATOR

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

TYPICAL CHARACTERISTICS

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DRAIN-SOURCE ON-STATE RESISTANC

vs

JUNCTION TEMPERATURE

120

Ω

VI = 3.3 V

100

80

60

40

20

0

−40 0 25 85 125

TJ − Junction Temperature − °C

IO = 3 A

EXTERNALLY SET OSCILLATOR

FREQUENCY

vs

JUNCTION TEMPERATURE

800

700

600

500

400

300

200

f − Externally Set Oscillator Frequency − kHz

−40 0 25

RT = 68 k

RT = 100 k

RT = 180 k

85 125

TJ − Junction Temperature − °C

Figure 4

DRAIN-SOURCE ON-STATE RESISTANC

vs

JUNCTION TEMPE R ATURE

100

Ω

VI = 5 V

80

60

40

20

0

−40 0 25 85 125

TJ − Junction Temperature − °C

IO = 3 A

VOLTAGE REFERENCE

vs

JUNCTION TEMPE R ATURE

0.895

0.893

0.891

0.889

− Voltage Reference − V
ref

0.887

V

0.885

−40 0 25

TJ − Junction Temperature − °C

85 125

Figure 5

FREQUENCY

vs

JUNCTION TEMPE R ATURE

750

650

550

450

350

f − Internally Set Oscillator Frequency −kHz

250

−40 0 25

FSEL ≥ 2.5 V

FSEL ≤ 0.8 V

85 125

TJ − Junction Temperature − °C

OUTPUT VOLTAGE REGULATION

vs

INPUT VOLTAGE

0.8950

0.8930

0.8910

0.8890

0.8870

− Output Voltage Regulation − V
O

V

0.8850

TA = 85°C

f = 350 kHz

3456

VI − Input Voltage − V

Figure 6

ERROR AMPLIFIER

OPEN LOOP RESPONSE

140

120

100

80

60

Gain − dB

40

20

0

−20
0 10 100 1 k 10 k 100 k 1 M

8

RL= 10 kΩ,
CL = 160 pF,
TA = 25°C

Phase

Gain

f − Frequency − Hz

Figure 7

INTERNAL SLOW-START TIME

vs

JUNCTION TEMPE R ATURE

0

−20

−40

−60

−80

−100

−120

−140

−160

−180

−200

10 M

3.80

3.65

3.50

3.35

3.20

Phase − Degrees

3.05

Internal Slow-Start Time − ms

2.90

2.75

−40 0 25 85

TJ − Junction Temperature − °C

Device Power Losses − W

125

Figure 8

DEVICE POWER LOSSES

vs

LOAD CURRENT

2.25
TJ − 125°C

2

fs = 700 kHz

1.75

1.5

1.25

1

0.75

0.5

0.25

0

01234

VI = 3.3 V

VI = 5 V

IL − Load Current − A

Figure 9

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APPLICATION INFORMATION

Figure 10 shows the schematic diagram for a typical
TPS54310 application. The TPS54310 (U1) can provide
up to 3 A of output current at a nominal output voltage of

VIN

J1

2

V

GND

1

I

1

Optional

C2

1

C3

0.1 µF

+

PWRGD

R1
10 kΩ

C4
100 pF

71.5 kΩ

C5
3900 pF

R2

3.74 kΩ

R3

R4

3.74 kΩ

TPS54310PWP

20

RT

19

FSEL

18

SS/ENA

17

VBIAS

4

PWRGD

3

COMP

2

VSENSE

1

AGND

U1

PwrPAD

C6

2700 pF



SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

3.3 V. For proper thermal performance, the power pad
underneath the TPS54310 integrated circuit needs to be
soldered well to the printed circuit board.

C8

L1

1.2 µH

10 µF

+

R7

49.9 Ω

C9
180 µF
4 V

C11
1000 pF

VIN
VIN
VIN

PH
PH
PH
PH
PH

BOOT
PGND
PGND
PGND

R5

10 kΩ

16
15
14
10
9
8
7
6
5
13
12
11

R6

732 Ω

C7

0.047 µF

J3

1

V

O

2

GND

Figure 10. TPS54310 Schematic

INPUT VOLTAGE

The input to the circuit is a nominal 5 VDC, applied at J1.
The optional input filter (C2) is a 220-µF POSCAP
capacitor, with a maximum allowable ripple current of 3 A.
C8 is the decoupling capacitor for the TPS54310 and must
be located as close to the device as possible.

FEEDBACK CIRCUIT

The resistor divider network of R5 and R4 sets the output
voltage for the circuit at 3.3 V. R5, along with R2, R6, C4,
C5, and C6 forms the loop compensation network for the
circuit. For this design, a Type 3 topology is used.

OPERATING FREQUENCY

In the application circuit, the 350-kHz operation is selected
by leaving RT and FSEL open. Connecting a 68-kΩ to
180-kΩ resistor between RT (pin 20) and analog ground
can be used to set the switching frequency from 280 kHz
to 700 kHz. To calculate the RT resistor, use
equation 1:

100 kW

R +

ƒ

SW

500 kHz

(1)

OUTPUT FILTER

The output filter is composed of a 1.2-µH inductor and
180-µF capacitor. The inductor is a low dc-resistance
(0.017 Ω) type, Coilcraft DO1813P-122HC. The capacitor
used is a 4-V special polymer type with a maximum ESR
of 0.015 Ω. The feedback loop is compensated so that the
unity gain frequency is approximately 75 kHz.

GROUNDING AND PowerPAD LAYOUT

The TPS54310 has two internal grounds (analog and
power). Inside the TPS54310, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerP AD must be tied
directly to AGND. Noise injected between the two grounds
can degrade the performance of the TPS54310,
particularly at higher output currents. However, ground
noise on a n analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground planes are
recommended. These two planes should tie together
directly at the IC to reduce noise between the two grounds.
The only components that should tie directly to the power
ground plane are the input capacitor, the output capacitor,
the input voltage decoupling capacitor, and the PGND pins
of the TPS54310. The layout of the TPS54310 evaluation
module is representative of a recommended layout for a

9



ÓÓÓ

ÓÓÓ

ÓÓÓ

ÓÓÓ

ÓÓÓ

ÓÓÓ

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

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2-layer board. Documentation for the TPS54310
evaluation module can be found on the Texas Instruments
web site under the TPS54310 product folder and in the
application note (SLVA109).

LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE

For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A
3 inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory , depending on ambient temperature
and airflow. Most applications have larger areas of internal

6 PL ∅ 0.0130

4 PL ∅ 0.0180

Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance

0.0227

0.0600

0.2454

0.2560

Minimum Recommended Top

Side Analog Ground Area

0.0400

0.0400

0.0600

ground plane available and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 3 A or greater
operation is desired. Connection from the exposed area of
the PowerP AD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Six vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the 10 recommended that
enhance thermal performance should be included in areas
not under the device package.

Minimum Recommended Thermal Vias: 6 × 0.013 dia.
Inside Powerpad Area 4 × 0.018 dia. Under Device as
Shown. Additional 0.018 dia. Vias May be Used if Top Side
Analog Ground Area is Extended.

0.0150

0.06

0.1010

0.0256

0.1700

0.1340

0.0620

0.0400

Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area

Figure 11. Recommended Land Pattern for 20-Pin PWP PowerPAD

10

www.ti.com

Figure 15

OUTPUT RIPPLE VOLTAGE

LOAD TRANSIENT RESPONSE

SLOW-START TIMING



SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

PERFORMANCE GRAPHS

EFFICIENCY

vs

OUTPUT CURRENT

100

VI = 4 V

95

90

85

80

Efficiency − %

75

70

65

012345

VI = 5 V

VI = 6 V

IO − Output Current − A

Figure 12

VO (AC)
10 mV/div

OUTPUT VOLTAGE

vs

LOAD CURRENT

3.4

3.38

3.36

3.34

3.32

3.3

− Output Voltage − %
O

3.28

V

3.26

3.24
012345

IL − Load Current − A

TA = 25°C
VI = 5 V

Figure 13

VI = 5 V
40 µs/div

VO (AC)
50 mV/div

60

40

20

Gain − dB

0

−20

−40

LOOP RESPONSE

Phase

Gain

TA = 25°C

100 1 k 10 k 100 k 1 M

f − Frequency − Hz

Figure 14

VI 2 V/div

VO 2 V/div

135

90

45

0

Phase − Degrees

−45

−90

VI = 5 V
IO = 3 A
400 ns/div

I

O

2 A/div

Figure 16

AMBIENT TEMPERATURE

vs

LOAD CURRENT

125
115

C

°

105

95
85
75
65
55

− Ambient Temperature −

45

A

T

35
25

†

The safe operating area is applicable to the test board

Safe Operating Area

01234

IL − Load Current − A

VI = 5 V

VI = 3.3 V

†

conditions listed in the Dissipation Rating Table section of
this data sheet.

Figure 18

V

PWRGD

Figure 17

5 V/div

1 ms/div

11



SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

www.ti.com

DETAILED DESCRIPTION

Under Voltage Lock Out (UVLO)

The TPS54310 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of

2.8 V. Hysteresis in the UVLO comparator and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.

Slow-Start/Enable (SS/ENA)

The slow-start/enable pin provides two functions; first, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.

The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND. Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between release
of the SS/ENA pin and start up of the output. The delay is
proportional t o the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:

+ C

(SS)

1.2 V
5 mA

0.7 V
5 mA

(2)

(3)

td+ C

(SS)

Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:

t

(SS)

The actual slow-start is likely to be less than the above
approximation due to the brief ramp-up at the internal rate.

VBIAS Regulator (VBIAS)

The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND. External loading
on VBIAS is allowed, with the caution that internal circuits
require a minimum VBIAS of 2.7 V, and external loads on
VBIAS with ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a reference
voltage for external circuits.

Voltage Reference

The voltage reference system produces a precise V

ref

signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54310, since it cancels
offset errors in the scale and error amplifier circuits.

Oscillator and PWM Ramp

The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the FSEL pin as a static
digital input. If a different frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 kHz to 700 kHz by connecting
a resistor to the RT pin to ground and floating the FSEL pin.
The switching frequency is approximated by the following
equation, where R is the resistance from RT to AGND:

SWITCHING FREQUENCY +

100 kW

R

500 kHz

(4)

External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into FSEL and connecting a
resistor from R T to AGND. Choose an R T resistor that sets
the free-running frequency to 80% of the synchronization
signal. Table 1 summarizes the frequency selection
configurations.

Table 1. Summary of the Frequency Selection

Configurations

SWITCHING

FREQUENCY

350 kHz, internally
set

550 kHz, internally
set

Externally set
280 kHz to 700 kHz

Externally
synchronized
frequency

(1)

(1)

T o ensure proper operation when RC filter is used between external
clock and FSEL pin, the recommended values are R ≤ 1 kΩ and
C ≤ 120 pF.

FSEL PIN RT PIN

Float or AGND Float

≥ 2.5 V Float

Float R = 68 kΩ to 180 kΩ

Synchronization
signal

R = RT value for 80% of
external synchronization
frequency

12

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

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

Error Amplifier

The high performance, wide bandwidth, voltage error
amplifier sets the TPS54310 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type 2 or Type 3
compensation can be employed using external
compensation components.

PWM Control

Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse duration.
During this period, the PWM ramp discharges rapidly to its
valley voltage. When the ramp begins to charge back up,
the low-side FET turns off and high-side FET turns on. As
the PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET . The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.

During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as V

. If the error

ref

amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54310 is capable of sinking current continuously
until the output reaches the regulation set-point.

If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.

Dead-Time Control and MOSFET Drivers

Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the

turn-on times of the MOSFET drivers. The high-side driver
does not turn on until the gate drive voltage to the low-side
FET is below 2 V. The low-side driver does not turn on until
the voltage at the gate of the high-side MOSFETs is below
2 V. The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive ef ficiency and
reduces external component count.

Overcurrent Protection

The cycle by cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
differential amplifier and comparing it to the preset
overcurrent threshold. The high-side MOSFET is turned
off within 200 ns of reaching the current limit threshold. A
100-ns leading edge blanking circuit prevents false
tripping of the current limit. Current limit detection occurs
only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current
sink operation is provided by thermal shutdown.

Thermal Shutdown

The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point and starts up
under control of the slow-start circuit. Thermal shutdown
provides protection when an overload condition is
sustained for several milliseconds. With a persistent fault
condition, the device cycles continuously; starting up by
control of the soft-start circuit, heating up due to the fault,
and then shutting down upon reaching the thermal
shutdown point.

Power Good (PWRGD)

The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or
thermal shutdown is asserted. When VIN = UVLO
threshold, SS/ENA = enable threshold, and VSENSE >
90% of V
high. A hysteresis voltage equal to 3% of V

, the open drain output of the PWRGD pin is

ref

and a 35-µs

ref

falling edge deglitch circuit prevent tripping of the power
good comparator due to high frequency noise.

13

PACKAGE OPTION ADDENDUM

www.ti.com

15-Feb-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

TPS54310QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1

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