Texas Instruments TPS 54310 – Q 1 INSTALLATION INSTRUCTIONS

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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FEATURES

D Qualification in Accordance With AEC-Q100
D Qualified for Automotive Applications
D Customer-Specific Configuration Control Can

Be Supported Along With Major-Change
Approval

D 60-mΩ MOSFET Switches for High Efficiency

at 3-A Continuous Output Source or Sink
Current

D 0.9-V to 3.3-V Adjustable Output Voltage With

1% Accuracy

D Externally Compensated for Design Flexibility
D Fast Transient Response
D Wide PWM Frequency: Fixed 350 kHz,

550 kHz, or Adjustable 280 kHz to 700 kHz

D Load Protected by Peak Current Limit and

Thermal Shutdown

D Integrated Solution Reduces Board Area and

Total Cost

(1)

Contact Texas Instruments for details. Q100 qualification data
available on request.

(1)

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

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DESCRIPTION

As members of the SWIFT family of dc/dc regulators,
the TPS54310 low-input-voltage high-output-current
synchronous-buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high-performance,
voltage error amplifier that provides high performance
under transient conditions, an undervoltage-lockout
circuit to prevent start up until the input voltage reaches
3 V, an internally and externally set slow-start circuit to
limit in-rush currents, and a power good output useful
for processor/logic reset, fault signaling, and supply
sequencing.

The TPS54310 device is available in a thermally
enhanced 20-pin TSSOP (PWP) PowerPAD
package, which eliminates bulky heatsinks. Texas
Instruments provides evaluation modules and the
SWIFT designer software tool to aid in quickly achieving
high-performance power supply designs to meet
aggressive equipment development cycles.

APPLICATIONS

D Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs, and
Microprocessors

D Automotive Systems

− Navigation Units

− Entertainment Modules

− Satellite Radio

D Industrial High-Density Systems With Power

Distributed at 5 V or 3.3 V

ORDERING INFORMATION

PACKAGED DEVICES

T

J

−40°C to 125°C 0.9 V to 3.3 V TPS54310QPWPRQ1

(1)

The PWP package is taped and reeled as indicated by the R suffix to the device type (i.e., TPS54310QPWPRQ1). See the Application section
of the data sheet for PowerPAD drawing and layout information.

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and SWIFT are trademarks of T exas Instruments.

  #$%&'()*#&$ # +,''-$* ) &% .,/0#+)*#&$ 1)*-2 '&1,+*
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OUTPUT VOLTAGE

PLASTIC HTSSOP

Copyright  2007, Texas Instruments Incorporated

(PWP)

(1)



Input voltage range, V

Output voltage range, V

Source current, I

Sink current

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

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Simplified Schematic

Input Output

VIN

TPS54310

VBIAS

BOOT
PGND

COMP

VSENSE

AGND

PH

Compensation
Network

96

94

92

90

88

86

Efficiency − %

84

82

80

0 0.5 1 1.5 2 2.5 3

EFFICIENCY

LOAD CURRENT

TA = 25°C
VI = 5 V
VO = 3.3 V

Load Current − A

vs

ABSOLUTE MAXIMUM RATINGS

over operat i n g f ree-air temperature range unless otherwise noted

VIN, SS/ENA, FSEL −0.3 to 7 V
RT −0.3 to 6 V

I

VSENSE −0.3 to 4 V
BOOT −0.3 to 17 V
VBIAS, PWRGD, COMP −0.3 to 7 V

O

PH −0.6 to 10 V
PH Internally Limited

O

COMP, VBIAS 6 mA
PH 6 A

Sink current

COMP 6 mA
SS/ENA,PWRGD 10 mA

Voltage dif ferential AGND to PGND ±0.3 V
Continuous power dissipation
Operating virtual junction temperature range, T

Storage temperature, T

stg

J

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

(1)

TPS54310-Q1 UNIT

See Power Dissipation

Rating Table

−40 to 150 °C

−65 to 150 °C

2

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RECOMMENDED OPERATING CONDITIONS

Input voltage range, V
Operating junction temperature, T

I

J

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SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

MIN NOM MAX UNIT

3 6 V

−40 125 °C

PACKAGE DISSIPATION RATINGS

PACKAGE

20-pin PWP with solder 26°C/W 3.85 W

20-pin PWP without solder 57.5°C/W 1.73 W 0.96 W 0.69 W

(1)

For more information on the PWP package, see the Texas Instruments technical brief (SLMA002).

(2)

Test board conditions:

1. 3” × 3”, 2 layers, Thickness: 0.062”

2. 1.5 oz copper traces located on the top of the PCB

3. 1.5 oz copper ground plane on the bottom of the PCB

4. Ten thermal vias (see the recommended land pattern in application section of this data sheet)

(3)

Maximum power dissipation may be limited by overcurrent protection.

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

(1) (2)

TA = 25°C

POWER RATING

(3)

TA = 70°C

POWER RATING

2.12 W 1.54 W

TA = 85°C

POWER RATING

3



V

V

Line regulation

(1) (3)

%/V

Load regulation

(1) (3)

%/A

Internally set free-running frequency range

kHz

Externally set free-running frequency range

kHz

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS

TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE, VIN

VIN input voltage range 3 6 V

fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase
pin open

Quiescent current

UNDER VOLTAGE LOCK OUT

Start threshold voltage, UVLO 2.95 3
Stop threshold voltage, UVLO 2.7 2.8
Hysteresis voltage, UVLO 0.16 V
Rising and falling edge deglitch, UVLO

BIAS VOLTAGE

O

CUMULATIVE REFERENCE

V

ref

REGULATION

OSCILLATOR

(1)
(2)
(3)
(4)

Output voltage, VBIAS I
Output current, VBIAS

Accuracy

Externally set free-running frequency range

High-level threshold voltage, FSEL 2.5 V
Low-level threshold voltage, FSEL 0.8 V
Pulse duration, FSEL
Frequency range, FSEL
Ramp valley
Ramp amplitude (peak-to-peak)
Minimum controllable on time
Maximum duty cycle

Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10.
To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1kΩ and
C ≤ 120 pF.

(1)

(1)

(2)

(1)

(1) (4)

(1)

(1)

(1)

(1)

fs = 550 kHz, FSEL ≥ 2.5 V, RT open, phase
pin open

Shutdown, SS/ENA = 0 V 1 1.4

= 0 2.7 2.8 2.95 V

(VBIAS)

0.882 0.891 0.900 V

IL = 1.5 A, fs = 350 kHz, TJ = 125°C 0.07
IL = 1.5 A, fs = 550 kHz, TJ = 125°C 0.07
IL = 0 A to 3 A, fs = 350 kHz, TJ = 125°C 0.03
IL = 0 A to 3 A, fs = 550 kHz, TJ = 125°C 0.03

FSEL ≤ 0.8 V, RT open 265 350 440
FSEL ≥ 2.5 V, RT open 415 550 680

(1)

(1)

252 280 308

663 700 762

330 700 kHz

90%

RT = 180 kΩ (1% resistor to AGND)
RT = 160 kΩ (1% resistor to AGND) 290 312 350
RT = 68 kΩ (1% resistor to AGND)

6.2 9.6

8.4 12.8

2.5 µs

50 ns

0.75 V
1 V

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mA

100 µA

kHz

200 ns

4

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Current limit trip point

A

r

Power MOSFET switches

m

ELECTRICAL CHARACTERISTICS (continued)

TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ERROR AMPLIFIER

Error amplifier open loop voltage gain 1-kΩ COMP to AGND
Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND
Error amplifier common-mode input voltage

range

I

IB

V

O

PWM COMPARATOR

SLOW-START/ENABLE

POWER GOOD

CURRENT LIMIT

THERMAL SHUTDOWN

OUTPUT POWER MOSFETS

DS(on)

(1)
(2)

Input bias current, VSENSE
Output voltage slew rate (symmetric),

(1)

COMP

PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
dead time)

Enable threshold voltage, SS/ENA 0.82 1.2 1.4 V
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA
Internal slow-start time
Charge current, SS/ENA SS/ENA = 0 V 2.5 5 8 µA
Discharge current, SS/ENA SS/ENA = 0.2 V , VI = 2.7 V 1.2 2.3 4 mA

Power good threshold voltage VSENSE falling 90 %V
Power good hysteresis voltage
Power good falling edge deglitch
Output saturation voltage, PWRGD I
Leakage current, PWRGD VI = 5.5 V 1 µA

Current limit leading edge blanking time 100 ns
Current limit total response time 200 ns

Thermal shutdown trip point
Thermal shutdown hysteresis

Specified by design
Matched MOSFETs, low side r

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

production tested, high side r

DS(on)

Powered by internal LDO
VSENSE = V

10-mV overdrive

= 2.5 mA 0.18 0.3 V

(sink)

VI = 3 V , output shorted
VI = 6 V , output shorted

IO = 3 A, VI = 6 V
IO = 3 A, VI = 3 V

(1)

ref

(1)

specified by design

DS(on)



SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

90 110 dB

(1)

(1)

(1)
(1)

(2)
(2)

3 5 MHz
0 VBIAS V

60 250 nA

1 1.4 V/µs

70 85 ns

0.03 V

2.5 µs

2.6 3.35 4.1 ms

3 %V

35 µs

4 6.5

4.5 7.5

135 150 165 °C

10 °C

59 88
85 136

ref
ref

Ω

5

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PWP PACKAGE

DESCRIPTION

SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007

PIN ASSIGNMENTS

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(TOP VIEW)

AGND

VSENSE

COMP

PWRGD

BOOT

PH
PH
PH
PH
PH

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND

Terminal Functions

TERMINAL

NAME NO.

AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor, and

BOOT 5 Bootstrap input. A 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

COMP 3 Error amplifier output. Connect the compensation network from COMP to VSENSE.
PGND 11−13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the

PH 6−10 Phase input/output. Junction of the internal high and low-side power MOSFETs and output inductor.
PWRGD 4 Power good open drain output. High when VSENSE ≥ 90% V

RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency , fs.
SS/ENA 18 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor

FSEL 19 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select

VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

VIN 14−16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to the device

VSENSE 2 Error amplifier inverting input.

FSEL pin. Make PowerPAD connection to AGND.

high-side FET driver.

input and output supply returns and negative terminals of the input and output capacitors.

, otherwise PWRGD is low. Note that output is low when

SS/ENA is low or internal shutdown signal active.

input to externally set the start-up time.

between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.

quality, low ESR 0.1-µF to 1-µF ceramic capacitor.

package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.

ref

6