Texas Instruments TPS51716RUKR Schematic [ru]
12
17
16
6
15
14
13
11
V5IN
TPS51716
S3
S5
VREF
VBST
DRVH
SW
DRVL
8
10
REFIN
PGND
7
19
GND
MODE
18 TRIP
20
9
2
3
PGOOD
VDDQSNS
VLDOIN
VTT
1
4
5
VTTSNS
VTTGND
VTTREF
UDG-12146
VDDQ
VTT
PGND
S3
S5
PGND
5VIN
PGND
VIN
VTTREF
AGNDAGND
Powergood
PGND
TPS51716
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Complete DDR2, DDR3, DDR3L, and LPDDR3 Memory Power Solution
Synchronous Buck Controller, 2-A LDO, with Buffered Reference
Check for Samples: TPS51716
1
FEATURES
2
• Synchronous Buck Controller (VDDQ)
– Conversion Voltage Range: 3 V to 28 V
– Output Voltage Range: 0.7 V to 1.8 V
– 0.8% V
– D-CAP2™ Mode for Ceramic Output
Capacitors
– Selectable 500 kHz/670 kHz Switching
Frequencies
– Optimized Efficiency at Light and Heavy
Loads with Auto-skip Function
– Supports Soft-Off in S4/S5 States
– OCL/OVP/UVP/UVLO Protections dedicated LDO supply input.
– Powergood Output
• 2-A LDO(VTT), Buffered Reference(VTTREF)
– 2-A (Peak) Sink and Source Current
– Requires Only 10-μF of Ceramic Output
Capacitance
– Buffered, Low Noise, 10-mA VTTREF
Output
– 0.8% VTTREF, 20-mV VTT Accuracy
– Support High-Z in S3 and Soft-Off in S4/S5
• Thermal Shutdown
• 20-Pin, 3 mm × 3 mm, QFN Package
Accuracy
REF
DESCRIPTION
The TPS51716 provides a complete power supply for
DDR2, DDR3, DDR3L, and LPDDR3 memory
systems in the lowest total cost and minimum space.
It integrates a synchronous buck regulator controller
(VDDQ) with a 2-A sink/source tracking LDO (VTT)
and buffered low noise reference (VTTREF). The
TPS51716 employs D-CAP2™ mode coupled with
500 kHz or 670 kHz operating frequencies that
supports ceramic output capacitors without an
external compensation circuit. The VTTREF tracks
VDDQ/2 with excellent 0.8% accuracy. The VTT,
which provides 2-A sink/source peak current
capabilities, requires only 10-μF of ceramic
capacitance. In addition, the device features a
The TPS51716 provides rich, useful functions as well
as excellent power supply performance. It supports
flexible power state control, placing VTT at high-Z in
S3 and discharging VDDQ, VTT and VTTREF (softoff) in S4/S5 state. It includes programmable OCL
with low-side MOSFET R
OVP/UVP/UVLO and thermal shutdown protections.
TI offers the TPS51716 in a 20-pin, 3 mm × 3 mm,
QFN package and specifies it for an ambient
temperature range between –40°C and 85°C.
TPS51716
SLUSB94 –OCTOBER 2012
DS(on)
sensing,
APPLICATIONS
• DDR2/DDR3/DDR3L/LPDDR3 Memory Power
Supplies
• SSTL_18, SSTL_15, SSTL_135 and HSTL
Termination
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
2D-CAP2, NexFET are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2012, Texas Instruments Incorporated
TPS51716
SLUSB94 –OCTOBER 2012
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ORDERING INFORMATION
T
A
PACKAGE PINS
–40°C to 85°C Plastic Quad Flat Pack (QFN) 20
ORDERABLE DEVICE OUTPUT MINIMUM
NUMBER SUPPLY QUANTITY
TPS51716RUKR Tape and reel 3000
TPS51716RUKT Mini reel 250
(1)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
MIN MAX
VBST –0.3 36
(3)
VBST
SW –5 30
Input voltage range
(2)
VLDOIN, VDDQSNS, REFIN –0.3 3.6 V
VTTSNS –0.3 3.6
PGND, VTTGND –0.3 0.3
V5IN, S3, S5, TRIP, MODE –0.3 6
DRVH –5 36
(3)
DRVH
VTTREF, VREF –0.3 3.6
Output voltage range
(2)
VTT –0.3 3.6
DRVL –0.3 6
PGOOD –0.3 6
Junction temperature range, T
Storage temperature range, T
J
STG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
–0.3 6
–0.3 6
V
125 °C
–55 150 °C
THERMAL INFORMATION
TPS51716
THERMAL METRIC UNITS
θ
θ
θ
ψ
ψ
θ
JA
JCtop
JB
JT
JB
JCbot
Junction-to-ambient thermal resistance 94.1
Junction-to-case (top) thermal resistance 58.1
Junction-to-board thermal resistance 64.3
Junction-to-top characterization parameter 31.8
Junction-to-board characterization parameter 58.0
Junction-to-case (bottom) thermal resistance 5.9
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RUK
(20) PINS
°C/W
TPS51716
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RECOMMENDED OPERATING CONDITIONS
MIN TYP MAX UNIT
Supply voltage V5IN 4.5 5.5 V
VBST –0.1 33.5
(1)
VBST
SW -3 28
(2)
Input voltage range V
SW
VLDOIN, VDDQSNS, REFIN –0.1 3.5
VTTSNS –0.1 3.5
PGND, VTTGND –0.1 0.1
S3, S5, TRIP, MODE –0.1 5.5
DRVH –3 33.5
(1)
DRVH
(2)
DRVH
Output voltage range VTTREF, VREF –0.1 3.5 V
VTT –0.1 3.5
DRVL –0.1 5.5
PGOOD –0.1 5.5
T
A
Operating free-air temperature –40 85 °C
(1) Voltage values are with respect to the SW terminal.
(2) This voltage should be applied for less than 30% of the repetitive period.
–0.1 5.5
–4.5 28
–0.1 5.5
–4.5 33.5
SLUSB94 –OCTOBER 2012
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3
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TPS51716
SLUSB94 –OCTOBER 2012
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, V
(unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
I
V5IN(S0)
I
V5IN(S3)
I
V5INSDN
I
VLDOIN(S0)
I
VLDOIN(S3)
I
VLDOINSDN
VREF OUTPUT
V
VREF
I
VREFOCL
VTTREF OUTPUT
V
VTTREF
V
VTTREF
I
VTTREFOCLSRC
I
VTTREFOCLSNK
I
VTTREFDIS
VTT OUTPUT
V
VTT
V
VTTTOL
I
VTTOCLSRC
I
VTTOCLSNK
I
VTTLK
I
VTTSNSBIAS
I
VTTSNSLK
I
VTTDIS
VDDQ OUTPUT
V
VDDQSNS
I
VDDQSNS
I
REFIN
I
VDDQDIS
I
VLDOINDIS
SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY
f
SW
t
ON(min)
t
OFF(min)
(1) Ensured by design. Not production tested.
V5IN supply current, in S0 TA= 25°C, No load, VS3= VS5= 5 V 590 μA
V5IN supply current, in S3 TA= 25°C, No load, VS3= 0 V, VS5= 5 V 500 μA
V5IN shutdown current TA= 25°C, No load, VS3= VS5= 0 V 1 μA
VLDOIN supply current, in S0 TA= 25°C, No load, VS3= VS5= 5 V 5 μA
VLDOIN supply current, in S3 TA= 25°C, No load, VS3= 0 V, VS5= 5 V 5 μA
VLDOIN shutdown current TA= 25°C, No load, VS3= VS5= 0 V 5 μA
Output voltage 0 μA ≤ I
Current limit V
Output voltage V
Output voltage tolerance to V
VDDQ
Source current limit V
Sink current limit V
VTTREF discharge current TA= 25°C, VS3= VS5= 0 V, V
Output voltage V
Output voltage tolerance to VTTREF mV
Source current limit V
Sink current limit V
Leakage current TA= 25°C , VS3= 0 V, VS5= 5 V, V
VTTSNS input bias current VS3= 5 V, VS5= 5 V, V
VTTSNS leakage current VS3= 0 V, VS5= 5 V, V
VTT Discharge current 7.8 mA
VDDQ sense voltage V
VDDQSNS input current V
REFIN input current V
VDDQ discharge current 12 mA
VLDOIN discharge current 1.2 A
VDDQ switching frequency kHz
Minimum on time DRVH rising to falling
Minimum off time DRVH falling to rising 200 320 450
= 5 V, VLDOIN is connected to VDDQ output, V
V5IN
I
= 30 μA, TA= 25°C 1.8000
VREF
<300 μA, TA= –10°C to 85°C 1.7856 1.8144 V
VREF
0 μA ≤ I
VREF
|I
VTTREF
|I
VTTREF
VDDQSNS
VDDQSNS
|I
VTT
|I
VTT
|I
VTT
|I
VTT
VDDQSNS
VDDQSNS
TA= 25°C, VS3= VS5= 0 V, V
V
VTT
VDDQSNS
REFIN
VS3= VS5= 0 V, V
discharge mode
VS3= VS5= 0 V, V
mode
VIN= 12 V, V
VIN= 12 V, V
<300 μA, TA= –40°C to 85°C 1.7820 1.8180
VREF
= 1.7 V 0.4 0.8 mA
| <100 μA, 1.2 V ≤ V
| <10 mA, 1.2 V ≤ V
= 1.8 V, V
= 1.8 V, V
VTTREF
VTTREF
| ≤ 10 mA, 1.2 V ≤ V
| ≤ 1 A, 1.2 ≤ V
| ≤ 2 A, 1.4 V ≤ V
VDDQSNS
VDDQSNS
| ≤ 1.5 A, 1.2 V ≤ V
= 1.8 V, V
= 1.8V, V
= 0.5 V, I
VTTREF
VTT
VTT
= 0 A
= 0 V 10 18 mA
VDDQSNS
VDDQSNS
= V
= V
VTTSNS
VTTSNS
VTTSNS
≤ 1.8 V 49.2% 50.8%
VDDQSNS
≤ 1.8 V 49% 51%
VDDQSNS
= 1.8 V 10 17 mA
= 0.5 V 0.8 1.3 mA
VTTREF
≤ 1.8 V, I
≤ 1.8 V, I
≤ 1.4 V, I
VTTSNS
= V
= V
VDDQSNS
≤ 1.8 V, I
VTTREF
= 0.7 V, I
= 1.1 V, I
= V
VTT
VTTREF
VTTREF
= 1.8 V,
= 0 A –20 20
VTTREF
= 0 A –30 30
= 0 A –40 40
VTTREF
= 0 A –40 40
VTTREF
= 0 A 2 3
VTTREF
= 0 A 2 3
VTTREF
VTTREF
= 1.8 V 39 μA
= 1.8 V –0.1 0.0 0.1 μA
= 0.5 V, non-tracking
VDDQSNS
= 0.5 V, tracking discharge
VDDQSNS
VDDQSNS
VDDQSNS
= 1.8 V, R
= 1.8 V, R
(1)
= 1 kΩ 500
MODE
= 12 kΩ 670
MODE
= 0 V, VS3= VS5= 5 V
MODE
/2 V
VDDQSNS
VTTREF
–0.5 0.0 0.5 μA
–1 0 1
REFIN
60
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V
A
5
ns
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Product Folder Links :TPS51716
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, V
(unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VDDQ MOSFET DRIVER
R
DRVH
R
DRVL
t
DEAD
INTERNAL BOOT STRAP SW
V
FBST
I
VBSTLK
LOGIC THRESHOLD
I
MODE
V
THMODE
V
IL
V
IH
V
IHYST
I
ILK
SOFT START
t
SS
PGOOD COMPARATOR
V
THPG
I
PG
t
PGDLY
t
PGSSDLY
DRVH resistance
DRVL resistance
Dead time ns
Forward Voltage V
VBST leakage current TA= 25°C, V
MODE source current 14 15 16 μA
MODE threshold voltage MODE 1-2 235 255 275 mV
S3/S5 low-level voltage 0.5
S3/S5 high-level voltage 1.8 V
S3/S5 hysteresis voltage 0.25
S3/S5 input leak current –1 0 1 μA
VDDQ soft-start time 1.1 ms
VDDQ PGOOD threshold
PGOOD sink current V
PGOOD delay time
PGOOD start-up delay C
= 5 V, VLDOIN is connected to VDDQ output, V
V5IN
Source, I
Sink, I
Source, I
Sink, I
= –50 mA 1.6 3.0
DRVH
= 50 mA 0.6 1.5
DRVH
= –50 mA 0.9 2.0
DRVL
= 50 mA 0.5 1.2
DRVL
DRVH-off to DRVL-on 10
DRVL-off to DRVH-on 20
, TA= 25°C, IF= 10 mA 0.1 0.2 V
V5IN-VBST
VBST
MODE 0-1 109 129 149
MODE 2-3 392 412 432
Internal soft-start time, C
S5 rising to V
VDDQSNS
PGOOD in from higher 106% 108% 110%
PGOOD in from lower 90% 92% 94%
PGOOD out to higher 114% 116% 118%
PGOOD out to lower 82% 84% 86%
= 0.5 V 3 5.9 mA
PGOOD
Delay for PGOOD in 0.8 1 1.2 ms
Delay for PGOOD out, with 100 mV over drive 330 ns
= 0.1 μF, S5 rising to PGOOD rising 2.5 ms
VREF
TPS51716
SLUSB94 –OCTOBER 2012
= 0 V, VS3= VS5= 5 V
MODE
= 33 V, VSW= 28 V 0.01 1.5 μA
= 0.1 μF,
VREF
> 0.99 × V
REFIN
Ω
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5
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TPS51716
SLUSB94 –OCTOBER 2012
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, V
(unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
PROTECTIONS
I
TRIP
TC
ITRIP
V
TRIP
V
OCL
V
OCLN
V
ZC
V
UVLO
V
OVP
t
OVPDLY
V
UVP
t
UVPDLY
t
UVPENDLY
V
OOB
THERMAL SHUTDOWN
T
SDN
TRIP source current TA= 25°C, V
TRIP source current temperature
coefficient
V
(2)
voltage range 0.2 3 V
TRIP
Current limit threshold V
Negative current limit threshold V
Zero cross detection offset 0 mV
V5IN UVLO threshold voltage V
VDDQ OVP threshold voltage OVP detect voltage 118% 120% 122%
VDDQ OVP propagation delay With 100 mV over drive 430 ns
VDDQ UVP threshold voltage UVP detect voltage 66% 68% 70%
VDDQ UVP delay 1 ms
VDDQ UVP enable delay 1.2 ms
OOB Threshold voltage 108%
Thermal shutdown threshold °C
= 5 V, VLDOIN is connected to VDDQ output, V
V5IN
TRIP
V
= 3.0 V 360 375 390
TRIP
= 1.6 V 190 200 210 mV
TRIP
V
= 0.2 V 20 25 30
TRIP
V
= 3.0 V –390 –375 –360
TRIP
= 1.6 V –210 –200 –190 mV
TRIP
V
= 0.2 V –30 –25 –20
TRIP
Wake-up 4.2 4.4 4.5
Shutdown 3.7 3.9 4.1
Shutdown temperature
Hysteresis
(2)
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= 0 V, VS3= VS5= 5 V
MODE
= 0.4 V 9 10 11 μA
4700 ppm/°C
(2)
140
10
(2) Ensured by design. Not production tested.
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Product Folder Links :TPS51716
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
17
1819
20
TPS51716
Thermal Pad
VTTSNS
VLDOIN
VTT
VTTGND
VTTREF
VREF
GND
REFIN
VDDQSNS
PGND
DRVL
V5IN
SW
DRVH
VBST
S5
S3
TRIP
MODE
PGOOD
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TPS51716
SLUSB94 –OCTOBER 2012
DEVICE INFORMATION
RUK PACKAGE (TOP VIEW)
PIN FUNCTIONS
PIN
NAME NO.
DRVH 14 O High-side MOSFET gate driver output.
DRVL 11 O Low-side MOSFET gate driver output.
GND 7 – Signal ground.
MODE 19 I Connect resistor to GND to configure switching frequency, control mode and discharge mode. (See Table 2)
PGND 10 – Gate driver power ground. R
PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
REFIN 8 I
SW 13 I/O High-side MOSFET gate driver return. R
S3 17 I S3 signal input. (See Table 1)
S5 16 I S5 signal input. (See Table 1)
TRIP 18 I Connect resistor to GND to set OCL at V
VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application.
VREF 6 O 1.8-V reference output.
VTT 3 O VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability.
VTTGND 4 – Power ground for VTT LDO.
VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.
VTTSNS 1 I VTT output voltage feedback.
V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal pad Thermal pad. Connect directly to system GND plane with multiple vias.
I/O DESCRIPTION
current sensing input(+).
DS(on)
Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for
stable operation.
current sensing input(–).
DS(on)
/8. Output 10-μA current at room temperature, TC= 4700 ppm/°C.
TRIP
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7
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10
13
PGND
SW
TPS517 16
OC
ZC
XCON
15
VBST
12 V5IN
PWM
9
REFIN
TRIP
Delay
20 PGOOD
Control Logic
UDG-12151
10 ?A
+
+
V
REFIN
+20%
+
+
8
VDDQSNS
+
+
18
14 DRVH
11 DRVL
t
ON
OneShot
UV
OV
V
REFIN
–32%
16S5
Soft-Start
+
NOC
+
8 R
6VREF
R
7GND
17S3
5VTTREF
1VTTSNS
4 VTTGND
3 VTT
+
+
+
+
2 VLDOIN
7 R
R
VTT Discharge
VTTREF Discharge
Mode
Selection
15 ?A
19 MODE
V
REFIN
+8/16 %
V
REFIN
–8/16 %
+
+
VDDQ
Discharge
V5OK
+
4.4 V/3.9 V
UVP
OVP
G
+
1.8 V
Σ
TPS51716
SLUSB94 –OCTOBER 2012
FUNCTIONAL BLOCK DIAGRAM
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50
60
70
80
90
100
110
120
130
140
150
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
OVP/UVP Threshold (%)
OVP
UVP
0
3
6
9
12
15
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
VDDQSNS Discharge Current (mA)
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
VLDOIN Suppy Current (µA)
4
6
8
10
12
14
16
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
TRIP Source Current (µA)
0
200
400
600
800
1000
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
V5IN Suppy Current (µA)
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
V5IN Shutdown Current (µA)
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Figure 1. V5IN Supply Current vs Junction Temperature Figure 2. V5IN Shutdown Current vs Junction Temperature
TPS51716
SLUSB94 –OCTOBER 2012
TYPICAL CHARACTERISTICS
Figure 3. VLDOIN Supply Current vs Junction Temperature Figure 4. Current Sense Current vs Junction Temperature
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Figure 5. OVP/UVP Threshold vs Junction Temperature Figure 6. VDDQSNS Discharge Current vs Junction
Temperature
Product Folder Links :TPS51716
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
0 2 4 6 8 10
VDDQ Output Current (A)
VDDQ Output Voltage (V)
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 12 V
VIN = 20 V
R
MODE
= 1 kΩ
G000
0
100
200
300
400
500
600
700
800
0 2 4 6 8 10
VDDQ Output Current (A)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 12 kΩ
VIN = 12 V
G000
200
300
400
500
600
700
800
6 8 10 12 14 16 18 20 22
Input Voltage (V)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 12 kΩ
I
VDDQ
= 5 A
0
100
200
300
400
500
600
700
800
0 2 4 6 8 10
VDDQ Output Current (A)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 1 kΩ
VIN = 12 V
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
VTT Discharge Current (mA)
200
300
400
500
600
700
800
6 8 10 12 14 16 18 20 22
Input Voltage (V)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 1 kΩ
I
VDDQ
= 5 A
TPS51716
SLUSB94 –OCTOBER 2012
TYPICAL CHARACTERISTICS (continued)
Figure 7. VTT Discharge Current vs Junction Temperature Figure 8. Switching Frequency vs Input Voltage
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Figure 9. Switching Frequency vs Input Voltage Figure 10. Switching Frequency vs Load Current
10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Figure 11. Switching Frequency vs Load Current Figure 12. Load Regulation
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