Texas Instruments TPS51427RHBR, TPS51427RHBT Schematic [ru]

TPS51427

TPS51427

www.ti.com

................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008

DUAL D-CAP™ SYNCHRONOUS STEP-DOWN CONTROLLER

FOR NOTEBOOK POWER RAILS

1

FEATURES

23

• Fixed-Frequency Emulated On-Time Control;

Frequency Selectable from Three Options

• D-CAP™ Mode Enables Fast Transient

Response Less than 100 ns

• Advanced Ramp Compensation Allows Low

Output Ripple with Minimal Jitter

• Selectable PWM-Only/ OOA™/Auto-Skip Modes

• Wide Input Voltage Range: 5.5 V to 28 V

• Dual Fixed or Adjustable SMPS:

– 0.7 V to 5.9 V (Channel1)
– 0.5 V to 2.5 V (Channel2)

• Fixed 3.3-V/5-V, or Adjustable Output 0.7-V to

4.5-V LDO; Capable of Sourcing 100 mA

• Fixed 3.3-VREF Output Capable of Sourcing

10 mA

• Temperature Compensated Low-Side R

Current Sensing

• Adaptive Gate Drivers with Integrated Boost

Switch

• Bootstrap Charge Auto Refresh

• Integrated Soft Start, Tracking Soft Stop

• Independent PGOOD and EN for Each Channel

APPLICATIONS

• Notebook I/O and System Bus Rails

• Graphics Application

• PDAs and Mobile Communication Devices

DS(on)

DESCRIPTION

The TPS51427 is a dual synchronous step-down
controller designed for notebook and mobile
communications applications. This device is part of a
low-cost suite of notebook power bus regulators that
enables system designs with low external component
counts. The TPS51427 includes two
pulse-width-modulation (PWM) controllers, SMPS1
and SMPS2. The output of SMPS1 can be adjusted
from 0.7 V to 5.9 V, while the output of SMPS2 can
be adjusted from 0.5 V to 2.5 V. This device also
features a low-dropout (LDO) regulator that provides
a 5-V/3.3-V output, or adjustable from 0.7-V to 4.5-V
output via LDOREFIN. The fixed-frequency emulated
adaptive on-time control supports seamless operation
between PWM mode under heavy load conditions
and reduced frequency operation at light loads for
high-efficiency down to the milliampere range. An
integrated boost switch enhances the high-side
MOSFET to further improve efficiency. The main
control loop is the D-CAP™ mode that is optimized
for low equivalent series resistance (ESR) output
capacitors such as POSCAP or SP-CAP. Advanced
ramp compensation minimizes jitter without degrading
line and load regulation. R
methods offers maximum cost saving.

The TPS51427 supports supply input voltages that
range from 5.5 V to 28 V. It is available in the 32-pin,
5-mm × 5-mm QFN package (Green, RoHs­compliant, and Pb-free). The device is specified from
– 40 ° C to +85 ° C.

current sensing

DS(on)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 D-CAP, OOA are trademarks of Texas Instruments.
3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2008, Texas Instruments Incorporated

TPS51427

SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

(1)

ORDERABLE

T

A

– 40 ° C to +85 ° C Tape and Reel

PACKAGE PART NO. TRANSPORT MEDIA QUANTITY ECO STATUS

Plastic Quad Flatpack

(32-pin QFN)

TPS51427RHBT 250 Green
TPS51427RHBR 3000

(RoHs and No

Sb/Br)

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

(2) Eco-Status information: Additional details including specific material content can be accessed at www.ti.com/leadfree

GREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight.

N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree .
Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total

product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range; all voltages are with respect to GND (unless otherwise noted).

PARAMETER VALUE UNIT

5V voltage range V5DRV, V5FILT – 0.3 to 7

VIN, ENLDO – 0.3 to 30
VBST1, VBST2 – 0.3 to 37
VBST1, VBST2 (w.r.t. LLx) – 0.3 to 7

Input voltage range

Output voltage

(2)

range

T

Storage temperature range – 55 to +150

stg

T

Junction temperature range +150

J

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

(2)

EN1, EN2, VOUT1, VOUT2, VFB1, REFIN2, TRIP1, TRIP2, SKIPSEL,
TONSEL, VSW, LDOREFIN

– 0.3 to 7

TRIP1, TRIP2 – 0.3 to (V5FILT + 0.3)
DRVH1, DRVH2 – 2 to 37
DRVH1, DRVH2 (w.r.t. LLx) – 0.3 to 7
LL1, LL2 – 2 to 30 V
DRVL1, DRVL2, VREF2, PGOOD1, PGOOD2, LDO, VREF3 – 0.3 to 7
PGND – 0.3 to 0.3

(2)

V

° C

DISSIPATION RATINGS

(1)

TA< +25 ° C DERATING FACTOR TA= +85 ° C

PACKAGE POWER RATING ABOVE TA= +25 ° C POWER RATING

32Ld 5 × 5 QFN 2.320 W 23.2 mW/ ° C 0.93 W

(1) Dissipation ratings are calculated based on the usage of nine standard thermal vias and thermal pad soldered on the PCB. If thermal

pad is not soldered to the PCB, the junction-to-ambient thermal resistance is 88.6 ° C/W.

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RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range (unless otherwise noted).

MIN TYP MAX UNIT

Supply input voltage range V5DRV, V5FILT 4.5 5.5 V
Input voltage range VBST1, VBST2 – 0.1 34

VBST1, VBST2 (with regard to LLx) – 0.1 5.5
EN1, EN2, VOUT1, VFB1, REFIN2, TRIP1, TRIP2, SKIPSEL, TONSEL, – 0.1 5.5

ENLDO,VSW, LDOREFIN
VOUT2 – 0.1 3.7

Output voltage range DRVH1, DRVH2 – 0.8 34 V

DRVH1, DRVH2 (w.r.t. LLx) – 0.1 5.5
LL1, LL2 – 0.8 28
DRVL1, DRVL2, VREF2, PGOOD1, PGOOD2, LDO, VREF3 – 0.1 5.5
PGND – 0.1 0.1

Operating free-air temperature, T

A

– 40 +85 ° C

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ELECTRICAL CHARACTERISTICS

Over recommended free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT SUPPLIES

VIN Input Voltage Range LDO in regulation 5.5 28 V
VIN Operating Supply Current LDO switched over to VSW, 4.5-V to 5.5-V SMPS 5 10 µ A

VIN Standby Current 115 150 µ A

VIN Shutdown Current 12 20 µ A

5.5 V ≤ V
V, EN1 = EN2 = VSW = 0 V

5.5 V ≤ V
EN1 = EN2 = VSW = 0 V

TA= +25 ° C, no load, EN_LDO = EN1 = EN2 = REFIN2

Quiescent Power Consumption = 5 V, VFB1 = SKIPSEL = 0 V, VOUT1 = VSW = 5.3 V, 5 7 mW

VOUT2 = 3.5 V

PWM CONTROLLERS

5-V Preset output: 5.5 V ≤ V
VFB1 = 0 V, SKIPSEL = 5 V ( – 1.5%) (+1.5%)

VOUT1 Output Voltage Accuracy 1.50 V

1.5-V Preset output: 5.5 V ≤ V
VFB1 = 5V, SKIPSEL = 5V ( – 1.2%) (+1.2%)

Adjustable feedback output, 0.693 0.707

5.5 V ≤ V

VOUT1 Voltage Adjust Range 0.707 5.900 V

VFB1 Threshold Voltage

5-V Preset output 0.20 V

1.5-V Preset output 3.90 V

VFB1 Input Current VFB1 = 0.8 V – 0.20 0.20 µ A

3.3-V Preset output: REFIN2 = 5 V, 5.5 V ≤ V
SKIPSEL = 5 V

VOUT2 Output Voltage Accuracy 1.05 V

1.05-V Preset output: REFIN2 = 3.3 V,

5.5 V ≤ V
Tracking output: REFIN2 = 1.0 V, 5.5 V ≤ V

SKIPSEL = 5 V
REFIN2 Voltage Adjust Range 0.50 2.50 V
REFIN2 Input Current 0.5 V ≤ V

REFIN2 Threshold Voltage V

1.05-V Preset output 3.00 3.45

3.3-V Preset output 3.90

Either SMPS, SKIPSEL = 5 V, 0 A to 5 A
DC Load Regulation Either SMPS, SKIPSEL = 2 V, 0 A to 5 A

Either SMPS, SKIPSEL = GND, 0 A to 5 A
Line Regulation Either SMPS, 5.5 V < VIN < 28 V

TONSEL = 0 V, 2 V, or OPEN (400 kHz),
Channel1 On-Time ns

VOUT1 = 5.05 V

TONSEL = 5 V (200 kHz), VOUT1 = 5.05 V 1895 2105 2315

TONSEL = 0 V (500 kHz), VOUT2 = 3.33 V 475 555 635
Channel2 On-Time ns

TONSEL = 2 V, OPEN, or 5 V (300 kHz),

VOUT2 = 3.33 V
Minimum Off-Time 300 400 500 ns
Soft Start Ramp Time Zero to full limit 1.8 ms
VOUT1, VOUT2 Discharge On

Resistance

EN1 = EN2 = 0 V, VOUT1 = VOUT2 = 0.5 V 17 35 Ω
OOA Operating Frequency SKIPSEL = 2 V or OPEN 22 30 kHz

(1) Ensured by design. Not production tested.

≤ 28 V, TA= +25 ° C, no load, EN_LDO = 5

VIN

≤ 28 V, TA= +25 ° C, no load, EN_LDO =

VIN

≤ 28 V, SKIPSEL = 5 V ( – 1%) (+1%)

VIN

≤ 28 V, SKIPSEL= 5 V

VIN

VREFIN2

= 5 V, V

V5DRV

VIN

= 12 V (unless otherwise noted).

VIN

≤ 28 V, 4.975 5.125

≤ 28 V, 1.482 1.518

VIN

5.05

0.70

≤ 28 V,

VIN

3.285 3.375

( – 1.4%) (+1.4%)

3.33

1.038 1.062

(-1.2%) (+1.2%)

≤ 28 V,

VIN

0.99 1.01

(-1%) (+1%)

1.00

≤ 2.5 V – 0.2 0.2 µ A

(1)
(1)

(1)

(1)

– 0.10%
– 2.20%
– 0.50%

0.005 %/V

895 1052 1209

833 925 1017

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ELECTRICAL CHARACTERISTICS (continued)

Over recommended free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LINEAR REGULATOR (LDO)

LDOREFIN = VSW = 0 V, 0 < I

6 V < VIN < 28 V
LDO Output Voltage 3.33 V

LDOREFIN Input Range VLDO = 2 × VLDOREFIN 0.35 2.25 V
LDOREFIN Leakage Current VLDOREFIN = 0 V or 5 V – 0.5 0.5 µ A

LDOREFIN Threshold Voltage V

LDO Output Current VSW = GND , VIN = 5.5 V to 28 V 100 mA
LDO Output Current During

Switchover to 5 V
LDO Output Current During

Switchover to 3.3 V
LDO Short-Circuit Current VSW = LDO = 0 V 140 180 220 mA

LDO 5-V Switchover Threshold V

LDO 3.3-V Switchover Threshold V

LDO Switchover Switch On
Resistance

LDO Switchover Delay Turning on 3.96 ms
LDO Undervoltage Lockout

Threshold

VIN POR Threshold V

Thermal-Shutdown Threshold Hysteresis = +10 ° C

3.3V ALWAYS-ON LINEAR REGULATOR (VREF3)

VREF3 Output Voltage V

VREF3 Load Regulation 0 mA < I
VREF3 Current Limit VREF3 = GND 15 20 mA

VREF3 Undervoltage Lockout
Threshold

(2) Ensured by design. Not production tested.

LDOREFIN = 5 V, VSW = 0 V, 0 < I

5.5 V < VIN < 28 V

LDOREFIN = 0.5 V, VSW = 0 V, 0 < I

5.5V < VIN < 28 V

Fixed LDO = 5 V 0.15

Fixed LDO = 3.3 V 3.90

VSW = 5 V , VIN = 5.5 V to 28 V, LDOREFIN = 0 V 340 500 mA

VSW = 3.3 V , VIN = 5.5 V to 28 V, LDOREFIN = 5 V 330 500 mA

Rising edge of VSW, LDOREFIN = 0 V

Hysteresis 0.20

Rising edge of VSW, LDOREFIN = 5 V

Hysteresis 0.150

LDO to VSW, VSW = 5 V, ILDO = 100 mA 0.7 1.5 Ω

Falling edge of V5FILT 3.80 3.93 4.10

Rising edge of V5FILT 4.20 4.37 4.50

Falling edge of VIN 1.8

Rising edge of VIN 2.1

No external load, V

No external load, V

< 10 mA 60 mV

LOAD

Falling edge of VREF3 2.96

Hysteresis 0.17

= 5 V, V

V5DRV

(2)

> 4.5 V 3.300

VSW

< 4.0 V 3.300

VSW

= 12 V (unless otherwise noted).

VIN

< 10 0mA,

LDO

< 100 mA,

LDO

< 50 mA,

LDO

4.94 5.11

( – 1.7%) (+1.7%)

3.28 3.38

( – 1.5%) (+1.5%)

0.98 1.02

( – 2%) (+2%)

4.63 4.78 4.93

(92.6%) (95.6%) (98.6%)

3.05 3.15 3.25

(92.5%) (95.5%) (98.5%)

3.250 3.350

( – 1.5%) (+1.5%)

3.220 3.380

( – 2.4%) (+2.4%)

5.025

1.00

+140 ° C

V

V

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ELECTRICAL CHARACTERISTICS (continued)

Over recommended free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REFERENCE (REF)

|I

| = 0 µ A 2.00

VREF2

VREF2 Output Voltage V

|I

| < 50 µ A 2.00

VREF2

VREF2 Sink Current VREF2 in regulation 50 µ A
VREF2 Undervoltage Lockout

Threshold

OUT1 FAULT DETECTION

Overvoltage Trip Threshold VFB1 with respect to nominal regulation point +12.5% +15% +17.5%
Overvoltage Fault Propagation

Delay
Undervoltage Trip Threshold VFB1 with respect to nominal output voltage – 35% – 30% – 25%
Undervoltage Fault Propagation

Delay
Undervoltage Fault Enable Delay From ENx signal 10 20 30 ms

PGOOD1 Lower Trip Threshold – 12.5% – 10% – 7.5%
PGOOD1 Low Propagation Delay Falling edge, 50-mV overdrive 10 µ s

PGOOD1 High Propagation Delay Rising edge, 50-mV overdrive 0.8 1.0 1.2 ms
PGOOD1 Output Low Voltage PGOOD1 Low impedance, I
Out-Of-Bound Threshold VFB1 with respect to nominal output voltage +5%
PGOOD1 Leakage Current PGOOD1 High impedance, forced to 5.5 V 1 µ A

OUT2 FAULT DETECTION

Overvoltage Trip Threshold REFIN2 with respect to nominal regulation point +12.5% +15.0% +17.5%
Overvoltage Fault Propagation

Delay
Undervoltage Trip Threshold REFIN2 with respect to nominal output voltage – 35% – 30% – 25%
Undervoltage Fault Propagation

Delay
Undervoltage Fault Enable Delay From ENx signal 10 20 30 ms

PGOOD2 Lower Trip Threshold – 12.5% – 10% – 7.5%
Out-Of-Bound Threshold REFIN2 with respect to nominal output voltage +5%

PGOOD2 Low Propagation Delay Falling edge, 50-mV overdrive 10 µ s
PGOOD2 High Propagation Delay Rising edge, 50-mV overdrive 0.8 1.0 1.2 ms
PGOOD2 Output Low Voltage PGOOD2 Low impedance, I
PGOOD2 Leakage Current PGOOD2 High impedance, forced to 5.5 V 1 µ A

Falling edge of VREF2 1.575 1.700 1.825

Hysteresis 0.1

VFB1 delay with 50-mV overdrive 10 µ s

VFB1 with respect to nominal output, falling edge,

typical hysteresis = 5%

REFIN2 delay with 50-mV overdrive 10 µ s

REFIN2 with respect to nominal output, falling edge,

typical hysteresis = 5%

= 5 V, V

V5DRV

= 12 V (unless otherwise noted).

VIN

1.98 2.02

( – 1%) (+1%)

1.975 2.025

( – 1.25%) (+1.25%)

0.8 1 1.2 ms

= 4 mA 0.4 0.8 V

SINK

0.8 1 1.2 ms

= 4 mA 0.4 0.8 V

SINK

V

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ELECTRICAL CHARACTERISTICS (continued)

Over recommended free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT LIMIT

TRIPx Adjustment Range 0.2 2.0 V
TRIPx Source Current 0.2 V < V
TRIPx Current Temperature Coefficient on the basis of TA= +25 ° C

GND – LLx, V

Current-Limit Threshold (Positive,
Adjustable)

GND – LLx, V

GND – LLx, V

GND – LLx, V
Current-Limit Threshold (Positive, V

Default) compensation)
Fixed 100-mV OCL TRIPx

Threshold Voltage

Current Limit Threshold (Negative) – 100%
Zero-Crossing Current Limit

Threshold

TRIPx

High threshold 3.0 3.2 3.3 V

Hysteresis 40 70 100 mV

With respect to valley current limit threshold,

SKIPSEL = 5 V

SKIPSEL = 0 V, 2 V, or OPEN, GND – LLx – 3.5 0 3.5 mV

GATE DRIVERS

DRVHx Gate-Driver
On-Resistance

DRVLx Gate-Driver On-Resistance Ω

DRVHx Gate-Driver Source
Current

Source, VBSTx-DRVHx = 0.1 V 1.0 3.6

Sink, DRVHx-LLx = 0.1 V 0.8 2.6

Source, V5DRV-DRVLx = 0.1 V 1.2 4.0

Sink, DRVLx-PGND = 0.1 V 0.6 1.5

VBSTx-LLx = 5 V, DRVHx = 2.0 V
DRVHx Gate-Driver Sink Current VBSTx-LLx = 5 V, DRVHx = 2.0 V

DRVLx Gate-Driver Source
Current

V5DRV-PGND = 5 V, DRVLx = 2.0 V
DRVLx Gate-Driver Sink Current V5DRV-PGND = 5 V, DRVLx = 2.0 V

DRVHx low (DRVHx = 1 V) to DRVLx high (DRVLx = 4
Dead Time

V), LLx = – 0.05 V

DRVLx low (DRVLx = 1 V) to DRVHx high (DRVHx = 4

V), LLx = – 0.05 V
Internal BST_ Switch

On-Resistance
VBSTx Leakage Current V

I

VBSTx

VBSTx

(3) Ensured by design. Not production tested.

< 2 V, TA= +25 ° C 5 µ A

TRIPx

TRIPx

TRIPx

TRIPx

TRIPx

= 5.0 V, GND – LLx (no temperature

= 10 mA, V5DRV = 5 V, TA= +25 ° C 10 Ω

= 35 V, LLx = 28 V 0.01 2.0 µ A

= 5 V, V

V5DRV

= 12 V (unless otherwise noted).

VIN

4.75 5.25

( – 5%) (+5%)

(3)

= 0.2 V 20

= 0.5 V 50

= 1 V 100

= 2 V 200

13 27

( – 35%) (+35%)

42.5 57.5

( – 15%) (+15%)

93 107

( – 7%) (+7%)

190 210

( – 5%) (+5%)

93 107

( – 7%) (+7%)

(3)

(3)

(3)

(3)

20 30 50 ns

25 40 60 ns

2900 ppm/ ° C

100 mV

1.8 A

1.6 A

1.4 A

2.6 A

mV

Ω

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ELECTRICAL CHARACTERISTICS (continued)

Over recommended free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUTS AND OUTPUTS

High level 2.9
TONSEL Input Logic Levels Float level 1.85 2.25 V

Low level 0.45

High threshold (PWM Only) 2.9
SKIPSEL Input Logic Levels Float level (OOA) 1.85 2.25 V

Low level (Auto Skip) 0.45
SKIPSEL, TONSEL Input Current SKIPSEL = TONSEL = 0 V 2.5 4.0 5.5 µ A

SMPS On level 2.9
EN1, EN2 Input Logic Levels Delay start level 1.85 2.25 V

SMPS Off level 0.45
EN1, EN2 Leakage Current EN1 = EN2 = 0 V – 0.1 0.1 µ A

EN_LDO Input Logic Levels V

EN_LDO Input Current µ A

Rising edge 1.3 1.65 1.9

Hysteresis 0.6

EN_LDO = 0 V 0.7 1.0 1.3

EN_LDO = 30 V – 0.1 0 0.1

= 5 V, V

V5DRV

= 12 V (unless otherwise noted).

VIN

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DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

NAME NO. I/O DESCRIPTION

DRVH1 15
DRVH2 26
DRVL1 18
DRVL2 23
EN1 14
EN2 27

EN_LDO 4 I
GND 21 I Analog ground for both channels and LDO.

LL1 16
LL2 25

LDO 7 O

LDOREFIN 8 I operation. LDOREFIN can be used to program LDO output voltage from 0.7 V to 4.5 V. LDO output is twice the voltage of

PGND 22 I
PGOOD1 13 Channel1/Channel2 power-good open-drain output. PGOOD1/PGOOD2 is low when the Channel1/Channel2 output voltage is

PGOOD2 28

REFIN2 32 I
NC 20 ­SKIPSEL 29 I

TONSEL 2 I 400-kHz/300-kHz operation. Connect to V5FILT for 200-kHz/300-kHz operation (5-V/3.3-V SMPS switching frequencies,

TRIP1 12
TRIP2 31

V5DRV 19 I
V5FILT 3 I 5-V analog supply input.
VFB1 11 I
VBST1 17

VBST2 24
VIN 6 I
VOUT1 10

VOUT2 30
VREF2 1 O 2-V reference output. Bypass to GND with a 0.1- µ F capacitor. VREF2 can source up to 50 µ A for external loads.
VREF3 5 O 3.3-V reference output. VREF3 can source up to 10 mA for external loads. Bypass to GND with a 1- µ F capacitor.

VSW 9 I

High-side N-Channel FET driver outputs. LL referenced floating drivers. The gate drive voltage is defined by the voltage across

O

VBST to LL node bootstrap capacitor.

O Synchronous low-side MOSFET driver outputs. Ground referenced drivers. The gate drive voltage is defined by V5DRV voltage.

Channel enable pins. If EN1 is connected to VREF2, Channel1 starts after Channel2 reaches regulation (delay start). If EN2 is

I

connected to VREF2, Channel2 starts after Chanel1 reaches regulation.
LDO Enable Input. The LDO is enabled if EN_LDO is within logic high level and disabled if EN_LDO is less than the logic low

level.

Phase node connections for high-side drivers. These connections also serve as inputs to current comparators for R

I/O

and input voltage monitor for on-time control circuitry.
Linear regulator output. The LDO regulator can provide a total of 100-mA external loads. The LDO regulates at 5 V If LDOREFIN

is connected to GND. When the LDO is set at 5 V and VSW is within a 5-V switchover threshold, the internal regulator shuts
down and the LDO output pin connects to VSW through a 0.7- Ω switch. The LDO regulates at 3.3 V if LDOREFIN is connected
to V5FILT. When the LDO is set at 3.3 V and VSW is within a 3.3-V switchover threshold, the internal regulator shuts down and
the LDO output pin connects to VSW through a 0.7- Ω switch. Bypass the LDO output with a minimum of 4.7- µ F ceramic
capacitance.

LDO Reference Input. Connect LDOREFIN to GND for fixed 5-V operation. Connect LDOREFIN to V5FILT for fixed 3.3-V
LDOREFIN. There is no switchover in adjustable mode.

Ground pin for drivers and LS synchronous FET source terminals. This pin is also the input to zero crossing comparator and
overcurrent comparator.

O 10% less than the normal regulation point, at onset of OVP events, or during soft start. PGOOD1/PGOOD2 is high impedance

when the output is in regulation and the soft-start circuit has terminated. PGOOD1/PGOOD2 is low in shutdown.
Output voltage control for Channel2. Connect REFIN2 to V5FILT for fixed 3.3-V operation. Connect REFIN2 to VREF3 for fixed

1.05-V operation. REFIN2 can be used to program Channel2 output voltage from 0.5 V to 2.5 V.

Low-noise mode control. Connect SKIPSEL to GND for Auto Skip mode operation or to V5FILT for PWM mode (fixed frequency).
Connect to VREF2 or leave floating for OOA™ mode operation.

Frequency select input. Connect to GND for 400-kHz/500-kHz operation. Connect to VREF2 (or leave open) for
respectively).

I Overcurrent trip point set input. Sourcing current is 5 µ A at RT with 2900 ppm/ ° C temperature coefficient.

Supply voltage for the low-side MOSFET driver DRVL1/DRVL2. Connect a 5-V power source to the V5DRV pin (bypass with

4.7- µ F MLCC capacitor to PGND if necessary).

Channel1 feedback input. Connect VFB1 to GND for fixed 5-V operation. Connect VFB1 to V5FILT for fixed 1.5-V operation.
Connect VFB1 to a resistive voltage divider from OUT1 to GND to adjust the output from 0.7 V to 5.9 V.

I Supply input for high-side MOSFET driver (bootstrap terminal). Connect a capacitor from this pin to the respective LL terminals.

Power supply input. VIN supplies power to the linear regulators. The linear regulators are powered by Channel1 if VOUT1 is set
greater than 5 V and VSW is tied to VOUT1.

O Output connections to SMPS. These terminals serve two functions: on-time adjustment and output discharge.

VSW is the switchover source voltage for the LDO when LDOREFIN is connected to GND or V5FILT. Connect VSW to 5 V if
LDOREFIN is tied GND. Connect VSW to 3.3 V if LDOREFIN is tied to V5FILT.

DS(on)

sensing

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1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

9 10 11 12 13 14 15 16

VREF2

VBST2

VSW

REFIN2

VOUT1

VFB1

TRIP1

PGOOD1

EN1

DRVH1

LL1

252627

282930

3132

TONSEL

V5FILT

EN_LDO

VREF3

VIN

LDO

LDOREFIN

DRVL2

NC

GND

PGND

V5DRV

DRVL1

VBST1

TRIP2

VOUT2

SKIPSEL

PGOOD2

EN2

DVRH2

LL2

TPS51427

RHB PACKAGE

(TOP VIEW)

TPS51427

SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................

QFN-32, 5-mm × 5-mm

(TOP VIEW)

www.ti.com

NC = No connection.

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140°C
/125°C

TPS51427

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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008

FUNCTIONAL BLOCK DIAGRAMS

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( )

f

VIN VOUT VOUT

OUT(LL)

SW VIN

V V V

1

I

2 L V

æ ö

- ´

æ ö

= ´

ç ÷

ç ÷

ç ÷

´ ´

è ø

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TPS51427

SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................

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DETAILED DESCRIPTION

BASIC PWM OPERATION

The main control loop of the TPS51427 is designed as an adaptive on-time pulse width modulation (PWM)
controller. It supports a proprietary D-CAP™ mode that uses internal compensation circuitry and is suitable for a
minimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) is
allowed. D-CAP mode can also enable stable operation when using capacitors with low ESR, such as specialty
polymer capacitors.

The basic operation of D-CAP mode can be described in this way: At the beginning of each cycle, the
synchronous high-side MOSFET turns on or goes to an ON state. This MOSFET turns off, or returns to an OFF
state, after an internal one-shot timer expires. The one-shot timer is determined by VIN and VOUT and keeps the
frequency fairly constant over the input voltage range under steady-state conditions; it is an adaptive on-time
control or fixed-frequency emulated on-time control. The MOSFET turns on again when the following two
conditions occur:

• Feedback information, monitored at the VFB1/VOUT2 voltage, indicates insufficient output voltage; and

• the inductor current information indicates that current is below the overcurrent limit.

Operating in this manner, the controller regulates the output voltage. The synchronous low-side or the rectifying
MOSFET is turned on each OFF state to keep the conduction loss minimum.

LIGHT LOAD CONDITIONS

The TPS51427 supports three selectable operating modes: PWM-only, Out-Of-Audio ( OOA™), and Auto-Skip.
If the SKIPSEL pin is connected to GND, Auto-Skip mode is selected. This mode enables a seamless transition

to the reduced frequency operation under light load conditions so that high efficiency is maintained over a wide
range of load current. This frequency reduction is achieved smoothly and without an increase in V
load regulation.

Auto-Skip operation can be described in this way: As the output current decreases from a heavy load condition,
the inductor current is also reduced. Eventually, the inductor current reaches the point that its valley equals zero
current; that is, the boundary between continuous conduction and discontinuous conduction modes. The
rectifying MOSFET turns off when this zero inductor current is detected. Because the output voltage remains
higher than the reference voltage at this point, both high-side and low-side MOSFETs are turned off and wait for
the next cycle. As the load current decreases further, the converter runs in discontinuous conduction mode and
takes longer to discharge the output capacitor below the reference voltage. Note that the ON time remains the
same as that in the heavy load condition. On the other hand, when the output current increases from a light load
to a heavy load, the switching frequency increases to the preset value as the inductor current reaches the
continuous conduction limit. The transition load point to the light load operation I

OUT(LL)

(that is, the threshold

between continuous conduction and discontinuous conduction mode) can be calculated as shown in Equation 1 :

ripple or

OUT

Where f
condition is a function of L, fSW, V
from the I

is the PWM switching frequency. Switching frequency versus output current under a light load

SW

threshold. For example, the frequency is approximately 60 kHz at I

OUT(LL)

IN

, and V

, but decreases at a near-proportional rate to the output current

OUT

/5 if the PWM switching

OUT(LL)

frequency is 300 kHz.
PWM-only mode is selected if the SKIPSEL pin is connected to 5 V. The rectifying MOSFET does not turn off

when the inductor current reaches zero. The converter runs in forced continuous conduction mode over the
entire load range. System designers may want to use this mode to avoid certain frequencies under light load
conditions but do so at the cost of lower efficiency. However, keep in mind that the output has the capability to
both source and sink current in this mode. If the output terminal is connected to a voltage source that is higher
than the regulator target value, the converter sinks current from the output and boosts the charge into the input
capacitors. This operation may cause an unexpected high voltage at VIN and may damage the power FETs.

If SKIPSEL pin is connected to VREF2 or left floating, OOA mode operation is selected.

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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008

Table 1. SKIPSEL Operating Modes

SKIPSEL GND FLOAT/VREF2 V5IN

Operating Mode Auto Skip OOA™ PWM Only

OUT-OF-AUDIO ( OOA™) OPERATION

If out-of-audio (OOA) operation is enabled, the switching frequency of the channel remains higher than the
audible frequency under any load condition, at a minimum of 22 kHz to minimize the audible noise in the system.
The TPS51427 automatically reduces switching frequencies under light load conditions. The OOA control circuit
monitors the switching period and forces the high-side MOSFET to turn on if the switching frequency goes below
the 22-kHz threshold.

The high-side MOSFET turns on even if the output voltage is higher than the target value; therefore, the output
voltage tends to be higher when operating in OOA mode. The OOA control circuit detects the overvoltage
condition and prevents the voltage from rising by re-modulating the device on time. The overvoltage condition is
detected by the VFB1/VOUT2 voltages.

The inductor current ripple (peak-to-peak) should be less than two-thirds of the OCL setting for the OOA circuit to
work properly at a 0-A load. To keep the OOA mode loop stable, the output voltage ripple cannot be too large. If
OOA mode operation is desired, the recommended output ripple voltage cannot be more than 1% of the target
dc voltage.

RAMP COMPENSATION

The TPS51427 employs an advanced ramp compensation technique in D-CAP mode to optimize jitter
performance. An internal ramp signal is added to the reference voltage to virtually increase the slope of the
VFB1/VOUT2 down ramp, which the PWM comparator uses to determine the turn-on timing.

LOW-SIDE DRIVER

The low-side driver is designed to drive high-current, low R
represented by its internal resistance: 1.2 Ω for V5DRV to DRVLx and 0.6 Ω for DRVLx to PGND. A dead time to
prevent shoot-through is generated internally between the two transistors, with the top MOSFET off and bottom
MOSFET on, and then with the bottom MOSFET off and the top MOSFET on. A 5-V bias voltage is delivered
from the V5DRV supply. The instantaneous drive current is supplied by an input capacitor connected between
V5DRV and GND. The average drive current is equal to the gate charge at V
frequency.

, N-channel MOSFET(s). The drive capability is

DS(on)

= 5 V times the switching

GS

HIGH-SIDE DRIVER

The high-side driver is also designed to drive high-current, low R
as a floating driver, a 5-V bias voltage is delivered from the V5DRV supply. The average drive current is also
calculated by the gate charge at V

= 5 V times the switching frequency. The instantaneous drive current is

GS

supplied by the floating capacitor between the VBSTx and LLx pins. The drive capability is represented by its
internal resistance: 1.0 Ω for VBSTx to DRVHx and 0.8 Ω for DRVHx to LLx.

, N-channel MOSFET(s). When configured

DS(on)

BOOSTRAP CHARGE AUTO REFRESH

Boost undervoltage protection is activated during the device ON time when the voltage difference between
DRVH and LL becomes less than 1.8 V. Upon detection of the undervoltage condition, the high-side gate driver
immediately turns off and the low-side gate driver turns on after the deadtime expires for the minimum off time in
an attempt to recharge the boost capacitor.

PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL

The TPS51427 employs an adaptive on-time control scheme and does not have a dedicated onboard oscillator.
However, the device runs with pseudo-constant frequency by feed-forwarding the input voltage and output
voltage into the on-time one-shot timer. The frequencies are set by the TONSEL terminal connection as Table 2
shows. The on-time is controlled: it is inversely proportional to the input voltage and proportional to the output
voltage, so that the duty ratio maintains technically as VOUT/VIN with the same cycle time. Although the
TPS51427 does not use VIN directly, the input voltage is monitored at the LLx pin during the ON state.

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