Texas Instruments tps51275 Datasheet

TPS51275, TPS51275B, TPS51275C

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SLUSB45B –JUNE 2012–REVISED MARCH 2013

Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs

1

FEATURES

2

• Input Voltage Range: 5 V to 24 V

• Output Voltages: 5 V and 3.3 V (Adjustable • Tablet Computers
Range ±10%)

• Built-in, 100-mA, 5-V and 3.3-V LDOs

• Clock Output for Charge-Pump

• ±1% Reference Accuracy

• Adaptive On-Time D-CAP™ Mode Control
Architecture with 300-kHz and 355-kHz
Frequency Setting

• Auto-skip Light Load Operation (TPS51275,
and TPS51275C)

• OOA Light Load Operation (TPS51275B)

• Internal 0.8-ms Voltage Servo Soft-Start

• Low-Side R

• Built-In Output Discharge Function

• Separate Enable Input for Switchers

• Dedicated OC Setting Terminals

• Power Good Indicator

• OVP, UVP and OCP Protection

• Non-Latch UVLO and OTP Protection

• 20-Pin, 3 mm x 3 mm, QFN (RUK)

ORDERABLE ENABLE

DEVICE NUMBER FUNCTION

TPS51275RUKR Tape and Reel 3000
TPS51275RUKT Mini reel 250

TPS51275BRUKR Tape and Reel 3000
TPS51275BRUKT Mini reel 250

TPS51275CRUKR Tape and Reel 3000

TPS51275CRUKT Mini reel 250

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Current Sensing Scheme

DS(on)

EN1 and EN2 OOA

NEED SOME SPACE

ORDERING INFORMATION

SKIP MODE ALWAYS On-LDO PACKAGE QUANTITY

Auto-skip VREG3

VREG3 and VREG5

Auto-skip

APPLICATIONS

• Notebook Computers

DESCRIPTION

The TPS51275, TPS51275B and TPS51275C are
cost-effective, dual-synchronous buck controllers
targeted for notebook system-power supply solutions.
It provides 5-V and 3.3-V LDOs and requires few
external components. The 260-kHz VCLK output can
be used to drive an external charge pump, generating
gate drive voltage for the load switches without
reducing the main converter efficiency. The
TPS51275, TPS51275B and TPS51275C supports
high efficiency, fast transient response and provides a
combined power-good signal. Adaptive on-time, D­CAP™ control provides convenient and efficient
operation. The device operates with supply input
voltage ranging from 5 V to 24 V and supports output
voltages of 5.0 V and 3.3 V. The TPS51275,
TPS51275B and TPS51275C are available in a 20­pin, 3 mm x 3 mm, QFN package and is specified
from –40°C to 85°C.

(1)

OUTPUT
SUPPLY

PLASTIC Quad

Flat Pack

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2012–2013, Texas Instruments Incorporated

VIN

VBST1

TPS51275B/C

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1EN-5V

VCLK

VREG5

V

IN

V

OUT

5 V

V

OUT

15 V

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

EN 3.3 V

V

OUT

3.3 V

PGOOD

3.3-V Always ON

UDG-12091

1 mF

5 V
Always ON

1 mF

VIN

VBST1

TPS51275

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1EN-5V

VCLK

VREG5

V

IN

V

OUT

5 V

V

OUT

15 V

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

EN 3.3 V

V

OUT

3.3 V

PGOOD

3.3-V Always ON

UDG-12090

1 mF

5 V

1 mF

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

TYPICAL APPLICATION DIAGRAM (TPS51275)

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TYPICAL APPLICATION DIAGRAM (TPS51275B and TPS51275C)

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TPS51275, TPS51275B, TPS51275C

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ABSOLUTE MAXIMUM RATINGS

(1)

SLUSB45B –JUNE 2012–REVISED MARCH 2013

over operating free-air temperature range (unless otherwise noted)

VALUE

MIN MAX

VBST1, VBST2 –0.3 32
VBST1, VBST2

(3)

–0.3 6

SW1, SW2 –6.0 26

Input voltage

(2)

VIN –0.3 26 V
EN1, EN2 –0.3 6
VFB1, VFB2 –0.3 3.6
VO1 –0.3 6
DRVH1, DRVH2 –6.0 32

(3)
(3)

(pulse width < 20 ns) –2.5 6

–0.3 6

Output voltage

DRVH1, DRVH2
DRVH1, DRVH2

(2)

DRVL1, DRVL2 –0.3 6 V
DRVL1, DRVL2 (pulse width < 20 ns) –2.5 6
PGOOD, VCLK, VREG5 –0.3 6
VREG3, CS1, CS2 –0.3 3.6

Electrostatic discharge kV

Junction temperature, T
Storage temperature, T

HBM QSS 009-105 (JESD22-A114A) 2
CDM QSS 009-147 (JESD22-C101B.01) 1

J

ST

150 °C
–55 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted
(3) Voltage values are with respect to SW terminals.

UNIT

THERMAL INFORMATION

TPS51275

(1)

θ

θ

θ

ψ

ψ

θ

JA
JCtop
JB

JT
JB

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 94.1
Junction-to-case (top) thermal resistance 58.1
Junction-to-board thermal resistance 64.3
Junction-to-top characterization parameter 31.8
Junction-to-board characterization parameter 58.0
Junction-to-case (bottom) thermal resistance 5.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS51275B
TPS51275C

20-PIN RUK

UNITS

°C/W

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TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

Supply voltage VIN 5 24

VBST1, VBST2 –0.1 30
VBST1, VBST2
SW1, SW2 –5.5 24 V

Input voltage

(1)

EN1, EN2 –0.1 5.5
VFB1, VFB2 –0.1 3.5
VO1 –0.1 5.5
DRVH1, DRVH2 –5.5 30
DRVH1, DRVH2

Output voltage

(1)

DRVL1, DRVL2 –0.1 5.5 V
PGOOD, VCLK, VREG5 –0.1 5.5
VREG3, CS1, CS2 –0.1 3.5

Operating free-air temperature, T

(1) All voltage values are with respect to the network ground terminal unless otherwise noted.
(2) Voltage values are with respect to the SW terminal.

(2)

(2)

A

–0.1 5.5

–0.1 5.5

–40 85 °C

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TPS51275, TPS51275B, TPS51275C

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V
noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SUPPLY CURRENT

I

VIN1

I

VIN2

I

VO1

I

VIN(STBY)

I

VIN(STBY)

INTERNAL REFERENCE

V

FBx

VREG5 OUTPUT

V

VREG5

I

VREG5

R

V5SW

VREG3 OUTPUT

V

VREG3

I

VREG3

DUTY CYCLE and FREQUENCY CONTROL

f

sw1

f

SW2

t

OFF(MIN)

MOSFET DRIVERS

R

DRVH

R

DRVL

t

D

INTERNAL BOOT STRAP SWITCH

R

VBST (ON)

I

VBSTLK

CLOCK OUTPUT

R

VCLK (PU)

R

VCLK (PD)

f

CLK

(1) Ensured by design. Not production tested.

VIN supply current-1 TA= 25°C, No load, V
VIN supply current-2 TA= 25°C, No load 30 μA
VO1 supply current TA= 25°C, No load, V
VIN stand-by current TPS51275 TA= 25°C, No load, V

VIN stand-by current 180 μA

VFB regulation voltage

VREG5 output voltage V

VREG5 current limit V
5-V switch resistance TA= 25°C, V

VREG3 output voltage V

VREG3 current limit V

CH1 frequency
CH2 frequency

(1)
(1)

Minimum off-time TA= 25°C 200 300 500 ns

DRVH resistance Ω

DRVL resistance Ω

Dead time ns

Boost switch on-resistance TA= 25°C, I
VBST leakage current TA= 25°C 1 µA

VCLK on-resistance (pull-up) TA= 25°C 10
VCLK on-resistance (pull-down) TA= 25°C 10
Clock frequency TA= 25°C 260 kHz

SLUSB45B –JUNE 2012–REVISED MARCH 2013

= 12 V, V

VIN

TA= 25°C, No load, V
TPS51275B/C)

= 5 V, V

VO1

= V

VFB1

=0 V 860 μA

VO1

= V

VFB1

= 0 V, V

VO1

=0 V, V

VO1

= 2 V, V

VFB2

=2.05 V 900 μA

VFB2

= V

EN1

EN2

=0V (

EN1=VEN2

= V

EN1

= 3.3 V (unless otherwise

EN2

= 0 V 95 μA

TA= 25°C 1.99 2.00 2.01 V

1.98 2.00 2.02 V

TA= 25°C, No load, V
V

> 7 V , V

VIN

V

VIN

V

VIN
VO1

No load, V
V

VIN

5.5 V < V

VO1

> 5.5 V , V
> 5 V, V

VO1

= 0 V, V

VREG5
VO1

= 0 V, TA= 25°C 3.267 3.300 3.333

VO1

> 7 V , V

VO1

, V

VIN

0°C ≤ TA≤ 85°C, V
I

< 35 mA

VREG3

0°C ≤ TA≤ 85°C, V
I

< 35 mA

VREG3

V

> 5 V, V

VIN
VO1

TA= 25°C, V
TA= 25°C, V

Source, (V
Sink, (V
Source, (V
Sink, V

VO1

= 0 V, V

VREG3

VIN
VIN

VBST

– VSW) = 0.25 V, (V

DRVH

VREG5

= 0.25 V, V

DRVL

= 0 V 4.9 5.0 5.1

VO1

= 0 V, I

= 0 V, I

VO1

= 0 V, I

= 4.5 V, V

= 5 V, I

= 0 V, I

= 0 V, I

VO1

VIN

VIN

= 0 V, I

= 3.0 V, V

< 100 mA 4.85 5.00 5.10

VREG5

< 35 mA 4.85 5.00 5.10

VREG5

< 20 mA 4.50 4.75 5.10

VREG5

= 7 V 100 150 mA

VIN

= 50 mA 1.8 Ω

VREG5

< 100 mA 3.217 3.300 3.383

VREG3

< 35 mA 3.234 3.300 3.366

VREG3

> 5.5 V, V

> 5.5 V, V

VREG3

= 0 V,

VO1

VO1

= 5 V,

3.267 3.300 3.333

3.267 3.300 3.333

< 35 mA 3.217 3.300 3.366

= 7 V 100 150 mA

VIN

= 20 V 240 300 360 kHz
= 20 V 280 355 430 kHz

– V

– V

DRVH

DRVL

) = 0.25 V, (V

) = 0.25 V, V

= 5 V 0.9

VREG5

– VSW) = 5 V 3.0

VBST

– VSW) = 5 V 1.9

VBST

= 5 V 3.0

VREG5

DRVH-off to DRVL-on 12
DRVL-off to DRVH-on 20

= 10 mA 13 Ω

VBST

Ω

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TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V
noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

OUTPUT DISCHARGE

R

DIS1

R

DIS2

R

DIS2

SOFT START OPERATION

t

SS

t

SSRAMP

POWER GOOD

V

PGTH

I

PGMAX

I

PGLK

t

PGDEL

CURRENT SENSING

I

CS

TC

CS

V

CS

V

ZC

LOGIC THRESHOLD

V

ENX(ON)

V

ENX(OFF)

I

EN

OUTPUT OVERVOLTAGE PROTECTION

V

OVP

t

OVPDLY

OUTPUT UNDERVOLTAGE PROTECTION

V

UVP

t

UVPDLY

t

UVPENDLY

UVLO

V

UVL0VIN

V

UVLO5

V

UVLO3

OVER TEMPERATURE PROTECTION

T

OTP

CH1 discharge resistance 35 Ω
CH2 discharge resistance TPS51275 TA= 25°C, V
CH2 discharge resistance 70 Ω

Soft-start time From ENx="Hi" and V
Soft-start time (ramp-up) V

PG threshold

PG sink current V
PG leak current V
PG delay From PG lower threshold (95%=typ) to PG flag high 0.7 ms

CS source current TA= 25°C, VCS= 0.4 V 9 10 11 μA
CS current temperature coefficient

(1)

CS Current limit setting range 0.2 2 V
Zero cross detection offset TA= 25°C –1 1 3 mV

EN threshold high-level SMPS on level 1.6 V
EN threshold low-level SMPS off level 0.3 V
EN input current V

OVP trip threshold 112.5% 115.0% 117.5%
OVP propagation delay TA= 25°C 0.5 µs

UVP trip Threshold 55% 60% 65%
UVP prop delay 250 µs
UVP enable delay From ENx ="Hi", V

VIN UVLO Threshold

VREG5 UVLO Threshold

VREG3 UVLO Threshold

OTP threshold

(1)

= 12 V, V

VIN

TA= 25°C, V
V

EN1

TA= 25°C, V
(TPS51275B/C)

OUT

= 5 V, V

VO1

= V

EN2

= 0% to V

VO1

= 0 V

SW2
SW2

OUT

VFB1

= 0.5 V

= 0.5 V, V
= 0.5 V, V

VREG5

= 95%, V

= V

= 2 V, V

VFB2

= V

EN1
EN1

> V

= 0 V 75 Ω

EN2

= V

= 0 V

EN2

to V

UVLO5

VREG5

OUT

= 5 V 0.78 ms

= V

EN1

= 3.3 V (unless otherwise

EN2

= 95% 0.91 ms

Lower (rising edge of PG-in) 92.5% 95.0% 97.5%
Hysteresis 5%
Upper (rising edge of PG-out) 107.5% 110.0% 112.5%
Hysteresis 5%

= 0.5 V 6.5 mA

PGOOD

= 5.5 V 1 µA

PGOOD

On the basis of 25°C 4500 ppm/°C

= 3.3 V –1 1 µA

ENx

= 5 V 1.35 ms

VREG5

Wake up 4.58 V
Hysteresis 0.5 V
Wake up 4.38 4.50 V
Hysteresis 0.4 V
Wake up 3.15 V
Hysteresis 0.15 V

Shutdown temperature 155
Hysteresis 10

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°C

(1) Ensured by design. Not production tested.

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1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

17

1819

20

TPS51275

TPS51275B

Thermal Pad

TPS51275C

CS1

VFB1

VREG3

VFB2

CS2

EN2

SW2

VBST2

DRVH2

DRVL2

VIN

VREG5

VO1

DRVL1

DRVH1

VBST1

SW1

VCLK

EN1

TPS51275, TPS51275B, TPS51275C

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SLUSB45B –JUNE 2012–REVISED MARCH 2013

DEVICE INFORMATION

RUK PACKAGE

20 PINS

(TOP VIEW)

PIN FUNCTIONS

PIN NO.

TPS51275
TPS51275B
TPS51275C

Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW
terminal.

Voltage feedback Input

Power conversion voltage input. Apply the same voltage as drain voltage of high-side MOSFETs of
channel 1 and channel 2.

NAME I/O DESCRIPTION

CS1 1 O Sets the channel 1 OCL trip level.
CS2 5 O Sets the channel 2OCL trip level.
DRVH1 16 O High-side driver output
DRVH2 10 O High-side driver output
DRVL1 15 O Low-side driver output
DRVL2 11 O Low-side driver output
EN1 20 I Channel 1 enable.
EN2 6 I Channel 2 enable.
PGOOD 7 O Power good output flag. Open drain output. Pull up to external rail via a resistor
SW1 18 O Switch-node connection.
SW2 8 O Switch-node connection.
VBST1 17 I
VBST2 9 I
VCLK 19 O Clock output for charge pump.
VFB1 2 I
VFB2 4 I

VIN 12 I
VO1 14 I Output voltage input, 5-V input for switch-over.

VREG3 3 O 3.3-V LDO output.
VREG5 13 O 5-V LDO output.
Thermal pad GND terminal, solder to the ground plane

Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7

VIN

VBST1

TPS51275
TPS51275 B
TPS51275 C

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1

VCLK

VREG5

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

UDG-12092

+ +

+

+

+

155°C/145°C

+

4.5 V/4.0 V

VO_OK

EN

FAULT

REF

PGOOD

DCHG

VIN VDDVDRV

GNDPGND

Switcher

Controller

(CH1)

EN

FAULT

REF

PGOOD

DCHG

VINVDD VDRV

GND PGND

Switcher

Controller

(CH2)

+

2 V

Osc

GND

(Thermal Pad)

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

FUNCTIONAL BLOCK DIAGRAM (TPS51275/B/C)

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DCHG

SW

TPS51275
TPS51275 B

NOC

ZC

XCON

VO_OK

DRVL

PWM

Control Logic

UDG-12093

+

+

V

REF

+15%

+

+

SKIP

UV

OV

V

REF

–40%

+

VIN

GND

REF

One-Shot

Discharge

10 µA

VBST

DRVH

FAULT

PGOOD

CS

+

VFB

OC

+

+

SS Ramp Comp

V

REF

+5%/10 %

V

REF

–5%/10%

+

+

EN

VDD

HS

LS

VDRV

PGND

PGOOD

TPS51275 C

TPS51275, TPS51275B, TPS51275C

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SWITCHER CONTROLLER BLOCK DIAGRAM

SLUSB45B –JUNE 2012–REVISED MARCH 2013

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( )

( )

- ´

= ´

´ ´

IN OUT OUT

OUT LL

SW IN

V V V

1

I

2 L f V

TPS51275, TPS51275B, TPS51275C

SLUSB45B –JUNE 2012–REVISED MARCH 2013

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DETAILED DESCRIPTION

PWM Operations

The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width
modulation (PWM) controller. It supports a proprietary D-CAP™ mode. D-CAP™ mode does not require external
conpensation circuit and is suitable for low external component count configuration when used with appropriate
amount of ESR at the output capacitor(s).

At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or enters the ON state. This
MOSFET is turned off, or enters the ‘OFF state, after the internal, one-shot timer expires. The MOSFET is turned
on again when the feedback point voltage, V

, decreased to match the internal 2-V reference. The inductor

VFB

current information is also monitored and should be below the overcurrent threshold to initiate this new cycle. By
repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side
(rectifying) MOSFET is turned on at the beginning of each OFF state to maintain a minimum of conduction loss.
The low-side MOSFET is turned off before the high-side MOSFET turns on at next switching cycle or when
inductor current information detects zero level. This enables seamless transition to the reduced frequency
operation during light-load conditions so that high efficiency is maintained over a broad range of load current.

Adaptive On-Time/ PWM Frequency Control

Because the TPS51275/B/C does not have a dedicated oscillator for control loop on board, switching cycle is
controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by
feed-forwarding the input and output voltage into the on-time one-shot timer. The target switching frequency is
varied according to the input voltage to achieve higher duty operation for lower input voltage application. The
switching frequency of CH1 (5-V output) is 300 kHz during continuous conduction mode (CCM) operation when
VIN= 20 V. The CH2 (3.3-V output) is 355 kHz during CCM when VIN= 20 V. (See Figure 27 and Figure 28).

To improve load transient performance and load regulation in lower input voltage conditions, TPS51275/B/C can
extend the on-time. The maximum on-time extension of CH1 is 4 times for CH2 is 3 times. To maintain a
reasonable inductor ripple current during on-time extension, the inductor ripple current should be set to less than
half of the OCL (valley) threshold. (See Step 2. Choose the Inductor). The on-time extension function provides
high duty cycle operation and shows better DC (static) performance. AC performance is determined mostly by
the output LC filter and resistive factor in the loop.

Light Load Condition in Auto-Skip Operation (TPS51275/C)

The TPS51275/C automatically reduces switching frequency during light-load conditions to maintain high
efficiency. This reduction of frequency is achieved smoothly and without an increase in output voltage ripple. A
more detailed description of this operation is as follows. As the output current decreases from heavy-load
condition, the inductor current is also reduced and eventually approaches valley zero current, which is the
boundary between continuous conduction mode and discontinuous conduction mode. The rectifying MOSFET is
turned off when this zero inductor current is detected. As the load current further decreases, the converter runs in
discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that
requires the next ON cycle. The ON time is maintained the same as that in the heavy-load condition. In reverse,
when the output current increase from light load to heavy load, the switching frequency increases to the preset
value as the inductor current reaches to the continuous conduction. The transition load point to the light load
operation I

OUT(LL)

as shown in Equation 1.

where

• fSWis the PWM switching frequency (1)

Switching frequency versus output current during light-load conditions is a function of inductance (L), input
voltage (VIN) and output voltage (V
I

.

OUT(LL)

(i.e. the threshold between continuous and discontinuous conduction mode) can be calculated

), but it decreases almost proportional to the output current from the

OUT

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