Texas Instruments TPS51206 Schematic [ru]

1

2

7

9

3

5

4

6

VTT

VTTSNS

PGND

VTTREF

VDDQSNS

VLDOIN

S3

S5

TPS51206

10 VDD

8GND

PowerPad

VTT

VTTREF

UDG-11024

S3_SLP

S5_SLP

5 V or 3.3 V

Supply

VDDQ

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TPS51206

SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered

Reference for DDR2, DDR3 and DDR3L

1 Features 3 Description

1

• Supply Input Voltage: Supports 3.3-V Rail and 5-V
Rail

• VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V

• VTT Termination Regulator
– Output Voltage Range: 0.5 V to 0.9 V
– 2-A Peak Sink and Source Current
– Requires Only 10-μF MLCC Output Capacitor
– ±20 mV Accuracy

• VTTREF Buffered Reference
– VDDQ/2 ± 1% Accuracy
– 10-mA Sink / Source Current

• Supports High-Z in S3 and Soft-Stop in S4/S5
with S3/S5 Inputs

• Overtemperature Protection

• 10-Pin 2-mm × 2-mm SON (DSQ) Package

2 Applications

• DDR2/DDR3/DDR3L Memory Power Supplies

• SSTL_18, SSTL_15, SSTL_135 and HSTL
Termination

The TPS51206 is a sink / source double date rate
(DDR) termination regulator with VTTREF buffered
reference output. It is specifically designed for low­input voltage, low-cost, low-external component count
systems where space is a key consideration. The
TPS51206 maintains fast transient response and only
requires 1 × 10-µF of ceramic output capacitance.
The TPS51206 supports a remote sensing function
and all power requirements for DDR2, DDR3 and
Low-Power DDR3 (DDR3L) VTT bus. The VTT
current capability is ±2-A peak. The TPS51206
supports all of the DDR power states, putting VTT to
High-Z in S3 state (suspend to RAM) and discharging
VTT and VTTREF in S4/S5 state (suspend to disk).

The TPS51206 is available in 10-pin, 2 × 2, SON
(DSQ) PowerPAD™ package and specified from
–40°C to 85°C.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS51206 WSON (10) 2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at

the end of the datasheet.

(1)

Simplified Application

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS51206

SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

www.ti.com

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

7 Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram....................................... 10

7.3 Feature Description................................................. 10

7.4 Device Functional Modes........................................ 11

8 Application and Implementation ........................ 12

8.1 Application Information............................................ 12

8.2 Typical Applications ................................................ 12

9 Power Supply Recommendations...................... 16

10 Layout................................................................... 16

10.1 Layout Guidelines ................................................. 16

10.2 Layout Example .................................................... 17

10.3 Thermal Considerations ....................................... 17

11 Device and Documentation Support................. 18

11.1 Device Support...................................................... 18

11.2 Trademarks........................................................... 18

11.3 Electrostatic Discharge Caution............................ 18

11.4 Glossary................................................................ 18

12 Mechanical, Packaging, and Orderable

Information........................................................... 18

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2013) to Revision B Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Original (MAY 2011) to Revision A Page

• Added minimum and maximum values to the wake up condition of the VDD UVLO threshold voltage specification........... 5

2 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: TPS51206

VDD

S5

S3

VTTREF

VDDQSNS

VLDOIN

VTT

PGND

Power

PAD

1

2

3

4

5

10

9

8

7

6

GND

VTTSNS

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SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

5 Pin Configuration and Functions

10-Pins

DSQ Package

Top View

Pin Functions

PIN

NAME NO.

GND 8 – Signal ground
PGND 4 – Power GND for VTT LDO
S3 7 I S3 signal input
S5 9 I S5 signal input
VDD 10 I Device power supply input (3.3 V or 5 V)
VDDQSN 1 I VDDQ sense input, reference input for VTTREF

S
VLDOIN 2 I Power supply input for VTT/ VTTREF
VTT 3 O Power output for VTT LDO, need to connect 10-μF or greater MLCC for stability
VTTREF 6 O VTTREF buffered reference output. Need to connect 0.22-µF or greater MLCC for stability
VTTSNS 5 I VTT LDO voltage sense input
Pad – – Solder to the ground plane for increased thremal performance.

I/O DESCRIPTION

TPS51206

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TPS51206

SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

6 Specifications

www.ti.com

6.1 Absolute Maximum Ratings

(1)

MIN MAX UNIT

VDD, S3, S5 –0.3 7 V

Input voltage range

(2)

VLDOIN, VTTSNS, VDDQSNS –0.3 3.6

PGND –0.3 0.3 V
Output voltage range
Junction temperature, T
Operating free-air temperature, T
Storage temperature, T

(1) Stresses beyond those listed under Absolute Maximum Ratings

(2)

J

stg

VTT, VTTREF –0.3 3.6

A

–55 150 °C
–55 150 °C

(1)

may cause permanent damage to the device. These are stress ratings

125 °C

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

6.2 ESD Ratings

VALUE UNIT

(1)

±2000

V

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

Electrostatic discharge V

(ESD)

Charged-device model (CDM), per JEDEC specification JESD22- ±500

(2)

C101

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN TYP MAX UNIT

Supply voltage VDD 3.1 6.5 V
Input voltage range

Output voltage VTT, VTTREF –0.1 3.5 V

(1)

range
Operating free-air temperature, T

(1) All voltage values are with respect to the network ground terminal unless otherwise noted.

(1)

S3, S5 –0.1 6.5 V
VLDOIN, VTTSNS, VDDQSNS –0.1 3.5
PGND –0.1 0.1

A

–40 85 °C

6.4 Thermal Information

TPS51206

THERMAL METRIC

θ

θ

θ

ψ

ψ

θ

JA
JCtop
JB

JT
JB

JCbot

Junction-to-ambient thermal resistance 70.3
Junction-to-case (top) thermal resistance 46.3
Junction-to-board thermal resistance 33.8
Junction-to-top characterization parameter 2.9
Junction-to-board characterization parameter 33.5
Junction-to-case (bottom) thermal resistance 16.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

4 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

(1)

Product Folder Links: TPS51206

DSQ UNIT

10 PINS

°C/W

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6.5 Electrical Characteristics

over operating free-air temperature range, V
noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SUPPLY CURRENT

I

VDD(S0)

I

VDD(S3)

I

VDDSDN

I

VLDOIN(S0)

I

VLDOIN(s3)

I

VLDOINSDN

VTTREF OUTPUT

V

VTTREF

V

VTTREFTOL

I

VTTREFSRC

I

VTTREFSNK

I

VTTREFDIS

VTT OUTPUT

V

VTT

V

VTTTOL

I

VTTOCLSRC

I

VTTOCLSNK

I

VTTLK

I

VTTSNSBIAS

I

VTTSNSLK

I

VTTDIS

VDDQ INPUT

I

VDDQSNS

UVLO/LOGIC THRESHOLD

V

VDDUV

V

LL

V

LH

V

LHYST

I

LHLK

OVER-TEMPERATURE PROTECTION

T

OTP

(1) Ensured by design. Not production tested.

VDD supply current, in S0 TA= 25°C, No load, VS3= VS5= 5 V, V
VDD supply current, in S3 TA= 25°C, No load, VS3= 0 V, VS5= 5 V, V
VDD shutdown current, in S4/S5 TA= 25°C, No load, VS3= VS5= 0 V, V
VLDOIN supply current, in S0 TA= 25°C, No load, VS3= VS5= 5 V, V
VLDOIN supply current, in S3 TA= 25°C, No load, VS3= 0 V, VS5= 5 V, V
VLDOIN shutdown current, in S4/S5 TA= 25°C, No load, VS3= VS5= 0 V, V

Output voltage V
Output voltage tolerance to

V

VDDQSNS

Source current V
Sink current V
VTTREF Discharge current TA= 25°C, VS3= VS5= 0V, V

Output voltage V

Output voltage tolerance to
V

/2

VDDQSNS

Source current limit V
Sink current limit V
Leakage current TA= 25°C , VS3= 0 V, VS5= 5 V, V
VTTSNS input bias current VS3= 5 V, VS5= 5 V, V
VTTSNS leakage current VS3= 0 V, VS5= 5 V, V
VTT Discharge current TA= 25°C, VS3= VS5= V

VDDQSNS input current V

VDD UVLO threshold voltage V

S3/S5 low-level voltage 0.5 V
S3/S5 high-level voltage 1.8 V
S3/S5 hysteresis voltage 0.3 V
S3/S5 input leak current –1 1 μA

Over temperature protection °C

TPS51206

SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

= 5 V, VLDOIN is connected to VDDQSNS, VS3= VS5= 5 V (unless otherwise

VDD

= 1.8 V 170 μA

VDDQSNS

= 1.8 V 80 μA

VDDQSNS

= 1.8 V 1 μA

VDDQSNS

= 1.8 V 5 μA

LDION

= 1.8 V 5 μA

LDION

= 1.8 V 5 μA

LDION

/2 V

VDDQSNS

|I

|< 10 mA, 1.5 V ≤ V

VTTREF

|I

|< 10 mA, 1.2 V ≤ V

VTTREF

= 1.8 V, V

VDDQSNS

= 0 V, V

VDDQSNS

|I

|≤ 10 mA, 1.4 V ≤ V

VTT

|I

|< 1 A, 1.4 V ≤ V

VTT

|I

|< 2 A, 1.4 V ≤ V

VTT

|I

|≤ 10 mA, 1.2 V ≤ V

VTT

|I

|< 1 A, 1.2 V ≤ V

VTT

|I

|< 1.5 A, 1.2 V ≤ V

VTT

= 1.8 V, V

VDDQSNS

= 1.8 V, V

VDDQSNS

= 1.8 V 30 μA

VDDQSNS

VTTREF

= 1.8 V 10 mA

VTTREF

VDDQSNS
VDDQSNS
VDDQSNS

VDDQSNS
VDDQSNS

VDDQSNS

= V

VTT

= V

VTT

VTTSNS
VTTSNS

VDDQSNS

Wake up 2.67 2.90 3.00
Hysteresis 0.2

Shutdown temperature
Hysteresis

(1)

(1)

≤ 1.8 V 49% 50% 51%

VDDQSNS

< 1.5 V 48.75% 51.25%

VDDQSNS

= 0 V 10 mA

= 0.5V 1.3 mA

VTTREF

/2 V

VDDQSNS

≤ 1.8 V –20 20

(1)

≤ 1.8 V
≤ 1.8 V

(1)

–30 30
–40 40

≤ 1.4 V –20 20

(1)

≤ 1.4 V

(1)

< 1.4 V

= 0.7 V 2 A

VTTSNS

= 1.1 V 2 A

VTTSNS

= V

VTT

VTTREF

= V

VTTREF

= V

VTTREF

= 0 V, V

= 0.5 V 7 mA

VTT

–30 30
–40 40

–0.1 0.1 μA
–0.1 0.1 μA

150

10

mV

5 μA

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0.880

0.885

0.890

0.895

0.900

0.905

0.910

0.915

0.920

−10 −8 −6 −4 −2 0 2 4 6 8 10
VTTREF Current (mA)

VTTREF Voltage (V)

TA = −40°C
TA = 25°C
TA = 85°C

V

VDDQSNS

= 1.8 V

V

VDD

= 5 V

0.730

0.735

0.740

0.745

0.750

0.755

0.760

0.765

0.770

−10 −8 −6 −4 −2 0 2 4 6 8 10
VTTREF Current (mA)

VTTREF Voltage (V)

TA = −40°C
TA = 25°C
TA = 85°C

V

VDDQSNS

= 1.5 V

V

VDD

= 5 V

0

1

2

3

4

5

−40 −25 −10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

VLDOIN Supply Current (µA)

0

1

2

3

4

5

−40 −25 −10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

VLDOIN Shutdown Current (µA)

0

50

100

150

200

250

300

−40 −25 −10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

VDD Supply Current (µA)

0

1

2

3

4

5

−40 −25 −10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

VDD Shutdown Current (µA)

TPS51206

SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

6.6 Typical Characteristics

Figure 1. VDD Supply Current vs. Junction Temperature Figure 2. VDD Shutdown Current vs. Junction Temperature

www.ti.com

Figure 3. VLDOIN Supply Current vs. Junction Temperature Figure 4. VLDOIN Shutdown Current vs. Junction

Figure 5. VTTREF Load Regulation (0.9 V) Figure 6. VTTREF Load Regulation (0.75 V)

6 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Temperature

Product Folder Links: TPS51206

0.625

0.635

0.645

0.655

0.665

0.675

0.685

0.695

0.705

0.715

0.725

−1.5 −1.0 −0.5 0.0 0.5 1.0 1.5
VTT Current (A)

VTT Voltage (V)

TA = −40°C
TA = 25°C
TA = 85°C

V

VDDQSNS

= 1.35 V

V

VDD

= 5 V

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

−1.5 −1.0 −0.5 0.0 0.5 1.0 1.5
VTT Current (A)

VTT Voltage (V)

TA = −40°C
TA = 25°C
TA = 85°C

V

VDDQSNS

= 1.2 V

V

VDD

= 5 V

0.850

0.860

0.870

0.880

0.890

0.900

0.910

0.920

0.930

0.940

0.950

−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0
VTT Current (A)

VTT Voltage (V)

TA = −40°C
TA = 25°C
TA = 85°C

V

VDDQSNS

= 1.8 V

V

VDD

= 5 V

0.700

0.710

0.720

0.730

0.740

0.750

0.760

0.770

0.780

0.790

0.800

−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0
VTT Current (A)

VTT Voltage (V)

TA = −40°C
TA = 25°C
TA = 85°C

V

VDDQSNS

= 1.5 V

V

VDD

= 5 V

0.660

0.665

0.670

0.675

0.680

0.685

0.690

−10 −8 −6 −4 −2 0 2 4 6 8 10
VTTREF Current (mA)

VTTREF Voltage (V)

TA = −40°C
TA = 25°C
TA = 85°C

V

VDDQSNS

= 1.35 V

V

VDD

= 5 V

0.585

0.590

0.595

0.600

0.605

0.610

0.615

−10 −8 −6 −4 −2 0 2 4 6 8 10
VTTREF Current (mA)

VTTREF Voltage (V)

TA = −40°C
TA = 25°C
TA = 85°C

V

VDDQSNS

= 1.2 V

V

VDD

= 5 V

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Typical Characteristics (continued)

Figure 7. VTTREF Load Regulation (0.675 V) Figure 8. VTTREF Load Regulation (0.6 V)

TPS51206

SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

Figure 9. VTT Load Regulation (0.9 V) Figure 10. VTT Load Regulation (0.75 V)

Figure 11. VTT Load Regulation (0.675 V) Figure 12. VTT Load Regulation (0.6 V)

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1000 10000 100000 1000000 10000000

−80

−60

−40

−20

0

20

40

60

80

−180

−135

−90

−45

0

45

90

135

180

Frequency (Hz)

Gain (dB)

Phase (°)

Gain
Phase

Sink: −1 A
V

VDD

= 5 V

V

VDDQSNS

= 1.5 V

1000 10000 100000 1000000 10000000

−80

−60

−40

−20

0

20

40

60

80

−180

−135

−90

−45

0

45

90

135

180

Frequency (Hz)

Gain (dB)

Phase (°)

Gain
Phase

Source: +1 A
V

VDD

= 5 V

V

VDDQSNS

= 1.5 V

I

VTT

(2 A/div)

V

VTTREF

(10 mV/div) 0.675 V offset

Time (200 ms/div)

V

VTT

(20 mV/div)

0.675 V offset

V

VDDQSNS

(50 mV/div)

1.35 V offset

I

VTT

(2 A/div)

V

VTTREF

(10 mV/div) 0.6 V offset

Time (200 ms/div)

V

VTT

(20 mV/div)

0.6 V offset

V

VDDQSNS

(50 mV/div)

1.2 V offset

I

VTT

(2 A/div)

V

VTTREF

(10 mV/div) 0.9 V offset

Time (200 ms/div)

V

VTT

(20 mV/div)

0.9 V offset

V

VDDQSNS

(50 mV/div)

1.8 V offset

I

VTT

(2 A/div)

V

VTTREF

(10 mV/div) 0.75 V offset

Time (200 ms/div)

V

VTT

(20 mV/div)

0.75 V offset

V

VDDQSNS

(50 mV/div)

1.5 V offset

TPS51206

SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

Typical Characteristics (continued)

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Figure 13. VTT Load Transient Response (0.9 V)

Figure 15. VTT Load Transient Response (0.675 V)

Figure 14. VTT Load Transient Response (0.75 V)

Figure 16. VTT Load Transient Response (0.6 V)

Figure 17. VTT (Sink: -1 A) Bode Plot (0.75 V) Figure 18. VTT (Source: +1 A) Bode Plot (0.75 V)

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I

VTTREF

= 0 A

I

VTT

= 0 A

S3/S5: High to Low

V

VTTREF

(500 mV/div)

V

VTT

(500 mV/div)

VS5(5 V/div)

VS3(5 V/div)

Time (2 s/div)

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.0 0.5 1.0 1.5 2.0
VTT Current (A)

VTT Dropout Voltage (V)

V

OUT

= 0.900 V

V

OUT

= 0.750 V

V

OUT

= 0.675 V

V

OUT

= 0.600 V

TA = 25°C
V

VDD

= 5 V

V

VTTREF

(500 mV/div)

Time (40 ms/div)

V

VTT

(500 mV/div)

VS5(5 V/div)

VS3(5 V/div)

I

VTTREF

= 0 A

S5: Low to High

I

VTTREF

= 0 A

I

VTT

= 0 A

S3: Low to High

V

VTTREF

(500 mV/div)

V

VTT

(500 mV/div)

VS5(5 V/div)

VS3(5 V/div)

Time (1 ms/div)

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Typical Characteristics (continued)

Figure 19. Start-Up Waveforms (S5: Low to High) Figure 20. Start-Up Waveforms (S3: Low to High)

TPS51206

SLUSAH1B –MAY 2011–REVISED DECEMBER 2014

Figure 21. Shutdown Waveforms (S3/ S5: High to Low)

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Figure 22. VTT Dropout Voltage

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