Texas Instruments TPS51117PW, TPS51117RGY Schematic [ru]

VBST

DRVH

EN_PSV

TON

VOUT

TPS51117RGY

TRIP

V5DRV

DRVL

PGND

V5FILT

VFB

PGOOD

GND

VOUT

0.75V~5.5V

PGND

PGOOD

+5V

EN_PSV

VIN

1.8V~28V

GND

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...................................................................................................................................... SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009

SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER

Check for Samples :TPS51117

FEATURES

• High Efficiency, Low Power Consumption,

4.5-μA Typical Shutdown Current

• Fixed Frequency Emulated On-Time Control, Adjustable from 100 kHz to 550 kHz

• D-CAP™ Mode with 100-ns Load Step Response

• < 1% Initial Reference Accuracy

• Output Voltage Range: 0.75 V to 5.5 V

• Wide Input Voltage Range: 1.8 V to 28 V

• Selectable Auto-Skip/PWM-Only Operation

• Temperature Compensated (4500 ppm/°C) Low-Side R

• Negative Overcurrent Limit

• Integrated Boost Diode

• Integrated OVP/UVP and Thermal Shutdown

• Power-Good Signal

• Internal 1.2-ms Voltage Softstart

• Integrated Output Discharge (Softstop)

Overcurrent Sensing

DS(on)

TPS51117

DESCRIPTION

The TPS51117 is a cost effective, synchronous buck controller for POL voltage regulation in notebook PC applications. The controller is dedicated for Adaptive On-Time D-CAP™ Mode operation that provides ease of use, low external component count, and fast transient response. Auto-skip mode for high efficiency down to the milli-ampere load range, or PWM-only mode for low noise operation is selectable.

The current sensing scheme for positive overcurrent and negative overcurrent protection is loss-less low-side R

DS(on)

compensation. The device receives a 5-V (4.5 V to

5.5 V) supply from another regulator such as the TPS51120 or TPS51020. The conversion input can be either VBAT or a 5-V rail, ranging from 1.8 V to 28 V, and the output voltage range is from 0.75 V to

5.5 V. The TPS51117 is available in a 14-pin QFN or a

14-pin TSSOP package and is specified from –40°C to 85°C.

sensing plus temperature

APPLICATIONS

• Notebook Computers

• I/O Supplies

• System Power Supplies

2D-CAP is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TPS51117

SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009......................................................................................................................................

ORDERING INFORMATION

–40°C to 85°C

(1) All packaging options have Cu NIPDAU lead/ball finish. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

PACKAGE PINS ORDER ECO PLAN

PLASTIC Green

TSSOP (PW) (RoHS & no Sb/Br)

PLASTIC QFN Green

(RGY) (RoHS & no Sb/Br)

ORDERING PART OUTPUT

NUMBER SUPPLY

TPS51117PW Tube 90

TPS51117PWR Tape-and-Reel 2000 TPS51117RGYT 250 TPS51117RGYR 1000

14 Tape-and-Reel

(1) (2)

MINIMUM

QUANTITY

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ABSOLUTE MAXIMUM RATINGS

VBST –0.3 to 36 VBST (with respect to LL) –0.3 to 6

Input voltage range EN_PSV, TRIP, V5DRV, V5FILT –0.3 to 6 V

VOUT –0.3 to 6 TON –0.3 to 6 DRVH –1 to 36 DRVH (with respect to LL) –0.3 to 6

Output voltage range LL –1 to 30 V

PGOOD, DRVL –0.3 to 6 PGND –0.3 to 0.3

Operating free-air temperature –40 to 85 °C

Storage temperature range –55 to 150 °C

stg

Junction temperature range –40 to 125 °C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

VALUE UNIT

DISSIPATION RATINGS

PACKAGE

14 Pin TSSOP 750 mW 7.5 mW/°C 300 mW

14 Pin QFN 1.3 W 13.0 mW/°C 520 mW

Ta <25°C DERATING FACTOR TA= 85°C

POWER RATING ABOVE TA= 25°C POWER RATING

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Supply input voltage range 4.5 5.5 V

VBST 4.5 34 VBST (with respect to LL) 4.5 5.5

Input voltage range EN_PSV, TRIP, V5DRV, V5FILT –0.1 5.5 V

VOUT –0.1 5.5 TON –0.1 5.5

Product Folder Link(s) :TPS51117

TPS51117

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RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

Output voltage range LL –0.8 28 V

Operating free-air temperature, T

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

SUPPLY CURRENT

V5FILTPWM

V5FILTSKIP

V5DRVSDN

V5FILTSDN

VOUT AND VFB VOLTAGES

OUT

VFB

VFB_TOL

VFB

Dischg

ON-TIME TIMER AND INTERNAL SOFT START

ONN

ONF

ONS

ON(MIN)

OFF(MIN)

OUTPUT DRIVERS

DRVH

DRVL

(1) Design constraint, ensure actual on-time is larger than the max value (i.e., design R

...................................................................................................................................... SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009

MIN MAX UNIT

DRVH –0.8 34 DRVH (with respect to LL) –0.1 5.5

PGOOD, DRVL –0.1 5.5 PGND –0.1 0.1

–40 85 °C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply current 400 750 μA

Supply current 250 470 μA

V5FILT + V5DRV current, PWM, EN_PSV = float, VFB = 0.77V, LL = –0.1 V

V5FILT + V5DRV current, auto-skip, EN_PSV = 5 V,

VFB = 0.77V, LL = 0.5 V V5DRV shutdown current V5DRV current, EN_PSV = 0 V 0 1 μA V5FILT shutdown current V5FILT current, EN_PSV = 0 V 4.5 7.5 μA

Output voltage Adjustable output range 0.75 5.5 V VFB regulation voltage 750 mV

TA= 25°C, bandgap initial accuracy –0.9% 0.9% VFB regulation voltage tolerance

TA= 0°C to 85°C –1.3% 1.3%

TA= -40°C to 85°C –1.6% 1.6% VFB input current VFB= 0.75 V, absolute value 0.02 0.1 μA VOUT discharge resistance EN_PSV = 0 V, V

Nominal on time VLL= 12 V, V Fast on time VLL= 12 V, V Slow on time VLL= 12 V, V Minimum on time V

Minimum off time 440 ns

Internal soft start time 0.82 1.2 1.5 ms

DRVH resistance

DRVL resistance

OUT

VFB= 0.7 V, LL = -0.1 V,

TRIP = open

Time from EN_PSV > 3 V to VFBregulation

value = 0.735 V

Source, V

Sink, V

Source, V

Sink, V

OUT OUT OUT

= 0.75 V, R

VBST-DRVH

DRVH-LL

V5DRV-DRVL

DRVL-PGND

DRVH-low (DRVH = 1 V) to DRVL-high Dead time

(DRVL = 4 V), LL = –0.05 V

DRVL-low (DRVL = 1 V) to DRVH-high

(DRVH = 4V), LL = –0.05 V

= 0.5 V 20 32 Ω

OUT

= 2.5 V, R = 2.5 V, R = 2.5 V, R

= 100 kΩ to 28 V

TON

= 250 kΩ 750 ns

TON

= 100 kΩ 264 330 396 ns

TON

= 400 kΩ 1169 ns

TON

(1)

80 110 140 ns

= 0.5 V 5 7 Ω

= 0.5 V 1.5 2.5 Ω

= 0.5 V 5 7 Ω

= 0.5 V 1.5 2.5 Ω

10 20 50 ns

30 40 60 ns

such that the min tolerance is 100 kΩ).

TON

Product Folder Link(s) :TPS51117

TPS51117

SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009......................................................................................................................................

ELECTRICAL CHARACTERISTICS (Continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL BST DIODE

FBST

VBSTLK

UVLO/LOGIC THRESHOLD

UVLO

EN_PSV

POWERGOOD COMPARATOR

THPG

PGMAX

PGDEL

CURRENT SENSE

TRIP

CITRIP

Rtrip

OCLoff

UCLoff

ZCoff

UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

OVP

OVPDEL

UVP

UVPDEL

UVPEN

THERMAL SHUTDOWN

SDN

(1) Ensured by design. Not production tested.

Forward voltage V

V5DRV-VBST

, IF = 10 mA, TA= 25°C 0.7 0.8 0.9 V

VBST leakage current VBST = 34 V, LL = 28 V 0.1 1 μA

V5FILT UVLO Threshold

Wake up 3.7 3.9 4.1 V Hysteresis 200 300 400 mV EN_PSV low 0.7 1.0 1.3 V

Hysteresis 150 200 250 mV EN_PSV logic input voltage

EN_PSV float (set PWM_only mode) 1.7 1.95 2.25 V

EN_PSV high (set Auto_skip mode) 2.4 2.65 2.9 V

Hysteresis 100 175 250 mV EN_PSV source current EN_PSV = GND, absolute value

(1)

1 μA

PG in from lower (PGOOD goes high) 92.5% 95% 97.5%

PG threshold

PG low hysteresis (PGOOD goes low) –4% –5.5% –7%

PG in from higher (PGOOD goes high) 102% 105% 107%

PG high hysteresis (PGOOD goes low) 4% 5.5% 7% PG sink current PGOOD = 0.5 V 2.5 7.5 mA PG delay Delay for PGOOD in 45 63 85 μs

TRIP source current V ITRIP temperature

coefffecient Current limit threshold

range setting range Overcurrent limit

comparator offset Negative overcurrent limit (V

comparator offset EN_PSV = float Zero crossing comparator

offset

< 0.3 V, TA= 25°C 9 10 11 μA

TRIP

On the basis of 25°C 4500 ppm/°C

TRIP-GND

TRIP-GND-VPGND-LL

TRIP-GND-VLL-PGND

PGND-LL

(1)

voltage

, all temperatures 30 200 mV

) voltage V ) voltage V

TRIP-GND

= 60 mV –10 0 10 mV = 60 mV,

–9.5 0.5 10.5 mV

voltage, EN_PSV = 3.3 V –9.5 0.5 10.5 mV

VFB OVP trip threshold OVP detect 111% 115% 119% VFB OVP propagation

delay

VFB UVP trip threshold

(1)

See

1.5 μs

UVP detect 65% 70% 75%

Hysteresis 10% VFB UVP delay 22 32 42 μs UVP enable delay After 1.7 × TSS, UVP protection engaged 1.4 2 2.6 ms

Thermal shutdown threshold

Shutdown temperature

Hysteresis

(1)

160 °C

12 °C

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Product Folder Link(s) :TPS51117

VBST

V5DRV

EN_PSV

TON

PGOOD

DRVH

DRVL

VFB

VOUT

V5FILT

TRIP

GND

PGND

TSSOP (PW)PACKAGE

(TOP VIEW)

VBST

DRVH

EN_PSV

TON

VOUT

TRIP

V5DRV

DRVL

PGND

V5FILT

VFB

PGOOD

GND

QFN(RGY)PACKAGE

(BOTTOMVIEW)

TPS51117

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NAME NO.

DRVH 13 O

DRVL 9 O

EN_PSV 1 I GND 7 I Signal ground pin.

LL 12 I/O High-side NFET gate driver return. Also serves as anode of overcurrent comparator. PGND 8 I/O

PGOOD 6 O TON 2 I On-time / frequency adjustment pin. Connect to LL with 100-kΩ to 600-kΩ resistor. TRIP 11 I

VBST 14 I internal PN diode is connected between V5DRV to this pin. Designer can add external schottky diode if

VFB 5 I SMPS voltage feedback input. Connect the resistor divider here for adjustable output. VOUT 3 I

V5DRV 10 I

V5FILT 4 I mV/μs or less and Tj< 85°C to secure safe start-up of the internal reference circuit. Apply RC filter consists of

...................................................................................................................................... SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

High-side NFET gate driver output. Source 5 Ω, sink 1.5 Ω LL-node referenced driver. Drive voltage corresponds to VBST to LL voltage.

Rectifying (low-side) NFET gate driver output. Source 5 Ω, sink 1.5 Ω PGND referenced driver. Drive voltage is V5DRV voltage.

Enable/power save pin. Connect to ground to disable SMPS. Connect to 3.3 V or 5 V to turn on SMPS and activate skip mode. Float to turn on SMPS but disable skip mode (forced continuous conduction mode).

Ground return for rectifying NFET gate driver. Also cathode of overcurrent protection and source node of the output discharge switch.

Power-good window comparator, open-drain, output. Pull up to 5-V rail with a pull-up resistor. Current capability is 7.5 mA.

Overcurrent trip point set input. Connect resistor from this pin to signal ground to set threshold for both overcurrent and negative overcurrent limit.

Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to LL-node. An forward drop is critical to drive the power NFET.

Connect to SMPS output. This terminal serves two functions: output voltage monitor for on-time adjustment, and input for the output discharge switch.

5-V Power supply input for FET gate drivers. Internally connected to VBST by a PN diode. Connect 1 μF or more between this pin and PGND to support instantaneous current for gate drivers.

5-V Power supply input for all the control circuitry except gate drivers. Supply 5-V ramp rate should be 17 300 Ω + 1 μF or 100 Ω + 4.7 μF at the pin input.

Product Folder Link(s) :TPS51117

2.9

3.9/3.6

TPS51117

SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009......................................................................................................................................

FUNCTIONAL BLOCK DIAGRAM

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DETAILED DESCRIPTION

PWM OPERATION

The main control loop of the TPS51117 is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports proprietary D-CAP™ Mode that uses an internal compensation circuit and is suitable for minimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) is allowed. Basic operation of D-CAP Mode can be described as follows.

Product Folder Link(s) :TPS51117

OUT

1 )

0.75 V

OUT(LL)

2 L ƒ

VIN* V

OUT

TPS51117

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At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after the internal one shot timer expires. This one shot is determined by VINand V hence it is called adaptive on-time control or fixed frequency emulated on-time control (see PWM frequency and Adaptive On-Time Control). The MOSFET is turned on again when both feedback information, monitored at V voltage, indicates insufficient output voltage AND inductor current information indicates below the overcurrent limit. Repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side or rectifying MOSFET is turned on each OFF state to keep the conduction loss to a minimum.

The TPS51117 supports selectable PWM-only and auto-skip operation modes. If EN_PSV is grounded, the switching regulator is disabled. If the EN_PSV pin is connected to 3.3 V or 5 V, the regulator is enabled with auto-skip mode selected. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables a seamless transition to reduced frequency operation during a light load condition so that high efficiency is maintained over a broad range of load currents. If the EN_PSV pin is floated, it is internally pulled up to 1.95 V, and the regulator is enabled with PWM-only mode selected. The rectifying MOSFET is not turned off when inductor current reaches zero. The converter runs forced continuous conduction mode for the entire load range. System designers may want to use this mode to avoid a certain frequency during a light load condition but with the cost of low efficiency. However, be aware the output has the capability to both source and sink current in this mode. If the output terminal is connected to a voltage source higher than the regulator’s target, the converter sinks current from the output and boosts the charge into the input capacitor. This may cause unexpected high voltage at VIN and may damage the power FETs.

DC output voltage can be set by the external resistor divider as follows (refer to Figure 23, Figure 24, and

Figure 25).

...................................................................................................................................... SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009

DETAILED DESCRIPTION (continued)

to keep the frequency fairly constant over the input voltage range at steady state,

OUT

(1)

LIGHT LOAD CONDITION WITH AUTO-SKIP FUNCTION

If auto-skip mode is selected, the TPS51117 automatically reduces the switching frequency during a light load condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without an increase of V

ripple or load regulation. Detailed operation is described as follows. As the output current decreases from a

out

heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. Since the output voltage is still higher than the reference at this moment, both high-side and low-side MOSFETs are turned off and wait for the next cycle. As the load current decreases further, the converter runs in discontinuous conduction mode, taking longer time to discharge the output capacitor below the reference voltage. Note the ON time is kept the same as during the heavy load condition. In reverse, when the output current increases from a light load to a heavy load, the switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to light load operation, I continuous and discontinuous conduction mode), can be calculated as follows:

where fswis the PWM switching frequency. Switching frequency versus output current in the light load condition is a function of L, fsw, VINand V

decreases almost proportional to the output current from the I at I

/5 if the PWM switching frequency is 300 kHz.

OUT(LL)

given above. For example, it is about 60 kHz

OUT(LL)

(i.e., the threshold between

(2)

, but it

OUT

Product Folder Link(s) :TPS51117

TON+ 19 10

*12

TON

(2ń3)V

OUT

) 100 mV

) 50 ns

100

200

300

400

500

600

f-Frequency-kHz

100

R -k

TON

400 500 600

700

200 300

V =15V, V =2.5V, PWM

OUT

TPS51117

SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009......................................................................................................................................

DETAILED DESCRIPTION (continued)

PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL

The TPS51117 employs an adaptive on-time control scheme and does not have a dedicated oscillator on board. However, the device emulates a constant frequency by feed-forwarding the input and output voltages into the on-time one-shot timer. The ON time is controlled inverse proportional to the input voltage, and proportional to the output voltage, so that the duty ratio is kept as V

OUT/VIN

shows a simplified calculation of the on time.

Here, R

is the external resistor connected from TON pin to the LL node. In the equation, 19 pF represents the

TON

internal timing capacitor with some typical parasitic capacitance at the TON pin. Also, 50 nsec is the turn-off delay time contributed by the internal circuit and that of the high-side MOSFET. Although this equation provides a good approximation to start with, the accuracy depends on each design and selection of the high-side MOSFET.

Figure 1 shows the relationship of R

to the switching frequency.

TON

technically with the same cycle time. Equation 3

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(3)

The TPS51117 does not have a pin connected to VIN, but the input voltage information comes from the switch node (LL node) during the ON state. An advantage of LL monitoring is that the loss in the high-side NFET is now a part of the on-time calculation, thereby making the frequency more stable with load.

Another consideration about frequency is jitter. Jitter may be caused by many reasons, but the constant on-time D-CAP mode scheme has some amount of inherent jitter. Since the output voltage ripple height is in the range of a couple of tens of milli-volts. A milli-volt order of noise on the feedback signal can affect the frequency by a few to ten percent. This is normal operation and has little harm to the power supply performance.

LOW-SIDE DRIVER

The low-side driver is designed to drive high-current, low R represented by its internal resistance, which is 5 Ω for V5DRV to DRVL and 1.5 Ω for DRVL to PGND. A dead time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. A 5-V bias voltage is delivered from V5DRV supply. The average drive current is calculated by the FET gate charge at Vgs= 5 V times the switching frequency. The instantaneous drive current is supplied by an input capacitor connected between V5DRV and GND.

Figure 1. Switching Frequency vs R

N-channel MOSFET(s). The drive capability is

DS(on)

Product Folder Link(s) :TPS51117

TON

TRIP

(mV) + R

TRIP

(kW) 10 (mA)

ocp

+ V

TRIPńRDS(on)

) I

ripple

ń2 +

TRIP

DS(on)

)

2 L ƒ

VIN* V

OUT

TPS51117

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HIGH-SIDE DRIVER

The high-side driver is designed to drive high-current, low R floating driver, 5-V bias voltage is delivered from V5DRV supply. An internal PN diode is connected between V5DRV to VBST. The designer can add an external schottky diode if forward drop is critical to drive the high-side NFET or to achieve the last one percent efficiency improvement. The average drive current is also estimated by the gate charge at Vgs= 5 V times the switching frequency. The instantaneous drive current is supplied by the flying capacitor between the VBST pin and LL pin. The drive capability is represented by its internal resistance, which is 5 Ω for VBST to DRVH and 1.5 Ω for DRVH to LL.

SOFTSTART

The TPS51117 has an internal, 1.2-ms, voltage servo softstart with overcurrent limit. When the EN_PSV pin becomes high, an internal DAC begins ramping up the reference voltage to the error amplifier. Smooth control of the output voltage is maintained during start up.

POWERGOOD

The TPS51117 has power-good output. PGOOD is an open drain 7.5-mA pull-down output. This pin should be typically connected to a 5-V power supply node through a 100-kΩ resistor. The power-good function is activated after the soft start has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect the power-good state and the power-good signal becomes high after a 64-μs internal delay. If the output voltage goes outside ±10% of the target value, the power-good signal becomes low immediately.

...................................................................................................................................... SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009

DETAILED DESCRIPTION (continued)

N-channel MOSFET(s). When configured as a

DS(on)

OUTPUT DISCHARGE CONTROL (SOFTSTOP)

The TPS51117 discharges output when EN_PSV is low or the converter is in a fault condition (UVP, OVP, UVLO, or thermal shutdown). The TPS51117 discharges output using an internal 20-Ω MOSFET which is connected to VOUT and PGND. The discharge time-constant is a function of the output capacitance and resistance of the discharge transistor.

OVERCURRENT LIMIT

The TPS51117 has cycle-by-cycle overcurrent limiting control. Inductor current is monitored during the OFF state and the controller keeps the OFF state when inductor current is larger than the overcurrent trip level. In order to provide both good accuracy and a cost effective solution, the TPS51117 supports temperature compensated MOSFET R R

. The TRIP terminal sources 10-μA I

TRIP

the following equation.

Inductor current is monitored by the voltage between the PGND pin and the LL pin so the LL pin should be connected to the drain terminal of the low-side MOSFET. I compensate the temperature dependency of the R PGND should be connected to the source terminal of the bottom MOSFET.

As the comparison is done during the OFF state, V current at overcurrent threshold, I

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall. Eventually it crosses the undervoltage protection threshold and shutdown.

sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor,

DS(on)

, can be calculated as follows;

ocp

current, and the trip level is set to the OCL trip voltage, V

TRIP

has 4500 ppm/°C temperature coefficient to

TRIP

. PGND is used as the positive current sensing node so

DS(on)

sets the valley level of the inductor current. Thus, the load

TRIP

as in

(4)

(5)

Product Folder Link(s) :TPS51117

t – Time

UDG-09142

V5DRV

EN_PSV

VOUT

PGOOD

5V UVLO

V5FILT

TPS51117

SLVS631B –DECEMBER 2005–REVISED SEPTEMBER 2009......................................................................................................................................

DETAILED DESCRIPTION (continued)

NEGATIVE OVERCURRENT LIMIT (PWM-ONLY MODE)

The TPS51117 also supports cycle-by-cycle negative overcurrent limiting in PWM-only mode. The overcurrent limit is set to be negative but is the same absolute value as the positive overcurrent limit. If output voltage continues to rise, the bottom MOSFET stays on, thus inductor current is reduced and reverses direction after it reaches zero. When there is too much negative current in the inductor, the bottom MOSFET is turned off and the current flows to VIN through the body diode of the top MOSFET. Because this protection reduces current to discharge the output capacitor, output voltage tends to rise, eventually hitting the overvoltage protection threshold and shutdown. In order to prevent false OVP from triggering, the bottom MOSFET is turned on again 400 ns after it is turned off. If the device hits the negative overcurrent threshold again before output voltage is discharged to the target level, the bottom MOSFET is turned off and the process repeats, which is called NOCL Buzz. It ensures maximum allowable discharge capability when output voltage continues to rise. On the other hand, if the output voltage is discharged to the target level before the NOCL threshold is reached, the bottom MOSFET is turned off, the top MOSFET is then turned on, and the device resumes normal operation.

OVERVOLTAGE PROTECTION

The TPS51117 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage condition. When the feedback voltage becomes higher than 115% of the target value, the top MOSFET is turned off and the bottom MOSFET is turned on immediately. The output is also discharged by the internal 20-Ω transistor. Also, the TPS51117 monitors VOUT terminal voltage directly and if it becomes greater than 5.75 V, it turns off the top MOSFET driver.

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UNDERVOLTAGE PROTECTION

When the feedback voltage becomes lower than 70% of the target value, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 μs, the TPS51117 latches off the high-side and low-side MOSFETs and discharges the output with the internal 20-Ω transistor. This function is enabled after 2 ms from when EN_PSV is brought high, i.e., UVP is disabled during start up.

START UP SEQUENCE

Referring to Figure 2 which illustrates the timing sequence, to guarantee the proper startup the TPS51117, always ensure that V

EN_PSV

is less or equal to that of V

V5FILT

prior to V

V5FILT

reaching V

UVLO

Figure 2. Startup Timing Sequence

Product Folder Link(s) :TPS51117

+ 21 hidden pages

Texas Instruments TPS51117PW, TPS51117RGY Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS (Continued)

DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM

DETAILED DESCRIPTION

PWM OPERATION

LIGHT LOAD CONDITION WITH AUTO-SKIP FUNCTION

PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL

LOW-SIDE DRIVER

HIGH-SIDE DRIVER

SOFTSTART

POWERGOOD

OUTPUT DISCHARGE CONTROL (SOFTSTOP)

OVERCURRENT LIMIT

NEGATIVE OVERCURRENT LIMIT (PWM-ONLY MODE)

OVERVOLTAGE PROTECTION

UNDERVOLTAGE PROTECTION

START UP SEQUENCE