Texas Instruments TPS5103IDB, TPS5103IDBR, TPS5103EVM-136 Datasheet

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SOFTSTART

INV

FB C

GND

REF

COMP

PWMSKIP

STBY

LH OUT_u LL OUT_d OUTGND TRIP VCC_SENSE VCC VREF5 VREG5V_IN

DB PACKAGE

(TOP VIEW)

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Step-Down DC-DC Converter

Three Operation-Mode – Heavy Load:

– Fixed Frequency PWM – Hysteretic (User Selctable)

– Light Load:

– Skip Mode

4.5 V to 25 V Input Voltage Range

Adjustable Output Voltage Down to 1.2 V

95% Efficiency

Stand-By Control

Over Current Protection

UVLO for Internal 5 V Regulation

Low Standby Current . . . 0.5 mA T ypical

TA = –40°C to 85°C

description

The TPS5103 is a synchronous buck dc/dc controller, designed for notebook PC system power . The controller has three user-selectable operation modes available; hysteretic mode, fixed frequency PWM control, or SKIP control.

In high current applications, where fast transient response is advantageous for reducing bulk capacitance, the hysteretic mode is selected by connecting the Rt pin to Vref5. Selecting the PWM/SKIP modes for less demanding transient applications is ideal for conserving notebook battery life under light load conditions. The device includes high-side and low-side MOSFET drivers capable of driving low Rds (on) N–channel MOSFET s.

The user-selectable overcurrent protection (OCP) threshold is set by an external TRIP pin resister in order to protect the system. The TPS5103 is configured so that a current sense resistor is not required, improving the operating efficiency.

SOFTSTART

INV

GND

REF

COMP

PWM/SKIP

STBY

OUTU

OUTD

OUTGND

TRIP

VCCSENSE

VREF5

VREG5V_IN

VCC

TPS5103

OUTPUT

5 V

Figure 1. Typical Design

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

_ +

Soft Start

_ +

1.185 V

Error Amp

_ +

PWM Comp.

One Shot ON

_ +

OSC

_ +

Disable

1.185 V

UVLO

_ +

VREF

1.185 V

SOFT START

INV

PWMSKIP

Comp

GND

STBY

REF

OUT_u LL

OUT_d OUTGND

TRIP

VCC_SENSE

VREF5

VREG5V_IN

AVAILABLE OPTIONS

PACKAGE

SSOP(DB) EVM

TPS5103IDB TPS5103EVM–136

–40 °C to 85

°C

TPS5103IDBR

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

COMP 8 I Comparator input for voltage monitor C

4 I/O

External capacitor from CT to GND for adjusting the triangle oscillator and decreasing the current limiting

voltage FB 3 O Feedback output of error amp GND 6 Control GND INV 2 I Inverting input of both error amp and hysteretic comparator LH 20 I/O Bootstrap. Connect 1 µF low-ESR capacitor from LH to LL.

LL 18 I/O

Bootstrap low. High side gate driving return and output current protection. Connect to the junction of the high

side and low side FETs for floating drive configuration. OUT_d 17 I/O Gate-drive output for low-side power switching FET s OUTGND 16 Ground for FET drivers OUT_u 19 O Gate-drive output for high-side power switching FETs

PWMSKIP 9 I

PWM/SKIP mode select

L:PWM mode

H:SKIP mode REF 7 O 1.185-V reference voltage output R

5 I/O External resistor connection for adjusting the triangle oscillator. SOFTSTAR T 1 I External capacitor from SOFTSTART to GND for soft start control STBY 10 I Standby control TRIP 15 I External resistor connection for output current control V

13 I Supply voltage input VCC_SENSE 14 I Supply voltage sense for current protection VREF5 12 O 5-V-internal regulator output VREG5V_IN 11 I External 5-V input (input voltage range = 4.5 V to 25 V)

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

REF

The reference voltage is used for the output voltage setting and the voltage protection(COMP). The tolerance is 1.5% typically .

VREF5

An internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage range is from 4.5 V to 25 V, this voltage offers a fixed voltage for the bootstrap voltage so that the design for the bootstrap is much easier. The tolerance is 6%.

hysteretic comparator

The hysteretic comparator is used to regulate the output voltage of the synchronous-buck converter. The hysteresis is set internally and is typically 9.7 mV. The total delay time from the comparator input to the driver output is typically 400 ns for going both high and low.

error amplifier

The error amplifier is used to sense the output voltage of the synchronous buck converter. The negative input of the error amplifier is connected to the Vref voltage(1.185 V) with a resistive divider network. The output of the error amplifier is brought out to the FB terminal to be used for loop gain compensation.

low-side driver

The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V from VREF5. The current rating of driver is typically 1.2 A at sink current, –1.5 A at source current.

high-side driver

The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is

1.2 A at sink current, –1.7 A at source current. When configured as a floating driver, the bias voltage to the driver is developed from the VREF5, limiting the maximum drive voltage between OUT_u and LL to 5 V . The maximum voltage that can be applied between LH and OUTGND is 30 V.

driver deadtime control

The deadtime control prevents shoot-through current from flowing through the main power FETs. During

switching transitions the

deadtime control actively controls the turnon time of the MOSFET drivers. The typical

deadtime from the low-side-driver-off to the high-side-driver-on is 90 ns, and 110 ns from high-side-driver-off to low-side-driver-on.

COMP

COMP is designed for use with a regulation output monitor. COMP also functions as an internal comparator used for any voltage protection such as the input under voltage protection. If the input voltage is lower than the setpoint, the comparator turns off and prevents external parts from damage. The investing terminal of the comparator is internally connected to REF(1.185 V).

current protection

Current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during on-time through VCC_SENSE and LL terminals. An external resistor between Vin and TRIP terminal with the internal current source connected to the current comparator negative input adjusts the current limit. The typical internal current source value is 15 µA in PWM mode, 5 µA in SKIP mode. When the voltage on the positive terminal is lower than the negative terminal, the current comparator turns on the trigger, and then activates the oscillator. This oscillator repeatedly reset the trigger until the over current condition is removed. The capacitor on the C

terminal can be open or added to adjust the reset frequency.

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

softstart

SOFTST ART sets the sequencing of the output for any possibility . The capacitor value for a start-up time can be calculated by the following equation: C = 2xT (uF) where C is the external capacitor value, T is the required start-up time in (ms).

standby

This controller can be switched into standby mode by grounding the STBY terminal. When it is in standby mode, the quiescent current is less than 1.0 uA.

UVLO

The under-voltage-lock-out (ULVO) threshold is approximately 3.8 V. The typical hysteresis is 55 mV.

5-V Switch

5-V Switch if the internal 5-V switch senses a 5-V input from REG5V terminal, the internal 5-V linear regulator will be disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and the high-side bootstrap, thus increasing the efficiency.

PWM/SKIP switch

The PWM/SKIP switch selects the output operating mode. This controller has three operational modes, PWM, SKIP, and Hysteretic. The PWM and SKIP mode control should be used for slower transient applications.

oscillator

The oscillator gives a triangle wave by connecting an external resistor to the R

terminal and an external capacitor to the CT terminal. The voltage amplitude is 0.43 V ~ 1.17 V. This wave is connected to the noninverting input of the PWM comparator.

Comparison Table Between PWM Mode and Hysteretic Mode

MODE PWM HYSTERETIC

Frequency Fixed Not Fixed Transient Response Normal Very fast Feed back compensation Need Needless

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, VCC (see Note 1) –0.3 V to 27 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, VI, INV, CT, RT, PWM/SKIP, SOFTSTART, COMP –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, VREG5V_IN –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, STBY –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, TRIP, VCC_SENSE –0.3 V to 27 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, I

3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Low level output voltage, VOL –0.3 V to 27 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

High level output voltage, V

–0.3 V to 32 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage, V

ref

–0.3 V to 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to the network ground terminal.

2. See Dissipation Rating Table for free-air temperature range above 25°C.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 85°C

POWER RATING

DB 801 mW 6.408mW/°C 416 mW

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage 4.5 25 V

INV, CT, RT, COMP, PWM_SKIP, SOFTSTART 6

VREG5V_IN 5.5

VIInput voltage

STBY 12

TRIP, VCC_SENCE 25

‡

Timing register 82 kΩ

‡

Oscillator frequency

Timing capacitor 100 pF f Frequency 200 kHz T

Operating temperature range –40 85 °C

‡

Not a JEDEC symbol.

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, VCC = 7 V (unless otherwise noted)

reference voltage

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TA = 25°C, I

vref

= 50 µA 1.167 1.185 1.203

ref

Reference voltage

vref

= 50 µA

‡

1.155 1.215

Regin Line regulation

†

VCC = 4.5 V to 25 V, I = 50 µA 0.2 12 mV

Regl Load regulation

†

I = 1 µA to 1 mA 0.5 10 mV

†

Not a JEDEC symbol.

oscillator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f Frequency PWM mode 500 kHz R

Timing resistor 47 kΩ

fdv

VCC = 4.5 V to 25 V 0.1%

fdt

Frequency change

†

TA = –40°C to 85°C 2%

DC includes internal comparator error 1 1.1 1.2

‡

High-level output voltage

f = 200 kHz, includes internal comparator error 1.17

DC includes internal comparator error 0.4 0.5 0.6

‡

Low-level output voltage

f = 200 kHz, includes internal comparator error 0.43

†

Not a JEDEC symbol.

‡

The output voltages of oscillator (f = 200 kHz) are ensured by design.

error amp

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V Input offset voltage TA = 25°C 2 10 mV Av Open-loop voltage gain

†

50 dB

GB Unity-gain bandwidth

†

0.8 MHz

Output sink current VO = 0.4 V 30 45 µA

Output source current VO = 1 V 300 µA

†

Not a JEDEC symbol.

hysteresis comparator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

hsy

Hysteresis window Hysteretic mode 6 9.7 13 mV Vp-VSOffset voltage 2 mV I Bias current 10 pA t

PHL

Propagation delay from INV to OUT_U TTL input signal 230 ns t

PLH

10 mV overdrive on hysteresis band signal 400 ns

The numbers in the table include the driver delay. All numbers are ensured by design.

control

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STBY 2.5

IHA

High-level input voltage

PWM_SKIP 2

STBY 0.5

ILA

Low-level input voltage

PWM_SKIP 0.5

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, VCC = 7 V (unless otherwise noted) (continued)

5-V regulator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage I = 10 mA 4.7 5.3 V

Regin Line regulation

†

VCC = 5.5 V to 25 V, I = 10 mA 20 mV

Regl Load regulation

†

I = 1 mA to 10 mA, VCC = 5.5 V 40 mV

Short-circuit output current V

ref

= 0 V 70 mA

†

Not a JEDEC symbol.

5-V switch

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IT(high)

4.2 4.9

IT(low)

Threshold voltage

†

4.1 4.8

hsy

Hysteresis) 50 150 250 mV

†

Not a JEDEC symbol.

UVLO

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IT(high)

3.6 4.2

IT(low)

Threshold voltage

†

3.5 4.1

hys

Hysteresis 10 150 mV

†

Not a JEDEC symbol.

output

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OUT_u sink curent VO = 3 V 0.5 1.2 A

OUT_u source current VO = 2 V –1 –1.7 A

OUT_d sink current VO = 3 V 0.5 1.2 A

OUT_d source current VO = 2 V –1 –1.5 A

PWM mode, VTRIP = 7 V 10 15 20

TRIP terminal current

SKIP mode, VTRIP = 7 V 3 5 7

High side driver is GND referenced. Input: INV = 0 – 3V

Rise time

tr/tf = 10 ns,

Frequency = 200 kHz

ns CL = 2200 pF 28 CL = 3300 pF 39 High side driver is GND referenced. Input: INV = 0 – 3 V

Fall time

tr/tf = 10 ns,

Frequency = 200 kHz

ns CL = 2200 pF 30 CL = 3300 pF 38

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, VCC = 7 V (unless otherwise noted) (continued)

softstart

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(CTRL)

Softstart current 1.9 2.5 3 µA

IT(high)

3.9

IT(low)

Threshold voltage (SKIP mode)

†

2.6

†

Not a JEDEC symbol.

output voltage monitor

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Threshold voltage 1.08 1.18 1.28 V

driver deadtime section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DRVLH

Low-side to high-side 90 ns

DRVHL

High-side to low-side 110 ns

whole device

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply current 0.5 1.2 mA

I Shutdown current STBY = 0 V 0.01 10 µA

SOFTSTART

INV

OUT_u

OUT_d

OUTGND

GND

TRIP REF COMP PWM SKIP

VREF5

STBY

5V_IN

VCC_SENSE

VCC

0.1 µF

Figure 2. Test Circuit

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 3

550

500

400

300

–40 –20 25

– Quiescent Current –

600

650

QUIESCENT CURRENT

JUNCTION TEMPERATURE

700

85 125

450

350

Aµ

TJ – Junction Temperature – °C

VCC = 25 V

VCC = 7 V

VCC = 4.5 V

Figure 4

20 15

–40 –20 25

85 125

– Quiescent Current –

QUIESCENT CURRENT

JUNCTION TEMPERATURE

CCS

Aµ

TJ – Junction Temperature – °C

VCC = 25 V

VCC = 7 V

VCC = 4.5 V

Figure 5

3.5

0.1 0.7

4.5

DRIVE OUTPUT VOLTAGE

DRIVE CURRENT

5.5

(OUT_source)

– Drive Source Current – A

VCC = 7 V, TJ = 25°C

– Drive Output Voltage – VV

(OUT_u)

Figure 6

1.5

0.5

0.1 0.7

2.5

DRIVE OUTPUT VOLTAGE

DRIVE CURRENT

– Drive Output Voltage – VV

(OUT_u)

(OUT_sink)

– Drive Source Current – A

VCC = 7 V, TJ = 25°C

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 7

0.1 0.7

DRIVE OUTPUT VOLTAGE

DRIVE CURRENT

(OUT_source)

– Drive Source Current – A

TJ = 25°C

– Drive Output Voltage – VV

(OUT_d)

Figure 8

0.1 0.7

3.5

4.5

2.5

1.5

0.5

DRIVE OUTPUT VOLTAGE

DRIVE CURRENT

– Drive Output Voltage – VV

(OUT_d)

(OUT_sink)

– Drive Source Current – A

TJ = 25°C

Figure 9

VCC = 4.5 V, VCC = 7 V, VCC = 25 V

1.095

1.085

1.075 –40 –20 25

– Oscillator Output Voltage – V

1.105

1.115

OSCILLATOR OUTPUT VOLTAGE

JUNCTION TEMPERATURE

1.125

85 125

TJ – Junction Temperature – °C

(osch)

Figure 10

490

485

480

–40 –20 25

495

500

85 125

VCC = 4.5 V, VCC = 7 V, VCC = 25 V

– Oscillator Output Voltage – V

OSCILLATOR OUTPUT VOLTAGE

JUNCTION TEMPERATURE

TJ – Junction Temperature – °C

(oscl)

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 11

0.5

–40 –20 25

– Error Amplifier Input Offset V oltage – mV

1.5

ERROR AMPLIFIER INPUT OFFSET VOLTAGE

JUNCTION TEMPERATURE

2.5

85 125

VCC = 4.5 V, VCC = 7 V, VCC = 25 V

TJ – Junction Temperature – °C

Figure 12

0.5

–40 –20 25

– Error Amplifier Output V oltage – mV

1.5

ERROR AMPLIFIER OUTPUT VOLTAGE

JUNCTION TEMPERATURE

2.5

85 125

VCC = 4.5 V, VCC = 7 V, VCC = 25 V

TJ – Junction Temperature – °C

om+

Figure 13

5.2

4.8

4.4

5.8

6.2

5.6

5.4

4.6

–40 –20 25

– Error Amplifier Output V oltage – mV

ERROR AMPLIFIER OUTPUT VOLTAGE

JUNCTION TEMPERATURE

85 125

VCC = 4.5 V, VCC = 7 V, VCC = 25 V

TJ – Junction Temperature – °C

om–

Figure 14

9.75

9.5

9.25

– Hysteresis Comparator Hysteresis Voltage – mV

10.25

HYSTERESIS COMPARATOR HYSTERESIS VOLTAGE

JUNCTION TEMPERATURE

10.5

hys

–40 –20 25 85 125

VCC = 7 V

TJ – Junction Temperature – °C

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 15

VCC = 4.5 V, VCC = 7 V

VCC = 25 V

VCC = 7 V

VCC = 4.5 V

1.5

0.5

–45 –25 25

– Standby Switch Threshold Voltage – V

STANDBY SWITCH THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

2.5

95 135

IH,

TJ – Junction Temperature – °C

Figure 16

TJ = 125°C

TJ = –40°C

TJ = 25°C

4.7

4.6

4.4

4.2 010

– VREF5 Output Voltage – V

4.9

5.1

VREF5 OUTPUT VOLTAGE

SUPPLY VOLTAGE

5.2

4.8

4.5

4.3

VCC – Supply Voltage – V

Figure 17

IO – Output Current – mA

TJ = 125°C

TJ = 25°C

TJ = –40°C

0 –10 –20 –30 –40

– VREF5 Output Voltage – V

VREF5 OUTPUT VOLTAGE

OUTPUT CURRENT

–50 –60 –70

Figure 18

VCC = 25 V

VCC = 7 V

VCC = 4.5 V

–40

–20

–40 –20 25

– VREF5 Short Current – mA

–60

–80

VREF5 SHORT CURRENT

JUNCTION TEMPERATURE

–100

85 125

TJ – Junction Temperature – °C

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 19

TLH

THL

3.85

3.80

3.75

3.70 –40 –20 25

– UVOL Threshold V oltage – V

3.90

3.95

UVLO THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

85 125

THL,

TLH

TJ – Junction Temperature – °C

Figure 20

–40 –20 25

– UVLO Hysteresis Voltage – mV

UVLO HYSTERESIS VOLTAGE

JUNCTION TEMPERATURE

85 125

hys

TJ – Junction Temperature – °C

Figure 21

TJ – Junction Temperature – °C

4.60

4.50

4.40

4.35

–45 –25 25

– 5 VSW Threshold Voltage – V

4.70

4.75

5 VSW THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

4.80

95 135

4.65

4.55

4.45

TLH

THL

THL,

TLH

Figure 22

140

–45 –25 25

– 5V SW Hysteresis Voltage – mV

160

180

5 VSW HYSTERESIS VOLTAGE

JUNCTION TEMPERATURE

200

95 135

120

100

hys

TJ – Junction Temperature – °C

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 23

–2.35

–2.30

–2.25

–2.20

–40 –20 25

– Softstart Current –

–2.40

SOFTSTART CURRENT

JUNCTION TEMPERATURE

–2.45

85 125

CTRL

Aµ

VCC = 25 V

VCC = 7 V

VCC = 4.5 V

TJ – Junction Temperature – °C

Figure 24

VCC = 7 V, VCC = 25 V

VCC = 4.5 V

2.5

1.5

–40 –20 25

– Softstart Threshold Voltage – V

3.5

SOFTSTART THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

4.5

85 125

0.5

TLH

TJ – Junction Temperature – °C

Figure 25

VCC = 7 V, VCC = 25 V

VCC = 4.5 V

TJ – Junction Temperature – °C

1.5

–40 –20 25

2.5

3.5

85 125

– Softstart Threshold Voltage – V

SOFTSTART THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

THL

Figure 26

VCC = 4.5 V, VCC = 7 V, VCC = 25 V

1.188

1.185

1.183

1.180 –40 –20 25

Threshold Voltage – V

1.190

1.193

OUTPUT VOLTAGE MONITOR COMPARATOR

THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

1.195

85 125

– Output Voltage Monitor Comparator V

TJ – Junction Temperature – °C

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TYPICAL CHARACTERISTICS

Figure 27

VCC = 4.5 V, VCC = 7 V, VCC = 25 V

F = 500 kHz

F = 200 kHz

300

200

100

–40 –20 25

– Oscillator Frequency – kHz

400

500

OSCILLATOR FREQUENCY

JUNCTION TEMPERATURE

600

85 125

osc

TJ – Junction Temperature – °C

Figure 28

OSCH

OSCL

0.8

0.4

10 100

– Oscillator Output Voltahe – V

1.2

1.4

OSCILLATOR OUTPUT VOLTAGE

FREQUENCY

1.6

1000

0.6

0.2

OSCH,

OSCL

OSC

– Frequency – kHz

Figure 29

Phase

Gain

–20

1.E+03 1.E+04 1.E+05

Error Amplifier Gain – dB

f – Frequency – Hz

ERROR AMPLIFIER GAIN AND PHASE SHIFT

1.E+06 1.E+07

Rs = 100 Ω, Rf = 10 kΩ

–10

100

–60

140

180

–20

Phase Shift – Deg

TPS5103

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TYPICAL CHARACTERISTICS

Figure 30

98.5

96.5

–40 –20 25

Maximum Duty Cycle – %

99.5

MAXIMUM DUTY CYCLE

JUNCTION TEMPERATURE

100

85 125

97.5

95.5

TJ – Junction Temperature – °C

f = 200 kHz

Figure 31

0.01 0.1 1

– Softstart Capacitance – pF

SOFTSTART CAPACITANCE

SOFTSTART TIME

10 100

100

TSS – Soft Start Time – ms

Figure 32

VCC = 4.5 V

DRVHL

DRVLH

VCC = 7 V,

VCC = 25 V

VCC = 7 V,

VCC = 25 V

VCC = 4.5 V

–45 –25 25

– Driver Dead Time – ns

100

120

DRIVER DEAD TIME

JUNCTION TEMPERATURE

140

95 135

DRVLH,

DRVHL

TJ – Junction Temperature – °C

Figure 33

TRIP

– Input Voltage – V

TA = 125°C

TA = 25°C

TA = –40°C

13.75

13.25

12.75

12.5

4.5 7

– Corrent Protection Source Current –

14.25

CURRENT PROTECTION SOURCE CURRENT

INPUT VOLTAGE PWM MODE

14.5

13.5

TRIP

Aµ

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TYPICAL CHARACTERISTICS

4.3

4.2

4.1

4.4

4.5

4.6

TRIP

– Input Voltage – V

TA = 125°C

TA = 25°C

TA = –40°C

4.5 7

– Corrent Protection Source Current –

CURRENT PROTECTION SOURCE CURRENT

INPUT VOLTAGE SKIP MODE

TRIP

Aµ

Figure 34

CT = 10 pF

CT = 15 pF

CT = 22 pF

CT = 33 pF

CT = 470 pF

CT = 680 pF

400

200

100

10 100

500

600

OSCILLATOR FREQUENCY

RESISTOR

700

1000

300

– Oscillator Frequency – kHzF

osc

RT – Resistor – kΩ

Figure 35

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APPLICATION INFORMATION

overshoot of output rectangle wave

The drivers in the TPS5103 controller are fast and can produce high transients on VCC or the junction of Q1 and Q2(shown below). Care must be taken to insure that these transients do not exceed the absolute maximum rating for the device or associated external component. A low-ESR capacitor connected directly from Q1 drain to Q2 source can greatly reduce transient pulses on VCC. Also, Q1 turn-on-speed can be reduced by adding a resistor (5 – 15 Ω) in series with OUT_u. Poor layout of the switching node (V1 in figure) can result in the requirement for additional snubber circuitry require from V1 to ground.

OUT_u

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application for general power

The design shown in this data sheet is a reference design for a general power supply application. An evaluation module (EVM), TPS5103EVM-136 (SLVP136), is available for customer testing and evaluation. The intent is to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. For subsequent customer board revisions, the EVM design can be copied onto the users PCB to shorten design cycle time, component count, and board cost.

To help the customers to design the power supply using TPS5103, some key design procedures are shown below.

R13

R6B

R6A

TP10

TP9

TP8

TP7

TP6

TP5

TP4

TP11

TP12

TP13

TP14

R10

JP1 JP2

TP2

TP1

TP3

TP15

TP16

TP17

TP18

C15

C10

TP26

R11

C14

J6 J7 J8

Input GND

SENSE

J13

C12

C13

C11

R12

J14

VoGND VoGND VoGND

J12

J11

J10

Figure 36. EVM Schematic

Rz2

(

Vz–Vr

)

Vr–Vo

Rtop

)

Rbtm

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output voltage setpoint calculation

The output voltage is set by the reference voltage and the voltage divider. In TPS5102, the reference voltage is 1.185 V , and the divider is composed of two resistors in the EVM design that are R4 and R5, or R14 and R15. The equation for the setpoint is:

R1 Vr Vo*Vr

Where R1 is the top resistor (kΩ) like R4 or R15; R2 is the bottom resistor (kΩ) such as R5 or R14; Vo is the required output voltage (V); Vr is the reference voltage (1.185 V in TPS5103).

Example: R1 = 1 kΩ; Vr = 1.185 V; Vo = 1.8 V, then R2 = 1.9 kΩ. For your convenience, some of the most popular output voltage setpoints are calculated in the table below:

Vo 1.3 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V R1 (top) (kΩ) 1 1 1 1 1 1 R2 (bottom) (kΩ) 10 3.7 1.9 0.9 0.56 0.31

If higher precision resistor is used, the output voltage setpoint can be more accurate. In some applications, the output voltage is required to be lower than the reference voltage. With few extra

components, the lower voltage can be easily achieved. The drawing below shows the method.

TPS5103

(top)

(bottom)

Zener

INV

In the schematic, the Rz1, Rz1, and the zener are the extra components. Rz1 is used to give zener enough current to build up the zener voltage. The zener voltage is added to INV through Rz2. Therefore, the voltage on INV is still equal to the IC internal voltage (1.185 V) even if the output voltage is regulated at lower setpoint. The equation for setting up the output voltage is shown below:

Where Rz2 is the adjusting resistor for low output voltage; Vz is the zener voltage; Vr is the internal reference voltage; Rtop is the top resistor of voltage sensing network; Rbtm is the bottom resistor of the sensing network; Vo is the required output voltage setpoint.

Example: Assuming the required output voltage setpoint is Vo = 0.8 V, Vz = 5 V; Rtop = 1 kΩ; Rbottom = 1 kΩ, then the Rz2 = 2.43 kΩ.

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switching frequency

With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the hysteresis window, the delay of the hysteresis comparator and the driver , the output inductance, the resistance in the output inductor, the output capacitance, the ESR and ESL in the output capacitor , the output current, and the turnon resistance of high side and low side MOSFET . It is a very complex equation if everything is included. To make it more useful to the designers, a simplified equation only considers the most influential factors. The tolerance of this equation is about 30%:

ƒs

out

) (ESR*(10 10

)

Td)ńC

out

)

Vin

(Vin

ESR (10 10

)

Td))0.0097 L

out

ESL Vin)

Where fs is the switching frequency (Hz);

Vout

is the output voltage (V);

Vin

is the input voltage (V);

Cout

is the

output capacitance;

ESR

is the equivalent series resistance in the output capacitor (Ω);

ESL

is the equivalent

series inductance in the output capacitor (H);

Lout

is the output inductance (H);

is output feedback RC filter

time constant (S). In the EVM module design, for the 1.8 V output, for example: Vin = 5 V, Vout = 1.8 V, Cout = 680 µF; ESR =

40 mΩ; ESL = 3 nH; Lout = 6 µH; Td = 0.5 µs. Then, the frequency

fs = 122 kHz.

output inductor ripple current

The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the output voltage capacitor selection. The equation is exhibited as below:

Iripple

Vin*Vout*Iout

(

Rdson)RL

)

Lout

Where

Iripple

is the peak-to-peak ripple current (A) through inductor;

Vin

is the input voltage (V);

Vout

the

output voltage (V);

Iout

is the output current;

Rdson

is the on-time resistance of MOSFET (Ω); D is the duty cycle; and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted by changing the output inductor value.

Example: Vin = 5 V; Vout = 1.8 V; Iout = 5 A; Rdson = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 10 µS; Lout = 6 µH Then, the ripple Iripple = 2 A.

output capacitor RMS current

Assuming the inductor ripple current totally goes through the output capacitor to the ground, the RMS current in the output capacitor can be calculated as:

Io(rms)

Where

I(orms)

is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple

current (A). Example: ∆I = 2 A, so Io(rms) = 0.58 A

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input capacitor RMS current

Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in the input capacitor can be calculated as:

Ii(rms)

D (1*D))

Iripple

Where

Ii(rms)

is the input RMS current in the input capacitor (A); Io is the output current (A); D is the duty cycle. From the equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage, so it is the worst case design for input capacitor ripple current.

Example: Io = 5 A; D = 0.36

Then, Ii(rms)= 3.36 A

softstart

The softstart timing can be adjusted by selecting the soft-start capacitor value. The equation is

soft

Where

soft

is the softstart capacitance (µF); T

soft

is the start-up time on softstart terminal (S).

Example: Tsoft = 5 mS, so Csoft = 0.01 µF.

current protection

The current protection in TPS5103 is set using an internal current source and an external resistor to set up the current limit. The sensed high side MOSFET drain-to-source voltage drop is compared to the set point, if the voltage drop exceeds the limit, the internal oscillator is activated, and it continuously resets the current limit until the over-current condition is removed. The equation below should be used for calculating the external resistor value for current protection:

Rcl

Rds(on) (Itrip)Iind(p-p)ń2)

0.000015

PWM or HYS mode

Rcl

Rds(on) (Itrip)Iind(p-p)ń2)

0.000005

SKIP mode

Where Rcl is the external current limit resistor (R10,R1 1); Rds(on) is the high side MOSFET on-time resistance. Itrip is the required current limit; Iind(p-p) is the peak-to-peak output inductor current.

Example: PWM mode or HYS mode Rds(on) = 10 mΩ, Itrip =5 A, Iind = 2 A, so Rcl = 4 kΩ Example: SKIP mode Rds(on) = 10 mΩ, Itrip = 2 A, Iind = 1 A, so Rcl = 5 kΩ

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APPLICATION INFORMATION

loop gain compensation

Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized control, two parts are discussed in this section: the power stage small signal modeling and the compensation circuit design.

For the buck converter, the small signal modeling circuit is shown below:

–

ap D

∧

Ic d

∧

From this equivalent circuit, several control transfer functions can be derived: input-to-output, output impedance, and control-to-output. Typically the control-to-output transfer function is used for the feedback control design.

Assuming Rc and RL are much smaller than R, the simplified small signal control-to-output transfer function is:

Vod

(

1)sCRc

)

1)sƪC

ǒRc)R

)

s2LC

∧

Where C is the output capacitance; Rc is the equivalent serial resistance (ESR) in the output capacitor; L is the output inductor; RL is the equivalent serial resistance (ESR) in the output inductor; R is the load resistance.

T o achieve the fast transient response and the better output voltage regulation, a compensation circuit is added to improve the feedback control. The whole system is shown below:

PWM

Power

Stage

Compensation

ref

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APPLICATION INFORMATION

The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit. The circuitry is displayed below.

_ +

R2R1

ref

To PWM

This circuit is composed of one integrator, two poles, and two zeros: Assuming R1 << R2 and C2 << C3, the equation is:

Comp

(

1)sC3R4) (1)sC2R2

)

sC3R2(1)sC2R4)(1)sC1R1

)

Therefore,

Pole1

2pC1R1

Pole2

2pC2R4

Zero2

2pC3R4

Zero1

2pC2R2

Integrator

2pƒC3R2

A simplified version used in the EVM design is exhibited below.

_ +

ref

Assuming C2 << C3, the equation is:

Comp

(

1)sC3R4

)

sC3R2(1)sC2R4

)

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there is one pole, one zero and one integrator:

Zero

2pC3R4

Pole

2pC2R4

Integrator

2pƒC3R2

The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived by that the control-to-output transfer function times the compensation:

Loop*gain+Vod X Comp

By using a bode plot, the amplitude and the phase of this equation can be drawn with software such as MathCad. In turn, the stability can be easily designed by adjusting the compensation perimeters. The sample bode plot is shown below to explain the phase margin, gain margin and the crossover frequency.

The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is added to the phase, so that the gain and phase share the same zero.

Where the gain curve touches the zero is the crossover frequency . The higher this frequency is, the faster the transient response is, since the transient recovery time is 1/(crossover frequency). The phase to the zero is the phase margin at the crossover frequency. The phase margin should be at least 60 degrees to cover all the condition changes such as temperature. The gain margin is the gap between gain curve and the zero when the phase curve touches the zero. This margin should be at least 20 dB to guarantee the stability over all conditions.

Phase

Margin

Phase

Gain

Crossover

Gain Margin

–2

–44

–100

166

f – Frequency – Hz

180

152 138 124

110

82 68

40 26 12

–16 –30

–58 –72 –86

10 100 10

20 Log (Loop-Gain)

180 + Phase

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synchronization

Some applications require switching clock synchronization. Two methods are used for synchronization:

Triangle wave synchronization

TPS5103

740 mV

Square wave synchronization

It can be seen that RT and CT are removed from the circuit. Therefore, two components are saved. This method is good for the synchronization between two controllers. If the controller needs to be synchronized with digital circuit such as DSP, usually the square-type clock signal is used. The configuration exhibited below is for this type of application:

TPS5103

An external resistor is added into the circuit, but R

is still removed. C

is kept to be a part of RC circuit generating triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the capacitor can be adjusted to achieve the correct peak–to–peak value and the offset value.

layout guidelines

Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult than most general PCB designs. The general design should proceed from the switching node to the output, then back to the driver section and, finally, place the low-level components. Below are several specific points to consider before layout of a TPS5103 design begins.

All sensitive analog components should be referenced to ANAGND. These include components connected to Vref5, Vref, INV, LH, and COMP .

Analog ground and drive ground should be isolated as much as possible. Ideally , analog ground will connect to the ground side of the bulk storage capacitors on VO, and drive ground will connect to the main ground plane close to the source of the low-side FET.

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APPLICATION INFORMATION

Connections from the drivers to the gate of the power FETs should be as short and wide as possible to reduce stray inductance. This becomes more critical if external gate resistors are not being used.

The bypass capacitor for VCC should be placed close to the TPS5103.

When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should be as short and as wide as possible.

When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to LL) should be placed close to the TPS5103.

When configuring the high-side driver as a ground-referenced driver, LL should be connected to DR VGND.

The bulk storage capacitors across VIN should be placed close to the power FETS. High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side FET and to the source of the low-side FET.

High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO.

LH and LL should be connected very close to the drain and source, respectively , of the high-side FET. LH and LL should be routed very close to each other to minimize differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to where VCC connects to Vin, to reduce high-frequency noise coupling on V

The output voltage sensing trace should be isolated by either ground trace or VCC trace.

test results

The tests are conducted at TA = 25°C, the point voltage is 5 V.

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APPLICATION INFORMATION

Figure 37

IO – Output Current – A

PWM Mode

SKIP Mode

0 0.5 1 1.5 2 2.5 3

Efficiency – %

EFFICIENCY

OUTPUT CURRENT

3.5 4

1.8 V Output Efficiency

Figure 38

0 0.1 0.2 0.3

0.4 0.5

IO – Output Current – A

PWM Mode

SKIP Mode

Efficiency – %

EFFICIENCY

OUTPUT CURRENT

1.8 V Output Efficiency

Figure 39

1.780

1.775

1.770 51015

– Output Voltage – V

1.785

OUTPUT VOLTAGE

INPUT VOLTAGE

1.790

20 250

VI – Input Voltage – V

1.8 V Line Regulation

Figure 40

1.780

1.770

1.760 0 0.5 1 1.5 2 2.5 3

1.780

1.790

OUTPUT VOLTAGE

OUTPUT CURRENT

1.790

3.5 4

– Output Voltage – VV

IO – Output Current – A

1.8 V Output Load Regulation

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

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Figure 41

0 0.5 1 1.5 2 2.5 3

3.5 4

IO – Output Current – A

Efficiency – %

EFFICIENCY

OUTPUT CURRENT

1.8 V Output Diode Type Efficiency

Figure 42

OUTPUT VOLTAGE

OUTPUT/VOLTAGE

Figure 43

TRANSIENT RESPONSE (OVERSHOOT)

Figure 44

TRANSIENT RESPONSE (UNDERSHOOT)

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

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APPLICATION INFORMATION

Table 1. Bill of Materials (see Note 3)

REF PN DESCRIPTION MFG SIZE

C1opt 10TPB220M Capacitor, POSCAP, 220 µF, 10 V Sanyo 7.3x4.3mm C1 RV-35V221MH10-R Capacitor, electrolytic, 220 µF, 35 V ELNA 10x10mm C2 GMK325F106ZH Capacitor, ceramic, 10 µF, 35 V Taiyo Yuden 1210 C3 4TPB470M Capacitor, POSCAP, 470 µF, 4 V Sanyo 7.3x4.3mm C4

†

std Open, capacitor, Ceramic, 2.2 µF, 16 V 805 C5 std Capacitor, ceramic, 1 µF, 16 V 805 C6 std Capacitor, ceramic, 0.01 µF, 16 V 805 C7 std Capacitor, ceramic, 220 pF, 16 V 805 C8 std Capacitor, ceramic, 100 pF, 16 V 805 C9 std Capacitor, ceramic, 1 µF, 16 V 805 C10 GMK316F225ZG Capacitor, ceramic, 2.2 µF, 35 V Taiyo Yuden 1206 C11

†

std Open 805 C12 GMK316F225ZG Capacitor, Ceramic, 2.2 µF, 35 V Taiyo Yuden 1206 C13 GMK325F106ZH Capacitor, Ceramic, 10 µF, 35 V Taiyo Y uden 1210 C14 Open C14†opt Open 10x10mm C15

†

std Open, capacitor, ceramic, 1000 pF, 16 V 805 D1 MBRS340T3 Diode, Schottky, 40 V, 3 A Motorola SMC D1opt MBRS130LT3 Diode, Schottky, 30 V, 1 A Motorola SMB D2 SD103-AWDICT-ND Diode, Schottky, 40 V, 200 mA, 400 mW Digikey 3.5x1.5mm L1 DO3316P-682 Inductor, 6.8 uH, 4.4 A Coilcraft 0.5x0.37 in J1–J14 CA26DA-D36W-0FC Edge connector, surface-mount, 0.040” board, 0.090” standoff NAS Interplex 0.040” JP1 S1132-2-ND Header, straight, 2–pin, 0.1 ctrs, 0.3” pins Sullins DigiKey #

S1132-2-ND

JP1 Shunt 929950-00-ND Shunt, jumper, 0.1” 3M DigiKey

#929950-00-ND

JP2 S1132-2-ND Header, straight, 2–pin, 0.1 ctrs, 0.3” pins Sullins DigiKey

#S1132-2-ND R1 std Resistor, 5.1 kΩ, 5 % 805 R2

†

std Open, resistor, 1 kΩ, 5% 805 R3 std Resistor, 910 Ω, 1% 805 R4 std Resistor, 1.74 kΩ, 1% 805 R5 std Resistor, 5.1 kΩ, 5% 805 R6A std Resistor, 82 kΩ, 5% 805 R6B

†

std Open, 0 Ω, 5% 805 R7 std Resistor, 1 kΩ, 5% 805 R9 std Resistor, 1 kΩ, 5% 805 R10 std Resistor, 1 kΩ, 5% 805 R11 std Resistor, 10 Ω, 5% 805 R12 std Resistor, 51 kΩ, 5% 805 R13

†

std Open 805 Q1 Si4410DY Transistor, MOSFET, n-ch, 30-V, 10-A, 13–mΩ Siliconix SO–8 Q2 Si4410DY Transistor, MOSFET, n-ch, 30-V, 10-A, 13-mΩ Siliconix SO–8 U1 TPS5103 IC, controller TI SSOP–20

†

Components for optional mode test only.

NOTE 3: This operation mode is PWM mode only.

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APPLICATION INFORMATION

Top Layer

Bottom Layer (Top V iew)

TPS5103

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APPLICATION INFORMATION

Top Assembly

Load

–

0 – 4 A

–

Power Supply

5–V, 5–A Supply

Test Setup

NOTE: All wire pairs should be twisted.

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

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Table 2. Test Specifications

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input voltage range 5 25 V Output voltage range Vi = 5 – 25 V Io = 0 – 4 A 1.7 1.8 1.9 V Output current range Vi = 5 – 10 V 0 4 A Output current limit Vi = 5 V 4.3 A Output ripple Vi =5 V, Io = 4 A 50 mVp–p Operating frequency Io = 4 A 150 250 KHz Efficiency Vi = 5 V, V o = 1.8 V, Io = 4 A 90 %

Table 3. EVM Operating Specifications

SKIP MODE HYS MODE

Remove JP1 shunt Remove R5, C6 and C7

Remove R6A Add R6B Add C15 If it needs the loop-compensation, add R2 and C4

This EVM is designed to cover as many applications as possible. For some more specific applications, the circuit can be simpler. The table below gives some recommendations.

Table 4. EVM Application Recommendations

5-V INPUT VOLTAGE <3-A OUTPUT CURRENT DIODE VERSION

Change C1 to low profile capacitor Sanyo 10TPB220M (220 µF, 10 V) Or 6TPB330M (330 µF, 6.3 V)

Change Q1 and Q2 to dual pack MOSFET, IRF7311 to reduce the cost.

Remove Q2 to reduce the cost.

Remove R10

Table 5. Vendor and Source Information

MATERIAL SOURCE PART NUMBER DISTRIBUTORS

In EVM design Si4410

MOSFETS (Q1–Q2)

Second source IRF7811 (International Rectifier)

Local distributor

In EVM design RV–35V221MH10–R (ELNA) Bell Microproducts 972–783–4191

INPUT CAPACITORS (C1)

Second source 35CV330AX/GX (Sanyo) 870–633–5030

UUR1V221MNR1GS (Nichicon) Future Electronics (Local Office)

MAIN DIODES (D1) In EVM design MBRS340T3 (Motorola) Local distributors

Second source U3FWJ44N (Toshiba) Local distributors

INDUCTORS (L1) In EVM design DO3316P–682 (Coilcraft) 972–458–2645

Second source

CTDO3316P–682 (Inductor Warehouse)

800–533–8295

CERAMIC CAPACITORS (C2, C14) (C12, C10)

IN EVM design

GMK325F106ZH GMK316F225ZG (Taiyo Yuden)

SMEC 512–331–1877

Taiyo Yuden representative e–mail: mike@millsales.com

TPS5103

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

High current applications are described in Table 6. The values are recommendations based on actual test circuits. Many variations are possible based on the requirements of the user. Performance of the circuit is dependent upon the layout rather than on the specific components, if the device parameters are not exceeded. The power stage, having the highest current levels and greatest dv/dt rates, should be given the most attention, as both the supply and load can be severely affected by the power levels and edge rates.

Table 6. High Current Applications

REFERENCE

DESIGNATIONS

FUNCTION 8-A OUTPUT 12-A OUTPUT 16-A OUTPUT

C1 Input bulk capacitor

2x ELNA RV-35V221MH10-R 220 µF, 35 V

3x ELNA RV-35V221MH10-R 220 µF, 35 V

4x ELNA RV-35V221MH10-R 220 µF, 35 V

C2 Input bypass capacitor

2x Taiyo Yuden GMK325F106ZH 10 µF, 35 V

3x Taiyo Yuden GMK325F106ZH 10 µF, 35 V

4x Taiyo Yuden GMK325F106ZH 10 µF, 35 V

L1 Output filter indicator

Coiltronics UP3B-2R2

2.2 µΗ, 9.2 A

Coiltronics UP4B-1R5

1.5 µΗ, 13.4 A

MicorMetals T68-8/90 Core w/7T, #16

1.0 µΗ, 25 A

C3 Output filter capacitor

2x Sanyo 4TPB470M 470 µF, 4 V

3x Sanyo 4TPB470M 470 µF, 4 V

4x Sanyo 4TPB470M 470 µF, 4 V

Q1 Power switch

2x Siliconix Si4410DY 30 V , 10 A, 13 mΩ

3x Siliconix Si4410DY 30 V , 10 A, 13 mΩ

4x Siliconix Si4410DY 30 V , 10 A, 13 mΩ

Q2 Power switch

2x Siliconix Si4410DY 30 V , 10 A, 13 mΩ

3x Siliconix Si4410DY 30 V , 10 A, 13 mΩ

4x Siliconix Si4410DY

30 V , 10 A, 13 mΩ R11 Gate drive resistor 7 Ω 5 Ω 4 Ω R12 Current limit resistor 10 kΩ 15 kΩ 20 kΩ

Switching frequency 200 kHz 150 kHz 100 kHz

TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER

SLVS240 – SEPTEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040065 /C 10/95

28 PINS SHOWN

Gage Plane

8,20 7,40

0,15 NOM

0,63

1,03

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60 5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65

0,15

0°–8°

0,10

3,30

2,70

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Texas Instruments TPS5103IDB, TPS5103IDBR, TPS5103EVM-136 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual