– Fixed Frequency PWM
– Hysteretic (User Selctable)
– Light Load:
– Skip Mode
D
4.5 V to 25 V Input Voltage Range
D
Adjustable Output Voltage Down to 1.2 V
D
95% Efficiency
D
Stand-By Control
D
Over Current Protection
D
UVLO for Internal 5 V Regulation
D
Low Standby Current . . . 0.5 mA Typical
D
TA =–40°C to 85°C
description
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
DB PACKAGE
(TOP VIEW)
1
20
SOFTSTART
INV
FB
C
R
GND
REF
COMP
PWMSKIP
STBY
2
3
4
T
5
T
6
7
8
9
10
LH
19
OUT_u
18
LL
17
OUT_d
16
OUTGND
15
TRIP
14
VCC_SENSE
13
VCC
12
VREF5
11
VREG5V_IN
The TPS5103 is a synchronous buck dc/dc controller, designed for notebook PC system power . The controller
has three user-selectable operation modes available; hysteretic mode, fixed frequency PWM control, or SKIP
control.
In high current applications, where fast transient response is advantageous for reducing bulk capacitance, the
hysteretic mode is selected by connecting the Rt pin to Vref5. Selecting the PWM/SKIP modes for less
demanding transient applications is ideal for conserving notebook battery life under light load conditions. The
device includes high-side and low-side MOSFET drivers capable of driving low Rds (on) N–channel MOSFET s.
The user-selectable overcurrent protection (OCP) threshold is set by an external TRIP pin resister in order to
protect the system. The TPS5103 is configured so that a current sense resistor is not required, improving the
operating efficiency.
L1
C4
C5
OUTPUT
+
R2
C1
C2
R1
1
2
3
4
5
6
7
8
9
10
TPS5103
SOFTSTART
INV
FB
CT
RT
GND
REF
COMP
PWM/SKIP
STBY
U1
OUTU
OUTD
OUTGND
VCCSENSE
VREF5
VREG5V_IN
LH
LL
TRIP
VCC
5 V
D1
20
19
18
17
16
15
14
13
12
11
C3
R3
R4
Q1
Q2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 1. Typical Design
Copyright 1999, Texas Instruments Incorporated
1
TPS5103
T
°C
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
functional block diagram
SOFT START
FB
INV
PWMSKIP
C
R
Comp
T
T
1.185 V
Soft Start
1.185 V
_
+
_
+
Error Amp
PWM Comp.
_
+
One Shot ON
_
+
OSC
_
+
Disable
_
+
UVLO
LH
OUT_u
LL
OUT_d
OUTGND
TRIP
VCC_SENSE
VREF5
GND
V
CC
STBY
REF
1.185 V
°
–40 °C to 85
VREF
AVAILABLE OPTIONS
A
°
SSOP(DB)EVM
TPS5103IDBTPS5103EVM–136
TPS5103IDBR
PACKAGE
_
+
VREG5V_IN
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O
DESCRIPTION
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
Terminal Functions
TERMINAL
NAMENO.
COMP8IComparator input for voltage monitor
C
T
FB3OFeedback output of error amp
GND6Control GND
INV2IInverting input of both error amp and hysteretic comparator
LH20I/OBootstrap. Connect 1 µF low-ESR capacitor from LH to LL.
LL18I/O
OUT_d17I/OGate-drive output for low-side power switching FET s
OUTGND16Ground for FET drivers
OUT_u19OGate-drive output for high-side power switching FET s
PWMSKIP9I
REF7O1.185-V reference voltage output
R
T
SOFTSTAR T1IExternal capacitor from SOFTST ART to GND for soft start control
STBY10IStandby control
TRIP15IExternal resistor connection for output current control
V
CC
VCC_SENSE14ISupply voltage sense for current protection
VREF512O5-V-internal regulator output
VREG5V_IN11IExternal 5-V input (input voltage range = 4.5 V to 25 V)
4I/O
5I/OExternal resistor connection for adjusting the triangle oscillator.
13ISupply voltage input
External capacitor from CT to GND for adjusting the triangle oscillator and decreasing the current limiting
voltage
Bootstrap low. High side gate driving return and output current protection. Connect to the junction of the high
side and low side FETs for floating drive configuration.
The reference voltage is used for the output voltage setting and the voltage protection(COMP). The tolerance
is 1.5% typically.
VREF5
An internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage
range is from 4.5 V to 25 V, this voltage offers a fixed voltage for the bootstrap voltage so that the design for
the bootstrap is much easier. The tolerance is 6%.
hysteretic comparator
The hysteretic comparator is used to regulate the output voltage of the synchronous-buck converter. The
hysteresis is set internally and is typically 9.7 mV. The total delay time from the comparator input to the driver
output is typically 400 ns for going both high and low.
error amplifier
The error amplifier is used to sense the output voltage of the synchronous buck converter. The negative input
of the error amplifier is connected to the Vref voltage(1.185 V) with a resistive divider network. The output of
the error amplifier is brought out to the FB terminal to be used for loop gain compensation.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V
from VREF5. The current rating of driver is typically 1.2 A at sink current, –1.5 A at source current.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1.2 A at sink current, –1.7 A at source current. When configured as a floating driver, the bias voltage to the driver
is developed from the VREF5, limiting the maximum drive voltage between OUT_u and LL to 5 V . The maximum
voltage that can be applied between LH and OUTGND is 30 V.
driver deadtime control
The deadtime control prevents shoot-through current from flowing through the main power FETs. During
switching transitions the
deadtime from the low-side-driver-off to the high-side-driver-on is 90 ns, and 110 ns from high-side-driver-off
to low-side-driver-on.
COMP
COMP is designed for use with a regulation output monitor. COMP also functions as an internal comparator
used for any voltage protection such as the input under voltage protection. If the input voltage is lower than the
setpoint, the comparator turns off and prevents external parts from damage. The investing terminal of the
comparator is internally connected to REF(1.185 V).
current protection
Current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during
on-time through VCC_SENSE and LL terminals. An external resistor between Vin and TRIP terminal with the
internal current source connected to the current comparator negative input adjusts the current limit. The typical
internal current source value is 15 µA in PWM mode, 5 µA in SKIP mode. When the voltage on the positive
terminal is lower than the negative terminal, the current comparator turns on the trigger, and then activates the
oscillator. This oscillator repeatedly reset the trigger until the over current condition is removed. The capacitor
on the C
terminal can be open or added to adjust the reset frequency.
T
deadtime control actively controls the turnon time of the MOSFET drivers. The typical
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
detailed description (continued)
softstart
SOFTST ART sets the sequencing of the output for any possibility. The capacitor value for a start-up time can
be calculated by the following equation: C = 2xT (uF) where C is the external capacitor value, T is the required
start-up time in (ms).
standby
This controller can be switched into standby mode by grounding the STBY terminal. When it is in standby mode,
the quiescent current is less than 1.0 uA.
UVLO
The under-voltage-lock-out (ULVO) threshold is approximately 3.8 V. The typical hysteresis is 55 mV.
5-V Switch
5-V Switch if the internal 5-V switch senses a 5-V input from REG5V terminal, the internal 5-V linear regulator
will be disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and
the high-side bootstrap, thus increasing the efficiency.
PWM/SKIP switch
TPS5103
The PWM/SKIP switch selects the output operating mode. This controller has three operational modes, PWM,
SKIP, and Hysteretic. The PWM and SKIP mode control should be used for slower transient applications.
oscillator
The oscillator gives a triangle wave by connecting an external resistor to the R
terminal and an external
T
capacitor to the CT terminal. The voltage amplitude is 0.43 V ~ 1.17 V. This wave is connected to the noninverting input of the PWM comparator.
Comparison Table Between PWM Mode and Hysteretic Mode
MODEPWMHYSTERETIC
FrequencyFixedNot Fixed
Transient ResponseNormalVery fast
Feed back compensationNeedNeedless
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPS5103
VIInput voltage
V
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. See Dissipation Rating Table for free-air temperature range above 25°C.
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V
(unless otherwise noted)
reference voltage
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ref
ReginLine regulation
ReglLoad regulation
†
Not a JEDEC symbol.
†
†
TA = 25°C,I
= 50 µA
‡
I
vref
VCC = 4.5 V to 25 V,I = 50 µA0.212mV
I = 1 µA to 1 mA0.510mV
oscillator
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fFrequencyPWM mode500kHz
R
T
fdv
fdt
HL
LL
†
Not a JEDEC symbol.
‡
The output voltages of oscillator (f = 200 kHz) are ensured by design.
Timing resistor47kΩ
VCC = 4.5 V to 25 V0.1%
TA = –40°C to 85°C2%
p
p
DC includes internal comparator error11.11.2
f = 200 kHz, includes internal comparator error1.17
DC includes internal comparator error0.40.50.6
f = 200 kHz, includes internal comparator error0.43
= 50 µA1.167 1.185 1.203
vref
1.1551.215
error amp
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VInput offset voltageTA = 25°C210mV
AvOpen-loop voltage gain
GBUnity-gain bandwidth
I
The drivers in the TPS5103 controller are fast and can produce high transients on VCC or the junction of Q1 and
Q2(shown below). Care must be taken to insure that these transients do not exceed the absolute maximum
rating for the device or associated external component. A low-ESR capacitor connected directly from Q1 drain
to Q2 source can greatly reduce transient pulses on VCC. Also, Q1 turn-on-speed can be reduced by adding
a resistor (5 – 15 Ω) in series with OUT_u. Poor layout of the switching node (V1 in figure) can result in the
requirement for additional snubber circuitry require from V1 to ground.
The design shown in this data sheet is a reference design for a general power supply application. An evaluation
module (EVM), TPS5103EVM-136 (SLVP136), is available for customer testing and evaluation. The intent is
to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. For subsequent
customer board revisions, the EVM design can be copied onto the users PCB to shorten design cycle time,
component count, and board cost.
To help the customers to design the power supply using TPS5103, some key design procedures are shown
below.
R2
R6B
R6A
R7
JP1JP2
C8
C9
R10
C4
C15
C5
R4
R5
C7
C6
R9
R3
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP18
TP17
TP16
TP15
TP14
TP13
TP12
TP11
D2
R13
C12
C10
C13
R11
R12
C11
TP26
J13
J14
Q2
Q1
C14
C1
+
C2
L1
+
D1
C3
J1
J2
J3
J4
J5
R1
J6
J7
J8
J9
J10
J11
J12
Vi
Vi
Input GND
Input GND
Input GND
SENSE
Vo
Vo
Vo
VoGND
VoGND
VoGND
Figure 36. EVM Schematic
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
output voltage setpoint calculation
The output voltage is set by the reference voltage and the voltage divider. In TPS5102, the reference voltage
is 1.185 V , and the divider is composed of two resistors in the EVM design that are R4 and R5, or R14 and R15.
The equation for the setpoint is:
R1Vr
R2
+
Vo*Vr
Where R1 is the top resistor (kΩ) like R4 or R15; R2 is the bottom resistor (kΩ) such as R5 or R14; Vo is the
required output voltage (V); Vr is the reference voltage (1.185 V in TPS5103).
Example: R1 = 1 kΩ; Vr = 1.185 V; Vo = 1.8 V, then R2 = 1.9 kΩ.
For your convenience, some of the most popular output voltage setpoints are calculated in the table below:
If higher precision resistor is used, the output voltage setpoint can be more accurate.
TPS5103
In some applications, the output voltage is required to be lower than the reference voltage. With few extra
components, the lower voltage can be easily achieved. The drawing below shows the method.
R
Zener
z1
V
CC
V
O
R
(top)
R
(bottom)
INV
TPS5103
R
z2
In the schematic, the Rz1, Rz1, and the zener are the extra components. Rz1 is used to give zener enough
current to build up the zener voltage. The zener voltage is added to INV through Rz2. Therefore, the voltage
on INV is still equal to the IC internal voltage (1.185 V) even if the output voltage is regulated at lower setpoint.
The equation for setting up the output voltage is shown below:
Rz2
+
ǒ
Vr–Vo
Rtop
(
Vz–Vr
Ǔ
)
)
Vr
Rbtm
Where Rz2 is the adjusting resistor for low output voltage; Vz is the zener voltage; Vr is the internal reference
voltage; Rtop is the top resistor of voltage sensing network; Rbtm is the bottom resistor of the sensing network;
Vo is the required output voltage setpoint.
Example: Assuming the required output voltage setpoint is Vo = 0.8 V, Vz = 5 V; Rtop = 1 kΩ; Rbottom = 1 kΩ,
then the Rz2 = 2.43 kΩ.
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver , the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor , the output current, and
the turnon resistance of high side and low side MOSFET . It is a very complex equation if everything is included.
To make it more useful to the designers, a simplified equation only considers the most influential factors. The
tolerance of this equation is about 30%:
*
7
)
Td)ńC
*
out
)
out
ESLVin)
ƒs
+
Vin
V
out
(Vin
(V
*
V
in
out
ESR(1010
)(ESR*(1010
*
7
)
Td))0.0097L
Where fs is the switching frequency (Hz);
output capacitance;
series inductance in the output capacitor (H);
time constant (S).
In the EVM module design, for the 1.8 V output, for example: Vin = 5 V, Vout = 1.8 V, Cout = 680 µF; ESR =
40 mΩ; ESL = 3 nH; Lout = 6 µH; Td = 0.5 µs.
Then, the frequency
ESR
is the equivalent series resistance in the output capacitor (Ω);
fs = 122 kHz.
Vout
is the output voltage (V);
Lout
is the output inductance (H);
Vin
is the input voltage (V);
ESL
Td
is output feedback RC filter
is the equivalent
output inductor ripple current
The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the
output voltage capacitor selection. The equation is exhibited as below:
Iripple
Where
the
cycle; and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted
by changing the output inductor value.
is the peak-to-peak ripple current (A) through inductor;
Iout
is the output current;
Lout
(
Rdson)RL
)
D
Rdson
Ts
Vin
is the input voltage (V);
is the on-time resistance of MOSFET (Ω); D is the duty
Cout
is the
Vout
is
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to the ground, the RMS current
in the output capacitor can be calculated as:
D
Io(rms)
Where
current (A).
Example: ∆I = 2 A, so Io(rms) = 0.58 A
22
I(orms)
I
+
Ǹ
12
is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
input capacitor RMS current
Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in
the input capacitor can be calculated as:
TPS5103
2
Ii(rms)
Where
From the equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage,
so it is the worst case design for input capacitor ripple current.
Ii(rms)
Ǹ
+
I
D(1*D))
o
is the input RMS current in the input capacitor (A); Io is the output current (A); D is the duty cycle.
1
12
D
Iripple
2
Example: Io = 5 A; D = 0.36
Then, Ii(rms)= 3.36 A
softstart
The softstart timing can be adjusted by selecting the soft-start capacitor value. The equation is
C
+2
soft
Where
Example: Tsoft = 5 mS, so Csoft = 0.01 µF.
C
soft
T
soft
is the softstart capacitance (µF); T
is the start-up time on softstart terminal (S).
soft
current protection
The current protection in TPS5103 is set using an internal current source and an external resistor to set up the
current limit. The sensed high side MOSFET drain-to-source voltage drop is compared to the set point, if the
voltage drop exceeds the limit, the internal oscillator is activated, and it continuously resets the current limit until
the over-current condition is removed. The equation below should be used for calculating the external resistor
value for current protection:
Rds(on)(Itrip)Iind(p-p)ń2)
Rcl
PWM or HYS mode
SKIP mode
Where Rcl is the external current limit resistor (R10,R1 1); Rds(on) is the high side MOSFET on-time resistance.
Itrip is the required current limit; Iind(p-p) is the peak-to-peak output inductor current.
Example: PWM mode or HYS mode
Rds(on) = 10 mΩ, Itrip =5 A, Iind = 2 A, so Rcl = 4 kΩ
Example: SKIP mode
Rds(on) = 10 mΩ, Itrip = 2 A, Iind = 1 A, so Rcl = 5 kΩ
Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized
control, two parts are discussed in this section: the power stage small signal modeling and the compensation
circuit design.
For the buck converter, the small signal modeling circuit is shown below:
Z
∧
V
ap
d
ac
i
a
+
V
I
D
Ic d
+
–
i
1
∧
D
p
c
L
R
L
L
C
Z
RC
R
C
V
O
R
From this equivalent circuit, several control transfer functions can be derived: input-to-output, output
impedance, and control-to-output. Typically the control-to-output transfer function is used for the feedback
control design.
Assuming Rc and RL are much smaller than R, the simplified small signal control-to-output transfer function is:
∧
Vod
∧
d
+
1)sƪC
(
1)sCRc
ǒRc)R
)
L
Ǔ
ƫ
)
)
L
s2LC
R
Where C is the output capacitance; Rc is the equivalent serial resistance (ESR) in the output capacitor; L is the
output inductor; RL is the equivalent serial resistance (ESR) in the output inductor; R is the load resistance.
T o achieve the fast transient response and the better output voltage regulation, a compensation circuit is added
to improve the feedback control. The whole system is shown below:
V
ref
PWM
Compensation
Power
Stage
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit.
The circuitry is displayed below.
TPS5103
C3
R4
C2
_
+
C1
R3
R2R1
V
ref
This circuit is composed of one integrator, two poles, and two zeros:
Assuming R1 << R2 and C2 << C3, the equation is:
Comp
(
1)sC3R4)(1)sC2R2
+
sC3R2(1)sC2R4)(1)sC1R1
)
)
Therefore,
Pole1
+
Zero2
+
Integrator
1
2pC1R1
1
2pC3R4
+
2pƒC3R2
Pole2
Zero1
1
+
2pC2R4
+
2pC2R2
1
1
To PWM
A simplified version used in the EVM design is exhibited below.
The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived
by that the control-to-output transfer function times the compensation:
Loop*gain+Vod XComp
By using a bode plot, the amplitude and the phase of this equation can be drawn with software such as MathCad.
In turn, the stability can be easily designed by adjusting the compensation perimeters. The sample bode plot
is shown below to explain the phase margin, gain margin and the crossover frequency.
The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is
added to the phase, so that the gain and phase share the same zero.
Where the gain curve touches the zero is the crossover frequency . The higher this frequency is, the faster the
transient response is, since the transient recovery time is 1/(crossover frequency). The phase to the zero is the
phase margin at the crossover frequency. The phase margin should be at least 60 degrees to cover all the
condition changes such as temperature. The gain margin is the gap between gain curve and the zero when the
phase curve touches the zero. This margin should be at least 20 dB to guarantee the stability over all conditions.
180
166
20 Log (Loop-Gain)
180 + Phase
152
138
124
110
96
82
68
54
40
26
12
–2
–16
–30
–44
–58
–72
–86
–100
Gain
1010010
Phase
Margin
Phase
Crossover
f – Frequency – Hz
Gain
Margin
3
10
4
10
5
10
6
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
synchronization
Some applications require switching clock synchronization. Two methods are used for synchronization:
D
Triangle wave synchronization
TPS5103
D
Square wave synchronization
740 mV
740 mV
C
R
t
t
TPS5103
It can be seen that RT and CT are removed from the circuit. Therefore, two components are saved. This method
is good for the synchronization between two controllers. If the controller needs to be synchronized with digital
circuit such as DSP, usually the square-type clock signal is used. The configuration exhibited below is for this
type of application:
C
t
TPS5103
R
t
An external resistor is added into the circuit, but R
is still removed. C
T
is kept to be a part of RC circuit generating
T
triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the
capacitor can be adjusted to achieve the correct peak–to–peak value and the offset value.
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPS5103 design begins.
D
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMP .
D
Analog ground and drive ground should be isolated as much as possible. Ideally , analog ground will connect
to the ground side of the bulk storage capacitors on VO, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
D
The bypass capacitor for VCC should be placed close to the TPS5103.
D
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
D
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5103.
D
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DR VGND.
D
The bulk storage capacitors across VIN should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
D
High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO.
D
LH and LL should be connected very close to the drain and source, respectively , of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces. Ceramic decoupling capacitors should be placed close to where VCC connects to Vin, to reduce
high-frequency noise coupling on V
D
The output voltage sensing trace should be isolated by either ground trace or VCC trace.
CC
.
test results
The tests are conducted at TA = 25°C, the point voltage is 5 V.
Remove R6A
Add R6B
Add C15
If it needs the loop-compensation, add R2 and C4
This EVM is designed to cover as many applications as possible. For some more specific applications, the circuit
can be simpler. The table below gives some recommendations.
Table 4. EVM Application Recommendations
5-V INPUT VOLTAGE<3-A OUTPUT CURRENTDIODE VERSION
Change C1 to low profile capacitor
Sanyo 10TPB220M (220 µF, 10 V)
Or 6TPB330M (330 µF, 6.3 V)
Remove R10
Change Q1 and Q2 to dual pack MOSFET,
IRF7311 to reduce the cost.
Remove Q2 to reduce the cost.
Table 5. Vendor and Source Information
MATERIALSOURCEPART NUMBERDISTRIBUTORS
In EVM designSi4410
Second sourceIRF7811 (International Rectifier)
In EVM designRV–35V221MH10–R (ELNA)Bell Microproducts 972–783–4191
Second source35CV330AX/GX (Sanyo)870–633–5030
High current applications are described in Table 6. The values are recommendations based on actual test
circuits. Many variations are possible based on the requirements of the user. Performance of the circuit is
dependent upon the layout rather than on the specific components, if the device parameters are not exceeded.
The power stage, having the highest current levels and greatest dv/dt rates, should be given the most attention,
as both the supply and load can be severely affected by the power levels and edge rates.
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
8
3,30
2,70
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /C 10/95
36
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