TEXAS INSTRUMENTS TPS40075 Technical data

1

2

3

4

19

18

17

16

SYNC

PGD

LVBP

RT

SA−

SAO

GND

SS

TPS40075

15

14

13

12

KFF

ILIM

VDD

HDRV

5

6

7

8

FB

COMP

PGND

LDRV

9 DBP

20

SA+

10

SW11BOOST

SYNC IN

PowerGood OUT

UDG−04075

V

IN

V

OUT

+

V

OUT

−

V

OUT

−

(at Load)

V

OUT

+

(at Load)

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SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

TPS40075

MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER

WITH VOLTAGE FEED-FORWARD

1

FEATURES

2

• Operation Over 4.5-V to 28-V Input Range

• Fixed-Frequency Voltage-Mode Controller

• Integrated Unity Gain Amplifier for Remote

Output Sensing

• Predictive Gate Drive™ Generation II for

Improved Efficiency

• <1% Internal 700-mV Reference

• Input Voltage Feed Forward Control

• Prebiased Output Compatible

• Internal Gate Drive Outputs for High-Side and

Synchronous N-Channel MOSFETs

• Switching Frequency Programmable to 1 MHz

• 20-Pin QFN Package

• Thermal Shutdown Protection

• Software Design Tool and EVM Available

APPLICATIONS

• Power Modules

• Networking/Telecom

• Industrial

• Servers

The TPS40075 drives external N-channel MOSFETs
using second generation Predictive Gate Drive to
minimize conduction in the body diode of the low side
FET and maximize efficiency. Pre-biased outputs are
supported by not allowing the low side FET to turn on
until the voltage commanded by the closed loop soft
start is greater than the pre-bias voltage. Voltage
feed forward provides good response to input
transients and provides a constant PWM gain over a
wide input voltage operating range to ease
compensation requirements. Programmable short
circuit protection provides fault current limiting and
hiccup recovery to minimize power dissipation with a
shorted output. The 20-pin QFN package gives good
thermal performance and a compact footprint.

SIMPLIFIED APPLICATION DIAGRAM

CONTENTS

Device Ratings 2
Electrical Characteristics 4
Terminal Information 12
Application Information 15
Design Example 26
Additional References 40

DESCRIPTION

The TPS40075 is a mid voltage, wide input (4.5-V to
28-V), synchronous, step-down controller, offering
design flexibility for a variety of user programmable
functions, including; soft start, UVLO, operating
frequency, voltage feed-forward and high-side FET
sensed short circuit protection.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 Predictive Gate Drive is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2006 – 2007, Texas Instruments Incorporated

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TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

ORDERING INFORMATION

T

A

40 ° C to 85 ° C Plastic QFN (RHL)

(1) The TPS40075 is available taped and reeled only. Add an T suffix (i.e. TPS40075RHLT) to the orderable part number for quantities of

250 units per small reel. .

(2) Add an R suffix (i.e. TPS40075RHLR) to the orderable part number for quantities of 3,000 units per large reel.

DEVICE RATINGS

PACKAGE PART NUMBER

TPS40075RHLT
TPS40075RHLR

(1)
(2)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

VDD, ILIM 30
FB, KFF, PGD, SYNC – 0.3 to 6

V

V

I

I

I

T
T

Input voltage range

DD

Output voltage range V

OUT

Output current source LDRV, HDRV 1.5

OUT

Output current sink

OUT

Output current source

OUT

Operating junction temperature range – 40 to 125

J

Storage temperature – 55 to 150

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

SW – 0.3 to 40 V
SA+, SA- – 0.3 to 11
SW, transient < 50 ns – 2.5
SW, transient – 125 V × ns
COMP, RT, SS – 0.3 to 6
BOOST, HDRV 50
DBP, SAO, LDRV 10.5
LVBP 6

LDRV, HDRV 2.0
KFF 10
RT 1 mA
LVBP 1.5

(1)

TPS40075 UNIT

A

° C

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TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

RECOMMENDED OPERATING CONDITIIONS

MIN NOM MAX UNIT

V
T

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Human body model 1500 V
CDM 1500

Input voltage 4.5 28 V

DD

Operating free-air temperature -40 85 ° C

A

PARAMETER MIN TYP MAX UNIT

PACKAGE DISSIPATION RATINGS

THERMAL IMPEDANCE

AIRFLOW (LFM) JUNCTION-TO-AMBIENT TA= 25 ° C POWER RATING (W) TA= 85 ° C POWER RATING (W)

Natural Convection 42 2.38 0.95

200 35 2.85 1.14
400 31 3.22 1.29

(1) For more information on the RHL package and the test method, refer to TI technical brief, literature number SZZA017. The ratings in this

table are for the JEDEC High-K board.

(1)

( ° C/W)

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TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS

TA= – 40 ° C to 85 ° C, V
(unless otherwise noted)

INPUT SUPPLY

V

DD

OPERATING CURRENT

I

DD

LVBP

V

LVBP

OSCILLATOR/RAMP GENERATOR

f

OSC

V

RT

t

ON(min)

V

IH

V

IL

I

SYNC

V

KFF

I

KFF

SOFT START

I

SS

t

DSCH

t

SS

V

SSSD

V

SSEN

V

SSSDHYS

DBP

V

DBP

ERROR AMPLIFIER

V

FB

V

SS(offset)

GBWP Gain bandwidth
A

VOL

I

SRC

I

SINK

I

BIAS

SHORT CIRCUIT CURRENT PROTECTION

I

ILIM

V

ILIM(ofst)

t

HSC

t

BLANK

Input voltage range, VIN 4.5 28 V

Quiescent current Output drivers not switching 2.5 3.5 mA

Output voltage TA= TJ= 25 ° C 3.9 4.2 4.5 V

Accuracy 450 500 550 kHz
RT voltage 2.23 2.40 2.58 V
Minimum output pulse time
High-level input voltage, SYNC 2 5
Low-level input voltage, SYNC 0.8
Input current, SYNC 5 10 µA

Maximum duty cycle

Feed-forward voltage 0.35 0.40 0.45 V
Feed-forward current operating range

Charge current 9.5 12 14.5 µA
Discharge time C

Soft-start time 210 290 500
Shutdown threshold, V

Enable threshold, V
Shutdown threshold hysteresis 35 130

Output voltage V

Feedback regulation voltage total variation 0 ° C ≤ TA= TJ≤ 85 ° C 0.690 0.700 0.707

Soft-start offset from VSS

Open loop gain 50 dB
Output source current 2.5 4.5
Output sink current 2.5 6
Input bias current V

Current sink into ILIM pin 115 135 150 µA
Current limit offset voltage V
Minimum HDRV pulse width During short circuit 135 225 ns
Propagation delay to output
Blanking time

= 12 Vdc, RT= 90.9 k Ω , I

IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SS

rising 310 410 mV

SS

(1)

(1)

= 300 µA, fSW= 500 kHz, all parameters at zero power dissipation

KFF

(1)

(1)

C

= 0 nF 150 ns

HDRV

V

= 0 V, 100 kHz ≤ fSW≤ 500 kHz 84% 95%

FB

V

= 0 V, fSW= 1 MHz 76% 93%

FB

20 1100 µA

= 3.9 nF 25 75

SS

C
V

= 3.9 nF, V

SS

rising from 0.7 V to 1.6

SS

falling 225 275 325

V

> 10 V 7 8 9

DD

V

VDD

= 4.5 V, I

= 25 mA 4.0 4.3

OUT

TA= TJ= 25 ° C 0.698 0.700 0.704

-40 ° C ≤ TA= TJ≤ 85 ° C 0.690 0.700 0.715

(1)

Offset from V

to error amplifier 1

SS

5 10 MHz

= 0.7 V – 250 0 nA

FB

= 11.5 V, (V

ILIM

(1)

- V

) V

SW

ILIM

= 12 V – 50 – 30 – 10 mV

VDD

50 ns
50 ns

V

µs

V

mA

(1) Ensured by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)

TA= – 40 ° C to 85 ° C, V
(unless otherwise noted)

t

OFF

V

SW

t

PC

V

ILIM(pre)

OUTPUT DRIVERS

t

HFALL

t

HRISE

t

HFALL

t

HRISE

t

LFALL

t

LRISE

t

LFALL

t

LRISE

V

OH

V

OL

V

OH

V

OL

BOOST REGULATOR

V

BOOST

UVLO

V

UVLO

POWER GOOD

V

PGD

V

FBH

V

FBL

SENSE AMPLIFIER

V

IO

A

DIFF

V

ICM

R

G

I

OH

I

OL

GBWP Gain bandwidth

THERMAL SHUTDOWN

Off time during a fault (SS cycle times) 7 cycles
Switching level to end precondition
Precondition time
Current limit precondition voltage threshold

High-side driver fall time
High-side driver rise time
High-side driver fall time
High-side driver rise time
Low-side driver fall time
Low-side driver rise time
Low-side driver fall time
Low-side driver rise time

High-level output voltage, HDRV V

Low-level output voltage, HDRV V

High-level output voltage, LDRV V

Low-level output voltage, LDRV V

Output voltage V

Programmable UVLO threshold voltage R
Programmable UVLO hysteresis R
Fixed UVLO threshold voltage Turn-on, V
Fixed UVLO hysteresis 275 365 mV

Powergood voltage I
High-level output voltage, FB 770 mV
Low-level output voltage, FB 630

Input offset voltage -9 9 mV
Differential gain V

Input common mode range
Internal resistance for setting gain 14 20 26 k Ω
Output source current 2 10 15
Output sink current 15 25 35

= 12 Vdc, RT= 90.9 k Ω , I

IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2)

(4)

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

= 300 µA, fSW= 500 kHz, all parameters at zero power dissipation

KFF

(1)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(3)

(V

- V

VDD

) 2 V

SW

100 ns

(2)

C

= 2200 pF, (HDRV - SW) ns

HDRV

C

= 2200 pF, (HDRV - SW)

HDRV

V

= 4.5 V

VDD

C

= 2200 pF ns

LDRV

C

= 2200 pF, VDD= 4.5 V ns

LDRV

I

= -0.01 A, (V

HDRV

I

= -0.1 A, (V

HDRV

(V

- V

HDRV

(V

HDRV

(V

DBP

(V

DBP

I

LDRV

I

LDRV

VDD

KFF
KFF

PGD

V

SA+

SA+ and SA-

SA+

), I

SW

- V

), I

SW

- V

), I

LDRV

- V

), I

LDRV

= 0.01 A 0.03 0.05
= 0.1 A 0.3 0.5

= 12 V 15.2 17.0 V

= 90.9 k Ω , turn-on, V
= 90.9 k Ω 1.10 1.55 2.00 V

rising 4.15 4.30 4.45

VDD

= 1 mA 370 550

= V

= 1.25 V, Offset referenced to

SA-

- V

= 4.5 V 0.995 1.000 1.005

SA-

- V

BOOST

BOOST

= 0.01A 0.06 0.10

HDRV

= 0.1 A 0.65 1.00

HDRV

= -0.01A 0.65 1.00

LDRV

= -0.1 A 0.875 1.300

LDRV

) 0.7 1.0

HDRV

- V

) 0.95 1.35

HDRV

rising 6.2 7.2 8.2

VDD

6.8 V

36
48
72
96
24
48
48
96

ns

0 6 V

mA

2 MHz

(2) Ensured by design. Not production tested.
(3) 3 V at internal amplifier terminals, 6 V at SA+ and SA- pins.
(4) Ensured by design. Not production tested.

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TJ − Junction Temperature − °C

V

LVPP

− LVBP Voltage − V

−50 −25 50 100 1250

4.15

4.10

4.30

4.20

4.25

4.05

4.00
25 75

VDD = 28 V

VDD = 12 V

−50 −25 50 100 1250

8.00

7.90

8.15

8.05

8.10

7.85

7.80
25 75

7.95

V

DBP

− DBP Voltage − V

VDD = 28 V

VDD = 12 V

TJ − Junction Temperature − °C

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

TA= – 40 ° C to 85 ° C, V
(unless otherwise noted)

Shutdown temperature threshold
Hysteresis

= 12 Vdc, RT= 90.9 k Ω , I

IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(4)

LVBP VOLTAGE DBP VOLTAGE

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

vs vs

= 300 µA, fSW= 500 kHz, all parameters at zero power dissipation

KFF

(4)

165

15

° C

TYPICAL CHARACTERISTICS

Figure 1. Figure 2.

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−50 −25 50 100 1250

4.46

4.43

4.50

4.48

4.49

4.41

4.40
25 75

4.44

4.42

4.47

4.45

V

DBP

− DBP Voltage − V

VDD = 4.5 V
I

LOAD

= 25 mA

TJ − Junction Temperature − °C

V

DROP

− Bootstrap Diode Voltage Drop − V

TJ − Junction Temperature − °C

−50 −25 50 100 1250

1.6

1.3

2.0

1.7

1.9

1.1

1.0
25 75

1.4

1.8

1.5

1.2

−50 −25 50 100 1250

115

150

140

100

25 75

135

125

110

105

120

145

130

I

ILIM

− Current Limit Sink Current − µA

TJ − Junction Temperature − °C

VDD
28 V
12 V

4.5 V

V

ILIM(offst)

– Current Limit Offset Voltage Drop – mV

TJ – Junction Temperature – °C

−50 −25 50 100 1250

−40

0

−10

−60
25 75

−20

−30

−50

Average

+3 S

−3 S

TYPICAL CHARACTERISTICS (continued)

DBP VOLTAGE BOOTSTRAP DIODE VOLTAGE

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

Figure 3. Figure 4.

CURRENT LIMIT OFFSET VOLTAGE CURRENT LIMIT SINK CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 5. Figure 6.

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−50 −25 50 100 1250

699

704

697

25 75

702

698

700

703

701

V

FB

− Feedback Voltage − V

TJ − Junction Temperature − °C

VDD
28 V

4.5 V
12 V

−50 −25 50 100 1250

0

30

−15
25 75

20

−10

5

25

10

−5

15

High Level Output Current

Low Level Output Current

I

SENSE

− Sense Amplifier Output Current − mA

TJ − Junction Temperature − °C

f

SW

− Switching Frequency − kHz

V

VDD

− Input Voltage − V

4 8 16 24 2812 20

500

490

497

491

493

498

496

494

499

495

492

RRT = 90.1kΩ

A

DIFF

− Sense Amplifier Gain − V/V

TJ − Junction Temperature − °C

−50 −25 50 100 1250 25 75

0.9965

0.9980

1.0005

0.9995

0.9970

0.9985

1.000

0.9990

0.9975

VDD = 4.5 V

VDD = 2.5 V

VDD = 1.25 V

VDD = 0.5 V

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS (continued)

FEEDBACK REGULATION VOLTAGE SENSE AMPLIFIER OUTPUT CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 7. Figure 8.

CURRENT SENSE AMPLIFIER GAIN SWITCHING FREQUENCY

vs vs

JUNCTION TEMPERATURE INPUT VOLTAGE

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Figure 9. Figure 10.

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−50 −25 50 100 1250 25 75

4.35

3.90

4.20

3.95

4.30

4.15

4.05

4.00

4.25

4.10

TJ − Junction Temperature − °C

V

UVLO

− Undervoltage Lockout Threshold − V

V

UVLO(on)

V

UVLO(off)

TJ − Junction Temperature − °C

D

MAX

− Maximum Duty Cycle − %

−50 −25 50 100 1250 25 75

93

83

90

84

86

92

89

87

85

91

88

fSW = 100 kHZ

fSW = 500 kHZ

fSW = 1 MHZ

−50 −25 50 100 1250 25 75

1.10

0.90

1.04

0.92

0.96

1.08

1.02

0.98

0.94

1.06

1.00

TJ − Junction Temperature − °C

V

UVLO

− Relative Programmable UVLO Threshold − %

V

UVLO(on)

V

UVLO(off)

TJ − Junction Temperature − °C

I

SS

− Soft−Start Charging Current − µA

−50 −25 50 100 1250 25 75

14.0

10.0

10.5

11.0

13.5

12.5

11.5

13.0

12.0

TYPICAL CHARACTERISTICS (continued)

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

MAXIMUM DUTY CYCLE UNDERVOLTAGE LOCKOUT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 11. Figure 12.

PROGRAMMABLE UVLO THRESHOLD SOFTSTART CHARGING CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 13. Figure 14.

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100

1.5

0.5
200 300 400 500 600 700 800 900 1000

1.0

3.0

2.0

2.5

3.5

5.0

4.0

4.5

VIN = 28 V

VIN = 24 V

VIN = 18 V

VIN = 15 V

VIN = 12 V

VIN = 10 V

VIN = 8 V

VIN = 5 V

f

OSC

− Oscillator Frequency − kHz

V

OUT

− Output Voltage − V

TJ − Junction Temperature − °C

I

BIAS

− Error Amplifier Input Bias Current − nA

−50 −25 50 100 1250 25 75

0

−90

−80

−70

−10

−30

−60

−20

−40

−50

VDD − Input Voltage − V

f

OSC

− Frequency − kHz

2 6 18 26 3010

500

495

505

520

510

515

490

485

480

14 22

fSW − Switching Frequency − kHz

0

100

0

200 400 600 800 1000

200

300

400

500

600

R

T

− Timing Resistance − kΩ

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS (continued)

ERROR AMPLIFIER INPUT BIAS CURRENT MINIMUM OUTPUT VOLTAGE

vs vs

JUNCTION TEMPERATURE FREQUENCY

Figure 15. Figure 16.

SWITCHING FREQUENCY TYPICAL SWITCHING FREQUENCY

vs vs

TIMING RESISTANCE INPUT VOLTAGE

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Figure 17. Figure 18.

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60 90 150 180 210 270120 240

4

2

8

6

10

14

12

18

16

20

R

KFF

− Feedforward Impedance − kΩ

V

UVLO

−

Programmable UVLO Threshold − V

UVLOV

ON

f

SW

= 500 kHz

UVLOV

OFF

R

KFF

− Feedforward Impedance − kΩ

100 150 250 300 350 450200 400

4

2

8

6

10

14

12

18

16

20

V

UVLO

−

Programmable UVLO Threshold − V

UVLOV

ON

f

SW

= 300 kHz

UVLOV

OFF

40 60 100 120 140 18080 160

4

2

8

6

10

14

12

18

16

20

R

KFF

− Feedforward Impedance − kΩ

V

UVLO

−

Programmable UVLO Threshold − V

UVLOV

ON

f

SW

= 750 kHz

UVLOV

OFF

8 16 20 24 28124

40

20

30

70

50

60

100

80

90

VIN − Input Voltage − V

Duty Cycle − %

UVLO

(on)

= 8 V

UVLO

(on)

= 15 V

UVLO

(on)

= 4.5 V

UVLO

(on)

= 12 V

TYPICAL CHARACTERISTICS (continued)

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

UVLO THRESHOLD VOLTAGE UVLO THRESHOLD VOLTAGE

vs vs

FEEDFORWARD IMPEDANCE FEEDFORWARD IMPEDANCE

Figure 19. Figure 20.

UVLO THRESHOLD VOLTAGE TYPICAL MAXIMUM DUTY CYCLE

vs vs

FEEDFORWARD IMPEDANCE INPUT VOLTAGE

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Figure 21. Figure 22.

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255 10 2015 30

4.10

4.00

4.05

4.15

4.20

4.35

4.25

4.30

4.40

4.45

4.50

VDD − Input Voltage − V

V

DBP

− Low Voltage Bypass Voltage − V

VDD − Input Voltage − V

V

DBP

− Driver Bypass Voltage − V

0

5

4

5 10 15 20 25

7

6

9

8

10

SAO
GND
SS
FB
COMP
PGND
LDRV
DBP

RHL PACKAGE

(BOTTOM VIEW)

SYNC

PGD

LVBP

RT
KFF
ILIM

VDD

HDRV

SA+

SA−

BOOST

SW

20 1

11 10

2
3
4
5
6
7
8
9

19
18
17
16
15
14
13
12

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

INPUT VOLTAGE INPUT VOLTAGE

vs vs

DBP VOLTAGE LOW VOLTAGE BYPASS VOLTAGE

TYPICAL CHARACTERISTICS (continued)

Figure 23. Figure 24.

TERMINAL INFORMATION

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TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME NO.

BOOST 11 I

COMP 6 O FB pin to compensate the overall loop. This pin is internally clamped to a 3.4-V maximum output drive capability

DBP 9 O

FB 5 I
GND 3 - Ground reference for the device.
HDRV 12 O

ILIM 14 I conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately V

KFF 15 I into this pin is used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage at

LDRV 8 O

LVBP 17 O

PGD 18 O

PGND 7
RT 16 I A resistor is connected from this pin to GND to set the switching frequency.

SA+ 20 I Noninverting input of the remote voltage sense amplifier.
SA- 1 I Inverting input of the remote voltage sense amplifier.
SAO 2 O Output of the remote voltage sense amplifier.

SS 4 I

SW 10 I timing. This pin is also the return path from the high-side FET for the floating high-side FET driver. A 1.5- Ω resistor

SYNC 19 I Logic input for pulse train to synchronize oscillator.
VDD 13 I Supply voltage for the device.

I/O DESCRIPTION

The BOOST voltage is 8-V greater than the input voltage. The peak voltage on BOOST is equal to the SW node
voltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internal
bootstrap diode or 300 mV for an external schottkey diode. The voltage differential between this pin and SW is the
available drive voltage for the high-side FET.

Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
for quicker recovery from a saturated feedback loop situation.

8-V regulator output used for the gate drive of the N-channel synchronous rectifier and as the supply for charging
the bootstrap capacitor. This pin should be bypassed to ground with a 1.0-µF ceramic capacitor.

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
voltage, 0.7 V.

Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).

Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sink
from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltage
on this pin is compared to the voltage drop (V

when SW is within 2 V of V
capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time,

or after a timeout (the precondition time) - whichever occurs first. Placing a

VDD

-V

VDD

) across the high side N-channel MOSFET during

SW

VDD

effectively programming the ILIM blanking time. See Applications Information section.
A resistor is connected from this pin to VDD programs the amount of input voltage feed-forward. The current fed

this pin is maintained at 400 mV.
Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to PGND (MOSFET

off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.

4.2-V reference used for internal device logic and analog functions. This pin should be bypassed to GND with a

0.1-µF ceramic capacitor. External loads less than 1 mA and electrically quiet may be applied.
This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a ± 10%

band around the 700 mV reference voltage.
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the

lower MOSFET(s).

Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The
capacitor is charged with an internal current source of 12 µA. The resulting voltage ramp on the SS pin is used as
a second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V
less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the
SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is below the
internal offset voltage of 1 V (300 mV minimum ensured), the resulting output voltage is zero. Also provides timing
for fault recovery attempts. Pulling this pin below 250 mV causes the controller to enter a shutdown state with
HDRV and LDRV held in a low state.

This pin is connected to the switched node of the converter and used for overcurrent sensing as well as gate drive
in series with this pin is required for protection against substrate current issues.

/2 and released

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9

12

8

13

17

16

15

VDD

LVBP

RT

KFF

DBP

HDRV

LDRV

18

3

5

4

PGD

GND

FB

SS

6COMP

Reference

Regulator

Predictive

Gate Drive

Control

Logic

UVLO

Controller

Oscillator

14 ILIM

Pulse

Control

SW

CLK

10 SW

Overcurrent

Comparator

and Control

CLK

ILIM OC

7 PGND

11 BOOST

VDD

UVLO

Ramp

Generator

Power

Good
Logic

770 mV
FB
630 mV

SS Active

PWM

OC

CLK

UVLO

FAULT

IZERO

DBP

+

+

700 mV

RAMP

Soft Start

and

Fault Control

OC
CLK

SW

PGND

LVBP

2SAO

20 SA+

1 SA−

R

R

R

+

R

UDG−04076

19SYNC

TPS40075

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

SIMPLIFIED BLOCK DIAGRAM

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