Texas Instruments TPS3840-Q1 Datasheet

TPS3840PL18

MR

VDD

GNDCT

RESET

TPS3840DL30

VDD

GND

RESET

MR

CT

Microcontroller

V

CORE

V

I/O

3.3V

1.8V

RESET

Product
Folder

Order
Now

Technical
Documents

Tools &
Software

Support &
Community

TPS3840-Q1

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

TPS3840-Q1 Automotive Nano IQVoltage Supervisor With MR and Programmable Delay

1 Features

1

• Qualified for automotive applications

• AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C

ambient operating temperature
– Device HBM ESD classification level 2
– Device CDM ESD classification level C7B

• Wide operating voltage : 1.5 V to 10 V
– Use external resistors to extend Vin range

• Nano supply current : 350 nA (Typ), 700 nA (Max)

• Fixed threshold voltage (V
– Threshold from 1.6 V to 4.9 V in 0.1-V steps
– High accuracy: 1% (Typ), 1.5% (Max)
– Built-in hysteresis (V

– 1.6 V < V
– 3.1 V ≤ V

• Fast start-up delay (t

≤ 3.0 V = 100 mV (typical)

IT-

< 4.9 V = 200 mV (typical)

IT-

STRT

• Programmable capacitor-based reset time delay:
– tD: 50 µs (no capacitor) to 6.2 s (10-µF)

• Active-low manual reset (MR)

• Three output topologies:
– TPS3840DL-Q1: open-drain, active-low

(RESET)

– TPS3840PL-Q1: push-pull, active-low

(RESET)

– TPS3840PH-Q1: push-pull, active-high

(RESET)

• Package: 5-pin SOT-23 (DBV)

)

IT-

)

IT+

): 350 µs (Max)

2 Applications

• Automotive head unit and cluster

• Automotive display, integrated cockpit and driver

monitoring

• Telematics control unit and emergency call

3 Description

The TPS3840-Q1 family of voltage supervisors or
reset ICs can operate at high voltage levels while
maintaining very low quiescent current across the
whole VDDand temperature range. TPS3840-Q1
offers best combination of low power consumption,
high accuracy and low propagation delay (t
µs typical).

Reset output signal is asserted when the voltage at
VDD drops below the negative voltage threshold (V
or when manual reset is pulled to a low logic (V
Reset signal is cleared when VDDrise above V
hysteresis (V
above V

) and manual reset (MR) is floating or

IT+

and the reset time delay (tD) expires.

MR_H

Reset time delay can be programmed by connecting
a capacitor between CT pin and ground. For a fast
reset CT pin can be left floating.

Additional features: Low power-on reset voltage
(V

), built-in glitch immunity protection for MR and

POR

VDD, built-in hysteresis, low open-drain output
leakage current (I

). TPS3840-Q1 is a perfect

LKG(OD)

voltage monitoring solution for automotive
applications and battery-powered / low power
applications.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS3840-Q1 SOT-23 (5) (DBV) 2.90 mm × 1.60 mm
(1) For package details, see the mechanical drawing addendum

at the end of the data sheet.

(1)

p_HL

IT-

= 30

IT-

MR_L

plus

)

).

Typical Application Circuit

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS3840-Q1

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

www.ti.com

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison ............................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 7

7.7 Typical Characteristics.............................................. 9

8 Detailed Description............................................ 16

8.1 Overview................................................................. 16

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 16

8.4 Device Functional Modes........................................ 19

9 Application and Implementation ........................ 20

9.1 Application Information............................................ 20

9.2 Typical Application ................................................. 20

10 Power Supply Recommendations ..................... 25

11 Layout................................................................... 25

11.1 Layout Guidelines ................................................. 25

11.2 Layout Example .................................................... 25

12 Device and Documentation Support ................. 26

12.1 Device Nomenclature............................................ 26

12.2 Receiving Notification of Documentation Updates 27

12.3 Community Resources.......................................... 27

12.4 Trademarks........................................................... 27

12.5 Electrostatic Discharge Caution............................ 27

12.6 Glossary................................................................ 27

13 Mechanical, Packaging, and Orderable

Information........................................................... 27

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (September 2019) to Revision B Page

• Changed equation 5 and 6 ................................................................................................................................................... 17

• Added section describing further details on capacitor. ........................................................................................................ 18

• Deleted non-relevant application design. ............................................................................................................................ 22

Changes from Original (April 2019) to Revision A Page

• Advance Information to Production Data Release ................................................................................................................ 1

2

Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

Product Folder Links: TPS3840-Q1

TPS3840 XX XX XXX Q1

OUTPUT TYPE

DL: Open-Drain Active-Low
PL: Push-Pull Active-Low
PH: Push-Pull Active-High

Threshold Voltage

16: 1.6V
17: 1.7V
...
49: 4.9V
See Device
Threshold Table

Package

DBV: SOT-23

TPS3840-Q1

www.ti.com

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

5 Device Comparison

Figure 1 shows the device nomenclature to determine the device variant. Other voltages from Table 3 at the end

of datasheet can be sampled upon request, please contact TI sales representative for details.

Figure 1. Device Nomenclature

Product Folder Links: TPS3840-Q1

Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

3

1RESET

2VDD

3GND 4 MR

5 CT

Not to scale

/ NC

1RESET

2VDD

3GND 4 MR

5 CT

Not to scale

/ NC

TPS3840-Q1

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

6 Pin Configuration and Functions

www.ti.com

DBV Package

5-Pin

TPS3840PL-Q1, TPS3840DL-Q1 Top View

DBV Package

5-Pin

TPS3840PH-Q1 Top View

Pin Functions

PIN

NAME TPS3840PL-Q1,

TPS3840PH-Q1

TPS3840DL-Q1

RESET N/A 1 O Active-High Output Reset Signal: This pin is driven high

RESET 1 N/A O Active-Low Output Reset Signal: This pin is driven logic

VDD 2 2 I Input Supply Voltage. TPS3840-Q1 monitors VDD voltage
GND 3 3 _ Ground
MR / NC 4 4 I Manual Reset. Pull this pin to a logic low (V

CT 5 5 - Capacitor Time Delay Pin. The CT pin offers a user-

I/O DESCRIPTION

when either the MR pin is driven to a logic low or VDD
voltage falls below the negative voltage threshold (V
RESET remains high (asserted) for the delay time period (tD)
after both MR is floating or above V
rise above V

IT+.

MR_L

when either the MR pin is driven to a logic low or VDD
voltage falls below the negative voltage threshold (V
RESET remains low (asserted) for the delay time period (tD)
after both MR is floating or above V
rise above V

IT+.

MR_L

reset signal in the output pin. After the MR pin is left floating
or pull to V
reset delay time(tD) expires. MR can be left floating when

the output goes to the nominal state after the

MR_H

not in use. NC stands for "No Connection" or floating.

programmable delay time. Connect an external capacitor on
this pin to adjust time delay. When not in use leave pin
floating for the smallest fixed time delay.

).

IT-

and VDD voltage

).

IT-

and VDD voltage

) to assert a

MR_L

4

Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

Product Folder Links: TPS3840-Q1

TPS3840-Q1

www.ti.com

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted

VDD –0.3 12
RESET (TPS3840PL) –0.3 VDD+ 0.3

Voltage

RESET (TPS3840PH) –0.3 VDD+ 0.3
RESET (TPS3840DL) –0.3 12

(2)

MR
CT –0.3 5.5

Current RESET pin and RESET pin ±70 mA

Temperature

(3)

Operating junction temperature, T
Storage, T

stg

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDDand out of MR. VMRshould not be higher than V
(3) As a result of the low dissipated power in this device, it is assumed that TJ= TA.

7.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-

(1)

V

(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

001
Charged device model (CDM), per JEDEC specification

JESD22-C101

(2)

(1)

MIN MAX UNIT

V

–0.3 12

J

–40 150
–65 150

°C

VALUE UNIT

± 2000

V

± 750

DD.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

V

DD

V

, V

RESET

RESET

I

, I

RESET

RESET

T

J

(1)

V

MR

(1) If the logic signal driving MR is less than VDD, then additional current flows into VDDand out of MR. VMRshould not be higher than V

Input supply voltage 1.5 10 V
RESET pin and RESET pin voltage 0 10 V
RESET pin and RESET pin current 0 ±5 mA
Junction temperature (free air temperature) –40 125 °C
Manual reset pin voltage 0 V

DD

V

7.4 Thermal Information

TPS3840

THERMAL METRIC

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 187.5 °C/W
Junction-to-case (top) thermal resistance 109.2 °C/W
Junction-to-board thermal resistance 92.8 °C/W
Junction-to-top characterization parameter 35.4 °C/W
Junction-to-board characterization parameter 92.5 °C/W
Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(1)

UNITDBV (SOT23-5)

5 PINS

DD.

Product Folder Links: TPS3840-Q1

Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

5

TPS3840-Q1

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

www.ti.com

7.5 Electrical Characteristics

At 1.5 V ≤ VDD≤ 10 V, CT = MR = Open, RESET pull-up resistor (R
and over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at TJ= 25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

COMMON PARAMETERS

V
V
V
V

I

DD

V
V
R
R

TPS3840PL (Push-Pull Active-Low)

V

V

V

TPS3840PH (Push-Pull Active-High)

V

V

V

TPS3840DL(Open-Drain)

V

V

I

lkg(OD)

(1) V
(2) V
(3) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR
(4) V

Input supply voltage 1.5 10 V

DD

Negative-going input threshold accuracy

IT­HYS
HYS

Hysteresis on V
Hysteresis on V

pin V

IT-

pin V

IT-

(1)

-40°C to 125°C –1.5 1 1.5 %
= 3.1 V to 4.9 V 175 200 225 mV

IT-

= 1.6 V to 3.0 V 75 100 125 mV

IT-

VDD = 1.5 V < VDD< 10 V

Supply current into VDD pin

VDD > V
TA= -40°C to 125°C

Manual reset logic low input

MR_L

Manual reset logic high input

MR_H

Manual reset internal pull-up resistance 100 kΩ

MR

CT pin internal resistance 350 500 650 kΩ

CT

Power on Reset Voltage

POR

Low level output voltage

OL

(3)

(3)

V

(4)

OL(max)

I

OUT(Sink)

1.5 V < VDD< 5 V

VDD< V
I

OUT(Sink)

1.5 V < VDD< 5 V

VDD> V

High level output voltage

OH

I

OUT(Source

5 V < VDD< 10 V
VDD> V
I

OUT(Source)

Power on Reset Voltage

POR

(4)

VOH, I

OUT(Source)

1.5 V < VDD< 5 V

VDD> V

Low level output voltage

OL

I

OUT(Sink)

1.5 V < VDD< 5 V

VDD> V
I

OUT(Sink)

High level output voltage 1.5 V < VDD< 5 V, VDD< V

OH

Power on Reset Voltage

POR

Low level output voltage

OL

(4)

I

OUT(Source)

V

OL(max)

I

OUT (Sink)

1.5 V < VDD< 5 V

VDD< V
I

OUT(Sink)

RESET pin in High Impedance,

Open-Drain output leakage current

threshold voltage range from 1.6 V to 4.9 V in 100 mV steps, for released versions see Device Voltage Thresholds table.

IT-

= V

IT+

POR

+ V

HYS

IT-

is the minimum VDDvoltage level for a controlled output state. VDDslew rate ≤ 100mV/µs

VDD= V
V

< V

IT+

) = 100 kΩ to VDD, output reset load (C

pull-up

(2)

IT+

0.7V

DD

= 200 mV

= 200 nA

IT-

= 2 mA

IT+

(2)

0.8V

DD

) = 2 mA

IT+

(2)

0.8V

DD

= 5 mA

= 500 nA 950 mV

(2)

IT+

= 2 mA

(2)

IT+

= 5 mA

,

= 2 mA

IT-

0.8V

DD

= 0.2 V

= 5.6 uA

IT-

= 2 mA

= 5.5 V

RESET

DD

) = 10 pF

LOAD

300 700 nA

600 mV

300 mV

200 mV

200 mV

200 mV

950 mV

200 mV

90 nA

V

V

V

V

6

Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

Product Folder Links: TPS3840-Q1

t

D

t

P_HL

VDD

V

POR

V

OH

V

OL

V

IT+

V

DD(MIN)

V

IT-

RESET

t

STRT + tD

t

P_HL

t

STRT + tD

TPS3840-Q1

www.ti.com

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

7.6 Timing Requirements

At 1.5 V ≤ VDD≤ 10 V, CT = MR = Open, RESET pull-up resistor (R
and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted.
Typical values are at TJ= 25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

STRT

t

P_HL

t

D

t

GI_VIT-

t

MR_PW

t

MR_RES

t

MR_tD

Startup Delay
Propagation detect delay for VDD falling

below V

Reset time delay

Glitch immunity V
MR pin pulse duration to initiate reset 300 ns
Propagation delay from MR low to reset VDD= 4.5 V, MR < V

Delay from release MR to deasert reset

(1) When VDD starts from less than the specified minimum VDDand then exceeds V

capacitor at CT pin will add tDdelay to t
(2) t
(3) The MIN and MAX reset time delay with external capacitor depends on RCTand is calculated using Equation 5 and Equation 6 in

measured from threhold trip point (V

P_HL

Section 8.3.2
(4) Overdrive % = [(VDD/ V

(1)

IT-

CT pin open 100 220 350 µs
VDD= V

IT+

to (V

CT pin = open

(3)

CT pin = 10 nF 6.2 ms
CT pin = 1 µF 619 ms
5% V

IT-

overdrive

IT-

VDD= 4.5 V,
MR = V

MR_L

time

STRT

) to VOLfor active low variants and VOHfor active high variants.

IT-

) - 1] × 100%

IT-

) = 100 kΩ to VDD, output reset load (C

pull-up

(2)

) - 10%

IT-

(4)

MR_L

to V

MR_H

, reset is release after the startup delay (t

IT+

) = 10 pF

LOAD

15 30 µs

50 µs

10 µs

700 ns

t

D

STRT

ms

), a

(1) t

D (no cap)

is included in t

time delay. If tDdelay is programmed by an external capacitor connected to CT pin then

STRT

tDprogrammed time will be added to the startup time, VDD slew rate = 100 mV / µs.

(2) Open-Drain timing diagram assumes pull-up resistor is connected to RESET

Figure 4. Timing Diagram TPS3840DL-Q1 (Open-Drain Active-Low)

Product Folder Links: TPS3840-Q1

Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

7

t

D

t

P_HL

VDD

V

POR

V

OH

V

OL

V

IT+

V

DD(MIN)

V

IT-

RESET

t

STRT + tD

t

P_HL

t

STRT + tD

t

D

t

P_HL

VDD

V

POR

V

OH

V

OL

V

IT+

V

DD(MIN)

V

IT-

RESET

t

P_HL

t

STRT + tD

t

STRT + tD

TPS3840-Q1

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

www.ti.com

(3) t

D (no cap)

is included in t

time delay. If tDdelay is programmed by an external capacitor connected to CT pin, then

STRT

tDprogrammed time will be added to the startup time. VDD slew rate = 100 mV / µs.

Figure 5. Timing Diagram TPS3840PL-Q1 (Push-Pull Active-Low)

(4) t

D (no cap)

tDprogrammed time will be added to the total startup time. VDD slew rate = 100 mV / µs.

is included in t

time delay. If tDdelay is programmed by an external capacitor connected to CT pin, then

STRT

Figure 6. Timing Diagram TPS3840PH-Q1 (Push-Pull Active-High)

8

Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

Product Folder Links: TPS3840-Q1

Temperature (°C)

VIT- Accuracy (%)

-40 -20 0 20 40 60 80 100 120 140

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

VIT_

PL16
PL28
PL49

Temperature (°C)

VIT- Accuracy (%)

-40 -20 0 20 40 60 80 100 120 140

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

VIT_

PH16
PH30
PH49

VDD (V)

IDD (µA)

1 2 3 4 5 6 7 8 9 10

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6
25°C

-40°C
125°C

Temperature (°C)

VIT- Accuracy (%)

-40 -20 0 20 40 60 80 100 120 140

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

VIT_

DL16
DL29
DL49

VDD (V)

IDD (µA)

1 2 3 4 5 6 7 8 9 10

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6
25°C

-40°C
125°C

VDD (V)

IDD (µA)

1 2 3 4 5 6 7 8 9 10

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6
25°C

-40°C
125°C

TPS3840-Q1

www.ti.com

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

7.7 Typical Characteristics

Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ= 25°C, VDD= 3.3 V,
R

pull-up

= 100 kΩ, C

= 50 pF, unless otherwise noted.

Load

Figure 7. Supply Current vs Supply Voltage for

TPS3840DL49-Q1

Figure 9. Supply Current vs Supply Voltage for

TPS3840PH49-Q1

Figure 8. Supply Current vs Supply Voltage for

TPS3840PL49-Q1

Figure 10. Negative-going Input Threshold Accuracy over

Temperature for TPS3840DL-Q1

Figure 11. Negative-going Input Threshold Accuracy over

Temperature for TPS3840PL-Q1

Product Folder Links: TPS3840-Q1

Figure 12. Negative-going Input Threshold Accuracy over

Temperature for TPS3840PH-Q1

Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

9

VDD (V)

V

RESET

(V)

0 1 2 3 4 5 6 7 8 9 10

-1

0

1

2

3

4

5

6

7

8

9

10

VRES

25°C

-40°C
125°C

VDD (V)

V

RESET

(V)

0 1 2 3 4 5 6 7 8 9 10

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VRES

25°C

-40°C
125°C

VDD (V)

V

RESET

(V)

0 1 2 3 4 5 6 7 8 9 10

-1

0

1

2

3

4

5

6

7

8

9

10

VRES

25°C

-40°C
125°C

Temperature (°C)

VHYS Accuracy (%)

-40 -20 0 20 40 60 80 100 120 140

-20

-15

-10

-5

0

5

10

15

20

Vhys

PH16
PH30
PH49

Temperature (°C)

VHYS Accuracy (%)

-40 -20 0 20 40 60 80 100 120 140

-20

-15

-10

-5

0

5

10

15

20

Vhys

DL16
DL29
DL49

Temperature (°C)

VHYS Accuracy (%)

-40 -20 0 20 40 60 80 100 120 140

-20

-15

-10

-5

0

5

10

15

20

Vhys

PL16
PL28
PL49

TPS3840-Q1

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

www.ti.com

Typical Characteristics (continued)

Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ= 25°C, VDD= 3.3 V,
R

pull-up

= 100 kΩ, C

= 50 pF, unless otherwise noted.

Load

Figure 13. Input Threshold V

TPS3840DL-Q1

Figure 15. Input Threshold V

TPS3840PH-Q1

Hysteresis Accuracy for

IT-

Hysteresis Accuracy for

IT-

Figure 14. Input Threshold V

Hysteresis Accuracy for

IT-

TPS3840PL-Q1

Figure 16. Output Voltage vs Input Voltage for

TPS3840DL49-Q1

10

Figure 17. Output Voltage vs Input Voltage for

TPS3840PL49-Q1

Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

Figure 18. Output Voltage vs Input Voltage for

TPS3840PH49-Q1

Product Folder Links: TPS3840-Q1

I

RESET

(mA)

V

OL

(V)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0

10

20

30

40

50

60

70

80

VOL_

25°C

-40°C
125°C

VDD (V)

VOL (V)

5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

VOLv

25°C

-40°C
125°C

I

RESET

(mA)

V

OL

(V)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-20

0

20

40

60

80

100

120

140

VOL_

25°C

-40°C
125°C

VDD (V)

VOL (V)

1.5 2 2.5 3 3.5 4 4.5 5

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

0.055

VOLv

25°C

-40°C
125°C

I

RESET

(mA)

V

OL

(V)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

0

20

40

60

80

100

120

140

VOL_

25°C

-40°C
125°C

VDD (V)

VOL (V)

1.5 2 2.5 3 3.5 4 4.5 5

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

0.055

VOLv

25°C

-40°C
125°C

TPS3840-Q1

www.ti.com

SNVSBA1B –APRIL 2019–REVISED APRIL 2020

Typical Characteristics (continued)

Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ= 25°C, VDD= 3.3 V,
R

pull-up

= 100 kΩ, C

= 50 pF, unless otherwise noted.

Load

Figure 19. Low Level Output Voltage vs I

TPS3840DL49-Q1

Figure 21. Low Level Output Voltage vs I

TPS3840PL49-Q1

RESET

RESET

for

for

Figure 20. Low Level Output Voltage vs VDDfor

TPS3840DL49-Q1

Figure 22. Low Level Output Voltage vs VDD for

TPS3840PL49-Q1

Figure 23. Low Level Output Voltage vs I

TPS3840PH49-Q1

for

RESET

Product Folder Links: TPS3840-Q1

Figure 24. Low Level Output Voltage vs VDD for

TPS3840PH49-Q1

Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

11