Texas Instruments TPS28225DRG4, TPS28225 Datasheet

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FEATURES DESCRIPTION

APPLICATIONS

TPS28225

SLUS710 – MAY 2006

High-Frequency 4-A Sink Synchronous MOSFET Driver

• Drives Two N-Channel MOSFETs with 14-ns

The TPS28225 is a high-speed driver for N-channel

Adaptive Dead Time

complimentary driven power MOSFETs with adaptive
dead-time control. This driver is optimized for use in

• Wide Gate Drive Voltage: 4.5V Up to 8.8V

variety of high-current one and multi-phase dc-to-dc

With Best Efficiency at 7V to 8V

converters. The TPS28225 is a solution that provides

• Wide Power System Train Input Voltage: 3V

highly efficient, small size low EMI emmissions.

Up to 27V

The performance is achieved by up to 8.8-V gate

• Wide Input PWM Signals: 2.0V up to 13.2-V

drive voltage, 14-ns adaptive dead-time control,

Amplitude

14-ns propagation delays and high-current 2-A

• Capable Drive MOSFETs with ≥ 40-A Current

source and 4-A sink drive capability. The 0.4- Ω

per Phase

impedance for the lower gate driver holds the gate of
power MOSFET below its threshold and ensures no

• High Frequency Operation: 14ns Propagation

shoot-through current at high dV/dt phase node

Delay and 10ns Rise/Fall Time Allow Fsw -

transitions. The bootstrap capacitor charged by an

2MHz

internal diode allows use of N-channel MOSFETs in

• Capable Propagate <30-ns Input PWM Pulses

half-bridge configuration.

• Low-Side Driver Sink On-Resistance (0.4 Ω )

The TPS28225 features a 3-state PWM input

Prevents dV/dT Related Shoot-Through

compatible with all multi-phase controllers employing

Current

3-state output feature. As long as the input stays

• 3-State PWM Input for Power Stage Shutdown

within 3-state window for the 250-ns hold-off time,
the driver switches both outputs low. This shutdown

• Space Saving Enable (input) and Power Good

mode prevents a load from the reversed-

(output) Signals on Same Pin

output-voltage.

• Thermal Shutdown

The other features include under voltage lockout,

• UVLO Protection

thermal shutdown and two-way enable/power good

• Internal Bootstrap Diode

signal. Systems without 3-state featured controllers
can use enable/power good input/output to hold both

• Economical SOIC-8 and Thermally Enhanced

outputs low during shutting down.

3-mm x 3-mm DFN-8 Packages

• High Performance Replacement for Popular

The TPS28225 is offered in an economical SOIC-8

3-State Input Drivers and thermally enhanced low-size Dual Flat No-Lead

(DFN-8) packages. The driver is specified in the
extended temperature range of –40 ° C to 125 ° C with
the absolute maximum junction temperature 150 ° C.

• Multi-Phase DC-to-DC Converters with

Analog or Digital Control

• Desktop and Server VRMs and EVRDs

• Portable/Notebook Regulators

• Synchronous Rectification for Isolated Power

Supplies

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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FUNCTIONAL BLOCK DIAGRAM

6

13K

2

VDD

EN / PG

BOOT

UGATE

PHASE

LGATE

GND

7

1

8

5

4

VDD

27K

3 −STATE

INPUT

CIRCUIT

PWM

3

SHOOT −

THROUGH

PROTECTION

THERMAL

SD

HLD−OFF

TIME

UVLO

TYPICAL APPLICATIONS

3

3

2

BOOT

UGATE

PHASE

LGATE

GND

1

8

5

4

6

VDD

ENBL

7

PWM

3

OUT

FB

3

GND

3

TPS28225

V

DD

(4.5Vto8V)

V

IN

(3Vto32V − VDD)

V

OUT

VCC

TPS40200

TPS28225

SLUS710 – MAY 2006

One-Phase POL Regulator

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PWM

CONTROLLER

ISOLATION

AND

FEEDBACK

C O NT RO L

DRIVE

LO

DRIVE

HI

HI

LI

HB

HO

HS

LO

2

BOOT

UGATE

PHASE

LGATE

GND

1

8

5

4

3

VDD

EN/PG

7

PWM

6

LINEAR

REG.

VDD(4.5Vto8V)

V

OUT

=3.3V

35Vto75V

12V

PrimaryHighSide

V

DD

HighVoltageDriver

V

SS

TPS28255

TPS28225

SLUS710 – MAY 2006

TYPICAL APPLICATIONS (continued)

Driver for Synchronous Rectification with Complementary Driven MOSFETs

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5

4

7 3

8

1

2

2

BOOT

UGATE

PHASE

LGATE

GND

1

8

5

4

6 VDD

EN/PG

7

PWM

3

2

BOOT

UGATE

PHASE

LGATE

GND

1

8

5

4

6 VDD

EN

/PG

7

PWM

3

VIN

PWM 4

GND

VOUT

PWM1

8

PWM3

Enable

PWM2

ToDriver

ToDriver

GNDS

ToController

CSCNCS 4

ToController

CS 1

VDD(4.5Vto8V)

V

IN

(3Vto32V − VDD)

TPS28225

TPS28225

TPS4009x

oranyotheranalog

ordigitalcontroller

V

OUT

TPS28225

SLUS710 – MAY 2006

TYPICAL APPLICATIONS (continued)

Multi-Phase Synchronous Buck Converter

ORDERING INFORMATION

(1) (2) (3)

TEMPERATURE RANGE, TA= T

J

PACKAGE TAPE AND REEL QTY. PART NUMBER

Plastic 8-pin SOIC (D) 250 TPS28225DT
Plastic 8-pin SOIC (D) 2500 TPS28225DR

-40°C to 125°C
Plastic 8-pin DFN (DRB) 250 TPS28225DRBT

Plastic 8-pin DFN (DRB) 3000 TPS28225DRBR

(1) SOIC-8 (D) and DFN-8 (DRB) packages are available taped and reeled. Add T suffix to device type (e.g. TPS28225DT) to order taped

devices and suffix R to device type to order reeled devices.

(2) The SOIC-8 (D) and DFN-8 (DRB) package uses in Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to

260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.

(3) In the DFN package, the pad underneath the center of the device is a thermal substrate. The PCB “thermal land” design for this

exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). This combination of
vias for vertical heat escape and buried planes for heat spreading allows the DFN to achieve its full thermal potential. This pad should
be either grounded for best noise immunity, and it should not be connected to other nodes.

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ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

(1)

RECOMMENDED OPERATING CONDITIONS

TPS28225

SLUS710 – MAY 2006

over operating free-air temperature range (unless otherwise noted)

(1) (2)

TPS28225 VALUE UNIT

Input supply voltage range, V

DD

(3)

–0.3 to 8.8

Boot voltage, V

BOOT

–0.3 to 33

DC –2 to 32 or V

BOOT

+ 0.3 – V

DD

whichever is less

Phase voltage, V

PHASE

Pulse < 400 ns, E = 20 µ J –7 to 33.1 or V

BOOT

+ 0.3 – V

DD

whichever is less

Input voltage range, V

PWM

, V

EN/PG

–0.3 to 13.2

V

PHASE

– 0.3 to V

BOOT

+ 0.3, (V

BOOT

– V

PHASE

< 8.8) V

Output voltage range, V

UGATE

Pulse < 100 ns, E = 2 µ J V

PHASE

– 2 to V

BOOT

+ 0.3, (V

BOOT

– V

PHASE

< 8.8)

–0.3 to V

DD

+ 0.3

Output voltage range, V

LGATE

Pulse < 100 ns, E = 2 µ J –2 to V

DD

+ 0.3
ESD rating, HBM 2 k
ESD rating, HBM ESD rating, CDM 500
Continuous total power dissipation See Dissipation Rating Table
Operating virtual junction temperature range, T

J

–40 to 150

Operating ambient temperature range, T

A

–40 to 125

° C

Storage temperature, T

stg

–65 to 150

Lead temperature (soldering, 10 sec.) 300

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(3) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. Consult

Packaging Section of the Data book for thermal limitations and considerations of packages.

DERATING FACTOR TA< 25 ° C TA=70 ° C TA= 85 ° C

BOARD PACKAGE R

θ JC

R

θ JA

ABOVE TA= 25 ° C POWER RATING POWER RATING POWER RATING

High-K

(2)

D 39.4 ° C/W 100°C/W 10 mW/°C 1.25 W 0.8 W 0.65 W

High-K

(3)

DRB 1.4 ° C/W 48.5°C/W 20.6 mW/°C 2.58 W 1.65 W 1.34 W

(1) These thermal data are taken at standard JEDEC test conditions and are useful for the thermal performance comparison of different

packages. The cooling condition and thermal impedance R

θ JA

of practical design is specific.

(2) The JEDEC test board JESD51-7, 3-inch x 3-inch, 4-layer with 1-oz internal power and ground planes and 2-oz top and bottom trace

layers.
(3) The JEDEC test board JESD51-5 with direct thermal pad attach, 3-inch x 3-inch, 4-layer with 1-oz internal power and ground planes and

2-oz top and bottom trace layers.

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

V

DD

Input supply voltage 4.5 7.2 8

V

V

IN

Power input voltage 3 32 V

–VDD

T

J

Operating junction temperature range –40 125 °C

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ELECTRICAL CHARACTERISTICS

(1)

TPS28225

SLUS710 – MAY 2006

V

DD

= 7.2 V, EN/PG pulled up to V

DD

by 100-k Ω resistor, TA= TJ= –40 ° C to 125 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UNDER VOLTAGE LOCKOUT

Rising threshold V

PWM

= 0 V 3.2 3.5 3.8

Falling threshold V

PWM

= 0 V 2.7 3.0 V

Hysteresis 0.5

BIAS CURRENTS

I

DD(off)

Bias supply current V

EN/PG

= low, PWM pin floating 350

µ A

I

DD

Bias supply current V

EN/PG

= high, PWM pin floating 500

INPUT (PWM)

V

PWM

= 5 V 185

I

PWM

Input current µ A

V

PWM

= 0 V –200

PWM 3-state rising threshold

(2)

1.0
V

PWM 3-state falling threshold V

PWM

PEAK = 5 V 3.4 3.8 4.0

t

HLD_R

3-state shutdown Hold-off time 250

ns

T

MIN

PWM minimum pulse to force U

GATE

pulse CL= 3 nF at U

GATE

, V

PWM

= 5 V 30

ENABLE/POWER GOOD (EN/PG)

Enable high rising threshold PG FET OFF 1.7 2.1
Enable low falling threshold PG FET OFF 0.8 1.0

V

Hysteresis 0.35 0.70
Power good output V

DD

= 2.5 V 0.2

UPPER GATE DRIVER OUTPUT (UGATE)

Source resistance 500 mA source current 1.0 2.0 Ω
Source current

(2)

V

UGATE-PHASE

= 2.5 V 2.0 A

t

RU

Rise time CL= 3 nF 10 ns
Sink resistance 500 mA sink current 1.0 2.0 Ω
Sink current

(2)

V

UGATE-PHASE

= 2.5 V 2.0 A

t

FU

Fall time CL= 3 nF 10 ns

LOWER GATE DRIVER OUTPUT (LGATE)

Source resistance 500 mA source current 1.0 2.0 Ω
Source current

(2)

V

LGATE

= 2.5 V 2.0 A

t

RL

Rise time

(2)

CL= 3 nF 10 ns
Sink resistance 500 mA sink current 0.4 1.0 Ω
Sink current

(2)

V

LGATE

= 2.5 V 4.0 A

Fall time

(2)

CL= 3 nF 5 ns

SWITCHING TIME

t

DLU

UGATE turn-off propagation Delay CL= 3 nF 14

t

DLL

LGATE turn-off propagation Delay CL= 3 nF 14

ns

t

DTU

Dead time LGATE turn-off to UGATE turn-on CL= 3 nF 14

t

DTL

Dead time UGATE turn-off to LGATE turn-on CL= 3 nF 14

BOOTSTRAP DIODE

V

F

Forward voltage Forward bias current 100 mA 1.0 V

THERMAL SHUTDOWN

Rising threshold

(2)

150 160 170

Falling threshold

(2)

130 140 150 ° C

Hysteresis 20

(1) Typical values for TA= 25°C
(2) Not tested in production

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DEVICE INFORMATION

1

2

3

4

8

7

6

5

UGATE

BOOT

PWM

GND

PHASE

EN/PG

VDD

LGATE

5

3

7

6

81

2BOOT

PWM VDD

EN/PG

LG ATEGND

UG ATE PHASE

4

Exposed

Thermal
Die Pad

6

13K

2

VDD

EN /PG

BOOT

UGATE

PHASE

LGATE

GND

7

1

8

5

4

VDD

27K

3−STATE

INPUT

CIRCUIT

PWM

3

SHOOT −

THROUGH

PROTECTION

THERMAL

SD

HLD−OFF

TIME

UVLO

TPS28225

SLUS710 – MAY 2006

SOIC-8 Package (top view)

DRB-8 Package (top view)

FUNCTIONAL BLOCK DIAGRAM

A. For the TPS28224DRB device the thermal PAD on the bottom side of package must be soldered and connected to

the GND pin and to the GND plane of the PCB in the shortest possible way. See Recommended Land Pattern in the
Application section.

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Normal switching

PWM

LGATE

UGATE

3 −State
window

90 %

10 %

t

DLL

50 %

t

FL

50 %

t

PWM_MIN

t

DTU

90 %

10 %

t

RU

90 %

10 %

t

DLU

t

FU

t

DTL

90 %

10 %

t

RL

t

HLD_R

90 %

10 %

90 %

90 %

t

HLD_F

Enter into 3 −State

at PWM rise

Exit 3 −State

Enter into 3 −State

at PWM fall

PWM Low and High after 3 −

State to allow Bootstrap

Capacitor Restore Charge

TRUTH TABLE

TPS28225

SLUS710 – MAY 2006

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

SOIC-8 DRB-8 NAME

1 1 UGATE O Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET.

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between

2 2 BOOT I/O this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper

MOSFET.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states

3 3 PWM I during operation, see the 3-state PWM Input section under DETAILED DESCRIPTION for further

details. Connect this pin to the PWM output of the controller.

4 4 GND — Ground pin. All signals are referenced to this node.

Exposed Thermal

— Connect directly to the GND for better thermal performance and EMI

die pad pad

Lower gate drive sink/source output. Connect to the gate of the low-side power N-Channel

5 5 LGATE O

MOSFET.

6 6 VDD I Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND.

Enable/Power Good input/output pin with 1M Ω impedance. Connect this pin to HIGH to enable
and LOW to disable the IC. When disabled, the device draws less than 350 µ A bias current. If the

7 7 EN/PG I/O

V

DD

is below UVLO threshold or over temperature shutdown occurs, this pin is internally pulled

low.
Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin

8 8 PHASE I

provides a return path for the upper gate driver.

TIMING DIAGRAM

V

DD

FALLING > 3 V AND TJ< 150 ° C

V

DD

RISING < 3.5 V EN/PG FALLING > 1.0 V

PIN

EN/PG RISING

OR TJ> 160 ° C

PWM > 1.5 V AND PWM SIGNAL SOURCE IMPEDANCE

< 1.7 V

PWM < 1 V

T

RISE

/T

FALL

< 200 ns >40 k Ω FOR > 250ns (3-State)

(1)

LGATE Low Low High Low Low

UGATE Low Low Low High Low

EN/PG Low

(1) To exit the 3-state condition, the PWM signal should go low. One Low PWM input signal followed by one High PWM input signal is

required before re-entering the 3-state condition.

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TYPICAL CHARACTERISTICS

−40 125

300

340

380

420

460

500

25

320

360

400

440

480

TJ − Temperature − °C

I

DD(off)

− Bias Supply − µA

2.00

2.75

3.25

4.00

2.25

2.50

3.00

3.50

3.75

UVLO − Under Voltage Lockout − V

−40 12525

Falling

Rising

TJ − Temperature − °C

0.0

PWM − PWM 3−State Threshold − V

−40 12525

2.0

3.0

5.0

0.5

1.0

2.5

2.5

4.5

1.5

4.0

Falling

Rising

TJ − Temperature − °C

−40 12525

0.00

0.75

1.25

2.00

0.25

0.50

1.00

1.50

1.75

Falling

Rising

TJ − Temperature − °C

EN/PG − Enable/Power Good − V

TPS28225

SLUS710 – MAY 2006

BIAS SUPPLY CURRENT UNDER VOLTAGE LOCKOUT THRESHOLD

vs vs

TEMPERATURE TEMPERATURE

(V

EN/PG

= Low, PWM Input Floating, V

DD

= 7.2V)

Figure 1. Figure 2.

ENABLE/POWER GOOD THRESHOLD PWM 3-STATE THRESHOLDS, (5-V Input Pulses)

vs vs

TEMPERATURE (V

DD

= 7.2 V) TEMPERATURE, (V

DD

= 7.2 V)

Figure 3. Figure 4.

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0

−40 12525

0.75

1.25

2.00

0.25

0.50

1.00

1.50

1.75

R

SINK

R

SOURCE

TJ − Temperature − °C

R

OUT

− Output Impedance − Ω

0

−40 12525

0.75

1.25

2.00

0.25

0.50

1.00

1.50

1.75

R

SINK

R

SOURCE

TJ − Temperature − °C

R

OUT

− Output Impedance − Ω

−40 12525

4

6

10

12

14

5

7

9

11

13

8

Falling

Rising

TJ − Temperature − °C

t

RL

/t

FL

− Rise and Fall Time − ns

6

8

11

13

15

7

9

10

12

14

−40 12525

Falling

Rising

TJ − Temperature − °C

t

RU

/t

FU

− Rise and Fall Time − ns

TPS28225

SLUS710 – MAY 2006

TYPICAL CHARACTERISTICS (continued)

UGATE DC OUTPUT IMPEDANCE LGATE DC OUTPUT IMPEDANCE

vs vs

TEMPERATURE, (V

DD

= 7.2 V) TEMPERATURE (V

DD

= 7.2 V)

Figure 5. Figure 6.

UGATE RISE AND FALL TIME LGATE RISE AND FALL TIME

vs vs

TEMPERATURE (V

DD

= 7.2 V, C

LOAD

= 3 nF) TEMPERATURE (V

DD

= 7.2 V, C

LOAD

= 3 nF)

Figure 7. Figure 8.

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