Texas Instruments TPS22966TDPURQ1 Schematic [ru]

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Supply

or

Dual

DC/DC

converter

OFF

ON

TPS22966-Q1

VIN1

VOUT1

R

L

C

L

GND

ON1

CT1

C

IN

OFF

ON

VIN2 VOUT2

C

L

GND

ON2

GND

C

IN

CT2

VBIAS

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TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

TPS22966-Q1 Dual-Channel, Ultralow Resistance Load Switch

1 Features 2 Applications

1

• Qualified for Automotive Applications

• AEC-Q100 Qualified With the Following Results: • ADAS (Advanced Driver Assistance Systems)
– Device Temperature Grade 2: –40°C to 105°C

Ambient Operating Temperature Range
– Device HBM ESD Classification Level H1C
– Device CDM ESD Classification Level C6

• Integrated Dual-Channel Load Switch

• Input Voltage Range: 0.8 V to 5.5 V

• Ultralow ON-Resistance (RON)
– RON= 16 mΩ at VIN= 5 V (V
– RON= 16 mΩ at VIN= 3.3 V (V
– RON= 16 mΩ at VIN= 1.8 V (V

BIAS

BIAS
BIAS

= 5 V)

= 5 V)
= 5 V)

• 4-A Maximum Continuous Switch Current per
Channel

• Low Quiescent Current
– 80 µA (Both Channels)
– 80 µA (Single Channel)

• Low Control Input Threshold Enables Use of

1.2-V, 1.8-V, 2.5-V, and 3.3-V Logic

• Configurable Rise Time

• Quick Output Discharge (QOD)

• SON 14-Pin Package With Thermal Pad

• Infotainment

3 Description

The TPS22966-Q1 device is a small, ultralow RON,
dual-channel load switch with adjustable rise time.
The device contains two N-channel MOSFETs that
can operate over an input voltage range of 0.8 V to

5.5 V and can support a maximum continuous current
of up to 4 A per channel. Each switch is
independently controlled by an on/off input (ON1 and
ON2), which can interface directly with low-voltage
control signals. The TPS22966-Q1 includes a 230-Ω
on-chip resistor for quick output discharge when the
switch is turned off.

The TPS22966-Q1 is available in a small, space­saving 2-mm × 3-mm 14-SON package (DPU) with
integrated thermal pad allowing for high power
dissipation. The device is characterized for operation
over the free-air temperature range of –40°C to
105°C.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS22966-Q1 WSON (14) 3.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at

the end of the datasheet.

(1)

Typical Application Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

www.ti.com

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics: V

6.6 Electrical Characteristics: V

6.7 Switching Characteristics.......................................... 7

6.8 Typical Characteristics.............................................. 8

= 5 V ...................... 5

BIAS

= 2.5 V ................... 6

BIAS

7 Parameter Measurement Information................ 13

8 Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram....................................... 14

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 15

9 Application and Implementation........................ 16

9.1 Application Information............................................ 16

9.2 Typical Application ................................................. 18

10 Power Supply Recommendations ..................... 20

11 Layout................................................................... 20

11.1 Layout Guidelines ................................................. 20

11.2 Layout Example .................................................... 21

12 Device and Documentation Support ................. 22

12.1 Trademarks........................................................... 22

12.2 Electrostatic Discharge Caution............................ 22

12.3 Glossary................................................................ 22

13 Mechanical, Packaging, and Orderable

Information........................................................... 22

4 Revision History

Changes from Original (December 2013) to Revision A Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966-Q1

Top View

Bottom View

1

VIN1

VIN1

ON

VBIAS

VIN2

VIN2

1

ON

2

VOUT2

VOUT1

CT

GND

1

CT

2

VOUT2

VOUT1

14

14

1

VOUT2

VOUT1

GND

CT

1

CT

2

VOUT2

VOUT1

VIN1

VIN1

VBIAS

VIN2

VIN2

ON

1

ON

2

TPS22966-Q1

www.ti.com

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

5 Pin Configuration and Functions

DPU Package
14-Pin WSON

Pin Functions

PIN

NO. NAME

1 VIN1 I Switch 1 input. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during

2 VIN1 I Switch 1 input. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during

3 ON1 I Active high switch 1 control input. Do not leave floating.
4 VBIAS I Bias voltage. Power supply to the device. See Application Information for more information.
5 ON2 I Active high switch 2 control input. Do not leave floating.
6 VIN2 I Switch 2 input. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during

7 VIN2 I Switch 2 input. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during

8 VOUT2 O Switch 2 output.
9 VOUT2 O Switch 2 output.
10 CT2 O Switch 2 slew rate control. Can be left floating. Capacitor used on this pin should be rated for a minimum of 25

11 GND – Ground
12 CT1 O Switch 1 slew rate control. Can be left floating. Capacitor used on this pin should be rated for a minimum of 25

13 VOUT1 O Switch 1 output.
14 VOUT1 O Switch 1 output.
15 Thermal Pad O Thermal pad (exposed center pad) to alleviate thermal stress. Tie to GND. See Layout Guidelines for layout

I/O DESCRIPTION

turnon of the channel. See Application Information section for more information.

turnon of the channel. See Application Informationfor more information.

turnon of the channel. See Application Information for more information.

turnon of the channel. See Application Information for more information.

V for desired rise time performance.

V for desired rise time performance.

guidelines.

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

V
V
V
V
I

MAX

I

PLS

T
T
T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

(2) All voltage values are with respect to network ground terminal.

Input voltage –0.3 6 V

IN1,2

Output voltage –0.3 6 V

OUT1,2

ON-pin voltage –0.3 6 V

ON1,2

VBIAS voltage –0.3 6 V

BIAS

Maximum continuous switch current per channel 4 A
Maximum pulsed switch current per channel, pulse <300 µs, 2% duty cycle 6 A
Maximum junction temperature 150 °C

J

Maximum lead temperature (10-s soldering time) 300 °C

LEAD

Storage temperature –65 150 °C

STG

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Electrostatic discharge V

(ESD)

Charged-device model (CDM), per JEDEC specification JESD22- ±1500

(2)

C101

(1) (2)

MIN MAX UNIT

VALUE UNIT

(1)

±4000

6.3 Recommended Operating Conditions

MIN MAX UNIT

V

IN1,2

V

BIAS

V

ON1,2

V

OUT1,2

V

IH

V

IL

C

IN1,2

T

A

(1) Refer to Application Information.
(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

Input voltage range 0.8 V
Bias voltage range 2.5 5.5 V
ON voltage range 0 5.5 V
Output voltage range V
High-level input voltage, ON V
Low-level input voltage, ON V
Input capacitor 1
Operating free-air temperature

have to be derated. Maximum ambient temperature [T
maximum power dissipation of the device in the application [P
in the application (θJA), as given by the following equation: T

= 2.5 V to 5.5 V 1.2 5.5 V

BIAS

= 2.5 V to 5.5 V 0 0.5 V

BIAS

(2)

] is dependent on the maximum operating junction temperature [T

A(max)

], and the junction-to-ambient thermal resistance of the part/package

D(max)

A(max)

= T

J(max)

– (θJA× P

D(max)

)

–40 105 °C

(1)

BIAS

IN

J(max)

V

V

µF

], the

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SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

6.4 Thermal Information

TPS22966-Q1

THERMAL METRIC

θ

θ

θ

ψ

ψ

θ

JA
JCtop
JB

JT
JB

JCbot

Junction-to-ambient thermal resistance 52.3
Junction-to-case (top) thermal resistance 45.9
Junction-to-board thermal resistance 11.5
Junction-to-top characterization parameter 0.8
Junction-to-board characterization parameter 11.4
Junction-to-case (bottom) thermal resistance 6.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(1)

DPU (WSON) UNIT

14 PINS

°C/W

6.5 Electrical Characteristics: V

BIAS

= 5 V

Unless otherwise noted, the specifications apply over the operating ambient temperature, –40°C ≤ TA≤ 105°C (full) and V
= 5 V. Typical values are for TA= 25°C (unless otherwise noted).

PARAMETER TEST CONDITIONS T

POWER SUPPLIES AND CURRENTS

V

quiescent current (both

I

IN(VBIAS-ON)

I

IN(VBIAS-ON)

I

IN(VBIAS-OFF)VBIAS

I

IN(VIN-OFF)

I

ON

BIAS

channels)
V

quiescent current (single

BIAS

channel)

shutdown current V

V

off-state supply current

IN1,2

(per channel)

ON pin input leakage current VON= 5.5 V –40°C to 105°C 1 µA

RESISTANCE CHARACTERISTICS

R

ON

R

PD

ON-state resistance (per
channel)

Output pulldown resistance –40°C to 105°C 230 330 Ω

I

= I

OUT2

= V

ON1,2

= I

OUT2

= V

ON1

= 0 V, V

= 0 V,

= 0 V

= 0 mA,

= V

BIAS

= 0 mA, V

= V

= 5 V

BIAS

= 0 V –40°C to 105°C 2 µA

OUT1,2

V

IN1,2

V

IN1,2

V

IN1,2

V

IN1,2

OUT1

V

IN1,2

I

OUT1

V

IN1,2
ON1,2

V

ON1,2

V

OUT1,2

VIN= 5 V –40°C to 85°C 21

VIN= 3.3 V –40°C to 85°C 21

VIN= 1.8 V –40°C to 85°C 21

I

= –200 mA,

OUT

V

= 5 V

BIAS

VIN= 1.5 V –40°C to 85°C 21

VIN= 1.2 V –40°C to 85°C 21

VIN= 0.8 V –40°C to 85°C 21

VIN= 5.0 V, VON= 0 V, I
15 mA

A

= 5 V

ON2

= 0 V

–40°C to 105°C 80 120 µA

–40°C to 105°C 80 120 µA

= 5 V 0.5 8
= 3.3 V 0.1 3
= 1.8 V 0.07 2

–40°C to 105°C µA

= 0.8 V 0.04 1

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

=

OUT

MIN TYP MAX UNIT

BIAS

mΩ

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6.6 Electrical Characteristics: V

BIAS

= 2.5 V

Unless otherwise noted, the specifications apply over the operating ambient temperature
–40°C ≤ TA≤ 105°C (full) and V

PARAMETER TEST CONDITIONS T

POWER SUPPLIES AND CURRENTS

V

quiescent current (both

I

IN(VBIAS-ON)

I

IN(VBIAS-ON)

I

IN(VBIAS-OFF)VBIAS

I

IN(VIN-OFF)

I

ON

RESISTANCE CHARACTERISTICS

R

ON

R

PD

BIAS

channels)
V

quiescent current (single

BIAS

channel)

shutdown current V

V

off-state supply current

IN1,2

(per channel)

ON pin input leakage current VON= 5.5 V –40°C to 105°C 1 µA

ON-state resistance VIN= 1.5 V –40°C to 85°C 24 mΩ

Output pulldown resistance VIN= 2.5 V, VON= 0 V, I

= 2.5 V. Typical values are for TA= 25°C (unless otherwise noted).

BIAS

A

I

= I

OUT2

= V

ON1,2

= I

OUT2

= V

ON1

= 0 V, V

= 0 V,

= 0 V

= 0 mA,

= V

= 2.5 V

BIAS

= 0 mA, V

= V

BIAS

OUT1,2

= 0 V

ON2

= 2.5 V
= 0 V –40°C to 105°C 2 µA

V

= 2.5 V 0.13 3

IN1,2

V

= 1.8 V 0.07 2

IN1,2

V

= 1.2 V 0.05 2

IN1,2

V

= 0.8 V 0.04 1

IN1,2

–40°C to 105°C 32 40 µA

–40°C to 105°C 32 40 µA

–40°C to 105°C µA

OUT1

V

IN1,2

I

OUT1

V

IN1,2
ON1,2

V

ON1,2

V

OUT1,2

25°C 21 24

VIN= 2.5 V –40°C to 85°C 27

–40°C to 105°C 29

25°C 19 22

VIN= 1.8 V –40°C to 85°C 25

–40°C to 105°C 27

25°C 18 21

I

= –200 mA,

OUT

V

= 2.5 V

BIAS

–40°C to 105°C 26

25°C 18 21

VIN= 1.2 V –40°C to 85°C 24

–40°C to 105°C 26

25°C 17 20

VIN= 0.8 V –40°C to 85°C 23

–40°C to 105°C 25

= 1 mA Full 280 330 Ω

OUT

MIN TYP MAX UNIT

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6.7 Switching Characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

VIN= VON= V

t
t
t
t
t

ON
OFF
R
F
D

Turnon time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 1559
Turnoff time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 6
V
V
ON delay time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 665

VIN= 0.8 V, VON= V

t
t
t
t
t

ON
OFF
R
F
D

Turnon time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 732
Turnoff time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 161
V
V
ON delay time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 544

VIN= 2.5 V, VON= 5 V, V

t
t
t
t
t

ON
OFF
R
F
D

Turnon time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 2410
Turnoff time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 7
V
V
ON delay time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 1181

VIN= 0.8 V, VON= 5 V, V

t
t
t
t
t

ON
OFF
R
F
D

Turnon time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 1575
Turnoff time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 124
V
V
ON delay time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 1089

= 5 V, TA= 25ºC (unless otherwise noted)

BIAS

rise time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 1991 µs

OUT

fall time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 2

OUT

= 5 V, TA= 25ºC (unless otherwise noted)

BIAS

rise time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 371 µs

OUT

fall time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 14

OUT

= 2.5 V, TA= 25ºC (unless otherwise noted)

BIAS

rise time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 2412 µs

OUT

fall time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 2

OUT

= 2.5 V, TA= 25ºC (unless otherwise noted)

BIAS

rise time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 927 µs

OUT

fall time RL= 10 Ω, CL= 0.1 µF, CT = 1000 pF 14

OUT

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

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12

13

14

15

16

17

18

19

20

21

22

-45 -20 5 30 55 80 105

R

ON

(m)

Temperature (ºC)

VIN = 0.8V
VIN = 1.2V
VIN = 1.5V
VIN = 2.5V
VIN = 3.3V
VIN = 5V

C006

V

BIAS

= 5V, I

OUT

= -200mA

12

14

16

18

20

22

24

26

28

-45 -20 5 30 55 80 105

R

ON

(m)

Temperature (ºC)

VIN = 0.8V
VIN = 1.2V
VIN = 1.5V
VIN = 1.8V
VIN = 2.5V

C005

V

BIAS

= 2.5V, I

OUT

= -200mA

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5

I

IN(VBIAS-OFF)

(µA)

V

BIAS

(V)

-40°C
25°C
105°C

C003

V

IN1=VIN2=VBIAS

, V

ON1

= V

ON2

= 0V, V

OUT

= 0V

0

0.05

0.1

0.15

0.2

0.25

0.3

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

I

IN(VIN-OFF)

(A)

VIN (V)

-40C

25C

105C

C004

V

BIAS

= 5V, V

ON

= 0V, V

OUT

= 0V

0

20

40

60

80

100

120

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5

I

IN(VBIAS-ON)

(µA)

V

BIAS

(V)

-40°C
25°C
105°C

C001

V

IN1

= V

IN2

= V

BIAS

, V

ON1

= V

ON2

= 5V, V

OUT

= Open

10

20

30

40

50

60

70

80

90

100

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5

I

IN(VBIAS-ON)

(µA)

V

BIAS

(V)

-40°C
25°C
105°C

C002

V

IN1

= V

IN2

= V

BIAS

, V

ON1

= V

ON2

= 5V, V

OUT

= Open

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

6.8 Typical Characteristics

www.ti.com

Figure 1. Quiescent Current vs. V

Figure 3. Shutdown Current vs. V

(Both Channels) Figure 2. Quiescent Current vs. V

BIAS

(Both Channels)

BIAS

Figure 4. Off-State VIN Current vs. VIN(Single Channel)

(Single Channel)

BIAS

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Figure 5. RONvs. Temperature (V

Channel)

= 2.5 V, Single

BIAS

Product Folder Links: TPS22966-Q1

Figure 6. RONvs. Temperature (V

= 5 V, Single Channel)

BIAS

0.0

0.5

1.0

1.5

2.0

2.5

0.5 1 1.5 2 2.5

V

OUT

(V)

VON (V)

VBIAS = 2.5V

VBIAS = 3.3V

VBIAS = 3.6V
VBIAS = 4.2V

VBIAS = 5V
VBIAS = 5.5V

C024

400

600

800

1000

1200

1400

1600

1800

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

D

(µs)

VIN (V)

-40°C

25°C
85°C

105°C

C012

V

BIAS

= 2.5V

CT = 1nF

18.5

19.0

19.5

20.0

20.5

21.0

21.5

22.0

22.5

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6

R

ON

(m)

VIN (V)

VBIAS = 2.5V VBIAS = 3.3V
VBIAS = 3.6V VBIAS = 4.2V
VBIAS = 5V VBIAS = 5.5V

C011

220

225

230

235

240

245

250

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

R

PD

()

VIN (V)

-40°C
25°C
105°C

C010

I

OUT

= 1mA, V

BIAS

= 5V, VON = 0V

10

12

14

16

18

20

22

24

26

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

R

ON

(m)

VIN (V)

-40°C
25°C
105°C

C007

V

BIAS

= 2.5V, I

OUT

= -200mA

12

13

14

15

16

17

18

19

20

21

22

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

R

ON

(m)

VIN (V)

-40°C
25°C

105°C

C008

V

BIAS

= 5V, I

OUT

= -200mA

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Typical Characteristics (continued)

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

Figure 7. RONvs. VIN(V

= 2.5 V, Single Channel) Figure 8. RONvs. VIN(V

BIAS

Figure 9. RONvs. VIN(TA= 25°C, Single Channel) Figure 10. RPDvs. VIN(V

= 5 V, Single Channel)

BIAS

= 5 V, Single Channel)

BIAS

Figure 11. V

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vs. VON(TA= 25°C, Single Channel) Figure 12. tDvs. VIN(V

OUT

Product Folder Links: TPS22966-Q1

= 2.5 V, CT = 1 nF)

BIAS

0

50

100

150

200

250

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

OFF

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C017

V

BIAS

= 5V, CT = 1nF

1000

1500

2000

2500

3000

3500

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

ON

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C018

V

BIAS

= 2.5V

CT = 1nF

0

5

10

15

20

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

F

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C015

V

BIAS

= 5V, CT = 1nF

0

20

40

60

80

100

120

140

160

180

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

OFF

(µs)

VIN (V)

-40°C
25°C
85°C

105°C

C016

V

BIAS

= 2.5V, CT = 1nF

300

400

500

600

700

800

900

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

D

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C013

V

BIAS

= 5V

CT = 1nF

0

2

4

6

8

10

12

14

16

18

20

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

F

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C014

V

BIAS

= 2.5V, CT = 1nF

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

Typical Characteristics (continued)

www.ti.com

Figure 13. tDvs. VIN(V

Figure 15. tFvs. VIN(V

= 5 V, CT = 1 nF)

BIAS

= 5 V, CT = 1 nF)

BIAS

Figure 14. tFvs. VIN(V

Figure 16. t

OFF

vs. VIN(V

= 2.5 V, CT = 1 nF)

BIAS

= 2.5 V, CT = 1 nF)

BIAS

Figure 17. t

10 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

OFF

vs. VIN(V

= 5 V, CT = 1 nF)

BIAS

Figure 18. tONvs. VIN(V

Product Folder Links: TPS22966-Q1

= 2.5 V, CT = 1 nF)

BIAS

250

750

1250

1750

2250

2750

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

R

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C021

V

BIAS

= 5V

CT = 1nF

500

1000

1500

2000

2500

3000

3500

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5

t

R

(µs)

V

BIAS

(V)

-40°C
25°C
85°C
105°C

C022

VIN = 2.5V
CT = 1nF

400

600

800

1000

1200

1400

1600

1800

2000

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

ON

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C019

V

BIAS

= 5V

CT = 1nF

500

1000

1500

2000

2500

3000

3500

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

R

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C020

V

BIAS

= 2.5V

CT = 1nF

www.ti.com

Typical Characteristics (continued)

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

Figure 19. tONvs. VIN(V

Figure 21. tRvs. VIN(V

= 5 V, CT = 1 nF)

BIAS

= 5 V, CT = 1 nF) Figure 22. tRvs. V

BIAS

6.8.1 Typical AC Scope Captures at TA= 25ºC, CT = 1 nF

Figure 20. tRvs. VIN(V

BIAS(VIN

= 2.5 V, CT = 1 nF)

BIAS

= 2.5 V, CT = 1 nF)

Figure 23. Turnon Response Time (VIN= 0.8 V, V

V, CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω) CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

= 2.5 Figure 24. Turnon Response Time (VIN= 0.8 V, V

BIAS

Product Folder Links: TPS22966-Q1

BIAS

= 5 V,

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

Typical AC Scope Captures at TA= 25ºC, CT = 1 nF (continued)

www.ti.com

Figure 25. Turnon Response Time (VIN= 2.5 V, V

V, CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω) CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

Figure 27. Turnoff Response Time (VIN= 0.8 V, V

V, CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω) CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

= 2.5 Figure 26. Turnon Response Time (VIN= 5 V, V

BIAS

= 2.5 Figure 28. Turnoff Response Time (VIN= 0.8 V, V

BIAS

BIAS

BIAS

= 5 V,

= 5 V,

Figure 29. Turnoff Response Time (VIN= 2.5 V, V

= 2.5 Figure 30. Turnoff Response Time (VIN= 5 V, V

BIAS

BIAS

= 5 V,

V, CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω) CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

12 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966-Q1

+

-

OFF

ON

TPS22966-Q1

VIN

VOUT

R

L

C

L

TEST CIRCUIT

GND

(A)

GND

ON

GND

CIN= 1µF

Single channel shown for clarity.

VBIAS

CT

t

R

t

F

t

ON

t

OFF

90% 90%

10% 10%

TIMING WAVEFORMS

(A) Control signal rise and fall times are 100 ns.

V

ON

V

OUT

V

OUT

50% 50%

50% 50%

t

D

10%

www.ti.com

7 Parameter Measurement Information

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

Figure 31. Test Circuit and Timing Waveforms

Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: TPS22966-Q1

Control

Logic

VIN1

ON1

VOUT1

GND

Charge Pump

Control

Logic

VIN2

ON2

VOUT2

CT1

CT2

VBIAS

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

www.ti.com

8 Detailed Description

8.1 Overview

The device is a dual-channel, 4-A automotive load switch in a 14-pin SON package. To reduce the voltage drop
in high current rails, the device implements a low-resistance N-channel MOSFET.

The device has a programmable slew rate for applications that require specific rise-time. The device has very low
leakage current during off state. This prevents downstream circuits from pulling high standby current from the
supply. Integrated control logic, driver, power supply, and output discharge FET eliminates the need for any
external components, which reduces solution size and bill of materials (BOM) count.

8.2 Functional Block Diagram

14 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966-Q1

SR 0.32 CT 13.7= ´ +

TPS22966-Q1

www.ti.com

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

8.3 Feature Description

8.3.1 Quick Output Discharge

Each channel of the TPS22966-Q1 includes a Quick Output Discharge (QOD) feature. When the switch is
disabled, a discharge resistor is connected between VOUT and GND. This resistor has a typical value of 230-Ω
and prevents the output from floating while the switch is disabled.

8.3.2 ON/OFF Control

The ON pins control the state of the switch. Asserting ON high enables the switch. ON is active high and has a
low threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard
GPIO logic threshold. It can be used with any microcontroller with 1.2-V or higher GPIO voltage. This pin cannot
be left floating and must be tied either high or low for proper functionality.

8.3.3 Adjustable Rise Time

A capacitor to GND on the CTx pins sets the slew rate for each channel. To ensure desired performance, a
capacitor with a minimum voltage rating of 25 V should be used on the CTx pin. An approximate formula for the
relationship between CTx and slew rate is (the equation below accounts for 10% to 90% measurement on V
and does NOT apply for CTx = 0 pF. Use Table 1 to determine rise times for when CTx = 0 pF):

where

• SR = slew rate (in µs/V)

• CT = the capacitance value on the CTx pin (in pF)

• The units for the constant 13.7 is in µs/V. (1)

Rise time can be calculated by multiplying the input voltage by the slew rate. Table 1 shows rise time values
measured on a typical device. Rise times shown below are only valid for the power-up sequence where VINand
V

are already in steady state condition, and the ON pin is asserted high.

BIAS

OUT

Table 1. Rise Time Values

RISE TIME (µs) 10% - 90%, CL= 0.1µF, CIN= 1µF, RL= 10Ω

CTx (pF)

5V 3.3V 1.8V 1.5V 1.2V 1.05V 0.8V

0 124 88 63 60 53 49 42
220 481 323 193 166 143 133 109
470 855 603 348 299 251 228 175

1000 1724 1185 670 570 469 411 342
2200 3328 2240 1308 1088 893 808 650
4700 7459 4950 2820 2429 1920 1748 1411

10000 16059 10835 6040 5055 4230 3770 3033

TYPICAL VALUES at 25°C, V

= 5V, 25V X7R 10% CERAMIC CAP

BIAS

8.4 Device Functional Modes

Table 2. Functional Table

ONx VINx to VOUTx VOUTx to GND

L Off On

H On Off

Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS22966-Q1

15

20

25

30

35

40

45

50

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6

R

ON

(m)

VIN (V)

VBIAS = 2.5V

VBIAS = 3.3V

VBIAS = 3.6V

VBIAS = 4.2V

VBIAS = 5V

VBIAS = 5.5V

C023

Temperature = 25£C, I

OUT

= -200mA

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

www.ti.com

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor, a capacitor needs to be placed between VIN and GND. A 1-µF ceramic capacitor, CIN,
placed close to the pins, is usually sufficient. Higher values of CINcan be used to further reduce the voltage drop
in high-current application. When switching heavy loads, it is recommended to have an input capacitor about 10
times higher than the output capacitor to avoid excessive voltage drop.

9.1.2 Output Capacitor (Optional)

Due to the integrated body diode in the NMOS switch, a CINgreater than CLis highly recommended. A C
greater than CINcan cause V
flow through the body diode from VOUT to VIN. A CINto CLratio of 10 to 1 is recommended for minimizing V
dip caused by inrush currents during start-up, however a 10 to 1 ratio for capacitance is not required for proper
functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more VINdip upon
turnon due to inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer rise
time (see Adjustable Rise Time).

to exceed VINwhen the system supply is removed. This could result in current

OUT

L

IN

9.1.3 VINand V

Voltage Range

BIAS

For optimal RONperformance, make sure VIN≤ V
exhibit RONgreater than what is listed in Electrical Characteristics. See Figure 32 for an example of a typical
device. Notice the increasing RONas VINexceeds V

16 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

. The device will still be functional if VIN> V

BIAS

voltage.

BIAS

Figure 32. RONvs. VIN(Single Channel)

Product Folder Links: TPS22966-Q1

BIAS

but it will

0.00

1.00

2.00

3.00

4.00

5.00

-40 -15 10 35 60 85 110

Continuous Current (A)

Ambient Temperature (°C)

100% On time

75% On time

12.5% On time

C002

VBIAS = 5.0 V

TPS22966-Q1

www.ti.com

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

Application Information (continued)

9.1.4 Safe Operating Area (SOA)

The SOA curves in Figure 33 show the continuous current carrying capability of the device versus ambient
temperature (TA) to ensure reliable operation over 100,000 hours of device lifetime. Each curve represents a
specific percent of time that the switch is on.

The 100% curve represents use for a full 24 hours in a day. The 75% curve indicates 18 hours of use in a day
while the 12.5% curve shows 3 hours of use per day.

Examples on how to use this plot:

• The application has an ambient temperature of 60°C and the switch will be on 100% of the time. The
maximum continuous current that can be applied is approximately 2.1 A.

• The application requires the switch to be on 12.5% of the time and the current while on will be 3 A. The
maximum ambient temperature is approximately 100°C.

• The application requires 2 A and will be operated at 70°C. The switch can be on for a maximum of 75% of the
time.

• It is expected that most applications will not have specific use cases as defined in the examples above.
Different use cases can be combined to generate a more complete view of a specific application. This
example shows use under various conditions simplified to an average use case. The application requires
operation at 4 A for 25% of the time, 1 A for 25% of the time and is off the remaining 50% of the time.
Ambient temperature will vary from 25°C to 50°C. Will there be any limitations? The average current can be
calculated as (4 A × 25% + 1 A * 25% + 0 A * 50%). The average current calculates to be 1.25 A. Assuming
worst case temperature of 50°C, the resulting application is within the safe operating area.

Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Figure 33. Safe Operating Area

Product Folder Links: TPS22966-Q1

Dual

Power

Supply

or

Dual

DC/DC

converter

OFF

ON

TPS22966-Q1

VIN1

VOUT1

R

L

C

L

GND

ON1

CT1

C

IN

OFF

ON

VIN2 VOUT2

C

L

GND

ON2

GND

C

IN

CT2

VBIAS

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

9.2 Typical Application

Figure 34. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 3 as the input parameters.

www.ti.com

Table 3. Design Parameters

DESIGN PARAMETER VALUE

Input voltage 3.3 V

Bias voltage 5 V

Load capacitance (CL) 22 µF

Maximum acceptable inrush current 400 mA

9.2.2 Detailed Design Procedure

When the switch is enabled, the output capacitors must be charged up from 0 V to the set value (3.3 V in this
example). This charge arrives in the form of inrush current. Inrush current can be calculated using Equation 2:

Inrush Current = C × dV/dt

where

• C = output capacitance

• dV = output voltage

• dt = rise time (2)

The TPS22966-Q1 offers adjustable rise time for VOUT. This feature allows the user to control the inrush current
during turnon. The appropriate rise time can be calculated using Table 3 and the inrush current equation.

400 mA = 22 μF × 3.3 V/dt (3)
dt = 181.5 μs (4)

To ensure an inrush current of less than 400 mA, choose a CT value that will yield a rise time of more than 181.5
μs. See the oscilloscope captures in for an example of how the CT capacitor can be used to reduce inrush
current.

18 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966-Q1

www.ti.com

9.2.3 Application Curves

V

= 5 V ; VIN= 3.3 V ; CL= 22 μF

BIAS

Figure 35. Inrush Current With CT = 0 pF Figure 36. Inrush Current With CT = 220 pF

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: TPS22966-Q1

J(max) A

D(max)

JA

T T

-

=

θ

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

www.ti.com

10 Power Supply Recommendations

The device is designed to operate from a VBIAS range of 2.5 V to 5.5 V and a VIN voltage range of 0.8 V to 5.5
V. The power supply should be well regulated and placed as close to the device terminals as possible. It must be
able to withstand all transient and load current steps. In most situations, using an input capacitance of 1 uF is
sufficient to prevent the supply voltage from dipping when the switch is turned on. In cases where the power
supply is slow to respond to a large transient current or large load current step, additional bulk capacitance may
be required on the input.

The requirements for larger input capacitance can be mitigated by adding additional capacitance to the CT pin.
This will cause the load switch to turn on more slowly. Not only will this reduce transient inrush current, but it will
also give the power supply more time to respond to the load current step.

11 Layout

11.1 Layout Guidelines

For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects
along with minimizing the case to ambient thermal impedance.

The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. To
calculate the maximum allowable power dissipation, P
use the following equation:

for a given output current and ambient temperature,

D(max)

where

• P

• T

• TA= ambient temperature

• ΘJA= junction to air thermal impedance. See Thermal Information section. This parameter is highly dependent

= maximum allowable power dissipation

D(max)

= maximum allowable junction temperature (150°C for the TPS22966-Q1)

J(max)

upon board layout. (5)

Figure 37 shows an example of a layout. Notice the thermal vias located under the exposed thermal pad of the

device. This allows for thermal diffusion away from the device.

20 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966-Q1

CT1 capacitor

CT2 capacitor

VIN1 capacitor

VOUT1 capacitor

VIN2 capacitor

VOUT2 capacitor

Thermal

relief vias

www.ti.com

11.2 Layout Example

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

Figure 37. Layout Example

Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: TPS22966-Q1

TPS22966-Q1

SLVSC71A –DECEMBER 2013–REVISED MARCH 2015

www.ti.com

12 Device and Documentation Support

12.1 Trademarks

All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

22 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

19-Feb-2015

PACKAGING INFORMATION

Orderable Device Status

TPS22966TDPURQ1 ACTIVE WSON DPU 14 3000 Green (RoHS

TPS22966TDPUTQ1 ACTIVE WSON DPU 14 250 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 966TQ1

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 966TQ1

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS22966-Q1 :

Catalog: TPS22966

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

19-Feb-2015

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Feb-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

TPS22966TDPURQ1 WSON DPU 14 3000 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
TPS22966TDPUTQ1 WSON DPU 14 250 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Feb-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS22966TDPURQ1 WSON DPU 14 3000 210.0 185.0 35.0
TPS22966TDPUTQ1 WSON DPU 14 250 210.0 185.0 35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
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