Texas Instruments TPS22966DPUR Schematic [ru]

Dual

Power

Supply

or

Dual

DC/DC

converter

OFF

ON

TPS22966

V

IN1

V

OUT1

R

L

C

L

GND

ON1

CT1

C

IN

OFF

ON

V

IN2

V

OUT2

C

L

GND

ON2

GND

C

IN

CT2

V

BIAS

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TPS22966 5.5-V, 6-A, 16-mΩ ON-Resistance Dual-Channel Load Switch

1 Features 3 Description

1

• Input Voltage Range: 0.8 V to 5.5 V

• Integrated Dual-Channel Load Switch

• ON-Resistance
– RON= 16 mΩ at VIN= 5 V (V
– RON= 16 mΩ at VIN= 3.6 V (V
– RON= 16 mΩ at VIN= 1.8 V (V

BIAS

BIAS
BIAS

= 5 V)

= 5 V)
= 5 V)

• 6-A Maximum Continuous Switch Current per
Channel

• Low Quiescent Current
– 80 µA (Both Channels)
– 60 µA (Single Channel)

• Low Control Input Threshold Enables Use of

1.2-V, 1.8-V, 2.5-V, and 3.3-V Logic

• Configurable Rise Time

• Quick Output Discharge (QOD)

• SON 14-Pin Package With Thermal Pad

• ESD Performance Tested per JESD 22
– 2-kV HBM and 1-kV CDM

The TPS22966 is a small, low RON, dual-channel load
switch with controlled turnon. The device contains two
N-channel MOSFETs that can operate over an input
voltage range of 0.8 V to 5.5 V and can support a
maximum continuous current of 6 A per channel.
Each switch is independently controlled by an on/off
input (ON1 and ON2), which can interface directly
with low-voltage control signals. In TPS22966, a 220­Ω on-chip load resistor is added for quick output
discharge when switch is turned off.

The TPS22966 is available in a small, space-saving
2-mm × 3-mm 14-SON package (DPU) with
integrated thermal pad allowing for high power
dissipation. The device is characterized for operation
over the free-air temperature range of –40°C to
105°C.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS22966 WSON (14) 3.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

(1)

2 Applications

• Ultrabook™

• Notebooks and Netbooks

• Tablet PCs

• Consumer Electronics

• Set-top Boxes and Residental Gateways

• Telecom Systems

• Solid-State Drives (SSD)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Application Circuit

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

www.ti.com

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics (V

6.6 Electrical Characteristics (V

6.7 Switching Characteristics.......................................... 7

6.8 Typical Characteristics.............................................. 8

6.9 Typical AC Characteristics...................................... 12

= 5.0 V).................. 5

BIAS

= 2.5 V).................. 6

BIAS

7 Parameter Measurement Information ................ 13

8 Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram....................................... 14

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 16

9 Application and Implementation ........................ 17

9.1 Application Information............................................ 17

9.2 Typical Application .................................................. 17

10 Power Supply Recommendations..................... 18

11 Layout................................................................... 19

11.1 Layout Guidelines ................................................. 19

11.2 Layout Example .................................................... 19

11.3 Power Dissipation ................................................. 19

12 Device and Documentation Support................. 20

12.1 Trademarks........................................................... 20

12.2 Electrostatic Discharge Caution............................ 20

12.3 Glossary................................................................ 20

13 Mechanical, Packaging, and Orderable

Information........................................................... 20

4 Revision History

Changes from Revision D (January 2015) to Revision E Page

• Added temperature operating ranges to Electrical Characteristics (V

• Added temperature operating ranges to Electrical Characteristics (V

• Updated graphics in the Typical Characteristics section........................................................................................................ 8

= 5.0 V) table....................................................... 5

BIAS

= 2.5 V) table....................................................... 6

BIAS

Changes from Revision C (June 2013) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

Changes from Revision B (December 2012) to Revision C Page

• Added VBIAS to ABSOLUTE MAXIMUM RATINGS table..................................................................................................... 4

• Updated SWITCHING CHARACTERISTIC MEASUREMENT INFORMATION. ................................................................... 7

• Updated Test Circuit Diagram .............................................................................................................................................. 13

• Updated Functional Block Diagram. .................................................................................................................................... 14

Changes from Revision A (July 2012) to Revision B Page

• Updated Application Schematic. ............................................................................................................................................ 1

2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966

Top View

Bottom View

1

VIN1

VIN1

ON

VBIAS

VIN2

VIN2

1

ON

2

VOUT2

VOUT1

CT

GND

1

CT

2

VOUT2

VOUT1

14

14

1

VOUT2

VOUT1

GND

CT

1

CT

2

VOUT2

VOUT1

VIN1

VIN1

VBIAS

VIN2

VIN2

ON

1

ON

2

www.ti.com

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

5 Pin Configuration and Functions

DPU Package
14-Pin WSON

Pin Functions

PIN

NAME NO.

VIN1 1 I Switch 1 input. Recommended voltage range for this pin for optimal RONperformance is 0.8 V to

VIN1 2 I Switch 1 input. Recommended voltage range for this pin for optimal RONperformance is 0.8 V to

ON1 3 I Active high switch 1 control input. Do not leave floating.
VBIAS 4 I Bias voltage. Power supply to the device. Recommended voltage range for this pin is 2.5 V to 5.5 V.

ON2 5 I Active high switch 2 control input. Do not leave floating.
VIN2 6 I Switch 2 input. Recommended voltage range for this pin for optimal RONperformance is 0.8V to

VIN2 7 I Switch 2 input. Recommended voltage range for this pin for optimal RONperformance is 0.8 V to

VOUT2 8 O Switch 2 output.
VOUT2 9 O Switch 2 output.
CT2 10 O Switch 2 slew rate control. Can be left floating. Capacitor used on this pin should be rated for a

GND 11 – Ground
CT1 12 O Switch 1 slew rate control. Can be left floating. Capacitor used on this pin should be rated for a

VOUT1 13 O Switch 1 output.
VOUT1 14 O Switch 1 output.
Thermal Pad – – Thermal pad (exposed center pad) to alleviate thermal stress. Tie to GND. See Layout for layout

I/O DESCRIPTION

V

. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during

BIAS

turn-on of the channel. See Application Information for more information.

V

. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during

BIAS

turn-on of the channel. See Application Information for more information.

See Application Information .

V

. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during

BIAS

turn-on of the channel. See Application Information for more information.

V

. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during

BIAS

turn-on of the channel. See Application Information for more information.

minimum of 25 V for desired rise time performance.

minimum of 25 V for desired rise time performance.

guidelines.

TPS22966

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

V
V
V
V
I

MAX

I

PLS

T
T
T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

(2) All voltage values are with respect to network ground terminal.

Input voltage –0.3 6 V

IN1,2

Output voltage –0.3 6 V

OUT1,2

ON-pin voltage –0.3 6 V

ON1,2

V

BIAS

voltage –0.3 6 V

BIAS

Maximum continuous switch current per channel 6 A
Maximum pulsed switch current per channel, pulse <300 µs, 2% duty cycle 8 A
Maximum junction temperature 125 °C

J

Maximum lead temperature (10-s soldering time) 300 °C

LEAD

Storage temperature –65 150 °C

stg

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

V

(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101

(1)

MIN MAX UNIT

(2)

VALUE UNIT

(1)

±2000
±1000

6.3 Recommended Operating Conditions

MIN MAX UNIT

V

IN1,2

V

BIAS

V

ON1,2

V

OUT1,2

V

IH

V

IL

C

IN1,2

T

A

(1) Refer to Input Capacitor (Optional) .
(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

Input voltage range 0.8 V
Bias voltage range 2.5 5.5 V
ON voltage range 0 5.5 V
Output voltage range V
High-level input voltage, ON V
Low-level input voltage, ON V
Input capacitor 1
Operating free-air temperature

have to be derated. Maximum ambient temperature [T
maximum power dissipation of the device in the application [P
in the application (θJA), as given by the following equation: TA

= 2.5 V to 5.5 V 1.2 5.5 V

BIAS

= 2.5 V to 5.5 V 0 0.5 V

BIAS

(2)

] is dependent on the maximum operating junction temperature [T

A(max)

], and the junction-to-ambient thermal resistance of the part/package

D(max)
(max)

= T

J(max)

– (θJA× P

D(max)

)

(1)

-40 105 °C

BIAS

V

V

IN

µF

], the

J(max)

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6.4 Thermal Information

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 52.3
Junction-to-case (top) thermal resistance 45.9
Junction-to-board thermal resistance 11.5
Junction-to-top characterization parameter 0.8
Junction-to-board characterization parameter 11.4
Junction-to-case (bottom) thermal resistance 6.9

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

TPS22966

THERMAL METRIC DPU UNIT

14 PINS

°C/W

6.5 Electrical Characteristics (V

BIAS

= 5.0 V)

Unless otherwise noted, the specification in the following table applies where V
(unless otherwise noted)

PARAMETER TEST CONDITIONS T

POWER SUPPLIES AND CURRENTS

I

= I

V

quiescent current (both

I

IN(VBIAS-ON)

I

IN(VBIAS-ON)

I

IN(VBIAS-OFF)VBIAS

I

IN(VIN-OFF)

I

ON

BIAS

channels)
V

quiescent current (single

BIAS

channel)

shutdown current V

V

off-state supply current (per

IN1,2

channel)

ON pin input leakage current VON= 5.5 V –40°C to 105°C 1 µA

RESISTANCE CHARACTERISTICS

R

ON

R

PD

ON-state resistance (per channel)

Output pulldown resistance VIN= 5.0 V, VON= 0 V, I

OUT1

V

IN1,2

I

OUT1

V

IN1,2
ON1,2

V

ON1,2

V

OUT1,2

I

= –200 mA,

OUT

V

BIAS

OUT2

= V

ON1,2

= I

OUT2

= V

ON1

= 0 V, V

= 0 V,

= 0 V

= 5.0 V

= 0 mA,

= V

= 5.0 V

BIAS

= 0 mA, V

= V

BIAS

OUT1,2

= 0 V

ON2

= 5.0 V
= 0 V –40°C to 105°C 2 µA

V

= 5.0 V –40°C to 105°C 0.5 8

IN1,2

V

= 3.3 V –40°C to 105°C 0.1 3

IN1,2

V

= 1.8 V –40°C to 105°C 0.07 2

IN1,2

V

= 0.8 V –40°C to 105°C 0.04 1

IN1,2

VIN= 5.0 V –40°C to 85°C 21

VIN= 3.3 V –40°C to 85°C 21

VIN= 1.8 V –40°C to 85°C 21 mΩ

VIN= 1.5 V –40°C to 85°C 21

VIN= 1.2 V –40°C to 85°C 21

VIN= 0.8 V –40°C to 85°C 21

= 15 mA

OUT

= 5.0 V. Typical values are for TA= 25°C.

BIAS

A

MIN TYP MAX UNIT

–40°C to 105°C 80 120 µA

–40°C to 105°C 60 120 µA

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

25°C 16 19

–40°C to 105°C 23

–40°C to 85°C 220 300 Ω

–40°C to 105°C 330

µA

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6.6 Electrical Characteristics (V

BIAS

= 2.5 V)

Unless otherwise noted, the specification in the following table applies where V
(unless otherwise noted)

PARAMETER TEST CONDITIONS T

POWER SUPPLIES AND CURRENTS

I

= I

V

quiescent current (both

I

IN(VBIAS-ON)

I

IN(VBIAS-ON)

I

IN(VBIAS-OFF)VBIAS

I

IN(VIN-OFF)

I

ON

BIAS

channels)
V

quiescent current (single

BIAS

channel)

shutdown current V

V

off-state supply current (per

IN1,2

channel)

ON pin input leakage current VON= 5.5 V –40°C to 105°C 1 µA

RESISTANCE CHARACTERISTICS

R

ON

R

PD

ON-state resistance VIN= 1.5 V –40°C to 85°C 24 mΩ

Output pulldown resistance VIN= 2.5 V, VON= 0 V, I

OUT1

V

IN1,2

I

OUT1

V

IN1,2
ON1,2

V

ON1,2

V

OUT1,2

I

= –200 mA,

OUT

V

BIAS

OUT2

= V

ON1,2

= I

OUT2

= V

ON1

= 0 V, V

= 0 V,

= 0 V

= 2.5 V

= 0 mA,

= V

= 2.5 V

BIAS

= 0 mA, V

= V

BIAS

OUT1,2

= 0 V

ON2

= 2.5 V
= 0 V –40°C to 105°C 2 µA

V

= 2.5 V –40°C to 105°C 0.13 3

IN1,2

V

= 1.8 V –40°C to 105°C 0.07 2

IN1,2

V

= 1.2 V –40°C to 105°C 0.05 2

IN1,2

V

= 0.8 V –40°C to 105°C 0.04 1

IN1,2

VIN= 2.5 V –40°C to 85°C 27

VIN= 1.8 V –40°C to 85°C 25

VIN= 1.2 V –40°C to 85°C 24

VIN= 0.8 V –40°C to 85°C 23

= 1 mA Ω

OUT

= 2.5 V. Typical values are for TA= 25°C

BIAS

A

MIN TYP MAX UNIT

–40°C to 85°C 32 37

–40°C to 105°C 40
–40°C to 105°C 23 40 µA

25°C 21 24

–40°C to 105°C 29

25°C 19 22

–40°C to 105°C 27

25°C 18 21

–40°C to 105°C 26

25°C 18 21

–40°C to 105°C 26

25°C 17 20

–40°C to 105°C 25

–40°C to 85°C 260 300

–40°C to 105°C 330

µA

µA

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6.7 Switching Characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

VIN= VON= V

t
t
t
t
t

ON
OFF
R
F
D

Turn-on time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 1310
Turn-off time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 6
V
V
ON delay time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 460

VIN= 0.8 V, VON= V

t
t
t
t
t

ON
OFF
R
F
D

Turn-on time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 550
Turn-off time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 170
V
V
ON delay time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 400

VIN= 2.5 V, VON= 5 V, V

t
t
t
t
t

ON
OFF
R
F
D

Turn-on time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 2050
Turn-off time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 5
V
V
ON delay time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 990

VIN= 0.8 V, VON= 5 V, V

t
t
t
t
t

ON
OFF
R
F
D

Turn-on time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 1300
Turn-off time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 130
V
V
ON delay time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 870

= 5 V, TA= 25ºC (unless otherwise noted)

BIAS

rise time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 1720 µs

OUT

fall time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 2

OUT

= 5 V, TA= 25ºC (unless otherwise noted)

BIAS

rise time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 325 µs

OUT

fall time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 16

OUT

= 2.5 V, TA= 25ºC (unless otherwise noted)

BIAS

rise time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 2275 µs

OUT

fall time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 2.5

OUT

= 2.5 V, TA= 25ºC (unless otherwise noted)

BIAS

rise time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 875 µs

OUT

fall time RL= 10 Ω, CL= 0.1 µF, CT= 1000 pF 16

OUT

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12

13

14

15

16

17

18

19

20

21

22

-45 -20 5 30 55 80 105

R

ON

(m)

Temperature (ºC)

VIN = 0.8V
VIN = 1.2V
VIN = 1.5V
VIN = 2.5V
VIN = 3.3V
VIN = 5V

C006

V

BIAS

= 5V, I

OUT

= -200mA

12

14

16

18

20

22

24

26

28

-45 -20 5 30 55 80 105

R

ON

(m)

Temperature (ºC)

VIN = 0.8V
VIN = 1.2V
VIN = 1.5V
VIN = 1.8V
VIN = 2.5V

C005

V

BIAS

= 2.5V, I

OUT

= -200mA

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5

I

IN(VBIAS-OFF)

(µA)

V

BIAS

(V)

-40°C
25°C
105°C

C003

V

IN1=VIN2=VBIAS

, V

ON1

= V

ON2

= 0V, V

OUT

= 0V

0

0.05

0.1

0.15

0.2

0.25

0.3

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

I

IN(VIN-OFF)

(A)

VIN (V)

-40C

25C

105C

C004

V

BIAS

= 5V, V

ON

= 0V, V

OUT

= 0V

0

20

40

60

80

100

120

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5

I

IN(VBIAS-ON)

(µA)

V

BIAS

(V)

-40°C
25°C
105°C

C001

V

IN1

= V

IN2

= V

BIAS

, V

ON1

= V

ON2

= 5V, V

OUT

= Open

10

20

30

40

50

60

70

80

90

100

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5

I

IN(VBIAS-ON)

(µA)

V

BIAS

(V)

-40°C
25°C
105°C

C002

V

IN1

= V

IN2

= V

BIAS

, V

ON1

= V

ON2

= 5V, V

OUT

= Open

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

6.8 Typical Characteristics

www.ti.com

Figure 1. Quiescent Current vs. V

Figure 3. Shutdown Current vs. V

(Both Channels) Figure 2. Quiescent Current vs. V

BIAS

(Both Channels)

BIAS

Figure 4. Off-State VIN Current vs. VIN(Single Channel)

(Single Channel)

BIAS

8 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Figure 5. RONvs. Temperature (V

Channel)

= 2.5 V, Single

BIAS

Figure 6. RONvs. Temperature (V

Product Folder Links: TPS22966

= 5 V, Single Channel)

BIAS

0.0

0.5

1.0

1.5

2.0

2.5

0.5 1 1.5 2 2.5

V

OUT

(V)

VON (V)

VBIAS = 2.5V

VBIAS = 3.3V

VBIAS = 3.6V
VBIAS = 4.2V

VBIAS = 5V
VBIAS = 5.5V

C024

400

600

800

1000

1200

1400

1600

1800

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

D

(µs)

VIN (V)

-40°C

25°C
85°C

105°C

C012

V

BIAS

= 2.5V

CT = 1nF

18.5

19.0

19.5

20.0

20.5

21.0

21.5

22.0

22.5

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6

R

ON

(m)

VIN (V)

VBIAS = 2.5V VBIAS = 3.3V
VBIAS = 3.6V VBIAS = 4.2V
VBIAS = 5V VBIAS = 5.5V

C011

220

225

230

235

240

245

250

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

R

PD

()

VIN (V)

-40°C
25°C
105°C

C010

I

OUT

= 1mA, V

BIAS

= 5V, VON = 0V

10

12

14

16

18

20

22

24

26

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

R

ON

(m)

VIN (V)

-40°C
25°C
105°C

C007

V

BIAS

= 2.5V, I

OUT

= -200mA

12

13

14

15

16

17

18

19

20

21

22

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

R

ON

(m)

VIN (V)

-40°C
25°C

105°C

C008

V

BIAS

= 5V, I

OUT

= -200mA

www.ti.com

Typical Characteristics (continued)

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

Figure 7. RONvs. VIN(V

= 2.5 V, Single Channel) Figure 8. RONvs. VIN(V

BIAS

Figure 9. RONvs. VIN(TA= 25°C, Single Channel) Figure 10. RPDvs. VIN(V

= 5 V, Single Channel)

BIAS

= 5 V, Single Channel)

BIAS

Figure 11. V

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

vs. VON(TA= 25°C, Single Channel) Figure 12. tDvs. VIN(V

OUT

Product Folder Links: TPS22966

= 2.5 V, CT = 1 nF)

BIAS

0

50

100

150

200

250

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

OFF

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C017

V

BIAS

= 5V, CT = 1nF

1000

1500

2000

2500

3000

3500

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

ON

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C018

V

BIAS

= 2.5V

CT = 1nF

0

5

10

15

20

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

F

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C015

V

BIAS

= 5V, CT = 1nF

0

20

40

60

80

100

120

140

160

180

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

OFF

(µs)

VIN (V)

-40°C
25°C
85°C

105°C

C016

V

BIAS

= 2.5V, CT = 1nF

300

400

500

600

700

800

900

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

D

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C013

V

BIAS

= 5V

CT = 1nF

0

2

4

6

8

10

12

14

16

18

20

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

F

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C014

V

BIAS

= 2.5V, CT = 1nF

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

Typical Characteristics (continued)

www.ti.com

Figure 13. tDvs. VIN(V

Figure 15. tFvs. VIN(V

= 5 V, CT = 1 nF)

BIAS

= 5 V, CT = 1 nF)

BIAS

Figure 14. tFvs. VIN(V

Figure 16. t

OFF

vs. VIN(V

= 2.5 V, CT = 1 nF)

BIAS

= 2.5 V, CT = 1 nF)

BIAS

Figure 17. t

10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

OFF

vs. VIN(V

= 5 V, CT = 1 nF)

BIAS

Figure 18. tONvs. VIN(V

Product Folder Links: TPS22966

= 2.5 V, CT = 1 nF)

BIAS

250

750

1250

1750

2250

2750

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

R

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C021

V

BIAS

= 5V

CT = 1nF

500

1000

1500

2000

2500

3000

3500

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5

t

R

(µs)

V

BIAS

(V)

-40°C
25°C
85°C
105°C

C022

VIN = 2.5V
CT = 1nF

400

600

800

1000

1200

1400

1600

1800

2000

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2

t

ON

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C019

V

BIAS

= 5V

CT = 1nF

500

1000

1500

2000

2500

3000

3500

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

t

R

(µs)

VIN (V)

-40°C
25°C
85°C
105°C

C020

V

BIAS

= 2.5V

CT = 1nF

www.ti.com

Typical Characteristics (continued)

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

Figure 19. tONvs. VIN(V

Figure 21. tRvs. VIN(V

= 5 V, CT = 1 nF)

BIAS

= 5 V, CT = 1 nF) Figure 22. tRvs. V

BIAS

Figure 20. tRvs. VIN(V

BIAS

BIAS(VIN

= 2.5 V, CT = 1 nF)

= 2.5 V, CT = 1 nF)

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: TPS22966

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

6.9 Typical AC Characteristics

at TA= 25ºC, CT = 1 nF

www.ti.com

Figure 23. Turnon Response Time (VIN= 0.8 V, V

CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω) CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

Figure 25. Turnon Response Time (VIN= 2.5 V, V

CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

= 2.5 V, Figure 24. Turnon Response Time (VIN= 0.8 V, V

BIAS

= 2.5 V, Figure 26. Turnon Response Time (VIN= 5 V, V

BIAS

CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

BIAS

BIAS

= 5 V,

= 5 V,

Figure 27. Turnoff Response Time (VIN= 0.8 V, V

= 2.5 V, Figure 28. Turnoff Response Time (VIN= 0.8 V, V

BIAS

BIAS

= 5.0 V,

CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω) CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966

+

-

OFF

ON

TPS22966

V

IN

V

OUT

R

L

C

L

TEST CIRCUIT

GND

(A)

GND

t

r

t

f

t

ON

t

OFF

90% 90%

10% 10%

tON/t

OFF

WAVEFORMS

(A) Rise and fall times of the control signal is 100ns.

V

ON

V

OUT

V

OUT

ON

GND

50% 50%

50% 50%

CIN= 1μF

t

D

Single channel shown for clarity.

V

BIAS

10%

CTx

www.ti.com

Typical AC Characteristics (continued)

at TA= 25ºC, CT = 1 nF

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

Figure 29. Turnoff Response Time (VIN= 2.5 V, V

CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω) CIN= 1 µF, CL= 0.1 µF, RL= 10 Ω)

7 Parameter Measurement Information

Figure 31. Test Circuit and TON/T

= 2.5 V, Figure 30. Turnoff Response Time (VIN= 5.0 V, V

BIAS

Waveforms

OFF

BIAS

= 5.0 V,

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: TPS22966

Control

Logic

VIN1

ON1

VOUT1

GND

Charge Pump

Control

Logic

VIN2

ON2

VOUT2

CT1

CT2

VBIAS

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

www.ti.com

8 Detailed Description

8.1 Overview

The device is a dual-channel, 6-A load switch in a 14-terminal SON package. To reduce the voltage drop in high
current rails, the device implements an low resistance N-channel MOSFET. The device has a programmable
slew rate for applications that require specific rise-time.

The device has very low leakage current during off state. This prevents downstream circuits from pulling high
standby current from the supply. Integrated control logic, driver, power supply, and output discharge FET
eliminates the need for any external components, which reduces solution size and bill of materials (BOM) count.

8.2 Functional Block Diagram

14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966

17

22

27

32

37

42

47

50

0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6
VIN (V)

Ron (mΩ)

VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 3.6V
VBIAS= 4.2V
VBIAS = 5V
VBIAS = 5.5V

Temperature=25C, IOUT=−200mA

G062

TPS22966

www.ti.com

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

8.3 Feature Description

8.3.1 ON/OFF Control

The ON pins control the state of the switch. Asserting ON high enables the switch. ON is active high and has a
low threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard
GPIO logic threshold. It can be used with any microcontroller with 1.2-V or higher GPIO voltage. This pin cannot
be left floating and must be tied either high or low for proper functionality.

8.3.2 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a
discharged load capacitor, a capacitor needs to be placed between VIN and GND. A 1-µF ceramic capacitor, CIN,
placed close to the pins, is usually sufficient. Higher values of CINcan be used to further reduce the voltage drop
during high-current application. When switching heavy loads, it is recommended to have an input capacitor about
10 times higher than the output capacitor to avoid excessive voltage drop.

8.3.3 Output Capacitor (Optional)

Due to the integrated body diode in the NMOS switch, a C
greater than CINcan cause V

to exceed VINwhen the system supply is removed. This could result in current

OUT

flow through the body diode from VOUT to VIN. A CINto CLratio of 10 to 1 is recommended for minimizing V
dip caused by inrush currents during startup, however a 10 to 1 ratio for capacitance is not required for proper
functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more VINdip upon
turn-on due to inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer
rise time (see Figure 4).

greater than CLis highly recommended. A C

I N

L

IN

8.3.4 VINand V

For optimal RONperformance, make sure VIN≤ V

Voltage Range

BIAS

. The device will still be functional if VIN> V

BIAS

BIAS

exhibit RONgreater than what is listed in Electrical Characteristics . See Figure 32 for an example of a typical
device. Notice the increasing RONas VINexceeds V
rating for VINand V

BIAS

.

Figure 32. RONvs VIN(VIN> V

voltage. Be sure to never exceed the maximum voltage

BIAS

, Single Channel)

BIAS

but it will

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS22966

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

8.4 Device Functional Modes

www.ti.com

Table 1. Functions Table

ONx VINx to VOUTx VOUTx to GND

L Off On

H On Off

16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966

Dual

Power

Supply

or

Dual

DC/DC

converter

OFF

ON

TPS22966

V

IN1

V

OUT1

R

L

C

L

GND

ON1

CT1

C

IN

OFF

ON

V

IN2

V

OUT2

C

L

GND

ON2

GND

C

IN

CT2

V

BIAS

TPS22966

www.ti.com

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

This application demonstrates how the TPS22966 can be used to limit inrush current when powering on
downstream modules.

9.2 Typical Application

Figure 33. Typical Application Circuit

9.2.1 Design Requirements

Table 2. Design Parameters

DESIGN PARAMETER VALUE

Input voltage 3.3 V

Bias voltage 5 V

Load capacitance (CL) 22 µF

Maximum acceptable inrush current 400 mA

9.2.2 Detailed Design Procedure

When the switch is enabled, the output capacitors must be charged up from 0 V to the set value (3.3 V in this
example). This charge arrives in the form of inrush current. Inrush current can be calculated using Equation 1:

Inrush Current = C × dV/dt

where

• C = output capacitance

• dV = output voltage

• dt = rise time (1)

The TPS22966 offers adjustable rise time for VOUT. This feature allows the user to control the inrush current
during turnon. The appropriate rise time can be calculated using Table 2 and the inrush current equation.

400 mA = 22 μF × 3.3 V/dt (2)
dt = 181.5 μs (3)

To ensure an inrush current of less than 400 mA, choose a CT value that will yield a rise time of more than 181.5
μs. See the oscilloscope captures in Application Curves for an example of how the CT capacitor can be used to
reduce inrush current.

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TPS22966

SR 0.32 CT 13.7= ´ +

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

www.ti.com

9.2.2.1 Adjustable Rise Time

A capacitor to GND on the CTx pins sets the slew rate for each channel. To ensure desired performance, a
capacitor with a minimum voltage rating of 25 V should be used on the CTx pin. An approximate formula for the
relationship between CTx and slew rate is (the equation below accounts for 10% to 90% measurement on V

OUT

and does NOT apply for CTx = 0 pF. Use Table 3 to determine rise times for when CTx = 0 pF):

where

• SR = slew rate (in µs/V)

• CT = the capacitance value on the CTx pin (in pF)

• The units for the constant 13.7 is in µs/V. (4)

Rise time can be calculated by multiplying the input voltage by the slew rate. Table 3 shows rise time values
measured on a typical device. Rise times shown below are only valid for the power-up sequence where VINand
V

are already in steady state condition, and the ON pin is asserted high.

BIAS

Table 3. Rise Time Values

RISE TIME (µs) 10% - 90%, CL= 0.1µF, CIN= 1µF, RL= 10Ω

CTx (pF)

5V 3.3V 1.8V 1.5V 1.2V 1.05V 0.8V

0 124 88 63 60 53 49 42
220 481 323 193 166 143 133 109
470 855 603 348 299 251 228 175

1000 1724 1185 670 570 469 411 342
2200 3328 2240 1308 1088 893 808 650
4700 7459 4950 2820 2429 1920 1748 1411

10000 16059 10835 6040 5055 4230 3770 3033

TYPICAL VALUES at 25°C, V

= 5V, 25V X7R 10% CERAMIC CAP

BIAS

9.2.3 Application Curves

V

= 5 V ; VIN= 3.3 V ; CL= 22 μF

BIAS

Figure 34. Inrush Current With CT = 0 pF Figure 35. Inrush Current With CT = 220 pF

10 Power Supply Recommendations

The device is designed to operate from a VBIAS range of 2.5 V to 5.5 V and a VIN range of 0.8 V to VBIAS.

18 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966

J(max) A

D(max)

JA

T T

-

=

θ

CT1 capacitor

CT2 capacitor

VIN1 capacitor

VOUT1 capacitor

VIN2 capacitor

VOUT2 capacitor

Thermal

relief vias

TPS22966

www.ti.com

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

11 Layout

11.1 Layout Guidelines

For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects
along with minimizing the case to ambient thermal impedance.

11.2 Layout Example

Notice the thermal vias located under the exposed thermal pad of the device. This allows for thermal diffusion
away from the device.

Figure 36. PCB Layout Example

11.3 Power Dissipation

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To
calculate the maximum allowable power dissipation, P
use the following equation:

for a given output current and ambient temperature,

D(max)

where

• P

• T

• TA= ambient temperature of the device

• θJA= junction to air thermal impedance. See Thermal Information . This parameter is highly dependent upon

= maximum allowable power dissipation

D(max)

= maximum allowable junction temperature (125°C for the TPS22966)

J(max)

board layout. (5)

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: TPS22966

TPS22966

SLVSBH4E –JUNE 2012–REVISED MARCH 2015

www.ti.com

12 Device and Documentation Support

12.1 Trademarks

Ultrabook is a trademark of Intel.
All other trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

20 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated

Product Folder Links: TPS22966

PACKAGE OPTION ADDENDUM

www.ti.com

19-May-2015

PACKAGING INFORMATION

Orderable Device Status

TPS22966DPUR ACTIVE WSON DPU 14 3000 Green (RoHS

TPS22966DPUT ACTIVE WSON DPU 14 250 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 RB966

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 RB966

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS22966 :

Automotive: TPS22966-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

19-May-2015

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Dec-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TPS22966DPUR WSON DPU 14 3000 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1
TPS22966DPUT WSON DPU 14 250 180.0 8.4 2.25 3.25 1.05 4.0 8.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Dec-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS22966DPUR WSON DPU 14 3000 210.0 185.0 35.0
TPS22966DPUT WSON DPU 14 250 210.0 185.0 35.0

Pack Materials-Page 2

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help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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