TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
Dual-Input, Single-Output MOSFET Switch
With No Reverse Current Flow (No Parasitic
Diodes)
D
IN1 . . . 250-mΩ, 500-mA N-Channel;
18-µA Supply Current
D
IN2 . . . 1.3-Ω, 100-mA P-Channel;
0.75-µA Supply Current (V
AUX
Mode)
D
Advanced Switch Control Logic
D
CMOS and TTL Compatible Enable Input
D
Controlled Rise, Fall, and Transition Times
D
2.7 V to 5.5 V Operating Range
D
SOT-23-5 and SOIC-8 Package
D
–40°C to 85°C Ambient Temperature Range
D
2-kV Human Body Model, 750-V Charged
Device Model, 200-V Machine-Model
ESD Protection
typical applications
D
Notebook and Desktop PCs
D
Cell phone, Palmtops, and PDAs
D
Battery Management
description
The TPS2104 and TPS2105 are dual-input, single-output power switches designed to provide uninterrupted
output voltage when transitioning between two independent power supplies. Both devices combine one
n-channel (250 mΩ) and one p-channel (1.3 Ω) MOSFET with a single output. The p-channel MOSFET (IN2)
is used with auxiliary power supplies that deliver lower current for standby modes. The n-channel MOSFET
(IN1) is used with a main power supply that delivers higher current required for normal operation. Low
on-resistance makes the n-channel the ideal path for higher main supply current when power-supply regulation
and system voltage drops are critical. When using the p-channel MOSFET, quiescent current is reduced to
0.75 µA to decrease the demand on the standby power supply . The MOSFETs in the TPS2104 and TPS2105
do not have the parasitic diodes, typically found in discrete MOSFETs, thereby preventing back-flow current
when the switch is off.
DBV PACKAGE
(TOP VIEW)
GND
IN2
IN1
OUT
EN
GND
IN2
IN1
OUT
EN
DBV PACKAGE
(TOP VIEW)
TPS2104
TPS2105
NC – No internal connection
1
2
3
4
8
7
6
5
IN2
GND
EN
NC
OUT
OUT
NC
IN1
D PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
IN2
GND
EN
NC
OUT
OUT
NC
IN1
1
2
3
5
4
1
2
35 4
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Figure 1. Typical Dual-Input Single-Output
Application
TPS2104
IN1
IN2
EN
5 V V
CC
5 V V
AUX
Control Signal
Holdup
Capacitor
LOAD
5 V
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Selection Guide, V
AUX
Power-Distribution Switches
DEVICE ENABLE
OPERATING
VOLTAGE RANGE
(V)
MAXIMUM INPUT
CURRENT, IN1
(mA)
MAXIMUM INPUT
CURRENT, IN2
(mA)
AMBIENT TEMPERATURE
RANGE (°C)
TPS2100 EN 2.7 to 4 500 10 –40 to 70
TPS2101 EN 2.7 to 4 500 10 –40 to 70
TPS2102 EN 2.7 to 4 500 100 –40 to 70
TPS2103 EN 2.7 to 4 500 100 –40 to 70
TPS2104 EN 2.7 to 5.5 500 100 –40 to 85
TPS2105 EN 2.7 to 5.5 500 100 –40 to 85
AVAILABLE OPTIONS FOR TPS2104, TPS2105
PACKAGED DEVICES
T
A
DEVICE ENABLE
SOT-23-5
(DBV)
†
SOIC-8
(D)
°
°
TPS2104 EN TSP2104DBV
†
TPS2104D
–
40°C to 85°C
TPS2105 EN TPS2105DBV
†
TPS2105D
Both packages are available left-end taped and reeled. Add an R suffix to the D device type
(e.g., TPS2105DR).
†
Add T (e.g., TPS2104DBVT) to indicate tape and reel at order quantity of 250 parts.
Add R (e.g., TPS2104DBVR) to indicate tape and reel at order quantity of 3000 parts.
Function Tables
TPS2104 TPS2105
VIN1 VIN2 EN OUT VIN1 VIN2 EN OUT
0 V 0 V XX GND 0 V 0 V XX GND
0 V 5 V L GND 0 V 5 V H GND
5 V 0 V L VIN1 5 V 0 V H VIN1
5 V 5 V L VIN1 5 V 5 V H VIN1
0 V 5 V H VIN2 0 V 5 V L VIN2
5 V 0 V H VIN2 5 V 0 V L VIN2
5 V 5 V H VIN2 5 V 5 V L VIN2
XX = don’t care
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2104 functional block diagram
V
CC
Select
Charge
Pump
Driver
GND
OUT
SW2
1.3 Ω
SW1
250 mΩ
Pullup
Circuit
Driver
IN1
EN
IN2
Discharge
Circuit
TPS2105 functional block diagram
V
CC
Select
Charge
Pump
Driver
GND
OUT
SW2
1.3 Ω
SW1
250 mΩ
Driver
IN1
EN
IN2
Pulldown
Circuit
Discharge
Circuit
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NO.
NAME
TPS2104 TPS2105
I/O
DESCRIPTION
DBV D DBV D
EN 1 3 I Active-high enable for IN1-OUT switch
EN 1 3 I Active-low enable for IN1-OUT switch
GND 2 2 2 2 I Ground
IN1
†
5 5 5 5 I Main input voltage, NMOS drain (250 mΩ), require 0.22 µF bypass
IN2
†
3 1 3 1 I Auxilliary input voltage, PMOS drain (1.3 Ω), require 0.22 µF bypass
OUT 4 7, 8 4 7, 8 O Power switch output
NC 4, 6 4, 6 No connection
†
Unused INx should not be grounded.
detailed description
power switches
n-channel MOSFET
The IN1-OUT n-channel MOSFET power switch has a typical on-resistance of 250 mΩ at 5-V input voltage, and
is configured as a high-side switch.
p-channel MOSFET
The IN2-OUT p-channel MOSFET power switch has a typical on-resistance of 1.3 Ω at 5-V input voltage and
is configured as a high-side switch. When operating, the p-channel MOSFET quiescent current is reduced to
typically 0.75 µA.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. T o limit large current surges
and reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry that
controls the rise times and fall times of the output voltage.
enable
The logic enable will turn on the IN2-OUT power switch when a logic high is present on EN (TPS2104) or logic
low is present on EN (TPS2105). A logic low input on EN (TPS2104) or logic high on EN (TPS2105) restores
bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input is compatible
with both TTL and CMOS logic levels.
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Input voltage range, V
I(IN1)
(see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I(IN2)
(see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI at EN or EN (see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O(IN1
) 700 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O(IN2)
140 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See dissipation rating table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine model 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged device model 750 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DBV 309 mW 3.1 mW/°C 170 mW 123 mW
D 568 mW 5.7 mW/°C 313 mW 227 mW
recommended operating conditions
MIN MAX UNIT
Input voltage, V
I(INx)
2.7 5.5 V
Input voltage, VI at EN and EN 0 5.5 V
Continuous output current, I
O(IN1)
500 mA
Continuous output current, I
O(IN2)
100
‡
mA
Operating virtual junction temperature, T
J
–40 125 °C
‡
The device can deliver up to 220 mA at I
O(IN2)
. However, operation at the higher current levels will result in greater voltage drop across the device,
and greater voltage droop when switching between IN1 and IN2.
electrical characteristics over recommended operating junction temperature range,
V
I(IN1)
= V
(IN2)
= 5 V, IO = rated current (unless otherwise noted)
power switch
PARAMETER
TEST
CONDITIONS
†
MIN TYP MAX UNIT
TJ = 25°C 250
IN1-OUT
TJ = 125°C 350 435
mΩ
r
DS(on)
On-state resistance
TJ = 25°C 1.3
IN2-OUT
TJ = 125°C 1.5 2.4
Ω
†
Pulse-testing techniques maintain junction temperature close to ambient termperature; thermal effects must be taken into account separately.
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range,
V
I(IN1)
= V
(IN2)
= 5 V, IO = rated current (unless otherwise noted) (continued)
enable input (EN and EN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IH
High-level input voltage 2.7 V ≤ V
I(INx)
≤ 5.5 V 2 V
V
IL
Low-level input voltage 2.7 V ≤ V
I(INx)
≤ 5.5 V 0.8 V
p
TPS2104 EN = 0 V or EN = V
I(INx)
–0.5 0.5 µA
IIInput current
TPS2105 EN = 0 V or EN = V
I(INx)
–0.5 0.5 µA
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN = H
,
TJ = 25°C 0.75
EN H,
IN2 selected
–40°C ≤ TJ ≤ 125°C 1.5
µ
A
TPS2104
EN = L
,
TJ = 25°C 18
pp
EN L,
IN1 selected
–40°C ≤ TJ ≤ 125°C 35
µ
A
IISupply current
EN = L,
TJ = 25°C 0.75
,
IN2 selected
–40°C ≤ TJ ≤ 125°C 1.5
µ
A
TPS2105
EN = H,
TJ = 25°C 18
,
IN1 selected
–40°C ≤ TJ ≤ 125°C 35
µ
A
switching characteristics, TJ = 25°C, V
I(IN1)
= V
I(IN2)
= 5 V (unless otherwise noted)
†
PARAMETER TEST CONDITIONS
†
MIN TYP MAX UNIT
CL = 1 µF, IL = 500 mA 340
IN1-OUT V
I(IN2)
= 0
CL = 10 µF, IL = 500 mA 340
p
()
CL = 1 µF, IL = 100 mA 312
trOutput rise time
CL = 1 µF, IL = 100 mA 3.4
µ
s
IN2-OUT V
I(IN1)
= 0
CL = 10 µF, IL = 100 mA 34
()
CL = 1 µF, IL = 10 mA 3.5
CL = 1 µF, IL = 500 mA 6
IN1-OUT V
I(IN2)
= 0
CL = 10 µF, IL = 500 mA 108
p
()
CL = 1 µF, IL = 100 mA 8
tfOutput fall time
CL = 1 µF, IL = 100 mA 100
µ
s
IN2-OUT V
I(IN1)
= 0
CL = 10 µF, IL = 100 mA 990
()
CL = 1 µF, IL = 10 mA 1000
p
p
IN1-OUT V
I(IN2)
= 0
55
t
PLH
Propagation delay time, low-to-high output
IN2-OUT V
I(IN1)
= 0
C
L
= 10 µF,
I
L
=
100 mA
1
µ
s
p
p
IN1-OUT V
I(IN2)
= 0
1.5
t
PHL
Propagation delay time, high-to-low output
IN2-OUT V
I(IN1)
= 0
C
L
= 10 µF,
I
L
=
100 mA
50
µ
s
†
All timing parameters refer to Figure 2.
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
PLH
t
PHL
EN or EN
V
O
EN or EN
V
O
50%
10%
V
I
GND
GND
V
I
90%
50%
90%
10%
V
O
GND
V
I
t
r
t
f
Propagation Delay Time, Low-to-High-Level Output Propagation Delay Time, High-to–Low-Level Output
Rise/Fall Time
t
on
t
off
EN or EN
V
O
EN or EN
V
O
50%
10%
V
I
GND
GND
V
I
90%
50%
Turnon Transition Time
Turnoff Transition Time
WAVEFORMS
OUT
C
L
I
O
LOAD CIRCUIT
Figure 2. Test Circuit and Voltage Waveforms
Table of Timing Diagrams
†
FIGURE
Propagation Delay and Rise Time With 1-µF Load, IN1 3
Propagation Delay and Rise Time With 1-µF Load, IN2 4
Propagation Delay and Fall Time With 1-µF Load, IN1 5
Propagation Delay and Fall Time With 1-µF Load, IN2 6
†
Waveforms shown in Figures 3–6 refer to TPS2104 at TJ = 25°C
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 3. Propagation Delay and Rise Time
With 1-µF Load, IN1 Turnon
EN
2 V/div)
t – Time – 200 µs/div
V
O
2 V/div)
V
I(IN1)
= 5 V
V
I(IN2)
= 0 V
CL = 1 µF
RL = 50 Ω
Figure 4. Propagation Delay and Rise Time
With 1-µF Load, IN2 Turnon
EN
(2 V/div)
t – Time – 2 µs/div
V
O
(2 V/div)
V
I(IN1)
= 0 V
V
I(IN2)
= 5 V
CL = 1 µF
RL = 50 Ω
Figure 5. Propagation Delay and Fall Time
With 1-µF Load, IN1 Turnoff
EN
(2 V/div)
t – Time – 10 µs/div
V
O
(2 V/div)
V
I(IN1)
= 5 V
V
I(IN2)
= 0 V
CL = 1 µF
RL = 50 Ω
Figure 6. Propagation Delay and Fall Time
With 1-µF Load, IN2 Turnoff
EN
(2 V/div)
t – Time – 50 µs/div
V
O
(2 V/div)
V
I(IN1)
= 0 V
V
I(IN2)
= 5 V
CL = 1 µF
RL = 50 Ω
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IN1 Switch Rise Time vs Output Current 7
IN2 Switch Fall Time vs Output Current 8
IN1 Switch Fall Time vs Output Current 9
IN2 Switch Fall Time vs Output Current 10
Output Voltage Droop vs Output Current When Output Is Switched From IN2 to IN1 11
Inrush Current vs Output Capacitance 12
IN1 Supply Current vs Junction Temperature (IN1 Enabled) 13
IN1 Supply Current vs Junction Temperature (IN1 Disabled) 14
IN2 Supply Current vs Junction Temperature (IN2 Enabled) 15
IN2 Supply Current vs Junction Temperature (IN2 Disabled) 16
IN1-OUT On-State Resistance vs Junction Temperature 17
IN2-OUT On-State Resistance vs Junction Temperature 18
Figure 7
310
280
250
0.01 0.1 1 10
– Rise Time –
340
370
IN1 SWITCH RISE TIME
vs
OUTPUT CURRENT
400
100 1000
CL = 47 µF
CL = 10 µF
CL = 1 µF
IO – Output Current – mA
t
r
sµ
V
I(IN1)
= 5 V
V
I(IN2)
= 0 V
TJ = 25°C
CL = 100 µF
Figure 8
10
0.1
0 102030405060
100
IN2 SWITCH RISE TIME
vs
OUTPUT CURRENT
1000
70 80 90 100
– Rise Time –
CL = 100 µF
CL = 47 µF
CL = 10 µF
CL = 1 µF
IO – Output Current – mA
t
r
sµ
V
I(IN1)
= 0 V
V
I(IN2)
= 5 V
TJ = 25°C
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
100
10
1
0.01 0.1 1 10
1000
IN1 SWITCH FALL TIME
vs
OUTPUT CURRENT
10000
100 1000
– Fall Time –
CL = 100 µF
CL = 47 µF
CL = 10 µF
CL = 1 µF
IO – Output Current – mA
t
f
sµ
V
I(IN1)
= 5 V
V
I(IN2)
= 0 V
TJ = 25°C
Figure 10
10
1
0.1
0.01 0.1
100
IN2 SWITCH FALL TIME
vs
OUTPUT CURRENT
1000
1 100
– Output Fall Time – ms
IO – Output Current – mA
t
f
V
I(IN1)
= 0 V
V
I(IN2)
= 5 V
TJ = 25°C
10
CL = 47 µF
CL = 10 µF
CL = 100 µF
CL = 1 µF
Figure 11
0.4
0.2
0
0.01 0.1
0.6
0.8
1
1 100
– Output Voltage Droop – V
OUTPUT VOLTAGE DROOP
vs
OUTPUT CURRENT WHEN OUTPUT
IS SWITCHED FROM IN2 TO IN1
†
V
O
CL = 100 µF
CL = 10 µF
CL = 1 µF
CL = 220 µF
IO – Output Current – mA
V
I(IN1)
= 5 V
V
I(IN2)
= 5 V
TJ = 25°C
CL = 47 µF
10
Figure 12
2
1
0
0 100 200 300
Inrush Current – A
2.5
3
INRUSH CURRENT
vs
OUTPUT CAPACITANCE
3.5
400 500
1.5
0.5
Co – Output Capacitance – µF
V
I(IN1)
= 5 V
V
I(IN2)
= 0 V
RL = 10 Ω
TJ = 25°C
†
If switching from IN1 to IN2, the voltage droop is much smaller. Therefore, the load capacitance should be chosen according to the curves in
Figure 15.
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
17
13
9
–40 –10 20 50
– Supply Current –
21
IN1 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN1 ENABLED)
29
11080 140
I
CC
Aµ
V
I(IN1)
= 4 V
V
I(IN1)
= 2.7 V
TJ – Junction Temperature – °C
V
I(IN1)
= 5 V
V
I(IN1)
= 5.5 V
25
V
I(IN1)
= 3.3 V
Figure 14
0.37
0.31
0.19
–40 –10 20 50
0.43
0.49
IN1 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN1 DISABLED)
0.55
80 110 140
TJ – Junction Temperature – °C
0.25
V
I(IN1)
= 5.5 V
V
I(IN1)
= 5 V
V
I(IN1)
= 4 V
V
I(IN1)
= 3.3 V
V
I(IN1)
= 2.7 V
– Supply Current –I
CC
Aµ
Figure 15
0.47
0.41
0.35
–40 –10 20 50
0.53
0.59
IN2 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN2 ENABLED)
0.65
80 110 140
TJ – Junction Temperature – °C
V
I(IN2)
= 5.5 V
V
I(IN2)
= 4 V
V
I(IN2)
= 3.3 V
V
I(IN2)
= 2.7 V
V
I(IN2)
= 5 V
– Supply Current –I
CC
Aµ
Figure 16
0.21
0.18
0.15
–40 –10 20 50
0.24
0.27
IN2 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN2 DISABLED)
0.3
80 110 140
TJ – Junction Temperature – °C
V
I(IN2)
= 5.5 V
V
I(IN2)
= 5 V
V
I(IN2)
= 4 V
V
I(IN2)
= 3.3 V
V
I(IN2)
= 2.7 V
– Supply Current –I
CC
Aµ
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 17
280
240
200
–40 –10 20 50
– IN1-OUT On-State resistance –
320
IN1-OUT ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
360
80 110 140
r
on
mΩ
TJ – Junction Temperature – °C
V
I(IN1)
= 2.7 V
V
I(IN1)
= 3.3 V
V
I(IN1)
= 4 V
V
I(IN1)
= 5 V
V
I(IN1)
= 5.5 V
Figure 18
1.5
1
0.5
–40 –10 20 50
2
2.5
IN2-OUT ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
3
80 110 140
– IN1-OUT On-State resistance –
r
on
Ω
V
I(IN2)
= 3.3 V
V
I(IN2)
= 2.7 V
TJ – Junction Temperature – °C
V
I(IN2)
= 5.5 V
V
I(IN2)
= 5 V
V
I(IN2)
= 4 V
APPLICATION INFORMATION
EN
IN1
IN2
OUT
GND
5 V V
AUX
5 V V
CC
CardBus or System Controller
TPS2104
0.22 µF
0.22 µF
1 µF xx µF
5 V
Figure 19. Typical Application
power-supply considerations
A 0.22-µF ceramic bypass capacitor between IN and GND, close to the device is recommended. The output
capacitor should be chosen based on the size of the load during the transition of the switch. A 220-µF capacitor
is recommended for 100-mA loads. Typical output capacitors (xx µF, shown in Figure 19) required for a given
load can be determined from Figure 1 1 which shows the output voltage droop when output is switched from IN2
to IN1. The output voltage droop is insignificant when output is switched from IN1 to IN2. Additionally , bypassing
the output with a 1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
power supply considerations (continued)
switch transition
The n-channel MOSFET on IN1 uses a charge pump to create the gate-drive voltage, which gives the IN1 switch
a rise time of approximately 0.4 ms. The p-channel MOSFET on IN2 has a simpler drive circuit that allows a
rise time of approximately 4 µs. Because the device has two switches and a single enable pin, these rise times
are seen as transition times, from IN1 to IN2, or IN2 to IN1, by the output. The controlled transition times help
limit the surge currents seen by the power supply during switching.
thermal protection
Thermal protection provided on the IN1 switch prevents damage to the IC when heavy-overload or short-circuit
faults are present for extended periods of time. The increased dissipation causes the junction temperature to
rise to dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts
it off at approximately 145°C (TJ). The switch remains off until the junction temperature has dropped
approximately 10°C. The switch continues to cycle in this manner until the load fault or input power is removed.
undervoltage lockout
An undervoltage lockout function is provided to ensure that the power switch is in the off state at power up.
Whenever the input voltage falls below approximately 2 V, the power switch quickly turns off. This function
facilitates the design of hot-insertion systems that may not have the capability to turn off the power switch before
input power is removed. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. First, find ron at the input voltage
and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and
read ron from Figure 17 or Figure 18. Next calculate the power dissipation using:
PD+
ron
I
2
Finally, calculate the junction temperature:
TJ+
PD
R
q
JA
)
T
A
Where:
T
A
= Ambient temperature
R
θJA
= Thermal resistance
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally
sufficient to obtain a reasonable answer.
ESD protection
All TPS2104 and TPS2105 terminals incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model, 750-V CDM, and 200-V machine-model discharge as defined in MIL-STD-883C.
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE
0,10
M
0,20
0,95
0°–8°
0,25
0,35
0,55
Gage Plane
0,15 NOM
4073253-4/E 05/99
2,60
3,00
0,50
0,30
1,50
1,70
45
31
2,80
3,00
0,95
1,45
0,05 MIN
Seating Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-178
TPS2104, TPS2105
V
AUX
POWER-DISTRIBUTION SWITCHES
SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
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