TEXAS INSTRUMENTS TPS1101, TPS1101Y Technical data

CHIP FORM

查询TPS1101DR供应商

TPS1101, TPS1101Y

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

D

Low r

DS(on)

D

3 V Compatible

D

Requires No External V

D

TTL and CMOS Compatible Inputs

D

V

GS(th)

D

Available in Ultrathin TSSOP Package (PW)

D

ESD Protection Up to 2 kV per
MIL-STD-883C, Method 3015

. . . 0.09 Ω Typ at VGS = –10 V

CC

= –1.5 V Max

SOURCE
SOURCE
SOURCE

GATE

D PACKAGE

D PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

DRAIN
DRAIN
DRAIN
DRAIN

description

The TPS1 101 is a single, low-r
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution
in battery-powered systems by means of the
Texas Instruments LinBiCMOS process. With a
maximum V

of –1.5 V and an I

GS(th)

0.5 µA, the TPS1101 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low r

and excellent ac

DS(on)

characteristics (rise time 5.5 ns typical) of the
TPS1101 make it the logical choice for
low-voltage switching applications such as power
switches for pulse-width-modulated (PWM)
controllers or motor/bridge drivers.

The ultrathin thin shrink small-outline package or
TSSOP (PW) version fits in height-restricted
places where other P-channel MOSFETs cannot.
The size advantage is especially important where
board height restrictions do not allow for an
small-outline integrated circuit (SOIC) package.
Such applications include notebook computers,
personal digital assistants (PDAs), cellular
telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other
P-channel MOSFETs in SOIC packages.

T

J

–40°C to 150°C TPS1101D TPS1101PWLE TPS1101Y

†

The D package is available taped and reeled. Add an R suffix to device type (e.g.,
TPS1101DR). The PW package is only available left-end taped and reeled (indicated by
the LE suffix on the device type; e.g., TPS1 101PWLE). The chip form is tested at 25 °C.

, P-channel,

DS(on)

DSS

SMALL OUTLINE

of only

SOURCE
SOURCE
SOURCE
SOURCE
SOURCE

AVAILABLE OPTIONS

PACKAGED DEVICES

(D)

PW PACKAGE

(TOP VIEW)

NC

GATE

NC

NC – No internal connection

†

TSSOP

(PW)

1
2
3
4
5
6
7
8

(Y)

PW PACKAGE

16
15
14
13
12
11
10

9

NC
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
NC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

schematic

SOURCE

ESD-

Protection

Circuitry

GATE

DRAIN

NOTE A: For all applications, all source terminals should be

connected and all drain terminals should be connected.

TPS1101Y chip information

This chip, when properly assembled, displays characteristics similar to the TPS1 101. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

80

(1)

(7)(8)

(2)

(6)

(3) (4)

(5)

(1)

SOURCE
SOURCE

(2)
(3)

GATE

CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS

TPS1100Y

(8)
(7)
(6)
(5)(4)

DRAINSOURCE
DRAIN

DRAIN
DRAIN

92

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D package

V

2.7 V

PW package

D package

V

V

PW package

Continuous drain current (T

150°C), I

‡

A

D package

V

V

PW package

D package

V

10 V

PW package

TPS1101, TPS1101Y

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Drain-to-source voltage, V
Gate-to-source voltage, V

Pulsed drain current, I
Continuous source current (diode conduction), I
Storage temperature range, T

Operating junction temperature range, T
Operating free-air temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

Maximum values are calculated using a derating factor based on R
These devices are mounted on an FR4 board with no special thermal considerations.

DS

GS

p

= –

GS

p

p

= –3

GS

p

°

=

J

‡

D

stg

D

p

= –4.5

GS

p

p

= –

GS

p

S

J

A

θJA

TA = 25°C ±0.62
TA = 125°C ±0.39
TA = 25°C ±0.61
TA = 125°C ±0.38
TA = 25°C ±0.88
TA = 125°C ±0.47
TA = 25°C ±0.86
TA = 125°C ±0.45
TA = 25°C ±1.52
TA = 125°C ±0.71
TA = 25°C ±1.44
TA = 125°C ±0.67
TA = 25°C ±2.30
TA = 125°C ±1.04
TA = 25°C ±2.18
TA = 125°C ±0.98
TA = 25°C ±10 A
TA = 25°C –1.1 A

= 158°C/W for the D package and R

= 176°C/W for the PW package.

θJA

2 or – 15 V

–55 to 150 °C
–40 to 150 °C

–40 to 125 °C

†

UNIT

– 15 V

DISSIPATION RATING TABLE

PACKAGE

D 791 mW 6.33 mW/°C 506 mW 411 mW 158 mW

PW 710 mW 5.68 mW/°C 454 mW 369 mW 142 mW

‡

Maximum values are calculated using a derating factor based on R
for the PW package. These devices are mounted on an FR4 board with no special thermal considerations.

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

‡

TA = 70°C

POWER RATING

θJA

TA = 85°C

POWER RATING

= 158°C/W for the D package and R

TA = 125°C

POWER RATING

= 176°C/W

θJA

3

TPS1101, TPS1101Y

PARAMETER

TEST CONDITIONS

UNIT

I

gg

V

12 V

V

0 V

A

r

Static drain to source

mΩ

I

A

PARAMETER

TEST CONDITIONS

UNIT

DD

,

L

,

D

,

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

electrical characteristics at TJ = 25°C (unless otherwise noted)

static

TPS1101 TPS1101Y

MIN TYP MAX MIN TYP MAX

V

GS(th)

V

SD

I

GSS

DSS

DS(on)

g

fs

†

Pulse test: pulse duration ≤ 300 µs, duty cycle ≤ 2%

Gate-to-source
threshold voltage

Source-to-drain voltage
(diode-forward voltage)

Reverse gate current,
drain short circuited to
source

Zero-gate-voltage drain
current

Static drain-to-source
on-state resistance

Forward
transconductance

†

†

VDS = VGS, ID = –250 µA –1 –1.25 –1.5 –1.25 V

IS = –1 A, VGS = 0 V –1.04 –1.04 V

†

VDS = 0 V, VGS = –12 V ±100 nA

= –

DS

VGS = –10 V ID = –2.5 A 90 90
VGS = –4.5 V
VGS = –3 V
VGS = –2.7 V

VDS = –10 V, ID = –2 A 4.3 4.3 S

,

GS

ID = –1.5 A 134 190 134

= –0.5

D

TJ = 25°C –0.5

=

TJ = 125°C –10

µ

198 310 198
232 400 232

dynamic

Q

g

Q

gs

Q

gd

t

d(on)

t

d(off)

t

r

t

f

t

rr(SD)

TPS1101, TPS1101Y

MIN TYP MAX

Total gate charge 11.25
Gate-to-source charge
Gate-to-drain charge 2.6
Turn-on delay time 6.5 ns

Turn-off delay time
Rise time
Fall time 13
Source-to-drain reverse recovery time IF = 5.3 A, di/dt = 100 A/µs 16

VDS = –10 V, VGS = –10 V, ID = –1 A

V

= –10 V, R

RG = 6 Ω,

= 10 Ω,I

See Figures 1 and 2

= –1 A,

1.5

19 ns

5.5

nC

ns

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS1101, TPS1101Y

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

PARAMETER MEASUREMENT INFORMATION

R

L

V

V

GS

R

G

DUT

DS
V

DD

–
+

Figure 1. Switching-Time Test Circuit

TYPICAL CHARACTERISTICS

Drain current vs Drain-to-source voltage 3
Drain current vs Gate-to-source voltage 4
Static drain-to-source on-state resistance vs Drain current 5
Capacitance vs Drain-to-source voltage 6
Static drain-to-source on-state resistance (normalized) vs Junction temperature 7
Source-to-drain diode current vs Source-to-drain voltage 8
Static drain-to-source on-state resistance vs Gate-to-source voltage 9
Gate-to-source threshold voltage vs Junction temperature 10
Gate-to-source voltage vs Gate charge 11

V

GS

90%

10%

V

DS

t

d(on)

t

r

Figure 2. Switching-Time Waveforms

Table of Graphs

t

d(off)

t

f

0 V

–10 V

FIGURE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

TYPICAL CHARACTERISTICS

DRAIN CURRENT

vs

DRAIN-TO-SOURCE VOLTAGE

– 10

– 9
– 8

– 7

– 6
– 5

– 4

– Drain Current – A

D

– 3

I

– 2
– 1

0

0 – 1– 2– 3– 4– 5– 6

VGS = –8 V
VGS = –5 V

VGS = –4 V

VGS = –3 V

VGS = –2 V

TJ = 25°C

– 7 – 8 – 9 – 10

VDS – Drain-to-Source Voltage – V

Figure 3

STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE

vs

DRAIN CURRENT

0.5
TJ = 25°C

0.4

DRAIN CURRENT

vs

GATE-TO-SOURCE VOLTAGE

– 10

VDS = –10 V

TJ = 25°C

– 8

TJ = –40°C

– 6

– 4

– Drain Current – A

D

I

– 2

0

0 – 2 – 3 – 5

– 1 – 4
VGS – Gate-to-Source Voltage – V

TJ = 150°C

Figure 4

†

800

700

600

CAPACITANCE

vs

DRAIN-TO-SOURCE VOLTAGE

†

C

iss

VGS = 0 V
f = 1 MHz

TJ = 25°C

Ω

0.3

VGS = –2.7 V

0.2

Resistance –

– Static Drain-to-Source On-State

DS(on)

r

6

VGS = –3 V

0.1

0

– 0.1 – 1

ID – Drain Current – A

Figure 5

VGS = –4.5 V

VGS = –10 V

– 10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

C – Capacitance – pF

†

C

‡

C

C

+

+

Cgs)

oss

‡

C

rss

VDS – Drain-to-Source Voltage – V

Cgd,C

Cgd,C

oss

+

500

400

300

200

100

0 – 1 – 2 – 3 – 4 – 5 – 6

iss

rss

ds(shorted)

Cds)

Figure 6

– 7 – 8 – 9 –12

CgsC

Cgs)

gd

C

–10 –1 1

≈ Cds)

gd

C

gd

STATIC DRAIN-TO-SOURCE

ON-STATE RESISTANCE (NORMALIZED)

JUNCTION TEMPERATURE

1.5
VGS = –10 V

ID = –1A

1.4

1.3

1.2

1.1

1

– Static Drain-to-Source

0.9

0.8

DS(on)

On-State Resistance (normalized)

r

0.7

vs

TPS1101, TPS1101Y

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

TYPICAL CHARACTERISTICS

SOURCE-TO-DRAIN DIODE CURRENT

vs

SOURCE-TO-DRAIN VOLTAGE

– 10

Pulse Test

– Source-to-Drain Diode Current – A

I

TJ = 150°C

– 1

SD

TJ = 25°C

TJ = –40°C

0.6

–50 0 50 100 150

TJ – Junction Temperature – °C

Figure 7

STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE

vs

GATE-TO-SOURCE VOLTAGE

0.5
ID = –1 A

TJ = 25°C

0.4

Ω

0.3

0.2

Resistance –

– Static Drain-to-Source On-State

0.1

DS(on)

r

0

– 1 – 3 – 5 – 7

VGS – Gate-to-Source Voltage – V

– 9 – 11

– 13 – 15

– 0.1

– 0.1

– 0.3 – 0.5 – 0.7

VSD – Source-to-Drain Voltage – V

– 0.9 – 1.1 – 1.3

Figure 8

GATE-TO-SOURCE THRESHOLD VOLTAGE

vs

JUNCTION TEMPERATURE

– 1.5

ID = –250 µA

– 1.4

– 1.3

– 1.2

– 1.1

– Gate-to-Source Threshold Voltage – V

– 1

GS(th)

V

– 0.9

–50 0 50 100 150

TJ – Junction Temperature – °C

Figure 9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 10

7

TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

TYPICAL CHARACTERISTICS

GATE-TO-SOURCE VOLTAGE

vs

GATE CHARGE

– 10

VDS = –10 V
ID = –1 A
TJ = 25°C

– 8

– 6

– 4

– Gate-to-Source Voltage – VV

GS

– 2

0

2812

04610

Q

– Gate Charge – nC

g

Figure 11

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS1101, TPS1101Y

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

THERMAL INFORMATION

DRAIN CURRENT

vs

DRAIN-TO-SOURCE VOLTAGE

– 100

Single Pulse
See Note A

– 10

– 1

– Drain Current – A

D

I

– 0.1

TJ = 150°C
TA = 25°C

– 0.01

– 0.1 – 1 – 10 – 100

VDS – Drain-to-Source Voltage – V

NOTE A: Values are for the D package and are

FR4-board-mounted only.

0.001 s

0.01 s

0.1 s

1 s
10 s
DC

Figure 12

TRANSIENT JUNCTION-TO-AMBIENT

THERMAL IMPEDANCE

vs

PULSE DURATION

100

Single Pulse
See Note A

C/W

10

°

1

Thermal Impedance –

– Transient Junction-to-AmbientZ

θJA

0.1

0.001 0.01 0.1 1 10
tw – Pulse Duration – s

NOTE A: Values are for the D package and are

FR4-board-mounted only.

Figure 13

APPLICATION INFORMATION

3 V or 5 V

Microcontroller

Load

Figure 14. Notebook Load Management

5 V

Driver

Microcontroller

Charge

Pump

–4 V

Figure 15. Cellular Phone Output Drive

GaAs FET

Amplifier

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated