Texas Instruments TPS1101PWR, TPS1101PWLE, TPS1101DR, TPS1101D Datasheet
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low r
DS(on)
. . . 0.09 Ω Typ at VGS = –10 V
D
3 V Compatible
D
Requires No External V
CC
D
TTL and CMOS Compatible Inputs
D
V
GS(th)
= –1.5 V Max
D
Available in Ultrathin TSSOP Package (PW)
D
ESD Protection Up to 2 kV per
MIL-STD-883C, Method 3015
description
The TPS1 101 is a single, low-r
DS(on)
, P-channel,
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution
in battery-powered systems by means of the
Texas Instruments LinBiCMOS process. With a
maximum V
GS(th)
of –1.5 V and an I
DSS
of only
0.5 µA, the TPS1101 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low r
DS(on)
and excellent ac
characteristics (rise time 5.5 ns typical) of the
TPS1101 make it the logical choice for
low-voltage switching applications such as power
switches for pulse-width-modulated (PWM)
controllers or motor/bridge drivers.
The ultrathin thin shrink small-outline package or
TSSOP (PW) version fits in height-restricted
places where other P-channel MOSFETs cannot.
The size advantage is especially important where
board height restrictions do not allow for an
small-outline integrated circuit (SOIC) package.
Such applications include notebook computers,
personal digital assistants (PDAs), cellular
telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other
P-channel MOSFETs in SOIC packages.
AVAILABLE OPTIONS
PACKAGED DEVICES
†
T
J
SMALL OUTLINE
(D)
TSSOP
(PW)
CHIP FORM
(Y)
–40°C to 150°C TPS1101D TPS1101PWLE TPS1101Y
†
The D package is available taped and reeled. Add an R suffix to device type (e.g.,
TPS1101DR). The PW package is only available left-end taped and reeled (indicated by
the LE suffix on the device type; e.g., TPS1 101PWLE). The chip form is tested at 25 °C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
1
2
3
4
8
7
6
5
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
GATE
NC
NC
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
NC
PW PACKAGE
(TOP VIEW)
NC – No internal connection
D PACKAGE
PW PACKAGE
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic
NOTE A: For all applications, all source terminals should be
connected and all drain terminals should be connected.
SOURCE
DRAIN
GATE
ESD-
Protection
Circuitry
TPS1101Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS1 101. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
80
92
TPS1100Y
(2)
(6)
(1)
(3)
(7)
(8)
(5)(4)
DRAINSOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
(2)
(1)
(3) (4)
(6)
(7)(8)
(5)
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
UNIT
Drain-to-source voltage, V
DS
– 15 V
Gate-to-source voltage, V
GS
2 or – 15 V
p
TA = 25°C ±0.62
D package
TA = 125°C ±0.39
V
GS
= –
2.7 V
p
TA = 25°C ±0.61
PW package
TA = 125°C ±0.38
p
TA = 25°C ±0.88
D package
TA = 125°C ±0.47
V
GS
= –3
V
p
TA = 25°C ±0.86
°
PW package
TA = 125°C ±0.45
Continuous drain current (T
J
=
150°C), I
D
‡
p
TA = 25°C ±1.52
A
D package
TA = 125°C ±0.71
V
GS
= –4.5
V
p
TA = 25°C ±1.44
PW package
TA = 125°C ±0.67
p
TA = 25°C ±2.30
D package
TA = 125°C ±1.04
V
GS
= –
10 V
p
TA = 25°C ±2.18
PW package
TA = 125°C ±0.98
Pulsed drain current, I
D
‡
TA = 25°C ±10 A
Continuous source current (diode conduction), I
S
TA = 25°C –1.1 A
Storage temperature range, T
stg
–55 to 150 °C
Operating junction temperature range, T
J
–40 to 150 °C
Operating free-air temperature range, T
A
–40 to 125 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
Maximum values are calculated using a derating factor based on R
θJA
= 158°C/W for the D package and R
θJA
= 176°C/W for the PW package.
These devices are mounted on an FR4 board with no special thermal considerations.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D 791 mW 6.33 mW/°C 506 mW 411 mW 158 mW
PW 710 mW 5.68 mW/°C 454 mW 369 mW 142 mW
‡
Maximum values are calculated using a derating factor based on R
θJA
= 158°C/W for the D package and R
θJA
= 176°C/W
for the PW package. These devices are mounted on an FR4 board with no special thermal considerations.
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