Texas Instruments TPIC 7410 – Q 1 INSTALLATION INSTRUCTIONS

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P0021-02

PWP HTSSOP PACKAGE

(TOP VIEW)

SCR1
Cboot2
Cboot1

V

L1

PGND

L2

V

5
A

driver

OUT

Vg

IN

SCR0
5Vg_ENABLE
ENABLE
V

GND
R

REST
A

RESET
CLP

logic

mod

OUT

20
19
18
17
16
15
14
13
12
11

1
2
3
4
5
6
7
8
9
10

BUCK/BOOST SWITCH-MODE REGULATOR

TPIC74100-Q1

SLIS125 – DECEMBER 2006

FEATURES

• Switch-Mode Regulator

– 5 V ±2%, Normal Mode
– 5 V ±3%, Low-Power or Crossover Mode

• Switching Frequency, 440 kHz (typical)

• Input Operating Range, 1.5 V to 40 V, (V

– 1-A Load-Current Capability
– 200-mA Load-Current Capability Down to

2-V Input (V

– 120-mA Load-Current Capability Down to

1.5-V Input (V

• Enable Function

• Low-Power Operation Mode

)

driver

)

driver

• Switched 5-V Regulated Output on 5Vg With

Current Limit

• Programmable Slew Rate and Frequency

Modulation for EMI Consideration

• Reset Function With Deglitch Timer and

)

driver

Programmable Delay

• Alarm Function for Undervoltage Detection

and Indication

• Thermally Enhanced Package for Efficient

Heat Management

APPLICATIONS

• Automotive Electronic Controller Power

Supply

DESCRIPTION

The TPIC74100-Q1 is a switch-mode regulator with integrated switches for voltage-mode control. With the aid of
external components (LC combination), the device regulates the output to 5 V ±3% for a wide input-voltage
range.

The TPIC74100-Q1 offers a reset function to detect and indicate when the 5-V output rail is outside of the
specified tolerance. This reset delay is programmable using an external timing capacitor on the REST terminal.
Additionally, an alarm (A
value (set by the A

The TPIC74100-Q1 has a frequency-modulation scheme to minimize EMI. The clock modulator permits a
modulation of the switching frequency to reduce interference energy in the frequency band.

The 5Vg output is a switched 5-V regulated output with internal current limiting to prevent RESET from being
asserted when powering a capacitive load on the supply line. This function is controlled by the 5Vg_ENABLE
terminal. If there is a short to ground on this output (5Vg output), the output self-protects by operating in a
chopping mode. This does, however, increase the output ripple voltage on V

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

) feature is activated when the input supply rail V

OUT

terminal).

IN

OUT

driver

during this fault condition.

is below a prescaled specified

Ordering Information

Part Number Package

TPIC74100QPWPRQ1 R-PDSO-G (PWP, 20-pin)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2006, Texas Instruments Incorporated

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B0130-01

Switch-Mode

ControllerWith

Dead Time

Charge

Pump

Vref

Bandgap

Ref

Vreg

Osc

+

-

+

-

PORWith

Delay Timer

V

driver

ENABLE

GND

L1

5VSupply

5Vg_Supply

-

+

L2

V

OUT

Q1

Q2

Q3

Q4

RESET

Temp

Monitor

Shutdown
Regulator

R

mod

Clock

Modulator

Cboot1

Cboot2

5Vg_ENABLE

A

OUT

REST

PGND

SCR0

SCR1

SlewRate

Control

5

Vg

Low-Power

Mode

Control

CLP

Inrush

CurrentLimit

4.7nF

22 H–
100 Hmm

4.7nF

5kW

12kW

R1

R2

L

C

470nF

2.2nF–150nF

Charge

Pump

Bandgap

Ref

V

logic

A

IN

Vbattery

22µF–470µF

1µF–100µF

ExternalSchottky

DiodeRequired,

Max.0.4V

@1 A

@125ºC

Low-PowerMode

DigitalSignal

5kW

TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR

SLIS125 – DECEMBER 2006

NOTE: All component values are typical.

2

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Table 1. Terminal Functions

TERMINAL

NAME NO. I/O

SCR1 1 I Programmable slew-rate control
Cboot2 2 I External bootstrap capacitor
Cboot1 3 I External bootstrap capacitor

V

driver

L1 5 I Inductor input (an external Schottky diode

PGND 6 I Power ground

L2 7 I Inductor output

V

OUT

5Vg 9 O Switched 5-V supply

A

IN

CLP 11 I/O Low-power operation mode (digital input)

RESET 12 O Reset function (open drain)

A

OUT

REST 14 O Programmable reset timer delay

R

mod

GND 16 I Ground
V

logic

ENABLE 18 I Switch-mode regulator enable/disable

5Vg_ENABLE 19 I Switched 5-V voltage regulator output enable/disable

SCR0 20 I Programmable slew-rate control

(1) Maximum 0.4 V @ 1 A @ 125°C

4 I Input voltage source

8 O 5-V regulated output

10 I Programmable alarm setting

13 O Alarm output (open drain)

15 I Main switching frequency modulation setting to minimize EMI

17 O Supply decoupling output (may be used as a 5-V supply for logic-level inputs)

Exposed thermal pad of the package should be connected to GND or left floating.

BUCK/BOOST SWITCH-MODE REGULATOR

DESCRIPTION

(1)

to GND must be connected to L1)

TPIC74100-Q1

SLIS125 – DECEMBER 2006

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TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR

SLIS125 – DECEMBER 2006

ABSOLUTE MAXIMUM RATINGS

over recommended operating free-air temperature range (unless otherwise noted)

Unregulated input voltage, V
Unregulated inputs, V

, V

(AIN)

Bootstrap voltages V

Switch mode voltages V

Logic input voltages, V
Low output voltages, V

(Rmod)

(RESET)

Electrostatic-discharge V
susceptibility

Thermal impedance, junction-to-case, R
Thermal impedance, R

junction-to-ambient
Continuous power dissipation, P

Operating virtual junction temperature range, T
Operating ambient temperature range, T
Storage temperature range, T
Lead temperature (soldering, 10 s), T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground.
(3) The human body model is a 100-pF capacitor discharged through a 1.5-k Ω resistor into each terminal.
(4) The thermal data is based on using 2-oz. copper trace with at least four square inches of copper footprint for heat dissipation. The

copper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated.
(5) The thermal data is based on using 1-oz. copper trace with at least four square inches of copper footprint for heat dissipation. The

copper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated.

(2)

(driver)

(2)

(ENABLE)

(Cboot1)

V

(Cboot2)
(L1)

V

(L2)

,V

,V

,V

(4)

(CLP)

, and V

, and V

(5Vg_ENABLE)
(2)

(REST)

J

(SCR0)

(SCR1)

,V

,V

(AOUT)

(logic)
(3)

(HBMESD)

V

(HBMESD)

θ JA

R

θ JA

D

stg

, pin 7 (L2), pin 8 (V

(3)

, pins 1–6 and 10–20 2 kV

θ JC

(4)
(5)

A

(LEAD)

(2)

), pin 9 (5Vg) 800 V

OUT

(1)

–0.5 V to 40 V
–0.5 V to 40 V

See Dissipation

–40°C to 150°C
–40°C to 125°C
–65°C to 125°C

52 V
14 V

–1 V to 40 V

–1 V to 7 V
–0.5 V to 7 V
–0.5 V to 7 V

2°C/W
32°C/W
40°C/W

Rating Table

260°C

DISSIPATION RATING TABLE

R

32°C/W 3.9 W 31.25 mW/°C 2.03 W 0.781 W
40°C/W 3.125 W 25 mW/°C 1.625 W 0.625 W

TA≤ 25°C Power Rating Derating Factor Above TA= 25°C TA= 85°C Power Rating TA= 125°C Power Rating

θ JA

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Unregulated input voltage, V
Unregulated input voltages, V

Switch-mode terminals V

Bootstrap voltages V

Logic levels (I/O), V
V

(REST)

(Rmod)

Operating ambient temperature range, T
Logic levels (I/O), V

(SCR0)

4

(driver)

and V

(AIN)

, V

(logic)

, V

(SCR1)

(ENABLE)

V

(L1)

V

(L2)

V

(Cboot1)

V

(Cboot2)

,V

,V

(SCR0)

(SCR1)

A

, V

directly connected to V

(CLP)

,V

(5Vg_ENABLE)

,V

, V

(RESET)

(logic)

, V

(AOUT)

, and

(CLP)

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6 24 V
0 24 V

–1 17

5 5.5

V

+ 10

(driver)

0 5.25 V

–40 125 °C

V

(logic)

V

(logic)

8

V

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BUCK/BOOST SWITCH-MODE REGULATOR

ELECTRICAL CHARACTERISTICS

V

= 6 V to 17 V, TA= -40°C to 125°C, unless otherwise noted

(driver)

Parameters TEST CONDITIONS Min Typ Max Unit

V

(driver)

V

(driver)

S

OM

I

(standby)

I

q

V

O

V

O

I

O

I

O(Boost)

I

PPn

I

PPl

I

P

V

(driver)

T

ot

5Vg Output and ENABLE

r

DS(on)

I

O

V

I

V

IH

V

IL

V

(hys)

r

(pd)

ENABLE

V

I

V

IH

V

IL

V

(hys)

(1) Ensured by characterization.
(2) Tested with inductor having following characteristics: L = 33 µH, R

when inductor R
(3) Ensured by characterization. For further details, see the Buck/Boost Transitioning section.
(4) Ensured by characterization; hysteresis 15°C (typical)

Unregulated input voltage 1.5 40 V
Start-up condition voltage IO= 600 mA 5 V

CO= 36 µF (min) to 220 µF (max) 4 20

Soft-start ramp V/ms

CO= 220 µF (min) to 470 µF (max), see

(1)

Note
Standby current ENABLE = low 10 20 µA
Quiescent current CLP = 0 V, V

= 11 V, IO= 0 mA 100 160 µ A

(driver)

Output voltage DC 5 V

Normal mode 2%
Output-voltage tolerance

Boost/buck crossover or low-power

mode
Output current V

Output current, boost mode mA

Internal peak current limit (normal
mode)

Internal peak current limit (low-power
mode)

Peak current V
Boost/buck crossover voltage

window
Thermal shutdown

(4)

≥ 7 V 1 A

(driver)

V

= 2 V, see Note

(driver)

V

= 1.5 V, see Note

(driver)

(1)

(1)

= 16 V, IO= 1 A, and L = 33 µH 1.5 A

(driver)

See Note

(3)

On-state resistance 135 225 m Ω
Output current 400 mA
5Vg_ENABLE input-voltage range –0.5 V
5Vg_ENABLE threshold high voltage V
5Vg_ENABLE threshold low voltage V

= 5 V 2.5 3 3.5 V

(5Vg)

= 0 V 1.5 2 2.5 V

(5Vg)

Hysteresis voltage 0.5 1 V
Internal pulldown resistor 300 500 850 k Ω

ENABLE input-voltage range –0.5 40 V

ENABLE threshold high voltage V

8 V ≤ V

6 V ≤ V

≤ 17 V 2.5 3 3.5

(driver)

< 8 V 1.9 3 3.5

(driver)

ENABLE threshold low voltage VO= 5 V 1.5 2 2.5 V

Hysteresis voltage V

(ESR) is increased.

max

8 V ≤ V

6 V ≤ V

≤ 17 V 0.5 1

(driver)

< 8 V 0.1

(driver)

= 0.1 Ω , IR= 1.8 A. Output current must be verified in application

max

TPIC74100-Q1

SLIS125 – DECEMBER 2006

2 20

3%

(2)

(2)

1.75 2.5 A

0.75 1.25

5 5.9 V

160 180 200 °C

200
120

O

V

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TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR

SLIS125 – DECEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

V

= 6 V to 17 V, TA= -40°C to 125°C, unless otherwise noted

(driver)

Parameters TEST CONDITIONS Min Typ Max Unit

RESET

V

(th)

V

(RESET)

t

(RESET)

V

OL

t

(deglitch)

Alarm

V

I

V

IL

V

IH

V

(hys)

V

OL

Low-Power Mode (Pulse Mode) PFM

I

O(LPM)

I

I(avg)

V

O

Digital Low-Power Mode (CLP)

V

IH

V

IL

Switching Parameters

f

(sw)

f

(sw)ac

f

(sw)min

f

(sw)max

f

(mod)span

f

(mod)

f

(mod)ac

RESET threshold voltage 4.51 4.65 4.79 V
RESET tolerance 3%

RESET time ms

RESET output low voltage mV

RESET deglitch time See Note

Alarm input-voltage range –0.5 40 V
Alarm threshold low voltage 2.2 2.3 2.35 V
Alarm threshold high voltage 2.43 2.5 2.58 V
Hysteresis voltage 200 mV

Alarm output low voltage mV

Load current in low-power mode V
Average input current V
Output-voltage tolerance VO= 5 V 2.4% 3%

High-level CLP input threshold
voltage

Low-level CLP input threshold
voltage

Switching frequency V

Operating-frequency accuracy

Modulation minimum frequency 270 330 445 kHz
Modulation maximum frequency 450 550 680 kHz
Modulation span 220 kHz
Modulation frequency R
Modulation-frequency accuracy 12%

C

= 10 nF 8 10 12

(REST)

C

= 100 nF, see Note

(REST)

I

= 5 mA 450

sink

I

= 1 mA 84

sink

I

sink

I

sink

(5)

= 5 mA 450
= 1 mA 84

< 7 V 50 mA

(driver)

= 11 V, IO= 5 mA, CLP = low 3.55 mA

(driver)

(5)

80 100 120

8 10 12.5 µs

Normal mode 2.6 V

Low-power mode 1.15 V

= 0 V, modulator OFF 440 kHz

(Rmod)

f

= 440 kHz 18%

(sw)

f

= 440 kHz 20%

(sw)

= 12 k Ω ±1% 28 kHz

mod

(5) Ensured by characterization.

6

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I

OUT

D * D

2

Ǹ

Upper:

Lower:

V =2.5V×

(driver)

R1+R2

R1

V =2.3V×

(driver)

R1+R2

R1

.

TPIC74100-Q1

BUCK/BOOST SWITCH-MODE REGULATOR

SLIS125 – DECEMBER 2006

PRINCIPLES OF OPERATION

Functional Principle

The TPIC74100-Q1 is a buck/boost switch-mode regulator that operates in a power-supply concept to ensure a
stable output voltage with input voltage excursions and specified load range.

The device provides an alarm indicator and reset output to interface with systems that require supervisory
function.

The switching regulator offers a clock modulator and a current-mode slew-rate control for the internal switching
transistor (Q1) to minimize EMI.

An internal low-r
output.

Description of the Functional Terminals

Switch-Mode Input/Output Terminals (L1, L2)

The external inductor for the switch-mode regulator is connected between terminals L1 and L2. This inductor is
placed close to the terminals to minimize parasitic effects. For stability, an inductor with 20 µ H to 100 µ H should
be used.

switch has a current-limit feature to prevent inadvertent reset when turning on the 5Vg

DS(on)

Supply Terminal (V

The input voltage of the device is connected to the V

)

driver

terminal. This input line requires a filter capacitor to

driver

minimize noise. A low-ESR aluminum or tantalum input capacitor is recommended. The relevant parameters for
the input capacitor are the voltage rating and RMS current rating. The voltage rating should be approximately

1.5 times the maximum applied voltage for an aluminum capacitor and 2 times for a tantalum capacitor. In buck
mode, the RMS current is

reached when D = 50% with I

RMS

, where D is the duty cycle and its maximum RMS current value is

= I

/2. In boost mode, the RMS current is 0.3 × ∆ I, where ∆ I is the

OUT

peak-to-peak ripple current in the inductor. To achieve this, ESR ceramic capacitors are used in parallel with the
aluminum or tantalum capacitors.

Internal Supply Decoupling Terminal (V

The V

terminal is used to decouple the internal power-supply noise by use of a 470-nF capacitor. This

logic

)

logic

terminal can also be used as an output supply for the logic-level inputs for this device (SCR0, SCR1, ENABLE,
CLP, and 5Vg_ENABLE).

Input Voltage Monitoring Terminal (A

The A

terminal is used to program the threshold voltage for monitoring and detecting undervoltage conditions

IN

)

IN

on the input supply. A maximum of 40 V may be applied to this terminal and the voltage at this terminal may
exceed the V

input voltage without effecting the device operation. The resistor divider network is

(driver)

programmed to set the undervoltage detection threshold on this terminal (see the application schematic). The
input has a typical hysteresis of 200 mV with a typical upper limit threshold of 2.5 V and a typical lower limit
threshold of 2.3 V. When V

falls below 2.3 V, V

(AIN)

is asserted low; when V

(AOUT)

exceeds 2.5 V, V

(AIN)

(AOUT)

the high-impedance state.
The equations to set the upper and lower thresholds of V

are:

(AIN)

is in

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TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR

SLIS125 – DECEMBER 2006

PRINCIPLES OF OPERATION (continued)

Input Undervoltage Alarm Terminal (A

The A
on the A

terminal is an open-drain output that asserts low when the input voltage falls below the set threshold

OUT

input.

IN

Reset Delay Timer Terminal (REST)

The REST terminal sets the desired delay time to assert the RESET terminal low after the 5-V supply has
exceeded 4.65 V (typical). The delay can be programmed in the range of 2.2 ms to 150 ms using capacitors in
the range of 2.2 nF to 150 nF. The delay time is calculated using the following equation:

RESET delay = C

(REST)

× 1 ms, where C

Reset Terminal (RESET)

The RESET terminal is an open-drain output. The power-on reset output is asserted low until the output voltage
exceeds the 4.65-V threshold and the reset delay timer has expired. Additionally, whenever the ENABLE
terminal is low, RESET is immediately asserted low regardless of the output voltage.

)

OUT

has nF units

(REST)

Main Regulator Output Terminal (V

The V

terminal is the output of the switch-mode regulated supply. This terminal requires a filter capacitor with

OUT

)

OUT

low-ESR characteristics to minimize output ripple voltage. For stability, a capacitor with 22 µ F to 470 µ F should
be used. The total capacitance at pin V

and pin 5Vg must be less than or equal to 470 µ F.

OUT

Low-Power-Mode Terminal (CLP)

The CLP terminal controls the low-power mode of the device. An external low digital signal switches the device
to low-power mode or normal mode when the input is high.

Switch-Output Terminal (5Vg)

The 5Vg terminal switches the 5-V regulated output. The output voltage of the regulator can be enabled or
disabled using this low-r

internal switch. This switch has a current-limiting function to prevent generation of

DS(on)

a reset signal at turnon caused by the capacitive load on the output or overload condition. When the switch is
enabled, the regulated output may deviate and drop momentarily to a tolerance of 7% until the 5Vg capacitor is
fully charged. This deviation depends on the characteristics of the capacitors on V

and 5Vg.

OUT

5Vg-Enable Terminal (5Vg_ENABLE)

The 5Vg_ENABLE is a logic-level input for enabling the switch output on 5Vg.
For the functional terminal, 5Vg_ENABLE results in the following table:

5Vg_ENABLE Function

0 5Vg is off

Open (internal pulldown = 500 k Ω ) 5Vg is off

1 5Vg is on

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S0174-01

5Vg_ENABLE

Switch

Control

PeakCurrentLimit

Gate

Driver

5

Vg

Q1

Q2

Q3

Q4

V

driver

L1 L2

33µH

V

OUT

V

OUT

47µF

100µF

5

Vg

SlewRateControl

RESET

ChargePump

RESET Deglitch

RESET

typ~V – 100mV

OUT

V

OUT

typ4.65V

Buck/Boost

GateDriver

BUCK/BOOST SWITCH-MODE REGULATOR

TPIC74100-Q1

SLIS125 – DECEMBER 2006

Figure 1. Current-Limit Switched Output 5Vg

Slew-Rate Control Terminals (SCR0, SCR1)

The slew rate of the switching transistor Q1 is set using the SCR0 and SCR1 terminals.
The following table shows the values of the slew rate (SR):

SCR1 SCR0 SR

0 0 Slow
0 1 Medium-slow
1 0 Medium-fast
1 1 Fast

Q1

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