TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low r
DS(on)
...7 Ω Typ
D
Avalanche Energy ...30 mJ
D
Eight Power DMOS Transistor Outputs of
100-mA Continuous Current
D
250-mA Current Limit Capability
D
ESD Protection . . . 2500 V
D
Output Clamp Voltage . . . 33 V
D
Devices Are Cascadable
D
Low Power Consumption
description
The TPIC6C595 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other low-current or
medium-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock
(RCK), respectively . The device transfers data out
the serial output (SER OUT) port on the rising
edge of SRCK. The storage register transfers data
to the output buffer when shift register clear (CLR
)
is high. When CLR is low, the input shift register is
cleared. When output enable (G
) is held high, all
data in the output buffers is held low and all drain
outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When
data in the output buffers is low , the DMOS transistor outputs are off. When data is high, the DMOS transistor
outputs have sink-current capability. The SER OUT allows for cascading of the data from the shift register to
additional devices.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
logic symbol
†
2
SRG8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
8
10
7
15
2
EN3
C2
R
C1
1D
G
RCK
CLR
SRCK
SER IN
3
5
4
11
6
13
12
9
14
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
G
GND
SRCK
DRAIN7
DRAIN6
DRAIN5
DRAIN4
RCK
SER OUT
D OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous
sink-current capability . Each output provides a 250-mA maximum current limit at TC = 25°C. The current limit
decreases as the junction temperature increases for additional device protection. The device also provides up
to 2500 V of ESD protection when tested using the human-body model and 200 V machine model.
The TPIC6C595 is characterized for operation over the operating case temperature range of –40°C to 125°C.
logic diagram (positive logic)
G
RCK
CLR
SRCK
SER IN
CLR
D
C1
D
C2
CLR
D
C1
SER OUT
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
3
DRAIN0
4
DRAIN1
16
GND
5
DRAIN2
6
DRAIN3
11
DRAIN4
12
DRAIN5
13
DRAIN6
14
DRAIN7
8
7
2
10
15
9
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
V
CC
Input
GND
GND
DRAIN
33 V
20 V
25 V
12 V
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)
†
Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, VI –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, VDS (see Note 2) 33 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode anode current 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-to-drain diode anode current (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, I
D
, T
C
= 25°C (see Note 3) 250 mA. . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, ID, TC = 25°C 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current single output, IDM,T
C
= 25°C (see Note 3) 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, EAS (see Figure 4) 30 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, I
AS
(see Note 4) 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 125°C
POWER RATING
D 1087 mW 8.7 mW/°C 217 mW
N 1470 mW 11.7 mW/°C 294 mW
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
Logic supply voltage, V
CC
4.5 5.5 V
High-level input voltage, V
IH
0.85 V
CC
V
Low-level input voltage, V
IL
0.15 V
CC
V
Pulsed drain output current, TC = 25°C, VCC = 5 V , all outputs on (see Notes 3 and 5 and Figure 11) 250 mA
Setup time, SER IN high before SRCK↑, tsu (see Figure 2) 20 ns
Hold time, SER IN high after SRCK↑, th (see Figure 2) 20 ns
Pulse duration, tw (see Figure 2) 40 ns
Operating case temperature, T
C
–40 125 °C
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-to-source breakdown voltage ID = 1 mA 33 37 V
V
SD
Source-to-drain diode forward voltage IF = 100 mA 0.85 1.2 V
p
IOH = –20 µA, VCC = 4.5 V 4.4 4.49
VOHHigh-level output voltage, SER OUT
IOH = –4 mA, VCC = 4.5 V 4 4.2
V
p
IOL = 20 µA, VCC = 4.5 V 0.005 0.1
VOLLow-level output voltage, SER OUT
IOL = 4 mA, VCC = 4.5 V 0.3 0.5
V
I
IH
High-level input current VCC = 5.5 V, VI = V
CC
1 µA
I
IL
Low-level input current VCC = 5.5 V, VI = 0 –1 µA
pp
All outputs off 20 200
ICCLogic supply current
V
CC
=
5.5 V
All outputs on 150 500
µ
A
I
CC(FRQ)
Logic supply current at frequency
f
SRCK
= 5 MHz,
All outputs off,
CL = 30 pF,
See Figures 2 and 6
1.2 5 mA
I
N
Nominal current
V
DS(on)
= 0.5 V,
TC = 85°C,
IN = ID,
See Notes 5, 6, and 7
90 mA
VDS = 30 V, VCC = 5.5 V 0.1 5
I
DSX
Off-state drain current
VDS = 30 V,
TC = 125°C
VCC = 5.5 V,
0.15 8
µA
ID = 50 mA,
VCC = 4.5 V
6.5 9
r
DS(on)
Static drain-source on-state resistance
ID = 50 mA,
TC = 125°C,
VCC = 4.5 V
See Notes 5 and 6
and Figures 7 and 8
9.9 12
Ω
ID = 100 mA,
VCC = 4.5 V
6.8 10
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output from G 80 ns
t
PHL
Propagation delay time, high-to-low-level output from G
50 ns
tpd Propagation delay time, SRCK to SEROUT
CL = 30 pF, ID = 75 mA,
20 ns
t
r
Rise time, drain output
See Figures 1, 2, and 9
100 ns
t
f
Fall time, drain output 80 ns
t
a
Reverse-recovery-current rise time
I
= 100 mA, di/dt = 10 A/µs,
100
t
rr
Reverse-recovery time
F
, µ ,
See Notes 5 and 6 and Figure 3
120
ns
NOTES: 5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
D package
p
p
115
°
R
θJA
Thermal resistance, junction-to-ambient
N package
All 8 outputs with equal power
85
°C/W
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
5 V
V
CC
DRAIN
GND
CLR
SER IN
RL = 200 Ω
CL = 30 pF
(see Note B)
VOLTAGE WAVEFORMS
G
Output
SRCK
RCK
Word
Generator
(see Note A)
76543210
5 V
SRCK
5 V
G
5 V
SER IN
RCK
CLR
5 V
5 V
DUT
15 V
DRAIN1
15 V
0 V
0 V
0 V
0.5 V
0 V
16
7
15
2
10
8
0 V
3–6,
11–14
I
D
1
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3–6,
11–14
TEST CIRCUIT
SWITCHING TIMES
G
5 V
50%
24 V
0.5 V
90%
10%
t
PLH
t
r
50%
90%
10%
t
PHL
t
f
SRCK
5 V
50%
SER IN
5 V
50%
50%
t
su
t
h
t
w
INPUT SETUP AND HOLD WAVEFORMS
5 V 15 V
V
CC
DRAIN
CLR
SER IN
RL = 200 Ω
CL = 30 pF
(see Note B)
G
Output
SRCK
RCK
DUT
GND
Output
Word
Generator
(see Note A)
16
7
15
2
10
8
0 V
0 V
0 V
I
D
1
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
0.1 A
I
F
0
I
RM
25% of I
RM
t
a
t
rr
di/dt = 10 A/µs
+
–
2500 µF
250 V
L = 0.85 mH
I
F
(see Note A)
R
G
V
GG
(see Note B)
Driver
TP A
50 Ω
Circuit
Under
Test
DRAIN
15 V
t
1
t
3
t
2
TP K
TEST CIRCUIT CURRENT WAVEFORM
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 10 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
15 V
30 Ω
1.5 H
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
t
w
t
av
IAS = 200 mA
V
(BR)DSX
= 33 V
VOLTAGE AND CURRENT WAVEFORMS
Input
I
D
V
DS
See Note B
V
CC
DRAIN
CLR
SER IN
G
SRCK
RCK
Word
Generator
(see Note A)
DUT
GND
5 V
V
DS
I
D
1
7
15
2
10
8
16
3–6,
11–14
5 V
0 V
MIN
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 200 mA.
Energy test level is defined as EAS = IAS × V
(BR)DSX
× tav/2 = 30 mJ.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
Figure 5
0.2
0.1
1
0.4
0.1 0.2 10.4 2 104
0.02
0.01
0.04
I – Peak Avalanche Current – A
AS
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
tav – Time Duration of Avalanche – ms
TC = 25°C
3
2
1
0
4
5
6
Figure 6
I – Supply Current – mA
CC
SUPPLY CURRENT
vs
FREQUENCY
f – Frequency – MHz
0.1 1 10 100
VCC = 5 V
TC = –40°C to 125°C
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 7
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
ID – Drain Current – mA
Ω
DS(on)
– Drain-to-Source On-State Resistance –r
10
5
0
50 70 90 110 130
15
20
25
150 170 190
VCC = 5 V
See Note A
TC = 25°C
TC = –40°C
TC = 125°C
250
30
Figure 8
VCC – Logic Supply Voltage – V
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
Ω
DS(on)
– Static Drain-to-Source On-State Resistance –r
6
4
2
0
4 4.5 5 5.5
8
10
12
6 6.5 7
TC = 125°C
TC = 25°C
TC = – 40°C
ID = 50 mA
See Note A
Switching Time – ns
SWITCHING TIME
vs
CASE TEMPERATURE
TC – Case Temperature – °C
80
40
20
0
–50 –25 0 25
100
120
140
50 100 125
60
75
ID = 75 mA
See Note A
t
PHL
t
PLH
t
r
t
r
Figure 9
NOTE A: Technique should limit TJ – TC to 10°C maximum.
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
Figure 10
– Maximum Continuous Drain Current
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
N – Number of Outputs Conducting Simultaneously
of Each Output – A
D
I
VCC = 5 V
TC = 25°C
TC = 125°C
TC = 100°C0.1
0.05
0
12 3 4
0.15
0.2
0.25
5867
Figure 11
– Maximum Peak Drain Current of Each Output – A
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
D
N – Number of Outputs Conducting Simultaneously
I
0.1
0.05
0.25
0
12 34 5
0.2
0.3
678
0.15
VCC = 5 V
TC = 25°C
d = tw/t
period
= 1 ms/t
period
d = 10%
d = 20%
d = 50%
d = 80%
TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A – JULY 1998 – REVISED JULY 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
D P ACKAGE
†
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
0.1
10
1
0.01
0.001
0.0001
DC Conditions
d = 0.5
d = 0.2
d = 0.1
d = 0.02
d = 0.05
d = 0.01
tw – Pulse Duration – s
0.0001 0.001 0.01 0.1 1 10
t
w
t
c
I
D
0
Single Pulse
JAθ
– Normalized Junction-to-Ambient Thermal Resistance –
R
†
Device mounted on FR4 printed-circuit board with no heat sink
NOTES: ZθA(t) = r(t) R
θJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/t
c
C/W
°
Figure 12
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accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 2000, Texas Instruments Incorporated
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