Texas Instruments TPIC1501ADWR, TPIC1501ADW Datasheet

TPIC1501A

QUAD AND HEX POWER DMOS ARRAY

SLIS046A – MAY 1995 – REVISED JUNE 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Low r

DS(on)

:

0.1 Ω Typ (Full H-Bridge)

0.4 Ω Typ (Triple Half H-Bridge)

D

Pulsed Current:

12 A Per Channel (Full H-Bridge)
6 A Per Channel (Triple Half H-Bridge)

D

Matched Sense Transistor for Class A-B
Linear Operation

D

Fast Commutation Speed

description

The TPIC1501A is a monolithic power array that
consists of ten electrically isolated N-channel
enhancement-mode power DMOS transistors, four
of which are configured as a full H-bridge and six as
a triple half H-bridge. The lower stage of the full
H-bridge features an integrated sense FET to allow
biasing of the bridge in class A-B operation.

The TPIC1501A is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for
operation over the case temperature range of –40°C to 125°C.

schematic

Q4B

GATE1A

17

OUTPUT1

19

GATE1B

21

Q2A

8

Q2B

6

4

D1

D2

GATE3A

22

OUTPUT3

1

GATE3B

3

D3

GATE4A

Q4A

18

OUTPUT4

11

GATE4B

7

GATE2A

OUTPUT2

GATE2B

Q3B

Q3A

15 10

Q1B

Q1A

Q5B

GATE5A

Q5A

16

OUTPUT5

13

GATE5B

9

14, 24

12

2, 23

GND

SOURCE

V

DD1

V

DD2

V

DD3

Q2C

20

5

GATE2C

SENSE

NOTES: A. Pins 2 and 23 must be externally connected.

B. Pins 14 and 24 must be externally connected.
C. No output may be taken greater than 0.5 V below GND.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1996, Texas Instruments Incorporated

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OUTPUT3

GND
GATE3B
GATE2B

SENSE

OUTPUT2

GATE4B
GATE2A
GATE5B

V

DD2

OUTPUT4

SOURCE

V

DD3

GND
GATE3A
GATE1B
GATE2C
OUTPUT1
GATE4A
GATE1A
GATE5A
V

DD1

V

DD3

OUTPUT5

DW PACKAGE

(TOP VIEW)

TPIC1501A
QUAD AND HEX POWER DMOS ARRAY

SLIS046A – MAY 1995 – REVISED JUNE 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings, TC = 25°C (unless otherwise noted)

†

Supply-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Source-to-GND voltage (Q3A, Q4A, Q5A) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sense-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate-to-source voltage range, V

GS

(Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) ±20 V. . . . .

Gate-to-source voltage range, V

GS

(Q2C) –0.7 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) 3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . .

Continuous drain current (Q2C) 15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) 3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1.5 A. . . . . . . . . . . . . . . . . . . . .

Continuous source-to-drain diode current (Q2C) 15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed drain current, each output, I

max

(Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) 12 A. . . . . . . .

Pulsed drain current, each output, I

max

(Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)

(see Note 1 and Figure 25) 6 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed drain current, I

max

(Q2C) (see Note 1) 60 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation, T

C

= 70°C (see Note 2 and Figures 24 and 25) 2.86 W. . . . . . . . . . . . .

Operating virtual junction temperature range, T

J

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating case temperature range, T

C

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%

2. Package is mounted in intimate contact with infinite heat sink.

TPIC1501A

QUAD AND HEX POWER DMOS ARRAY

SLIS046A – MAY 1995 – REVISED JUNE 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(BR)DSX

Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V

V

GS(th)

Gate-to-source threshold voltage

ID = 1 mA,
See Figure 5

VDS = VGS,

1.4 1.7 2.1 V

V

GS(th)match

Gate-to-source threshold voltage matching ID = 1 mA, VDS = V

GS

40 mV

V

(BR)

Reverse drain-to-GND breakdown voltage

Drain-to-GND current = 250 µA
(D1, D2)

20 V

V

DS(on)

Drain-to-source on-state voltage

ID = 2 A,
See Notes 3 and 4

VGS = 10 V,

0.2 0.24 V

V

F

Forward on-state voltage, GND-to-V

DD1

,

GND-to-V

DD2

ID = 3 A (D1, D2)
See Notes 3 and 4

1.8 V

IS = 2 A, VGS = 0,
See Notes 3 and 4 and Figure 19

0.85

1.05

V

F(SD)

Forward on-state voltage, source-to-drain

IS = 3 A, VGS = 0,

V

See Notes 3 and 4 and Figure 19

0.9

1.1

V

= 16 V,

TC = 25°C 0.05 1

I

DSS

Zero-gate-voltage drain current

DS

,

VGS = 0

TC = 125°C 0.5 10

µ

A

I

GSSF

Forward-gate current, drain short circuited
to source

VGS = 16 V, VDS = 0 10 100 nA

I

GSSR

Reverse-gate current, drain short circuited
to source

VSG = 16 V, VDS = 0 10 100 nA

Leakage current, V

-to-GND,

TC = 25°C 0.05 1

I

lkg

g,

DD1

,

V

DD2

-to-GND, gate shorted to source

V

DGND

= 16

V

TC = 125°C 0.5 10

µ

A

VGS = 10 V,
I

= 2 A,

TC = 25°C 0.1 0.12

D

,

See Notes 3 and 4
and Figure 9

TC = 125°C 0.14 0.18

r

DS(on)

Static drain-to-source on-state resistance

VGS = 10 V,
I

= 3 A,

TC = 25°C 0.1 0.12

Ω

D

,

See Notes 3 and 4
and Figures 7 and 9

TC = 125°C 0.14 0.18

VDS = 14 V,
See Notes 3 and 4

ID = 1 A,

1.5 2.5

g

fs

Forward transconductance

VDS = 14 V,

ID = 1.5 A,

S

See Notes 3 and 4 and Figure 13

2

3.1

C

iss

Short-circuit input capacitance, common
source

240

C

oss

Short-circuit output capacitance, common
source

VDS = 14 V,
f = 1 MHz,

VGS = 0,
See Figure 17

170

pF

C

rss

Short-circuit reverse transfer capacitance,
common source

130

α

s

Sense-FET drain current ratio VDS = 6 V, I

D(Q2C)

= 40 µA 75 130 200

NOTES: 3. Technique should limit TJ – TC to 10°C maximum.

4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

TPIC1501A
QUAD AND HEX POWER DMOS ARRAY

SLIS046A – MAY 1995 – REVISED JUNE 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

rr

Reverse-recovery time

IS = 1.5 A,

VGS = 0,

70 ns

Q

RR

Total diode charge

V

DS

= 14 V,

See Figures 1 and 23

di/dt

=

100 A/

µs,

90 nC

t

rr

Reverse-recovery time

IS = 2 A, VGS = 0,

75 ns

Q

RR

Total diode charge

S

VDS = 14 V,

GS

di/dt = 100 A/µs

110 nC

resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(on)

Turn-on delay time 20

t

d(off)

Turn-off delay time

V

= 14 V, R

= 9.3 Ω,t

= 10 ns,

30

t

r

Rise time

DD

,

t

dis

= 10 ns,

L

,

See Figure 3

en

,

15

ns

t

f

Fall time 25

Q

g

Total gate charge

5.6 7

Q

gs(th)

Threshold gate-to-source charge

VDS = 14 V,

ID = 1.5 A, VGS = 10 V,

0.8 1

nC

Q

gd

Gate-to-drain charge

See Figure 4

1.4 1.75

L

(drain)

Internal drain inductance 5

L

(source)

Internal source inductance 5

nH

r

(gate)

Internal gate resistance 0.25 Ω

TPIC1501A

QUAD AND HEX POWER DMOS ARRAY

SLIS046A – MAY 1995 – REVISED JUNE 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(BR)DSX

Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 V 20 V

V

GS(th)

Gate-to-source threshold voltage

ID = 1 mA,
See Figure 6

VDS = V

GS,

1.4 1.7 2.1 V

V

GS(th)match

Gate-to-source threshold voltage matching ID = 1 mA, VDS = V

GS

40 mV

V

(BR)

Reverse drain-to-GND breakdown voltage Drain-to-GND current = 250 µ A (D3) 20 V

V

DS(on)

Drain-to-source on-state voltage

ID = 1.5 A,
See Notes 3 and 4

VGS = 10 V,

0.6 0.68 V

V

F

Forward on-state voltage, GND-to-V

DD3

ID = 1.5 A (D3)
See Notes 3 and 4

1.7 V

IS = 1.5 A, VGS = 0,
See Notes 3 and 4 and Figure 20

1

1.2

V

F(SD)

Forward on-state voltage, source-to-drain

IS = 2 A, VGS = 0,

V

See Notes 3 and 4 and Figure 20

1.1

1.3

V

= 16 V,

TC = 25°C 0.05 1

I

DSS

Zero-gate-voltage drain current

DS

,

VGS = 0

TC = 125°C 0.5 10

µ

A

I

GSSF

Forward-gate current, drain short circuited
to source

VGS = 16 V, VDS = 0 10 100 nA

I

GSSR

Reverse-gate current, drain short circuited
to source

VSG = 16 V, VDS = 0 10 100 nA

Leakage current, V

-to-GND,

TC = 25°C 0.05 1

I

lkg

g,

DD3

,

gate shorted to source

V

DGND

=

16 V

TC = 125°C 0.5 10

µ

A

VGS = 10 V,
I

= 0.3 A,

TC = 25°C 0.35 0.39

D

,

See Notes 3 and 4
and Figure 10

TC = 125°C 0.5 0.56

r

DS(on)

Static drain-to-source on-state resistance

VGS = 10 V,
I

= 1.5 A,

TC = 25°C 0.4 0.45

Ω

D

,

See Notes 3 and 4
and Figures 8 and 10

TC = 125°C 0.56 0.65

VDS = 14 V, ID = 500 mA,
See Notes 3 and 4

0.3

0.8

g

f

s

Forward transconductance

VDS = 14 V, ID = 750 mA,
See Notes 3 and 4 and Figure 14

0.4 0.93

S

C

iss

Short-circuit input capacitance, common
source

96

C

oss

Short-circuit output capacitance, common
source

VDS = 14 V,
f = 1 MHz,

VGS = 0,
See Figure 18

98

pF

C

rss

Short-circuit reverse transfer capacitance,
common source

65

NOTES: 3. Technique should limit TJ – TC to 10°C maximum.

4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

TPIC1501A
QUAD AND HEX POWER DMOS ARRAY

SLIS046A – MAY 1995 – REVISED JUNE 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

rr

Reverse-recovery time

IS = 750 mA,

VGS = 0,

60 ns

Q

RR

Total diode charge

V

DS

= 14 V,

See Figures 2 and 23

di/dt

=

100 A/

µs,

55 nC

t

rr

Reverse-recovery time

IS = 1.5 A, VGS = 0,

120 ns

Q

RR

Total diode charge

S

VDS = 14 V,

GS

di/dt = 100 A/µs

150 nC

resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(on)

Turn-on delay time 18

t

d(off)

Turn-off delay time

V

= 14 V, R

= 18.7 Ω,t

= 10 ns,

25

t

r

Rise time

DD

,

t

dis

= 10 ns,

L

,

See Figure 3

en

,

13

ns

t

f

Fall time 20

Q

g

Total gate charge

1.6 2

Q

gs(th)

Threshold gate-to-source charge

VDS = 14 V,

ID = 750 mA, VGS = 10 V,

0.26 0.32

nC

Q

gd

Gate-to-drain charge

See Figure 4

0.42 0.52

L

(drain)

Internal drain inductance 5

L

(source)

Internal source inductance 5

nH

r

(gate)

Internal gate resistance 0.25 Ω

thermal resistance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R

θJA

Junction-to-ambient thermal resistance See Notes 5 and 8 90

R

θJB

Junction-to-board thermal resistance See Notes 6 and 8 38

°C/W

R

θJP

Junction-to-pin thermal resistance See Notes 7 and 8 28

NOTES: 5. Package is mounted on a FR4 printed-circuit board with no heat sink.

6. Package is mounted on a 24 in2, 4-layer FR4 printed-circuit board.

7. Package is mounted in intimate contact with infinite heat sink.

8. All outputs have equal power.