TEXAS INSTRUMENTS TPIC1021A-Q1 Technical data

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FEATURES

RXD

TXD

NWake

INH

LIN

GND

Receiver

Filter

TPIC1021A

SUP

Wake Up, State,

and INH Control

Fault

Detection

and Protection

Driver With Slope Control

Dominant

State

Timeout

SUP

Filter

• LIN Physical Layer Specification Revision 2.0 • Dominant State Timeout Protection

Compliant and Conforms to SAEJ2602 Recommended Practice for LIN

• LIN Bus Speed up to 20-kbps LIN Specified

Maximum

• Sleep Mode: Ultralow Current Consumption,

Allows Wake-Up Events From LIN Bus, Wake-Up Input (External Switch), or Host MCU

• High-Speed Receive Capable

• ESD Protection to ± 12 kV (Human-Body

Model) on LIN Pin

• LIN Pin Handles Voltage From –40 V to 40 V

• Survives Transient Damage in Automotive

Environment (ISO 7637)

• Extended Operation With Supply From 7 V to

27 V DC (LIN Specification 7 V to 18 V)

• Interfaces to MCU With 5-V or 3.3-V I/O Pins

• Wake-Up Request on RXD Pin

• Control of External Voltage Regulator

(INH Pin)

• Integrated Pullup Resistor and Series Diode

for LIN Slave Applications

• Low Electromagnetic Emission (EME), High

Electromagnetic Immunity (EMI)

• Bus Terminal Short Circuit Protected for

Short to Battery or Short to Ground

• Thermally Protected

• Ground Disconnection Fail Safe at System

Level

• Ground Shift Operation at System Level

• Unpowered Node Does Not Disturb the

Network

• Supports ISO9141 (K-Line)-Like Functions

TPIC1021A-Q1

LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

FUNCTIONAL BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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1 2 3 4

8 7 6 5

RXD

NWake

TXD

INH V

SUP

LIN GND

D PACKAGE

(TOP VIEW)

TPIC1021A-Q1 LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

DESCRIPTION

The TPIC1021A is the Local Interconnect Network (LIN) physical interface, which integrates the serial transceiver with wake-up and protection features. The LIN bus is a single-wire bidirectional bus typically used for low-speed in-vehicle networks using data rates between 2.4 kbps and 20 kbps. The LIN protocol output data stream on TXD is converted by the TPIC1021A into the LIN bus signal through a current-limited wave-shaping driver as outlined by the LIN Physical Layer Specification Revision 2.0. The receiver converts the data stream from the LIN bus and outputs the data stream via RXD. The LIN bus has two states: dominant state (voltage near ground) and the recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the TPIC1021A’s internal pullup resistor (30 k Ω ) and series diode, so no external pullup components are required for slave applications. Master applications require an external pullup resistor (1 k Ω ) plus a series diode per the LIN specification.

In sleep mode, the TPIC1021A requires low quiescent current even though the wake-up circuits remain active, allowing for remote wake up via the LIN bus or local wake up via the NWake or EN pins.

The TPIC1021A has been designed for operation in the harsh automotive environment. The device can handle LIN bus voltage swings from 40 V down to ground and survive –40 V. The device also prevents back-feed current through LIN to the supply input, in case of a ground shift or supply voltage disconnection. It also features undervoltage, overtemperature, and loss-of-ground protection. In the event of a fault condition, the output is immediately switched off and remains off until the fault condition is removed.

TERMINAL FUNCTIONS

TERMINAL ASSIGNMENTS

NAME NO.

RXD 1 O RXD output (open drain) interface reporting state of LIN bus voltage EN 2 I Enable input NWake 3 I High voltage input for device wake up TXD 4 I TXD input interface to control state of LIN output GND 5 GND Ground LIN 6 I/O LIN bus single-wire transmitter and receiver V

SUP

INH 8 O Inhibit controls external voltage regulator with inhibit input

PART NUMBER PACKAGE

TPIC1021A-Q1 SOIC-8 – D TPIC1021AQDRQ1 (reel) T1021A

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .

7 Supply Device supply voltage (connected to battery in series with external reverse blocking diode)

TYPE DESCRIPTION

ORDERING INFORMATION

(2)

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

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TPIC1021A-Q1

LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

Local Interconnect Network (LIN) Bus

This I/O pin is the single-wire LIN bus transmitter and receiver.

Transmitter Characteristics

The driver is a low-side transistor with internal current limitation and thermal shutdown. There is an internal 30-k Ω pullup resistor with a serial diode structure to V slave mode applications. An external pullup resistor of 1 k Ω , plus a series diode to V the device is used for master node applications.

Voltage on LIN can go from –40-V to 40-V dc without any currents other than through the pullup resistance. There are no reverse currents from the LIN bus to supply (V supply (V

SUP

The LIN thresholds and ac parameters are LIN Protocol Specification Revision 2.0 compliant. During a thermal shut down condition the driver is disabled.

Receiver Characteristics

The receiver’s characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%, with a hysteresis between 5% and 17.5% of supply.

The receiver is capable of receiving higher data rates (>100 kbps) than supported by LIN or SAEJ2602 specifications. This allows the TPIC1021A to be used for high-speed downloads at end-of-line production or other applications. The actual data rates acheivable depend on system time constants (bus capacitance and pullup resistance) and driver characteristics used in the system.

, so no external pullup components are required for LIN

SUP

), even in the event of a ground shift or loss of

SUP

must be added when

SUP

Transmit Input (TXD)

TXD is the interface to the MCU’s LIN protocol controller or SCI/UART used to control the state of the LIN output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is recessive (near battery). The TXD input structure is compatible with microcontrollers with 3.3-V and 5-V I/O. TXD has an internal pulldown resistor.

TXD Dominant State Timeout

If TXD is inadvertently driven permanently low by a hardware or software application failure, the LIN bus is protected by TPIC1021A’s dominant state timeout timer. This timer is triggered by a falling edge on TXD. If the low signal remains on TXD for longer than t

, the transmitter is disabled, thus allowing the LIN bus to return to

DST

the recessive state and communication to resume on the bus. The timer is reset by a rising edge on TXD.

Receive Output (RXD)

RXD is the interface to the MCU’s LIN protocol controller or SCI/UART, which reports the state of the LIN bus voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground) is represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the TPIC1021A to be used with 3.3-V and 5-V I/O microcontrollers. If the microcontroller’s RXD pin does not have an integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required.

RXD Wake-up Request

When the TPIC1021A has been in low-power mode and encounters a wake-up event from the LIN bus or NWake pin, RXD goes low, while the device enters and remains in standby mode (until EN is reasserted high and the device enters normal mode).

Supply Voltage (V

is the TPIC1021A device power supply pin. V

SUP

)

SUP

is connected to the battery through an external reverse

SUP

battery blocking diode. The continuous dc-operating voltage range for the TPIC1021A is from 7 V to 27 V. V is protected for harsh automotive conditions up to 40 V.

The device contains a reset circuit to avoid false bus messages during undervoltage conditions when V less than V

SUP_UNDER

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SUP

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TPIC1021A-Q1 LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

Ground (GND)

GND is the TPIC1021A device ground connection. The TPIC1021A can operate with a ground shift as long as the ground shift does not reduce V ECU level, the TPIC1021A does not have a significant current consumption on LIN bus.

Enable Input (EN)

EN controls the operation mode of the TPIC1021A (normal or sleep mode). When EN is high, the TPIC1021A is in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep mode and there are no transmission paths available. The device can enter normal mode only after being woken up. EN has an internal pulldown resistor to ensure the device remains in low-power mode even if EN floats.

NWake Input (NWake)

NWake is a high-voltage input used to wake up the TPIC1021A from low-power mode. NWake is usually connected to an external switch in the application. A low on NWake that is asserted longer than the filter time (t

) results in a local wake-up. NWake provides an internal pullup source to V

NWAKE

Inhibit Output (INH)

INH is used to control an external voltage regulator that has an inhibit input. When the TPIC1021A is in normal operating mode, the inhibit high-side switch is enabled and the external voltage regulator is activated. When TPIC1021A is in low-power mode, the inhibit switch is turned off, which disables the voltage regulator. A wake-up event on for the TPIC1021A returns INH to V connected to an MCU interrupt input.

below the minimum operating voltage. If there is a loss of ground at the

SUP

level. INH can also drive an external transistor

SUP

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OPERATING STATES

Unpowered System

V V

sup sup_under

Standby Mode

Driver : Off

RXD: Low

INH: High (On)

Termination: 30 kW

EN = high

EN = low

EN = high

LIN Bus Wake-Up

Nwake Pin Wake-Up

V > V

EN = low

sup sup_under

V V

sup sup_under

V V

sup sup_under

V V

sup sup_under

£V > V

EN = high

sup sup_under

Sleep Mode

Driver : Off

RXD: Floating

INH: High impedance (Off)

Termination:Weak pullup

Normal Mode

Driver : On

RXD: LIN bus data

INH: High (On)

Termination: 30 kW

TPIC1021A-Q1

LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

MODE EN RXD INH TRANSMITTER COMMENTS

Sleep Low Floating Weak current pullup High impedance Off Standby Low Low 30 k Ω (typ) High Off Normal High LIN bus data 30 k Ω (typ) High On LIN transmission up to 20 kbps

Normal Mode

This is the normal operational mode, in which the receiver and driver are active, and LIN transmission up to the LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and outputs it on RXD for the LIN controller, where recessive on the LIN bus is a digital high, and dominate on the LIN bus is digital low. The driver transmits input data on TXD to the LIN bus. Normal mode is entered as EN transitions high while the TPIC1021A is in sleep or standby mode.

Sleep Mode

Sleep mode is the power saving mode for the TPIC1021A and the default state after power up (assuming EN is low during power up). Even with the extremely low current consumption in this mode, the TPIC1021A can still wake up from LIN bus via a wake-up signal, a low on NWake, or if EN is set high. The LIN bus and NWake are filtered to prevent false wake-up events. The wake-up events must be active for their respective time periods (t

LINBUS

The sleep mode is entered by setting EN low.

Figure 1. Operating States Diagram

Table 1. Operating Modes

LIN BUS

, t

NWake

TERMINATION

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Wake-up event detected, waiting on MCU to set EN

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INH

High Impedance

TXD

MODE

Sleep

Normal

RXD

Floating

LIN

t > t

go_to_operate

sup

TPIC1021A-Q1 LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

While the device is in sleep mode, the following conditions exist:

• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if LIN is short circuited to ground). However, the weak current pullup is active to prevent false wake-up events in case an external connection to the LIN bus is lost.

• The normal receiver is disabled.

• INH is high impedance.

• EN input, NWake input, and the LIN wake-up receiver are active.

Wake-Up Events

There are three ways to wake up the TPIC1021A from sleep mode:

• Remote wake-up via recessive (high) to dominant (low) state transition on LIN bus. The dominant state must be held for t from disturbances on the LIN bus or if the bus is shorted to ground).

• Local wake-up via a low on NWake, which is asserted low longer than the filter time t wake-ups from disturbances on NWake)

• Local wake-up via EN being set high

Standby Mode

This mode is entered whenever a wake-up event occurs via LIN bus or NWake while the TPIC1021A is in sleep mode. The LIN bus slave termination circuit and INH are turned on when standby mode is entered. The application system powers up once INH is turned on, assuming the system is using a voltage regulator connected via INH. Standby mode is signaled via a low level on RXD.

When EN is set high while the TPIC1021A is in standby mode the device returns to normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.

filter time and then the bus must return to the recessive state (to eliminate false wake-ups

LINBUS

NWake

(to eliminate false

Figure 2. Wake-Up Via EN

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LIN

INH

High Impedance

RXD

Floating

TXD

MODE

Sleep

Standby

Normal

sup

t > t

go_to_operate

sup

t < t

LINBUS

0.4 × V

SUP

0.4 V×

SUP

0.6 V×

SUP

0.6 V×

SUP

LINBUS

NWake

INH

High Impedance

RXD

Floating

TXD

MODE Sleep

Normal

LIN

t > t

go_to_operate

sup

t < t

NWake

NWake V

sup

NWake

Standby

TPIC1021A-Q1

LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

Figure 3. Wake-Up Via LIN

Figure 4. Wake-Up Via NWake

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TPIC1021A-Q1 LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

PARAMETER RATING UNIT

(2)

SUP

Supply line supply voltage V

NWake dc and transient input voltage (through 33-k Ω serial resistor) –1 to 40 V Logic pin input voltage RXD, TXD, EN –0.3 to 5.5 V LIN dc-input voltage –40 to 40 V

Electrostatic discharge

stg

θ JA

Operational free-air temperature range –40 to 125 ° C Junction temperature range –40 to 150 ° C Storage temperature range –40 to 165 ° C Thermal resistance, junction to ambient 145 ° C/W Thermal shutdown 200 ° C Thermal shutdown hysteresis 25 ° C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND. (3) The human body model is a 100-pF capacitor discharged through a 1.5-k Ω resistor into each pin. (4) Tested in accordance to JEDEC Standard 22, Test Method C101 (JESD22-C101).

Continuous 0 to 27 Transient 0 to 40

(3)

Human-Body Model NWake

Charge-Device Model All pins

LIN

All other pins

(3)

(4)

–12 to 12 –11 to 11 kV

–1500 to 1500 V

–4 to 4

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LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

ELECTRICAL CHARACTERISTICS

= 7 V to 27 V, TA= –40 ° C to 125 ° C (unless otherwise noted)

SUP

PARAMETER TEST CONDITIONS MIN TYP

SUPPLY

Device is operational beyond the LIN 2.0

Operational supply voltage

Nominal supply line voltage V

undervoltage threshold 4.5 V

SUP

(2)

defined nominal supply line voltage range 7 14 27 V of 7 V < V

< 18 V

SUP

Normal and standby modes 7 14 18 Sleep mode 7 12 18

Normal mode, EN = High, Bus dominant (total bus load where R C

≤ 10 nF (see Figure 7 )

LIN

NWake = V

SUP

≥ 500 Ω and

LIN

(3)

, INH = V

SUP

Standby mode, EN = Low, Bus dominant (total bus loadwhere R C

≤ 10 nF (see Figure 7 )

LIN

NWake = V

Supply current

Normal mode, EN = High, Bus recessive, LIN = V

SUP

, INH = V

LIN

, NWake = V

SUP

≥ 500 Ω and

(3)

, INH = V

SUP

Standby mode, EN = Low, Bus recessive, LIN = V

SUP

, INH = V

, NWake = V

SUP

Sleep mode, EN = 0, 7 V < V NWake = V

≤ 12 V, LIN = V

SUP

, 15 30 μ A

SUP

Sleep mode, EN = 0, 12 V < V NWake = V

< 27 V, LIN = V

SUP

, 50 μ A

SUP

RXD OUTPUT PIN

V I

IKG

Output voltage –0.3 5.5 V

Low-level output current, open drain

Leakage current, high-level LIN = V

LIN = 0 V, RXD = 0.4 V 3.5 mA

, RXD = 5 V –5 0 5 μ A

SUP

TXD INPUT PIN

V V

Low-level input voltage –0.3 0.8 V

High-level input voltage 2 5.5 V

Input threshold hysteresis

voltage

30 500 mV

Pulldown resistor 125 350 800 k Ω

(1) Typical values are given for V (2) All voltages are defined with respect to ground; positive currents flow into the TPIC1021A device.

Low-level input current TXD = Low –5 0 5 μ A

= 14 V at 25 ° C, except for low power mode where typical values are given for V

SUP

(3) In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN slave termination

resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN

slave termination is 20 k Ω , so the maximum supply current attributed to the termination is:

SUP (dom) max termination

≈ (V

– (V

SUP

LIN_Dominant

+ 0.7 V) / 20 k Ω

(1)

1.2 7.5 mA

1 2.1 mA

450 775 μ A

SUP

TPIC1021A-Q1

MAX UNIT

= 12 V at 25 ° C.

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TPIC1021A-Q1 LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

ELECTRICAL CHARACTERISTICS (continued)

= 7 V to 27 V, TA= –40 ° C to 125 ° C (unless otherwise noted)

SUP

PARAMETER TEST CONDITIONS MIN TYP

LIN PIN (Referenced to V

V R

High-level output voltage V

Low-level output voltage 0 0.2 × V

Pullup resistor to V

slave

Pullup current source to V

LKG

V V V V

Limiting current TXD = 0 V 45 160 250 mA Leakage current LIN = V

Leakage current, loss of supply

Low-level input voltage LIN dominant 0 × V

High-level input voltage LIN recessive 0.6 × V

Input threshold voltage 0.4 × V

Hysteresis voltage 0.05 × V

hys

Low-level input voltage for

wake-up

EN PIN

V V V

Low-level input voltage –0.3 0.8 V

High-level input voltage 2 5.5 V

Hysteresis voltage 30 500 mV

hys

Pulldown resistor 125 350 800 k Ω

Low-level input current EN = Low –5 0 5 μ A

INH PIN

V R I

IKG

DC output voltage –0.3 V

On state resistance 35 85 Ω

Leakage current Low-power mode, 0 < INH < V

NWake PIN

V V

Low-level input voltage –0.3 V

High-level input voltage V

Pullup current NWake = 0 V –45 –10 –2 μ A

IKG

Leakage current V

THERMAL SHUTDOWN

Shutdown junction thermal temperature

)

SUP

LIN recessive, TXD = High, IO= 0 mA, V

LIN dominant, TXD = Low, IO= 40 mA, V

SUP

Normal and standby modes 20 30 60 k Ω Sleep mode, V

SUP

7 V < LIN ≤ 12 V, V 12 V < LIN < 18 V, V

Between V Normal or standby mode

SUP

(1)

– 1 V

= 14 V

SUP

= 14 V

= 14 V, LIN = GND –2 –20 μ A

SUP

–5 0 5 μ A

= GND 5

SUP

= GND 10

SUP

SUP SUP

0.5 × V

SUP SUP

SUP

0 0.4 × V

and INH, INH = 2-mA drive,

SUP

–5 0 5 μ A

– 1 V

SUP

0.4 × V

0.6 × V

0.175 × V

SUP

SUP SUP

MAX UNIT

SUP

SUP SUP SUP

SUP

+ 0.3 V

– 3.3 V + 0.3 V

= NWake –5 0 5 μ A

190 ° C

μ A

V V V V

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LIN PHYSICAL INTERFACE

ELECTRICAL CHARACTERISTICS (continued)

= 7 V to 27 V, TA= –40 ° C to 125 ° C (unless otherwise noted)

SUP

PARAMETER TEST CONDITIONS MIN TYP

AC CHARACTERISTICS

D1 Duty cycle 1

D2 Duty cycle 2

D3 Duty cycle 3

D4 Duty cycle 4

rx_pdr

rx_pdf

Receiver rising propagation delay time

Receiver falling propagation delay time

REC(max)

DOM(max)

(4)

SUP

BIT

D1 = t See Figure 5

REC(min)

DOM(min)

(4)

SUP

BIT

D2 = t See Figure 5

REC(max)

DOM(max)

(4)

SUP

BIT

D3 = t See Figure 5

REC(min)

DOM(min)

(4)

SUP

BIT

D4 = t See Figure 5

RXD

See Figure 6 6 μ s See Figure 7

RXD

See Figure 6 6 μ s See Figure 7

= 7 V to 18 V,

= 50 μ s (20 kbps),

Bus_rec(min)

= 0.422 × V

= 0.284 × V

= 7.6 V to 18 V,

= 50 μ s (20 kbps),

Bus_rec(max)

= 7 V to 18 V,

= 96 μ s (10.4 kbps),

Bus_rec(min)

= 0.389 × V

= 0.251 × V

= 7.6 V to 18 V,

= 96 μ s (10.4 kbps),

Bus_rec(max)

= 2.4 k Ω , C

= 0.744 × V

= 0.581 × V

/ (2 × t

= 0.778 × V

= 0.616 × V

/ (2 × t

RXD

= 20 pF

SUP

0.396

BIT

SUP

BIT

SUP

0.417

BIT

SUP

BIT

rising edge with respect to falling edge (t

= t

- t

rx_sym

Symmetry of receiver propagation delay time

rx_sym

R See Figure 6

RXD

rx_pdf

= 2.4 k Ω , C

)

rx_pdr

= 20 pF –2 2 μ s

RXD

See Figure 7

NWake

NWake filter time for local wake-up

See Figure 4 25 50 150 μ s

LIN wake-up filter time

LINBUS

DST

go_to_operate

(4) Duty cycles: LIN driver bus load conditions (C

(dominant time for wake-up See Figure 3 25 50 150 μ s via LIN bus)

Dominant state timeout

(5)

5.5 20 ms

See Figure 2 to Figure 3 0.5 1 μ s

, R

defined for 10.4-kbps operation. The TPIC1021A also meets these lower data rate requirements, while it is capable of the higher speed

LINBUS

): Load1 = 1 nF, 1 k Ω ; Load2 = 10 nF, 500 Ω . Duty cycles 3 and 4 are

LINBUS

20-kbps operation as specified by Duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle

definitions, for details see the SAEJ2602 specification. (5) Dominant state timeout limits the minimum data rate to 2.4 kbps.

(1)

TPIC1021A-Q1

SLIS117 – AUGUST 2007

MAX UNIT

0.581

0.59

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LIN Bus Signal

DOMINANT

RECESSIVE

D= 0.5

Thresholds:

Worst case 1

Thresholds: Worst case 2

Bit

sup

Rec(max)

Dom(max)

Rec(min)

Dom(min)

TXD (Input)

Bus_dom(max)

Bus_dom(min)

Bus_rec(max)

Bus_rec(min)

D = t

Bus_rec(min)

/(2 x t

Bit

)

D = t

Bus_rec(max)

/(2 x t

Bit

)

RXD D2 (20 kbps) and D4 (10 kbps) case

RXD D1 (20 kbps) and D3 (10 kbps) case

TPIC1021A-Q1 LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

TIMING DIAGRAMS

Figure 5. Definition of Bus Timing Parameters

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50% 50%

LIN Bus

RXD

0.4 V

SUP

0.6 V

SUP

rx_pdf

rx_pdr

TPIC1021A

RXD

TXD

NWake

INH

LIN

GND

RXD

SUP

LIN

100 nF

TIMING DIAGRAMS (continued)

TPIC1021A-Q1

LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

Figure 6. Propagation Delay

Figure 7. Test Circuit for AC Characteristics

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BAT

SUP

INH

NWake

TPIC1021A

MCU

MASTER

NODE

TMS470

LIN

Controller

SCI/UART

(1)

RXD

TXD

MCU w/o

pullup

(2)

VDDI/O

GND

8 3 7

4 5

Master

Node

Pullup

(3)

1 k

LIN

220 pF

SUP

TPIC7xxxx

SUP

INH

NWake

TPIC1021A

MCU

TMS470

LIN

Controller

SCI/UART

(1)

TXD

MCU w/o

pullup

(2)

VDDI/O

GND

8 3 7

4 5

LIN

220 pF

RXD

SLAVE

NODE

LIN Bus

I/O

TPIC7xxxx

SUP

TPIC1021A-Q1 LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

APPLICATION INFORMATION

(1) RXD on MCU or LIN slave has internal pullup, no external pullup resistor is needed. (2) RXD on MCU or LIN slave without internal pullup, requires external pullup resistor. (3) Master node applications require an external 1-k Ω pullup resistor and serial diode.

Figure 8.

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TPIC1021A-Q1

LIN PHYSICAL INTERFACE

SLIS117 – AUGUST 2007

APPLICATION INFORMATION (continued)

Device Comparison: TPIC1021 vs TPIC1021A

The TPIC1021A is pin-to-pin compatible to the TPIC1021 device. The TPIC1021A is an enhanced LIN transceiver, including enhanced immunity to RF disturbances. Table 2 is a summary of the differences between the two devices.

Table 2. TPIC1021A vs TPIC1021 Differences

SPECIFICATION TPIC1021A TPIC1021

Pinout and package 8-pin SOIC D package, Green 8-pin SOIC D package LIN termination Weak current pullup in sleep mode High Ω in low-power mode LIN receiver Enhanced high-speed receive capable High-speed receive capable LIN leakage current

(unpowered device): <5 μ A at 12 V (max) <10 μ A at 12 V (typ) 7 V < LIN < 12 V, V

LIN bus wake-up transition on LIN bus where dominant bus state

Low-power current <30 μ A at 12 V (max) <50 μ A at 14 V (max) INH pin Driving of bus master termination

= GND

SUP

Remote wake-up via recessive-to-dominant transition on LIN bus where dominant bus state is held for at least t transition back to the recessive state

Enhanced driving of bus master termination via lower R

LINBUS

time followed by a

Remote wake-up via recessive-to-dominant is held for at least t

time

LINBUS

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PACKAGE OPTION ADDENDUM

www.ti.com

22-Oct-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

TPIC1021AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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TEXAS INSTRUMENTS TPIC1021A-Q1 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

TERMINAL FUNCTIONS

Local Interconnect Network (LIN) Bus

Transmitter Characteristics

Receiver Characteristics

Transmit Input (TXD)

TXD Dominant State Timeout

Receive Output (RXD)

RXD Wake-up Request

Ground (GND)

Enable Input (EN)

NWake Input (NWake)

Inhibit Output (INH)

OPERATING STATES

Sleep Mode

Normal Mode

Wake-Up Events

Standby Mode

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

APPLICATION INFORMATION

Device Comparison: TPIC1021 vs TPIC1021A