TEXAS INSTRUMENTS TMS320VC5409A Technical data

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TMS320VC5409A

Fixed-PointDigital Signal Processor

Data Manual

Literature Number: SPRS140F

November 2000 – Revised January 2005

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TMS320VC5409A Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

This data sheet revision history highlights the technical changes made to the SPRS140E device-specific data sheet to make it an SPRS140F revision.

Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date with the following corrections.

SECTION ADDITIONS/CHANGES/DELETIONS

Table 2-2 Added Note 6.

Section 5.2 Changed IOHfrom -2 to -8 mA and IOLfrom 2 to 8 mA. Changed Note 2 to read "These output current limits

are used for the test conditions on V

Section 5.3 Changed test conditions for V

IOH= – 2 mA".

Table 5-1 In Note 1, changed symbol for Infinity from " ω " to " ∞ ". Figure 5-29 Updated figure to reduce confusion caused by unnecessary information. Section 6.1 Moved the Package Thermal Resistance Characteristics to this section.

Global A font substitution caused some symbols to display incorrectly in the E revisions of this document. This error

has been corrected and validated in the F revision including the Electrical Specifications.

Revision History

and VOH, except where noted otherwise."

from "DV

= 2.7 V to 3.0 V, IOH= MAX" to "DV

= 2.7 V to 3.0 V,

Revision History2

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TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

Contents

Revision History ........................................................................................................................... 2

1 TMS320VC5409A Features .................................................................................................... 9

2 Introduction ....................................................................................................................... 10

2.1 Description .................................................................................................................. 10

2.2 Pin Assignments ............................................................................................................ 10

2.2.1 Terminal Assignments for the GGU Package ............................................................... 10

2.2.2 Pin Assignments for the PGE Package ...................................................................... 12

2.3 Signal Descriptions ......................................................................................................... 13

3 Functional Overview ........................................................................................................... 17

3.1 Memory ...................................................................................................................... 17

3.1.1 Data Memory .................................................................................................... 17

3.1.2 Program Memory ............................................................................................... 18

3.1.3 Extended Program Memory ................................................................................... 18

3.2 On-Chip ROM With Bootloader ........................................................................................... 18

3.3 On-Chip RAM ............................................................................................................... 19

3.4 On-Chip Memory Security ................................................................................................. 19

3.5 Memory Map ................................................................................................................ 20

3.5.1 Relocatable Interrupt Vector Table ........................................................................... 20

3.6 On-Chip Peripherals ....................................................................................................... 22

3.6.1 Software-Programmable Wait-State Generator ............................................................. 22

3.6.2 Programmable Bank-Switching ............................................................................... 23

3.6.3 Bus Holders ..................................................................................................... 25

3.7 Parallel I/O Ports ........................................................................................................... 25

3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) ......................................................... 25

3.7.2 HPI Nonmultiplexed Mode ..................................................................................... 26

3.8 Multichannel Buffered Serial Ports (McBSPs) .......................................................................... 27

3.9 Hardware Timer ............................................................................................................ 30

3.10 Clock Generator ............................................................................................................ 30

3.11 Enhanced External Parallel Interface (XIO2) ........................................................................... 32

3.12 DMA Controller ............................................................................................................. 35

3.12.1 Features .......................................................................................................... 35

3.12.2 DMA External Access .......................................................................................... 35

3.12.3 DMPREC Issue ................................................................................................. 36

3.12.4 DMA Memory Map .............................................................................................. 38

3.12.5 DMA Priority Level .............................................................................................. 39

3.12.6 DMA Source/Destination Address Modification ............................................................. 39

3.12.7 DMA in Autoinitialization Mode ............................................................................... 40

3.12.8 DMA Transfer Counting ........................................................................................ 40

3.12.9 DMA Transfer in Doubleword Mode .......................................................................... 41

3.12.10 DMA Channel Index Registers .............................................................................. 41

3.12.11 DMA Interrupts ................................................................................................ 41

3.12.12 DMA Controller Synchronization Events ................................................................... 42

3.13 General-Purpose I/O Pins ................................................................................................. 43

3.13.1 McBSP Pins as General-Purpose I/O ........................................................................ 43

3.13.2 HPI Data Pins as General-Purpose I/O ...................................................................... 43

3.14 Device ID Register ......................................................................................................... 44

3.15 Memory-Mapped Registers ............................................................................................... 45

3.16 McBSP Control Registers and Subaddresses .......................................................................... 47

3.17 DMA Subbank Addressed Registers .................................................................................... 48

Contents 3

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TMS320VC5409A Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

3.18 Interrupts .................................................................................................................... 50

4 Support ............................................................................................................................. 51

4.1 Documentation Support ................................................................................................... 51

4.2 Device and Development-Support Tool Nomenclature ................................................................ 52

5 Electrical Specifications ...................................................................................................... 53

5.1 Absolute Maximum Ratings ............................................................................................... 53

5.2 Recommended Operating Conditions ................................................................................... 53

5.3 Electrical Characteristics Over Recommended Operating Case Temperature

Range (Unless Otherwise Noted) ........................................................................................ 54

5.4 Test Load Circuit ........................................................................................................... 55

5.5 Timing Parameter Symbology ............................................................................................ 55

5.6 Internal Oscillator With External Crystal ................................................................................. 55

5.7 Clock Options ............................................................................................................... 57

5.7.1 Divide-By-Two and Divide-By-Four Clock Options .......................................................... 57

5.7.2 Multiply-By-N Clock Option (PLL Enabled) ................................................................... 59

5.8 Memory and Parallel I/O Interface Timing .............................................................................. 60

5.8.1 Memory Read ................................................................................................... 60

5.8.2 Memory Write ................................................................................................... 63

5.8.3 I/O Read ......................................................................................................... 65

5.8.4 I/O Write ......................................................................................................... 67

5.9 Ready Timing for Externally Generated Wait States .................................................................. 68

5.10 HOLD and HOLDA Timings ............................................................................................... 71

5.11 Reset, BIO, Interrupt, and MP/ MC Timings ............................................................................. 73

5.12 Instruction Acquisition ( IAQ) and Interrupt Acknowledge ( IACK) Timings .......................................... 75

5.13 External Flag (XF) and TOUT Timings .................................................................................. 76

5.14 Multichannel Buffered Serial Port (McBSP) Timing .................................................................... 77

5.14.1 McBSP Transmit and Receive Timings ...................................................................... 77

5.14.2 McBSP General-Purpose I/O Timing ......................................................................... 80

5.14.3 McBSP as SPI Master or Slave Timing ...................................................................... 81

5.15 Host-Port Interface Timing ................................................................................................ 85

5.15.1 HPI8 Mode ....................................................................................................... 85

5.15.2 HPI16 Mode ..................................................................................................... 89

6 Mechanical Data ................................................................................................................. 93

6.1 Package Thermal Resistance Characteristics .......................................................................... 93

4 Contents

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TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

List of Figures

2-1 144-Ball GGU MicroStar BGA™ (Bottom View) .............................................................................. 10

2-2 144-Pin PGE Low-Profile Quad Flatpack (Top View) ........................................................................ 12

3-1 TMS320VC5409A Functional Block Diagram ................................................................................. 17

3-2 Program and Data Memory Map ................................................................................................ 20

3-3 Extended Program Memory Map ............................................................................................... 20

3-4 Processor Mode Status Register (PMST) ..................................................................................... 21

3-5 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] ......................... 22

3-6 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] ................................................... 23

3-7 Bank-Switching Control Register (BSCR) [MMR Address 0029h] .......................................................... 24

3-8 Host-Port Interface — Nonmultiplexed Mode ................................................................................. 26

3-9 HPI Memory Map ................................................................................................................. 27

3-10 Pin Control Register (PCR) ...................................................................................................... 28

3-11 Multichannel Control Register 2x (MCR2x) .................................................................................... 29

3-12 Multichannel Control Register 1x (MCR1x) .................................................................................... 29

3-13 Receive Channel Enable Registers Bit Layout for Partitions A to H ....................................................... 29

3-14 Transmit Channel Enable Registers Bit Layout for Partitions A to H ....................................................... 30

3-15 Nonconsecutive Memory Read and I/O Read Bus Sequence .............................................................. 32

3-16 Consecutive Memory Read Bus Sequence (n = 3 reads) ................................................................... 33

3-17 Memory Write and I/O Write Bus Sequence ................................................................................... 34

3-18 DMA Transfer Mode Control Register (DMMCRn) ........................................................................... 35

3-19 DMA Channel Enable Control Register (DMCECTL) ......................................................................... 37

3-20 On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) .......................................... 38

3-21 On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) ...................................... 39

3-22 DMPREC Register ................................................................................................................ 40

3-23 General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] ................................................ 43

3-24 General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] ................................................. 43

3-25 Device ID Register (CSIDR) [MMR Address 003Eh] ......................................................................... 44

3-26 IFR and IMR ....................................................................................................................... 50

5-1 Tester Pin Electronics ............................................................................................................ 55

5-2 Internal Divide-By-Two Clock Option With External Crystal ................................................................. 56

5-3 External Divide-By-Two Clock Timing .......................................................................................... 58

5-4 Multiply-By-One Clock Timing ................................................................................................... 60

5-5 Nonconsecutive Mode Memory Reads ......................................................................................... 61

5-6 Consecutive Mode Memory Reads ............................................................................................. 62

5-7 Memory Write ( MSTRB = 0) ..................................................................................................... 64

5-8 Parallel I/O Port Read ( IOSTRB = 0) ........................................................................................... 66

5-9 Parallel I/O Port Write ( IOSTRB = 0) ........................................................................................... 67

5-10 Memory Read With Externally Generated Wait States ....................................................................... 69

5-11 Memory Write With Externally Generated Wait States ....................................................................... 69

List of Figures 5

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TMS320VC5409A Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

5-12 I/O Read With Externally Generated Wait States ............................................................................. 70

5-13 I/O Write With Externally Generated Wait States ............................................................................. 70

5-14 HOLD and HOLDA Timings (HM = 1) .......................................................................................... 72

5-15 Reset and BIO Timings ........................................................................................................... 73

5-16 Interrupt Timing .................................................................................................................... 74

5-17 MP/ MC Timing ..................................................................................................................... 74

5-18 Instruction Acquisition ( IAQ) and Interrupt Acknowledge ( IACK) Timings ................................................. 75

5-19 External Flag (XF) Timing ........................................................................................................ 76

5-20 TOUT Timing ...................................................................................................................... 76

5-21 McBSP Receive Timings ......................................................................................................... 78

5-22 McBSP Transmit Timings ........................................................................................................ 79

5-23 McBSP General-Purpose I/O Timings .......................................................................................... 80

5-24 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ..................................................... 81

5-25 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ..................................................... 82

5-26 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ..................................................... 83

5-27 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ..................................................... 84

5-28 HPI-8 Mode Timing, Using HDS to Control Accesses ( HCS Always Low) ................................................ 87

5-29 HPI-8 Mode Timing, Using HCS to Control Accesses ....................................................................... 88

5-30 HPI-8 Mode, HINT Timing ....................................................................................................... 88

5-31 GPIOx

5-32 HPI-16 Mode, Nonmultiplexed Read Timings ................................................................................. 91

5-33 HPI-16 Mode, Nonmultiplexed Write Timings ................................................................................. 91

5-34 HPI-16 Mode, HRDY Relative to CLKOUT .................................................................................... 92

(A)

Timings .................................................................................................................. 88

6 List of Figures

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TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

List of Tables

2-1 Terminal Assignments ........................................................................................................... 11

2-2 Signal Descriptions ............................................................................................................... 13

3-1 Standard On-Chip ROM Layout ................................................................................................ 19

3-2 Processor Mode Status Register (PMST) Field Descriptions ............................................................... 21

3-3 Software Wait-State Register (SWWSR) Field Descriptions ................................................................ 22

3-4 Software Wait-State Control Register (SWCR) Field Descriptions ......................................................... 23

3-5 Bank-Switching Control Register (BSCR) Field Descriptions ............................................................... 24

3-6 Bus Holder Control Bits .......................................................................................................... 25

3-7 Sample Rate Generator Clock Source Selection ............................................................................. 28

3-8 Receive Channel Enable Registers for Partitions A to H Field Descriptions .............................................. 30

3-9 Transmit Channel Enable Registers for Partitions A to H Field Descriptions ............................................. 30

3-10 Clock Mode Settings at Reset ................................................................................................... 31

3-11 DMD Section of the DMMCRn Register ........................................................................................ 36

3-12 DMA Channel Enable Control Register (DMCECTL) Field Description .................................................... 37

3-13 DMA Reload Register Selection ................................................................................................ 40

3-14 DMA Interrupts .................................................................................................................... 41

3-15 DMA Synchronization Events .................................................................................................... 42

3-16 DMA Channel Interrupt Selection ............................................................................................... 42

3-17 CPU Memory-Mapped Registers ................................................................................................ 45

3-18 Peripheral Memory-Mapped Registers for Each DSP Subsystem ......................................................... 45

3-19 McBSP Control Registers and Subaddresses ................................................................................. 47

3-20 DMA Subbank Addressed Registers ........................................................................................... 48

3-21 Interrupt Locations and Priorities ................................................................................................ 50

5-1 Input Clock Frequency Characteristics ......................................................................................... 56

5-2 Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options ........................................ 57

5-3 Divide-By-2 and Divide-By-4 Clock Options Timing Requirements ........................................................ 57

5-4 Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics .................................................... 57

5-5 Multiply-By-N Clock Option Timing Requirements ............................................................................ 59

5-6 Multiply-By-N Clock Option Switching Characteristics ....................................................................... 59

5-7 Memory Read Timing Requirements ........................................................................................... 60

5-8 Memory Read Switching Characteristics ....................................................................................... 60

5-9 Memory Write Switching Characteristics ....................................................................................... 63

5-10 I/O Read Timing Requirements ................................................................................................. 65

5-11 I/O Read Switching Characteristics ............................................................................................. 65

5-12 I/O Write Switching Characteristics ............................................................................................. 67

5-13 Ready Timing Requirements for Externally Generated Wait States ....................................................... 68

5-14 Ready Switching Characteristics for Externally Generated Wait States ................................................... 68

5-15 HOLD and HOLDA Timing Requirements ..................................................................................... 71

5-16 HOLD and HOLDA Switching Characteristics ................................................................................. 71

List of Tables 7

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TMS320VC5409A Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

5-17 Reset, BIO, Interrupt, and MP/ MC Timing Requirements ................................................................... 73

5-18 Instruction Acquisition ( IAQ) and Interrupt Acknowledge ( IACK) Switching Characteristics ............................ 75

5-19 External Flag (XF) and TOUT Switching Characteristics .................................................................... 76

5-20 McBSP Transmit and Receive Timing Requirements ........................................................................ 77

5-21 McBSP Transmit and Receive Switching Characteristics ................................................................... 78

5-22 McBSP General-Purpose I/O Timing Requirements ......................................................................... 80

5-23 McBSP General-Purpose I/O Switching Characteristics ..................................................................... 80

5-24 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................... 81

5-25 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) .............................. 81

5-26 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................... 82

5-27 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) .............................. 82

5-28 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................... 83

5-29 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) .............................. 83

5-30 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................... 84

5-31 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) .............................. 84

5-32 HPI8 Mode Timing Requirements ............................................................................................... 85

5-33 HPI8 Mode Switching Characteristics .......................................................................................... 86

5-34 HPI16 Mode Timing Requirements ............................................................................................. 89

5-35 HPI16 Mode Switching Characteristics ......................................................................................... 90

6-1 Thermal Resistance Characteristics ............................................................................................ 93

8 List of Tables

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1 TMS320VC5409A Features

• Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and One Program Memory Bus

• 40-Bit Arithmetic Logic Unit (ALU) Including a

40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

• 17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation

• Compare, Select, and Store Unit (CSSU) for the

Add/Compare Selection of the Viterbi Operator

• Exponent Encoder to Compute an Exponent

Value of a 40-Bit Accumulator Value in a Single Cycle

• Two Address Generators With Eight Auxiliary

Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

• Data Bus With a Bus Holder Feature

• Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program Space

• 32K x 16-Bit On-Chip RAM Composed of: – Four Blocks of 8K × 16-Bit On-Chip

Dual-Access Program/Data RAM

• 16K × 16-Bit On-Chip ROM Configured for Program Memory

• Enhanced External Parallel Interface (XIO2)

• Single-Instruction-Repeat and Block-Repeat

Operations for Program Code

• Block-Memory-Move Instructions for Better Program and Data Management

• Instructions With a 32-Bit Long Word Operand

• Instructions With Two- or Three-Operand

Reads

• Arithmetic Instructions With Parallel Store and Parallel Load

• Conditional Store Instructions Boundary Scan Architecture.

• Fast Return From Interrupt

• On-Chip Peripherals

– Software-Programmable Wait-State

– On-Chip Programmable Phase-Locked

– One 16-Bit Timer – Six-Channel Direct Memory Access (DMA)

– Three Multichannel Buffered Serial Ports

– 8/16-Bit Enhanced Parallel Host-Port

• Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With Power-Down Modes

• CLKOUT Off Control to Disable CLKOUT

• On-Chip Scan-Based Emulation Logic, IEEE

Std 1149.1 (JTAG) Boundary Scan Logic

• 144-Pin Ball Grid Array (BGA) (GGU Suffix)

• 144-Pin Low-Profile Quad Flatpack (LQFP)

(PGE Suffix)

• 6.25-ns Single-Cycle Fixed-Point Instruction

Execution Time (160 MIPS)

• 8.33-ns Single-Cycle Fixed-Point Instruction

Execution Time (120 MIPS)

• 3.3-V I/O Supply Voltage (160 and 120 MIPS)

• 1.6-V Core Supply Voltage (160 MIPS)

• 1.5-V Core Supply Voltage (120 MIPS)

(1) The on-chip oscillator is not available on all 5409A devices.

For applicable devices, see the TMS320VC5409A Digital Signal Processor Silicon Errata (literature number SPRZ186).

(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and

TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

Generator and Programmable Bank-Switching

Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source

Controller

(McBSPs)

Interface (HPI8/16)

(1)

(2)

TMS320C54x, MicroStar BGA, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

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A B

E F

H J

L M

3456781012 1113 9

TMS320VC5409A Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

2 Introduction

This section lists the pin assignments and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).

2.1 Description

The TMS320VC5409A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5409A unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5409A also includes the control mechanisms to manage interrupts, repeated operations, and function calls.

NOTE

2.2 Pin Assignments

Figure 2-1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. Figure 2-2 provides the pin assignments for the 144-pin low-profile quad flatpack (LQFP) package.

2.2.1 Terminal Assignments for the GGU Package

Figure 2-1. 144-Ball GGU MicroStar BGA™ (Bottom View)

10 Introduction

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Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

Table 2-1 lists each signal name and BGA ball number for the 144-pin TMS320VC5409AGGU package. Table 2-2 lists each terminal name, terminal function, and operating modes for the TMS320VC5409A.

Table 2-1. Terminal Assignments

TMS320VC5409A

SIGNAL SIGNAL SIGNAL SIGNAL

QUADRANT 1 QUADRANT 2 QUADRANT 3 QUADRANT 4

BGA BALL # BGA BALL # BGA BALL # BGA BALL #

A1 BFSX1 N13 CV

N1 A19 A13

A22 B1 BDX1 M13 BCLKR1 N2 A20 A12

C2 DV C1 DV

DD SS

L12 HCNTL0 M3 CV L13 DV

N3 DV

SS DD

A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10

HD7 D3 CLKMD2 K11 BCLKR2 L4 D7 C10

A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10 A12 D1 HPI16 K13 BFSR2 N4 D9 A10 A13 E4 HD2 J10 BDR0 K5 D10 D9 A14 E3 TOUT J11 HCNTL1 L5 D11 C9 A15 E2 EMU0 J12 BDR2 M5 D12 B9

E1 EMU1/ OFF J13 BCLKX0 N5 HD4 A9

HAS F4 TDO H10 BCLKX2 K6 D13 D8

HCS G2 TMS G12 BFSX0 M7 CV

HR/ W G1 CV

READY G3 CV

PS G4 HPIENA G10 DV DS H1 DV

IS H2 CLKOUT F12 HD0 M8 DV

F3 TDI H11 CV

L6 D14 C8 F2 TRST H12 HINT M6 D15 B8 F1 TCK H13 CV

SS DD

G13 BFSX2 N7 CV G11 HRDY L7 HDS1 C7

F13 DV

DD SS

N6 HD5 A8

DD SS

K7 DV

N8 HDS2 A6

R/ W H3 HD3 F11 BDX0 L8 A0 C6

MSTRB H4 X1 F10 BDX2 K8 A1 D6

IOSTRB J1 X2/CLKIN E13 IACK N9 A2 A5

MSC J2 RS E12 HBIL M9 A3 B5

XF J3 D0 E11 NMI L9 HD6 C5

HOLDA J4 D1 E10 INT0 K9 A4 D5

IAQ K1 D2 D13 INT1 N10 A5 A4

HOLD K2 D3 D12 INT2 M10 A6 B4

BIO K3 D4 D11 INT3 L10 A7 C4

MP/ MC L1 D5 C13 CV

L2 A16 C12 HD1 M11 A9 B3 L3 DV

C11 CV

N11 A8 A3

L11 CV

BDR1 M1 A17 B13 BCLKX1 N12 A21 A2

BFSR1 M2 A18 B12 DV

M12 DV

B11 A11

B7 A7

Introduction 11

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HDS1

A18 A17 DV

A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT DV

HPIENA CV

TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT HD2 HPI16 CLKMD3 CLKMD2 CLKMD1 DV

BDX1 BFSX1

A22

A10

HD7

A11 A12 A13 A14 A15

HAS

HCS

HR/W

READY

PS DS

R/W

MSTRB

IOSTRB

MSC

HOLDA

IAQ

HOLD

BIO

MP/MC

BDR1

BFSR1

144

A21

143

142

141

140A7139

A6138

137

A4136

HD6

135

A3134

A2133

132

A0131

130

129

128

127CV126

125

HD5124

D15123

D14

122

D13121

HD4120

D12119

D11118

117

D9116

115D7114

D6113

112

515253

555657585960616263646566676869

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

HCNTL0

BCLKR0

BCLKR2

BFSR0

BFSR2

BDR0

HCNTL1

BDR2

BCLKX0

BCLKX2

HD0

BDX0

BDX2

IACK

HBIL

NMI

INT0

INT1

INT2

INT3

HD1

HRDY

HINT

111

110

A19

109

707172

D10

BFSX2

A20

CV HDS2

BFSX0

TMS320VC5409A Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

2.2.2 Pin Assignments for the PGE Package

The TMS320VC5409APGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-2 .

12 Introduction

A. DV

is the power supply for the I/O pins while CV

the I/O pins while CV ground plane in a system.

Figure 2-2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)

is the ground for the core CPU. The DV

is the power supply for the core CPU. DV

and CV

pins can be connected to a common

is the ground for

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TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

2.3 Signal Descriptions

Table 2-2 lists each signal, function, and operating mode(s) grouped by function. See Section Section 2.2 for exact pin locations based on package type.

Table 2-2. Signal Descriptions

TERMINAL

NAME

A22 (MSB) A21 A20 A19 A18 A17 A16 A15 Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen A14 LSB lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB A13 lines, A16 to A22, address external program space memory. A22-A0 is placed in the high-impedance state A12 in the hold mode. A22-A0 also goes into the high-impedance state when OFF is low. A11 I/O/Z A10 interface (HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs. A9 The address bus has a bus holder feature that eliminates passive components and the power dissipation A8 associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes A7 into a high-impedance state. A6 A5 A4 A3 A2 A1 A0 (LSB)

D15 (MSB) D14 D13 D12 D11 Parallel data bus D15 (MSB) through D0 (LSB). D15-D0 is multiplexed to transfer data between the core D10 CPU and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high). D9 D15-D0 is placed in the high-impedance state when not outputting data or when RS or HOLD is asserted. D8 D15-D0 also goes into the high-impedance state when OFF is low. These pins also have Schmitt trigger D7 inputs. The data bus has a bus holder feature that eliminates passive components and the power D6 dissipation associated with them. The bus holder keeps the data bus at the previous logic level when the D5 bus goes into the high-impedance state. The bus holders on the data bus can be enabled/disabled under D4 software control. D3 D2 D1 D0 (LSB)

IACK O/Z fetching the interrupt vector location designated by A15-A0. IACK also goes into the high-impedance state

(2)

INT0

(2)

INT1

(2)

INT2

(2)

INT3

(2)

NMI

(2)

(1)

I/O

DATA SIGNALS

(2) (3)

A15-A0 are inputs in HPI16 mode. These pins can be used to address internal memory via the host-port

(2) (3)

I/O/Z

INITIALIZATION, INTERRUPT AND RESET OPERATIONS

Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is when OFF is low. External user interrupt inputs. INT0- INT3 are maskable and are prioritized by the interrupt mask register

I (IMR) and the interrupt mode bit. INT0 - INT3 can be polled and reset by way of the interrupt flag register

(IFR). Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.

When NMI is activated, the processor traps to the appropriate vector location. Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program

I counter to 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program

memory. RS affects various registers and status bits.

DESCRIPTION

(1) I = Input, O = Output, Z = High-impedance, S = Supply (2) These pins have Schmitt trigger inputs. (3) This pin has an internal bus holder controlled by way of the BSCR register.

Introduction 13

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TMS320VC5409A Fixed-PointDigital Signal Processor

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Table 2-2. Signal Descriptions (continued)

TERMINAL

NAME

MP/ MC I driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program

(2)

BIO

XF O/Z

DS PS O/Z IS

MSTRB O/Z to data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes

READY I

R/ W O/Z

IOSTRB O/Z I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the

HOLD I

HOLDA O/Z the address, data, and control lines are in the high-impedance state, allowing them to be available to the

MSC O/Z inactive high at the beginning of the last software wait state. If connected to the READY input, MSC forces

IAQ O/Z

CLKOUT O/Z configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the

CLKMD1 CLKMD2 CLKMD3

X2/CLKIN

X1 O unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision depended,

TOUT O/Z

(2) (2) (2)

(2)

(1)

I/O

Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is

space. This pin is only sampled at reset, and the MP/ MC bit of the processor mode status (PMST) register can override the mode that is selected at reset.

MULTIPROCESSING SIGNALS

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes

I the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the

XC instruction, and all other instructions sample BIO during the read phase of the pipeline. External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set

low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset.

MEMORY CONTROL SIGNALS

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating to a particular external space. Active period corresponds to valid address information. DS, PS, and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance state when OFF is low.

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access into the high-impedance state when OFF is low.

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states.

Read/write signal. R/ W indicates transfer direction during communication to an external device. R/ W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/ W is placed in the high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an high-impedance state when OFF is low.

Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the 5409A, these lines go into the high-impedance state.

Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that external circuitry. HOLDA also goes into the high-impedance state when OFF is low.

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes

one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF is low.

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus and goes into the high-impedance state when OFF is low.

OSCILLATOR/TIMER SIGNALS

Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as machine-cycle rate divided by 4.

Clock mode select signals. CLKMD1-CLKMD3 allow the selection and configuration of different clock modes such as crystal, external clock, and PLL mode. The external CLKMD1-CLKMD3 pins are sampled

to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software.

Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.

(This is revision depended, see Section Section 3.10 for additional information.) Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

see Section Section 3.10 for additional information.) Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one

CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.

DESCRIPTION

14 Introduction

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TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

Table 2-2. Signal Descriptions (continued)

TERMINAL

NAME

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),

BCLKR0 BCLKR1 BCLKR2

(2) (2) (2)

BDR0 BDR1 I Serial data receive input BDR2

BFSR0 BFSR1 I/O/Z BFSR2

BCLKX0 BCLKX1 BCLKX2

(2) (2) (2)

BDX0 BDX1 O/Z BDX2

BFSX0 Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process BFSX1 I/O/Z over BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX2 BFSX goes into the high-impedance state when OFF is low.

HD0-HD7

HCNTL0 HCNTL1

HBIL

HCS HDS1

HDS2 HAS

HR/ W

(2) (3)

(4) (4)

(4)

(2) (4)

(2) (4) (2) (4)

(2) (4)

(4)

HRDY O/Z

HINT O/Z

HPIENA

HPI16

CV CV DV

(5)

SS DD SS

(1)

I/O

DESCRIPTION

AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS

I/O/Z

Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.

Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured as an input following reset. The BFSR pulse initiates the receive data process over BDR.

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be

I/O/Z configured as an input or an output, and is configured as an input following reset. BCLKX enters the

high-impedance state when OFF goes low. Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is

asserted, or when OFF is low.

HOST-PORT INTERFACE SIGNALS

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the HPI registers. These pins can also be used as general-purpose I/O pins. HD0-HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus

I/O/Z holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is

not being driven by the 5409A, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs.

Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control

I inputs have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16

= 1. Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup

resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1. Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select

input has an internal pullup resistor that is only enabled when HPIENA = 0. Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The

strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0. Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the

HPIA register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0. Read/write. HR/ W controls the direction of the HPI transfer. HR/ W has an internal pullup resistor that is

only enabled when HPIENA = 0. Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the

host when the HPI is ready for the next transfer. Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high.

HINT goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1. HPI module select. HPIENA must be tied to DV

connected to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled,

and the HPI data bus has holders set. HPIENA is provided with an internal pulldown resistor that is always

to have HPI selected. If HPIENA is left open or

active. HPIENA is sampled when RS goes high and is ignored until RS goes low again. HPI16 mode selection. This pin must be tied to DV

pulldown resistor which is always active. If HPI16 is left open or driven low, the HPI16 mode is disabled.

to enable HPI16 mode. The pin has an internal

SUPPLY PINS

S Ground. Dedicated ground for the core CPU S +V

. Dedicated power supply for the core CPU

S Ground. Dedicated ground for I/O pins

(4) This pin has an internal pullup resistor. (5) This pin has an internal pulldown resistor.

Introduction 15

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TMS320VC5409A Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

Table 2-2. Signal Descriptions (continued)

TERMINAL

NAME

(2) (4)

TCK

(4)

TDI

TDO O/Z shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the

(4)

TMS

(5)

TRST

(6)

EMU0

EMU1/ OFF

(6)

(1)

I/O

S +V

. Dedicated power supply for I/O pins

DESCRIPTION

TEST PINS

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller,

instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.

IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected

register (instruction or data) on a rising edge of TCK. IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are

scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low. IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked

into the TAP controller on the rising edge of TCK. IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of

I the operations of the device. If TRST is not connected or driven low, the device operates in its functional

mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When

I/O/Z TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as

input/output by way of the IEEE standard 1149.1 scan system. Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/ OFF is used as an interrupt to or from

the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/ OFF is configured as OFF. The EMU1/ OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation

I/O/Z

purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply:

• TRST= low,

• EMU0 = high

• EMU1/ OFF = low

(6) This pin must be pulled up with a 4.7-k Ω resistor to ensure the device is operable in functional mode or emulation mode.

16 Introduction

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3 Functional Overview

GPIO

MBus

32K RAM

Dual Access

Program/Data

McBSP1

McBSP2

McBSP3

RHEA Bus

APLL

TIMER

JTAG

Clocks

RHEAbus

RHEA Bridge

TI BUS

xDMA

logic

16K Program

ROM

Pbus

Cbus

Dbus

Ebus

RHEA bus

MBus

Pbus

Cbus

Dbus

Ebus

Pbus

Enhanced XIO

P, C, D, E Buses and Control Signals

XIO

HPI

54X cLEAD

HPI

The following functional overview is based on the block diagram in Figure 3-1 .

TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

3.1 Memory

3.1.1 Data Memory

Figure 3-1. TMS320VC5409A Functional Block Diagram

The 5409A device provides both on-chip ROM and RAM memories to aid in system performance and integration.

The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access.

The advantages of operating from on-chip memory are as follows:

• Higher performance because no wait states are required

• Higher performance because of better flow within the pipeline of the central arithmetic logic unit

(CALU)

• Lower cost than external memory

• Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

Functional Overview 17

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TMS320VC5409A Fixed-PointDigital Signal Processor

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3.1.2 Program Memory

Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows:

• Higher performance because no wait states are required

• Lower cost than external memory

• Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

3.1.3 Extended Program Memory

The 5409A uses a paged extended memory scheme in program space to allow access of up to 8192K of program memory. In order to implement this scheme, the 5409A includes several features which are also present on C548/549/5410:

• Twenty-three address lines, instead of sixteen

• An extra memory-mapped register, the XPC

• Six extra instructions for addressing extended program space

Program memory in the 5409A is organized into 128 pages that are each 64K in length. The value of the XPC register defines the page selection. This register is memory-mapped into data space

to address 001Eh. At a hardware reset, the XPC is initialized to 0.

3.2 On-Chip ROM With Bootloader

The 5409A features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program memory space.

Customers can arrange to have the ROM of the 5409A programmed with contents unique to any particular application.

A bootloader is available in the standard 5409A on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If MP/ MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program.

The standard 5409A devices provide different ways to download the code to accommodate various system requirements:

• Parallel from 8-bit or 16-bit-wide EPROM

• Parallel from I/O space, 8-bit or 16-bit mode

• Serial boot from serial ports, 8-bit or 16-bit mode

• Host-port interface boot

• Serial EEPROM mode

• Warm boot

18 Functional Overview

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The standard on-chip ROM layout is shown in Table 3-1 .

3.3 On-Chip RAM

The 5409A device contains 32K-word × 16-bit of on-chip dual-access RAM (DARAM).

TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

Table 3-1. Standard On-Chip ROM Layout

ADDRESS RANGE DESCRIPTION

C000h-D4FFh ROM tables for the GSM EFR speech codec D500h-F7FFh Reserved F800h-FBFFh Bootloader FC00h-FCFFh µ-Law expansion table FD00h-FDFFh A-Law expansion table FE00h-FEFFh Sine look-up table FF00h-FF7Fh Reserved FF80h-FFFFh Interrupt vector table

(1) In the 5409A ROM, 128 words are reserved for factory device-testing purposes. Application code to

be implemented in on-chip ROM must reserve these 128 words at addresses FF00h-FF7Fh in program space.

(1)

The DARAM is composed of four blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address range 0080h-7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one.

3.4 On-Chip Memory Security

The 5409A device has a maskable option to protect the contents of on-chip memories. When the ROM protect bit is set, no externally originating instruction can access the on-chip memory spaces; HPI writes have no restriction, but HPI reads are restricted to 4000h - 5FFFh.

Functional Overview 19

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Reserved

(OVLY = 1)

External

(OVLY = 0)

Page 0 Program

Hex

Data

On-Chip

DARAM0-3

(OVLY = 1)

External

(OVLY = 0)

MP/MC= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

007F

0080

FFFF

Interrupts (External)

FF80

Memory-Mapped

Registers

On-Chip

DARAM0-3

(32K x 16-bit)

0080

FFFF

FF7F

0060 007F

0000

Hex

External

Scratch-Pad

RAM

005F

On-Chip ROM

(4K x 16-bit)

Interrupts (On-Chip)

7FFF

8000

Page 0 Program

Hex

0000

007F

0080

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

FF80

FF7F

External

7FFF

8000

Reserved

FF00

FEFF

C000

BFFF

8000

7FFF

On-Chip DARAM0-3 (OVLY = 1)

External

(OVLY = 0)

External

Hex

010000

01FFFF

Program

Page 1 XPC=1

On-Chip

DARAM0-3

(OVLY=1)

External

(OVLY=0)

External

Hex

Program On-Chip

DARAM0-3

(OVLY=1)

External

(OVLY=0)

7F0000

7FFFFF

Page 127

XPC=7Fh

External

7F7FFF 7F8000

017FFF

018000

......

TMS320VC5409A Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

3.5 Memory Map

Figure 3-2. Program and Data Memory Map

3.5.1 Relocatable Interrupt Vector Table

Address ranges for on-chip DARAM in data memory are: DARAM0: 0080h-1FFFh; DARAM1: 2000h-3FFFh DARAM2: 4000h-5FFFh; DARAM3: 6000h-7FFFh

Figure 3-3. Extended Program Memory Map

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate interrupt service routine without the overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.

NOTE: The hardware reset ( RS) vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

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TMS320VC5409A

Fixed-PointDigital Signal Processor

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15 8

IPTR

R/W-1FF

7 6 5 4 3 2 1 0

IPTR MP/ MC OVLY AVIS Reserved SMUL SST

R/W-1FF R/W - MP/ MC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-4. Processor Mode Status Register (PMST)

Table 3-2. Processor Mode Status Register (PMST) Field Descriptions

BIT FIELD VALUE DESCRIPTION

Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt

15-7 IPTR 1FFh

MP/ MC Microprocessor/microcomputer mode. MP/ MC enables/disables the on-chip ROM to be addressable in

6 MP/ MC

5 OVLY 0 The on-chip RAM is addressable in data space but not in program space.

4 AVIS not affected and the address bus is driven with the last address on the bus.

3 Reserved 2 CLKOFF 0

1 SMUL N/A performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1

0 SST N/A

vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The RESET instruction does not affect this field.

pin program memory space.

0 The on-chip ROM is enabled and addressable. 1 The on-chip ROM is not available.

MP/ MC is set to the value corresponding to the logic level on the MP/ MC pin when sampled at reset. This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also be set or cleared by software.

RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are:

The on-chip RAM is mapped into program space and data space. Data page 0 (addresses 0h to 7Fh),

however, is not mapped into program space. Address visibility mode. AVIS enables/disables the internal program address to be visible at the

address pins. The external address lines do not change with the internal program address. Control and data lines are

This mode allows the internal program address to appear at the pins of the 5409A so that the internal

1 program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with

IACK when the interrupt vectors reside on on-chip memory.

CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high level.

Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before and FRCT = 1.

Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation.

CLK OFF

Functional Overview 21

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TMS320VC5409A Fixed-PointDigital Signal Processor

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3.6 On-Chip Peripherals

The 5409A device has the following peripherals:

• Software-programmable wait-state generator

• Programmable bank-switching

• A host-port interface (HPI8/16)

• Three multichannel buffered serial ports (McBSPs)

• A hardware timer

• A clock generator with a multiple phase-locked loop (PLL)

• Enhanced external parallel interface (XIO2)

• A DMA controller (DMA)

3.6.1 Software-Programmable Wait-State Generator

The software wait-state generator of the 5409A can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the 5409A.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3-5 and described in Table 3-3 .

15 14 12 11 9 8

XPA I/O Data Data

R/W-0 R/W-111 R/W-111 R/W-111

7 6 5 3 2 0

Data Program Program

R/W-111 R/W-111 R/W-111

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address

0028h]

Table 3-3. Software Wait-State Register (SWWSR) Field Descriptions

BIT FIELD VALUE DESCRIPTION

15 XPA 0

14-12 I/O 111 within addresses 0000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for

11-9 Data 111 data space accesses within addresses 8000-FFFFh. The SWSM bit of the SWCR defines a

Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states.

I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses the base number of wait states.

Upper data space. The field value (0-7) corresponds to the base number of wait states for external multiplication factor of 1 or 2 for the base number of wait states.

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Table 3-3. Software Wait-State Register (SWWSR) Field Descriptions (continued)

BIT FIELD VALUE DESCRIPTION

8-6 Data 111 data space accesses within addresses 0000-7FFFh. The SWSM bit of the SWCR defines a

5-3 Program 111

2-0 Program 111

The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3-6 and described in Table 3-4 .

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

LEGEND: R = Read, W = Write, n = value at reset

Lower data space. The field value (0-7) corresponds to the base number of wait states for external multiplication factor of 1 or 2 for the base number of wait states.

Upper program space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within the following addresses:XPA = 0: xx8000 - xxFFFFhXPA = 1: 400000h

- 7FFFFFhThe SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

Program space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within the following addresses:XPA = 0: xx0000 - xx7FFFhXPA = 1: 000000 3FFFFFhThe SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

Reserved

Reserved SWSM

R/W-0

Figure 3-6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]

Table 3-4. Software Wait-State Control Register (SWCR) Field Descriptions

BIT FIELD VALUE DESCRIPTION

15-1 Reserved These bits are reserved and are unaffected by writes.

Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a

0 SWSM

factor of 1 or 2. 0 Wait-state base values are unchanged (multiplied by 1). 1 Wait-state base values are multiplied by 2 for a maximum of 14 wait states.

3.6.2 Programmable Bank-Switching

Programmable bank-switching logic allows the 5409A to switch between external memory banks without requiring external wait states for memories that need additional time to turn off. The bank-switching logic automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or data space.

Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at address 0029h. The bit fields of the BSCR are shown in Figure 3-7 and are described in Table 3-5 .

15 14 13 12 11 8

CONSEC DIVFCT IACK OFF Reserved

R/W-1 R/W-11 R/W-1 R

7 3 2 1 0

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Reserved HBH BH Reserved

R R/W-0 R/W-0 R

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]

Table 3-5. Bank-Switching Control Register (BSCR) Field Descriptions

BIT FIELD VALUE DESCRIPTION

Consecutive bank-switching .Specifies the bank-switching mode. Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for continuous

15 CONSEC

13-14 DIVFCT

12 IACKOFF 0 The IACK signal output off function is disabled.

11-3 Reserved Reserved

2 HBH

1 BH 0 The bus holder is disabled.

0 Reserved Reserved

(1)

memory reads (i.e., no starting and trailing cycles between read cycles). Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles: starting

cycle, read cycle, and trailing cycle. CLKOUT output divide factor . The CLKOUT output is driven by an on-chip source having a frequency

equal to 1/(DIVFCT+1) of the DSP clock. 00 CLKOUT is not divided. 01 CLKOUT is divided by 2 from the DSP clock. 10 CLKOUT is divided by 3 from the DSP clock. 11 CLKOUT is divided by 4 from the DSP clock (default value following reset).

IACK signal output off . Controls the output of the IACK signal. IACKOFF is set to 1 at reset.

1 The IACK signal output off function is enabled.

HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.

0 The bus holder is disabled except when HPI16=1.

The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous logic

level.

Bus holder. Controls the bus holder. BH is cleared to 0 at reset.

1 The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic level.

(1) For additional information, see Section Section 3.11 of this document.

The 5409A has an internal register that holds the MSB of the last address used for a read or write operation in program or data space. In the non-consecutive bank switches ( CONSEC = 0), if the MSB of the address used for the current read does not match that contained in this internal register, the MSTRB (memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address. The contents of the internal register are replaced with the MSB for the read of the current address. If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.

In non-consecutive bank switches ( CONSEC = 0), if repeated reads are performed from the same memory bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts are avoided by inserting an extra cycle. For more information, see Section Section 3.11 of this document.

The bank-switching mechanism automatically inserts one extra cycle in the following cases:

• A memory read followed by another memory read from a different memory bank.

• A program-memory read followed by a data-memory read.

• A data-memory read followed by a program-memory read.

• A program-memory read followed by another program-memory read from a different page.

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3.6.3 Bus Holders

The 5409A has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of the address bus (A[15-0]), data bus (D[15-0]), and the HPI data bus (HD[7-0]). Bus keeper enabling/disabling is described in Table 3-5 .

Table 3-6. Bus Holder Control Bits

HPI16 PIN BH HBH D[15-0] A[15-0] HD[7-0]

0 0 0 OFF OFF OFF 0 0 1 OFF OFF ON 0 1 0 ON OFF OFF 0 1 1 ON OFF ON 1 0 0 OFF OFF ON 1 0 1 OFF ON ON 1 1 0 ON OFF ON 1 1 1 ON ON ON

TMS320VC5409A

3.7 Parallel I/O Ports

The 5409A has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5409A can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.

3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)

The 5409A host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier TMS320C54x™ DSPs (542, 545, 548, and 549). The 5409A HPI can be used to interface to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface to external devices in program/data/IO spaces), the 5409A HPI can be configured as an HPI16 to interface to a 16-bit host. This configuration can be accomplished by connecting the HPI16 pin to logic "1".

When the HPI16 pin is connected to a logic "0", the 5409A HPI is configured as an HPI8. The HPI8 is an 8-bit parallel port for interprocessor communication. The features of the HPI8 include:

Standard features:

• Sequential transfers (with autoincrement) or random-access transfers

• Host interrupt and C54x™ interrupt capability

• Multiple data strobes and control pins for interface flexibility

The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8 through three dedicated registers — the HPI address register (HPIA), the HPI data register (HPID), and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the 5409A.

Enhanced features:

• Access to entire on-chip RAM through DMA bus

• Capability to continue transferring during emulation stop

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HPID[15:0]

HAS

HDS1, HDS2, HCS

DMA

Internal

Memory

PPD[15:0]

DATA[15:0]

Address[15:0]

R/W

Data Strobes

READY

HPI16

HRDY

54xx CPU

HCNTL0 HCNTL1

HR/W

HINT

HBIL

HOST

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The HPI16 is an enhanced 16-bit version of the TMS320C54x™ DSP 8-bit host-port interface (HPI8). The HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface. Some of the features of the HPI16 include:

• 16-bit bidirectional data bus

• Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts

• Only nonmultiplexed address/data modes are supported

• 16-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including

internal extended address pages)

• HRDY signal to hold off host accesses due to DMA latency

• The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the

DSP.

Only the nonmultiplexed mode is supported when the 5409A HPI is configured as a HPI16 (see Figure 3-8 ).

The 5409A HPI functions as a slave and enables the host processor to access the on-chip memory. A major enhancement to the 5409A HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one cycle. Note that since host accesses are always synchronized to the 5409A clock, an active input clock (CLKIN) is required for HPI accesses during IDLE states, and host accesses are not allowed while the 5409A reset pin is asserted.

NOTE

3.7.2 HPI Nonmultiplexed Mode

26 Functional Overview

In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 16-bit HA address bus. The host initiates the access with the strobe signals ( HDS1, HDS2, HCS) and controls the direction of the access with the HR/ W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. Figure 3-8 shows a block diagram of the HPI16 in nonmultiplexed mode.

Figure 3-8. Host-Port Interface — Nonmultiplexed Mode

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Address (Hex)

Reserved

Scratch-Pad

RAM

DARAM0 -

DARAM3

000 7FFF

000 8000

000 007F 000 0080

000 005F 000 0060

000 0000

Reserved

07F FFFF

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3.8 Multichannel Buffered Serial Ports (McBSPs)

The 5409A device provides high-speed, full-duplex serial ports that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. There are three multichannel buffered serial ports (McBSPs) on-chip.

The McBSP provides:

• Full-duplex communication

• Double-buffer data registers, which allow a continuous data stream

• Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

• Direct interface to: – T1/E1 framers – MVIP switching-compatible and ST-BUS compliant devices – IOM-2 compliant device – AC97-compliant device – Serial peripheral interface (SPI)

• Multichannel transmit and receive of up to 128 channels

• A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits

• µ-law and A-law companding

• Programmable polarity for both frame synchronization and data clocks

• Programmable internal clock and frame generation

Figure 3-9. HPI Memory Map

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The 5409A McBSPs have been enhanced to provide more flexibility in the choice of the sample rate generator input clock source. On previous TMS320C5000™ DSP platform devices, the McBSP sample rate input clock can be driven from one of two possible choices: the internal CPU clock, or the external CLKS pin. However, most C5000™ DSP devices have only the internal CPU clock as a possible source because the CLKS pin is not implemented on most device packages.

To accommodate applications that require an external reference clock for the sample rate generator, the 5409A McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be configured as the input clock to the sample rate generator. This enhancement is enabled through two register bits: pin control register (PCR) bit 7 - enhanced sample clock mode (SCLKME), and sample rate generator register 2 (SRGR2) bit 13 - McBSP sample rate generator clock mode (CLKSM). SCLKME is an addition to the PCR contained in the McBSPs on previous C5000 devices. The new bit layout of the PCR is shown in Figure 3-10 . For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302).

15 14 13 12 11 10 9 8

Reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM

R,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0

7 6 5 4 3 2 1 0

SCLKME CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP

RW,+0 R,+0 R,+0 R,+0 RW,+0 RW,+0 RW,+0 RW,+0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-10. Pin Control Register (PCR)

The selection of the sample rate generator (SRG) clock input source is made by the combination of the CLKSM and SCLKME bit values as shown in Table 3-7 .

Table 3-7. Sample Rate Generator Clock Source Selection

SCLKME CLKSM SRG CLOCK SOURCE

0 0 CLKS (not available as a pin on 5409A) 0 1 CPU clock 1 0 BCLKR pin 1 1 BCLKX pin

When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the BCLKX pin because the BCLKR output is automatically disabled.

The McBSP supports independent selection of multiple channels for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled.

The 5409A McBSPs have two working modes that are selected by setting the RMCME and XMCME bits in the multichannel control registers (MCR1x and MCR2x, respectively). See Figure 3-11 and Figure 3-12 . For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302).

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• In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each containing 16 channels as shown in Figure 3-11 and Figure 3-12 . This is compatible with the McBSPs used in some earlier TMS320C54x devices, where only 32-channel selection is enabled (default).

15 14 13 12 11 10 9 8

Reserved XMCME XPBBLK

R,+0 RW,+0 RW,+0

7 6 5 4 2 1 0

XPBBLK XPABLK XCBLK XMCM

RW,+0 RW,+0 R,+0 RW,+0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-11. Multichannel Control Register 2x (MCR2x)

15 14 13 12 11 10 9 8

Reserved RMCME RPBBLK

R,+0 RW,+0 RW,+0

7 6 5 4 2 1 0

RPBBLK RPABLK RCBLK RMCM

RW,+0 RW,+0 R,+0 RW,+0

LEGEND: R = Read, W = Write, n = value at reset

TMS320VC5409A

Figure 3-12. Multichannel Control Register 1x (MCR1x)

• In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128 channel selection capability. Twelve new registers (RCERCx-RCERHx and XCERCx-XCERHx) are used to enable the 128 channel selection. The subaddresses of the new registers are shown in Table 3-19 . These new registers, functionally equivalent to the RCERA0-RCERB1 and XCERA0-XCERB1 registers in the 5420, are used to enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G, and H) in the128 channel stream. For example, XCERH1 is the transmit enable for channel partition H (channels 112 to 127) of MCBSP1 for each DSP subsystem. See Figure 3-13 , Table 3-8 , Figure 3-14 , and Table 3-9 for bit layout and function of the receive and transmit registers .

15 14 13 12 11 10 9 8

RCERyz15 RCERyz14 RCERyz13 RCERyz12 RCERyz11 RCERyz10 RCERyz9 RCERyz8

RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0

7 6 5 4 3 2 1 0

RCERyz7 RCERyz6 RCERyz5 RCERy4 RCERyz3 RCERyz2 RCERyz1 RCERyz0

RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-13. Receive Channel Enable Registers Bit Layout for Partitions A to H

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Table 3-8. Receive Channel Enable Registers for Partitions A to H Field Descriptions

BIT FIELD VALUE DESCRIPTION

Receive Channel Enable Register

15-0 RCERyz(15:0) 0 Disables reception of nth channel in partition y.

1 Enables reception of nth channel in partition y.

15 14 13 12 11 10 9 8

XCERyz15 XCERyz14 XCERyz13 XCERyz12 XCERyz11 XCERyz10 XCERyz9 XCERyz8

RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0

7 6 5 4 3 2 1 0

XCERyz7 XCERyz6 XCERyz5 XCERy4 XCERyz3 XCERyz2 XCERyz1 XCERyz0

RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-14. Transmit Channel Enable Registers Bit Layout for Partitions A to H

Table 3-9. Transmit Channel Enable Registers for Partitions A to H Field Descriptions

Bit FIELD VALUE DESCRIPTION

Transmit Channel Enable Register

15-0 XCERyz(15:0) 0 Disables transmit of nth channel in partition y.

1 Enables transmit of nth channel in partition y.

The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface (SPI) protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum McBSP multichannel operating frequency on the 5409A is 9 MBps. Nonmultichannel operation is limited to 38 MBps.

3.9 Hardware Timer

The 5409A device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits.

3.10 Clock Generator

The clock generator provides clocks to the 5409A device, and consists of a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the 5409A device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

30 Functional Overview

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