TEXAS INSTRUMENTS TMS320VC5407, TMS320VC5404 Technical data

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TMS320VC5407/TMS320VC5404

Fixed-Point Digital Signal

Processors

Data Manual

Literature Number: SPRS007D

November 2001 − Revised April 2004

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright  2004, Texas Instruments Incorporated

Revision History

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS007C device-specific data
sheet to make it an SPRS007D revision.

Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date with the following changes.

PAGE(S)

NO.

21 Added “This pin must be tied directly to DVDD to enable HPI.” to the HPIENA description and “This pin must be tied directly to

38 Added the following to Section 3.9: “Since the Timer1 output is multiplexed externally with the HINT output, the HPI must be

42 Changed the parenthetical statement “(such as the McBSPs)” in Section 3.12. to read “(such as the McBSPs, but not the

48 Added the following footnote to Table 3−12: “Note that the UART DMA synchronization event is usable as a synchronization

59 Changed Figure 3−23, bit 15 from “Reserved” to “TOUT1”.

60 Added the following paragraph to Section 3.14.2: “Bit 15 of the GPIOCR is also used as the Timer1 output enable bit, TOUT1.

71 Changed the I

DV

to enable HPI16 mode.” to the HPI16 description in Table 2−2. Also deleted “Internally pulled low.” from the HPI16

DD

description.

disabled (HPIENA input pin = 0) if the Timer1 output is to be used. The Timer1 output also has a dedicated enable bit in the
General Purpose I/O Control Register (GPIOCR) located at data memory address 003Ch. If the external Timer1 output is to
be used, in addition to disabling the HPI, the TOUT1 bit in the GPIOCR must also be set to 1.”

UART)”

event only, and is not usable for transferring data to or from the UART. The DMA cannot be used to transfer data to or from
the UART.”

The TOUT1 bit enables or disables the Timer1 output on the HINT
available externally; if TOUT1 = 1, the Timer1 output is driven on the HINT
only available when the HPI is disabled (HPIENA input pin = 0).”

parameter from “60” to “42” in the Electrical Characteristics Over Recommended Operating Case

Temperature Range table.

DDC

ADDITIONS/CHANGES/DELETIONS

/TOUT1 pin. If TOUT1 = 0, the Timer1 output is not

/TOUT1 pin. Note also that the Timer1 output is

November 2001 − Revised April 2004 SPRS007D

3

Revision History

4

November 2001 − Revised April 2004SPRS007D

Contents

Contents

Section Page

1 TMS320VC5407/TMS320VC5404 Features 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Introduction 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Description 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Pin Assignments 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Terminal Assignments for the GGU Package 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Pin Assignments for the PGE Package 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Signal Descriptions 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Functional Overview 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Memory 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 Data Memory 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 Program Memory 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 Extended Program Memory 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 On-Chip ROM With Bootloader 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 On-Chip RAM 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 On-Chip Memory Security 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Memory Maps 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 5407 Memory Map 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 5404 Memory Map 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.3 Relocatable Interrupt Vector Table 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 On-Chip Peripherals 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 Software-Programmable Wait-State Generator 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.2 Programmable Bank-Switching 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.3 Bus Holders 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Parallel I/O Ports 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) 33. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.2 HPI Nonmultiplexed Mode 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 Multichannel Buffered Serial Ports (McBSPs) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9 Hardware Timers 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 Clock Generator 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11 Enhanced External Parallel Interface (XIO2) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12 DMA Controller 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.1 Features 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.2 DMA External Access 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.3 DMA Memory Map 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.4 DMA Priority Level 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.5 DMA Source/Destination Address Modification 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.6 DMA in Autoinitialization Mode 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.7 DMA Transfer Counting 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.8 DMA Transfer in Doubleword Mode 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.9 DMA Channel Index Registers 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.10 DMA Interrupts 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.11 DMA Controller Synchronization Events 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

November 2001 − Revised April 2004 SPRS007D

5

Contents

Section Page

3.13 Universal Asynchronous Receiver/Transmitter (UART) 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.1 UART Accessible Registers 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.2 FIFO Control Register (FCR) 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.3 FIFO Interrupt Mode Operation 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.4 FIFO Polled Mode Operation 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.5 Interrupt Enable Register (IER) 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.6 Interrupt Identification Register (IIR) 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.7 Line Control Register (LCR) 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.8 Line Status Register (LSR) 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.9 Modem Control Register (MCR) 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.10 Programmable Baud Generator 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.14 General-Purpose I/O Pins 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.14.1 McBSP Pins as General-Purpose I/O 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.14.2 HPI Data Pins as General-Purpose I/O 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.15 Device ID Register 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.16 Memory-Mapped Registers 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.17 McBSP Control Registers and Subaddresses 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.18 DMA Subbank Addressed Registers 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.19 Interrupts 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.19.1 IFR and IMR Registers 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Documentation Support 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Device and Development-Support Tool Nomenclature 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Electrical Specifications 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Absolute Maximum Ratings 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Recommended Operating Conditions 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Electrical Characteristics Over Recommended Operating Case Temperature

Range (Unless Otherwise Noted) 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Package Thermal Resistance Characteristics 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Timing Parameter Symbology 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Internal Oscillator With External Crystal 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Clock Options 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.1 Divide-By-Two and Divide-By-Four Clock Options 73. . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.2 Multiply-By-N Clock Option (PLL Enabled) 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Memory and Parallel I/O Interface Timing 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8.1 Memory Read 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8.2 Memory Write 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8.3 I/O Read 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8.4 I/O Write 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Ready Timing for Externally Generated Wait States 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 HOLD

and HOLDA Timings 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11 Reset, BIO, Interrupt, and MP/MC Timings 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings 90. . . . . . . . . . . . . . . . .

5.13 External Flag (XF) and TOUT Timings 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

November 2001 − Revised April 2004SPRS007D

Contents

Section Page

5.14 Multichannel Buffered Serial Port (McBSP) Timing 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.14.1 McBSP Transmit and Receive Timings 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.14.2 McBSP General-Purpose I/O Timing 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.14.3 McBSP as SPI Master or Slave Timing 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.15 Host-Port Interface Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.15.1 HPI8 Mode 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.15.2 HPI16 Mode 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.16 UART Timing 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Mechanical Data 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Ball Grid Array Mechanical Data 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Low-Profile Quad Flatpack Mechanical Data 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

November 2001 − Revised April 2004 SPRS007D

7

Figures

List of Figures

Figure Page

2−1 144-Ball GGU MicroStar BGA (Bottom View) 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 144-Pin PGE Low-Profile Quad Flatpack (Top View) 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 TMS320VC5407/TMS320VC5404 Functional Block Diagram 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 5407 Program and Data Memory Map 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 5407 Extended Program Memory Map 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 5404 Program and Data Memory Map 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 5404 Extended Program Memory Map 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 Processor Mode Status (PMST) Register 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] 30. . .

3−8 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] 31. . . . . . . . . . . . . . . . . . . . . . .

3−9 Bank-Switching Control Register (BSCR) [MMR Address 0029h] 32. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10 Host-Port Interface — Nonmultiplexed Mode 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 HPI Memory Map 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 Multichannel Control Register (MCR1) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 Multichannel Control Register (MCR2) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−14 Pin Control Register (PCR) 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−15 Nonconsecutive Memory Read and I/O Read Bus Sequence 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16 Consecutive Memory Read Bus Sequence (n = 3 reads) 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−17 Memory Write and I/O Write Bus Sequence 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−18 DMA Transfer Mode Control Register (DMMCRn) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−19 On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) 45. . . . . . . . . . . . . . . .

3−20 On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) 46. . . . . . . . . . . . .

3−21 DMPREC Register 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−22 UART Functional Block Diagram 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−23 General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] 59. . . . . . . . . . . . . . . . . . . .

3−24 General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] 60. . . . . . . . . . . . . . . . . . . . .

3−25 Device ID Register (CSIDR) [MMR Address 003Eh] 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−26 IFR and IMR 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 3.3-V Test Load Circuit 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Internal Divide-by-Two Clock Option With External Crystal 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3 External Divide-by-Two Clock Timing 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−4 Multiply-by-One Clock Timing 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−5 Nonconsecutive Mode Memory Reads 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−6 Consecutive Mode Memory Reads 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−7 Memory Write (MSTRB = 0) 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−8 Parallel I/O Port Read (IOSTRB = 0) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−9 Parallel I/O Port Write (IOSTRB = 0) 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

November 2001 − Revised April 2004SPRS007D

Figures

Figure Page

5−10 Memory Read With Externally Generated Wait States 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−11 Memory Write With Externally Generated Wait States 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−12 I/O Read With Externally Generated Wait States 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−13 I/O Write With Externally Generated Wait States 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−14 HOLD

and HOLDA Timings (HM = 1) 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−15 Reset and BIO Timings 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−16 Interrupt Timing 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−17 MP/MC Timing 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−18 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings 90. . . . . . . . . . . . . . . . . . . . .

5−19 External Flag (XF) Timing 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−20 TOUT Timing 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−21 McBSP Receive Timings 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−22 McBSP Transmit Timings 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−23 McBSP General-Purpose I/O Timings 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−24 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 96. . . . . . . . . . . . . . . . . . . . . . . .

5−25 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 97. . . . . . . . . . . . . . . . . . . . . . . .

5−26 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 98. . . . . . . . . . . . . . . . . . . . . . . .

5−27 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 99. . . . . . . . . . . . . . . . . . . . . . . .

5−28 Using HDS to Control Accesses (HCS Always Low) 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−29 Using HCS to Control Accesses 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−30 HINT Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−31 GPIOx Timings 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−32 Nonmultiplexed Read Timings 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−33 Nonmultiplexed Write Timings 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−34 HRDY Relative to CLKOUT 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−35 UART Timings 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 TMS320VC5407/TMS320VC5404 144-Ball MicroStar BGA Plastic Ball Grid Array Package 108. . . .

6−2 TMS320VC5407/TMS320VC5404 144-Pin Low-Profile Quad Flatpack (PGE) 109. . . . . . . . . . . . . . . .

November 2001 − Revised April 2004 SPRS007D

9

Tables

List of Tables

Table Page

2−1 Terminal Assignments for the 144-Pin BGA Package 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Signal Descriptions 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Standard On-Chip ROM Layout 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Processor Mode Status (PMST) Register Bit Fields 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Software Wait-State Register (SWWSR) Bit Fields 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Software Wait-State Control Register (SWCR) Bit Fields 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 Bank-Switching Control Register (BSCR) Fields 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 Bus Holder Control Bits 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 Sample Rate Input Clock Selection 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 Clock Mode Settings at Reset 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−9 DMD Section of the DMMCRn Register 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10 DMA Reload Register Selection 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 DMA Interrupts 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 DMA Synchronization Events 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 DMA/CPU Channel Interrupt Selection 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−14 UART Reset Functions 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−15 Summary of Accessible Registers 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16 Receiver FIFO Trigger Level 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−17 Interrupt Control Functions 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−18 Serial Character Word Length 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−19 Number of Stop Bits Generated 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−20 Baud Rates Using a 1.8432-MHz Clock 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−21 Baud Rates Using a 3.072-MHz Clock 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−22 Device ID Register (CSIDR) Bit Functions 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−23 CPU Memory-Mapped Registers 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−24 Peripheral Memory-Mapped Registers for Each DSP Subsystem 62. . . . . . . . . . . . . . . . . . . . . . . . . .

3−25 McBSP Control Registers and Subaddresses 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−26 DMA Subbank Addressed Registers 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−27 Interrupt Locations and Priorities 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 Thermal Resistance Characteristics 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Input Clock Frequency Characteristics 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3 Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options 73. . . . . . . . . . . . . .

5−4 Divide-By-2 and Divide-by-4 Clock Options Timing Requirements 74. . . . . . . . . . . . . . . . . . . . . . . . . .

5−5 Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics 74. . . . . . . . . . . . . . . . . . . . . . .

5−6 Multiply-By-N Clock Option Timing Requirements 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−7 Multiply-By-N Clock Option Switching Characteristics 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−8 Memory Read Timing Requirements 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−9 Memory Read Switching Characteristics 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−10 Memory Write Switching Characteristics 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−11 I/O Read Timing Requirements 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−12 I/O Read Switching Characteristics 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−13 I/O Write Switching Characteristics 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

November 2001 − Revised April 2004SPRS007D

Tables

Table Page

5−14 Ready Timing Requirements for Externally Generated Wait States 84. . . . . . . . . . . . . . . . . . . . . . . . .

5−15 Ready Switching Characteristics for Externally Generated Wait States 84. . . . . . . . . . . . . . . . . . . . . .

5−16 HOLD

and HOLDA Timing Requirements 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−17 HOLD and HOLDA Switching Characteristics 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−18 Reset, BIO, Interrupt, and MP/MC Timing Requirements 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−19 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics 90. . . . .

5−20 External Flag (XF) and TOUT Switching Characteristics 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−21 McBSP Transmit and Receive Timing Requirements 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−22 McBSP Transmit and Receive Switching Characteristics 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−23 McBSP General-Purpose I/O Timing Requirements 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−24 McBSP General-Purpose I/O Switching Characteristics 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−25 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 96. . . . . . . . . .

5−26 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 96. . . . . .

5−27 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 97. . . . . . . . . .

5−28 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 97. . . . . . .

5−29 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 98. . . . . . . . . .

5−30 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 98. . . . . .

5−31 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 99. . . . . . . . . .

5−32 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 99. . . . . . .

5−33 HPI8 Mode Timing Requirements 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−34 HPI8 Mode Switching Characteristics 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−35 HPI16 Mode Timing Requirements 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−36 HPI16 Mode Switching Characteristics 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−37 UART Timing Requirements 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−38 UART Switching Characteristics 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

November 2001 − Revised April 2004 SPRS007D

11

Tables

12

November 2001 − Revised April 2004SPRS007D

1 TMS320VC5407/TMS320VC5404 Features

Features

D Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and
One Program Memory Bus

D 40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators

D 17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation

D Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi
Operator

D Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle

D Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)

D Data Bus With a Bus Holder Feature
D Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program
Space

D On-Chip ROM

− 128K × 16-Bit (5407) Configured for
Program Memory

− 64K × 16-Bit (5404) Configured for
Program Memory

D On-Chip RAM

− 40K x 16-Bit (5407) Composed of
Five Blocks of 8K × 16-Bit On-Chip
Dual-Access Program/Data RAM

− 16K x 16-Bit (5404) Composed of
Two Blocks of 8K × 16-Bit On-Chip
Dual-Access Program/Data RAM

D Enhanced External Parallel Interface (XIO2)
D Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

D Block-Memory-Move Instructions for Better

Program and Data Management

D Instructions With a 32-Bit Long Word

Operand

D Instructions With Two- or Three-Operand

Reads

D Arithmetic Instructions With Parallel Store

and Parallel Load

D Conditional Store Instructions
D Fast Return From Interrupt
D On-Chip Peripherals

− Software-Programmable Wait-State
Generator and Programmable
Bank-Switching

− On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
External Clock Source

− Two 16-Bit Timers

− Six-Channel Direct Memory Access

(DMA) Controller

− Three Multichannel Buffered Serial Ports
(McBSPs)

− 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)

− Universal Asynchronous Receiver/
Transmitter (UART) With Integrated Baud
Rate Generator

D Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With
Power-Down Modes

D CLKOUT Off Control to Disable CLKOUT
D On-Chip Scan-Based Emulation Logic,

IEEE Std 1149.1
Logic

†

(JTAG) Boundary Scan

D 144-Pin Ball Grid Array (BGA)

(GGU Suffix)

D 144-Pin Low-Profile Quad Flatpack (LQFP)

(PGE Suffix)

D 8.33-ns Single-Cycle Fixed-Point

Instruction Execution Time (120 MIPS)

D 3.3-V I/O Supply Voltage
D 1.5-V Core Supply Voltage

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

All trademarks are the property of their respective owners.

November 2001 − Revised April 2004 SPRS007D

13

Introduction

2 Introduction

This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404
(hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407
and 5404 are essentially the same device except for differences in their memory maps.

This section lists the pin assignments and describes the function of each pin. This data manual also provides
a detailed description section, electrical specifications, parameter measurement information, and mechanical
data about the available packaging.

NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional
Overview (literature number SPRU307).

2.1 Description

The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree
of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing
a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In
addition, data can be transferred between data and program spaces. Such parallelism supports a powerful
set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle.
These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function
calls.

2.2 Pin Assignments

Figure 2−1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction
with Table 2−1 to locate signal names and ball grid numbers. Figure 2−2 provides the pin assignments for the
144-pin low-profile quad flatpack (LQFP) package.

TMS320C54x is a trademark of Texas Instruments.

14

November 2001 − Revised April 2004SPRS007D

2.2.1 Terminal Assignments for the GGU Package

Figure 2−1. 144-Ball GGU MicroStar BGA (Bottom View)

Introduction

12

3456781012 1113 9

A

B

C

D

E

F

G

H

J

K

L

M

N

Table 2−1 lists each signal name and BGA ball number for the 144-pin TMS320VC5407/
TMS320VC5404GGU package. Table 2−2 lists each terminal name, terminal function, and operating modes
for the TMS320VC5407/TMS320VC5404.

MicroStar BGA is a trademark of Texas Instruments.

November 2001 − Revised April 2004 SPRS007D

15

Introduction

†

SIGNAL

QUADRANT 4

SIGNAL

QUADRANT 1

V

SS

Table 2−1. Terminal Assignments for the 144-Pin BGA Package

SIGNAL

BGA BALL #

QUADRANT 2

BGA BALL #

A1 BCLKRX2 N13 V

SIGNAL

QUADRANT 3

SS

BGA BALL #

N1 A19 A13

A22 B1 BDX2 M13 TX N2 A20 A12

V

DV

SS

DD

C2 DV

C1 V

SS

DD

L12 HCNTL0 M3 V

L13 V

SS

N3 DV

SS

DD

A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10

HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10

A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10

A12 D1 HPI16 K13 BFSR1 N4 D9 A10

A13 E4 HD2 J10 BDR0 K5 D10 D9

A14 E3 TOUT J11 HCNTL1 L5 D11 C9

A15 E2 EMU0 J12 BDR1 M5 D12 B9

CV

DD

E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9

HAS F4 TDO H10 BCLKX1 K6 D13 D8

V

SS

V

SS

CV

DD

HCS G2 TMS G12 BFSX0 M7 CV

HR/W G1 V

READY G3 CV

PS G4 HPIENA G10 DV

DS H1 V

IS H2 CLKOUT F12 HD0 M8 DV

F3 TDI H11 V

SS

L6 D14 C8

F2 TRST H12 HINT/TOUT1 M6 D15 B8

F1 TCK H13 CVDD N6 HD5 A8

DD

SS

DD

SS

G13 BFSX1 N7 V

SS

G11 HRDY L7 HDS1 C7

K7 V

SS

N8 HDS2 A6

DD

F13 V

DD

SS

R/W H3 HD3 F11 BDX0 L8 A0 C6

MSTRB H4 X1 F10 BDX1 K8 A1 D6

IOSTRB J1 X2/CLKIN E13 IACK N9 A2 A5

MSC J2 RS E12 HBIL M9 A3 B5

XF J3 D0 E11 NMI L9 HD6 C5

HOLDA J4 D1 E10 INT0 K9 A4 D5

IAQ K1 D2 D13 INT1 N10 A5 A4

HOLD K2 D3 D12 INT2 M10 A6 B4

BIO K3 D4 D11 INT3 L10 A7 C4

MP/MC L1 D5 C13 CV

DV

DD

V

SS

L2 A16 C12 HD1 M11 A9 B3

L3 V

SS

C11 V

DD

SS

N11 A8 A3

L11 CV

DD

BDR2 M1 A17 B13 RX N12 A21 A2

BFSRX2 M2 A18 B12 V

SS

M12 V

SS

BGA BALL #

B11

A11

B7

A7

D7

B6

C3

B2

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the
core CPU.

16

November 2001 − Revised April 2004SPRS007D

2.2.2 Pin Assignments for the PGE Package

The TMS320VC5407/TMS320VC5404PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are
shown in Figure 2−2.

Introduction

V
A22
V

DV

DD

A10

HD7

A11
A12
A13
A14
A15

CV

DD

HAS

V
V

CV

DD

HCS

HR/W

READY

PS
DS

R/W

MSTRB

IOSTRB

MSC

XF

HOLDA

IAQ

HOLD

BIO

MP/MC

DV

DD

V

BDR2

BFSRX2

DD

SS

A9

A21

V

144CV143

142

141A8140A7139A6138A5137A4136

1

SS

2

3

SS

4

5

6

7

8

9

10

11

12

13

14

SS

15

SS

16

17

18

19

20

21

22

IS

23

24

25

26

27

28

29

30

31

32

33

34

SS

35

36

373839404142434445464748495051525354555657585960616263646566676869

HD6

135A3134A2133A1132A0131DV130

DD

HDS2SSV

129

128

SS

V

HDS1

127

126

DD

CV

125

HD5

124

D15

123

D14

122

D13

121

HD4

120

D12

119

D11

118

D10

117D9116D8115D7114D6113

DD

DV

112

SS

V

A20

111

110

707172

A19

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

A18
A17
V

SS

A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
V

SS

HPIENA
CV

DD

V

SS

TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
V

SS

DV

DD

BDX2
BCLKRX2

V

SS

TX

V

HCNTL0SSBCLKR0

BFSR0

BCLKR1

BDR0

BFSR1

BDR1

BCLKX0

HCNTL1

SS

V

BCLKX1

DD

CV

BFSX0

BFSX1

DD

HRDY

DV

SS

HD0

V

BDX0

IACK

BDX1

HBIL

NMI

INT0

INT1

INT2

INT3

DD

CV

HD1

SS

SS

RX

V

V

HINT/TOUT1

NOTE A: DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and

the core CPU.

Figure 2−2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)

November 2001 − Revised April 2004 SPRS007D

17

Introduction

2.3 Signal Descriptions

Table 2−2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.

Table 2−2. Signal Descriptions

TERMINAL

NAME

A22 (MSB)
A21
A20
A19
A18
A17
A16

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)

D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)

IACK O/Z Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching

INT0
INT1
INT2
INT3

NMI I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.

†

I = Input, O = Output, Z = High-impedance, S = Supply

†

I/O

EXTERNAL MEMORY INTERFACE PINS

O/Z Parallel address bus A22 (MSB) through A0 (LSB). The lower sixteen address pins—A0 to A15—are

I/O/Z D15 (MSB)

multiplexed to address all external memory (program, data) or I/O, while the upper seven address
pins—A22 to A16—are only used to address external program space. These pins are placed in the
high-impedance state when the hold mode is enabled, or when OFF

A15 (MSB)
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)

D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)

the interrupt vector location designated by A15–0. IACK
is low.

I External user interrupt inputs. INT0−3 are prioritized and maskable via the interrupt mask register and

interrupt mode bit. The status of these pins can be polled by way of the interrupt flag register.

When NMI

I These pins can be used to address internal memory via the HPI when the HPI16 pin

is high.

I/O Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins, D0 to D15,

are multiplexed to transfer data between the core CPU and external data/program
memory, I/O devices, or HPI in 16-bit mode. The data bus is placed in the
high-impedance state when not outputting or when RS
data bus also goes into the high-impedance state when OFF

The data bus includes bus holders to reduce the static power dissipation caused by
floating, unused pins. The bus holders also eliminate the need for external bias
resistors on unused pins. When the data bus is not being driven by the DSP, the bus
holders keep the pins at the logic level that was most recently driven. The data bus
holders of the DSP are disabled at reset, and can be enabled/disabled via the BH bit
of the BSCR.

INITIALIZATION, INTERRUPT, AND RESET PINS

is activated, the processor traps to the appropriate vector location.

DESCRIPTION

is low.

or HOLD is asserted. The

is low.

also goes into the high-impedance state when OFF

18

November 2001 − Revised April 2004SPRS007D

Introduction

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

RS I Reset input. RS causes the DSP to terminate execution and causes a re-initialization of the CPU and

MP/MC I Microprocessor/microcomputer mode select pin. If active low at reset, microcomputer mode is selected, and

BIO I Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor

XF O/Z External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set

DS
PS
IS

MSTRB O/Z Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access

READY I Data ready input. READY indicates that an external device is prepared for a bus transaction to be

R/W O/Z Read/write signal. R/W indicates transfer direction during communication to an external device. Normally in

IOSTRB O/Z I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an

HOLD I Hold input. HOLD is asserted to request control of the address, data, and control lines. When

HOLDA O/Z Hold acknowledge signal. HOLDA indicates that the DSP is in a hold state and that the address, data, and

MSC O/Z Microstate complete. MSC indicates completion of all software wait states. When two or more software wait

IAQ O/Z Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the

†

I = Input, O = Output, Z = High-impedance, S = Supply

†

INITIALIZATION, INTERRUPT, AND RESET PINS (CONTINUED)

peripherals. When RS

affects various registers and status bits.

RS

the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is
driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program
space. This pin is only sampled at reset, and the MP/MC
that is selected at reset.

MULTIPROCESSING AND GENERAL PURPOSE PINS

executes the conditional instruction. The BIO
for XC instruction, and all other instructions sample BIO

low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,
and is set high at reset.

O/Z Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for

accessing a particular external memory space. Active period corresponds to valid address information.
Placed into a high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state
when OFF

to data or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the
high-impedance state when OFF is low.

completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY
again. Note that the processor performs ready detection if at least two software wait states are
programmed. The READY signal is not sampled until the completion of the software wait states.

read mode (high), unless asserted low when the DSP performs a write operation. Placed in high-impedance
state in hold mode. R/W also goes into the high-impedance state when OFF is low.

I/O device. Placed in high-impedance state in hold mode. IOSTRB
when OFF

acknowledged by the C54x DSP, these lines go into high-impedance state.

control lines are in a high-impedance state, allowing the external memory interface to be accessed by other
devices. HOLDA also goes into the high-impedance state when is OFF low.

states are enabled, the MSC
inactive (high) at the beginning of the last software wait state. If connected to the ready input, MSC
one external wait state after the last internal wait state is completed. MSC
impedance state when OFF

address bus and goes into the high-impedance state when OFF

is low.

is low.

is brought to a high level, execution begins at location 0FF80h of program memory.

MEMORY CONTROL PINS

pin goes active at the beginning of the first software wait state, and goes

is low.

DESCRIPTIONI/O

bit of the PMST register can override the mode

condition is sampled during the decode phase of the pipeline

during the read phase of the pipeline.

also goes into the high-impedance state

also goes into the high

is low.

forces

C54x is a trademark of Texas Instruments.

November 2001 − Revised April 2004 SPRS007D

19

Introduction

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

CLKOUT O/Z Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine

CLKMD1
CLKMD2
CLKMD3

X2/CLKIN I Input pin to internal oscillator from the crystal. If the internal oscillator is not being used, an external clock

X1 O Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

TOUT O Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT

TOUT1 I/O/Z Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is a

BCLKR0
BCLKR1
BCLKRX2

BDR0
BDR1
BDR2

BFSR0
BFSR1
BFSRX2

BCLKX0
BCLKX1

†

OSCILLATOR/TIMER PINS

cycle is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when
OFF

is low.

I Clock mode external/internal input signals. CLKMD1−CLKMD3 allows you to select and configure different

clock modes such as crystal, external clock, various PLL factors.

source can be applied to this pin. The internal machine cycle time is determined by the clock operating
mode pins (CLKMD1, CLKMD2 and CLKMD3).

unconnected. X1 does not go into the high-impedance state when OFF
see Section 3.10 for additional information.)

cycle wide. TOUT also goes into the high-impedance state when OFF

CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT
available when the HPI is disabled.

MULTICHANNEL BUFFERED SERIAL PORT PINS

I/O/Z Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver. BCLKRX2

I/O/Z Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over

I/O/Z Transmit clock. BCLKX serves as the serial shift clock for the buffered serial port transmitter. The BCLKX

is McBSP2 transmit AND receive clock.

I Serial data receive input.

BDR. BFSRX2 is McBSP2 transmit AND receive frame sync.

pins are configured as inputs after reset. BCLKX goes into the high-impedance state when OFF

DESCRIPTIONI/O

is low. (This is revision depended,

is low.

pin of the HPI, and TOUT1 is only

is low.

BDX0
BDX1
BDX2

BFSX0
BFSX1

TX O UART asynchronous serial transmit data output.

RX I UART asynchronous serial receive data input.

†

I = Input, O = Output, Z = High-impedance, S = Supply

20

O/Z Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is

I/O/Z Frame synchronization pulse for transmit output. The BFSX pulse initiates the transmit data process over

asserted or when OFF

BDX. The BFSX pins are configured as inputs after reset. BFSX goes into the high-impedance state when
OFF

is low.

is low.

UART

November 2001 − Revised April 2004SPRS007D

Introduction

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

A0−A15 I These pins can be used to address internal memory via the HPI when the HPI16 pin is HIGH.

D0−D15 I/O These pins can be used to read/write internal memory via the HPI when the HPI16 pin is high. The sixteen

HD0−HD7 I/O/Z Parallel bi-directional data bus. These pins can also be used as general-purpose I/O pins when the HPI16 pin

HCNTL0
HCNTL1

HBIL I Byte identification input. Identifies first or second byte of transfer. (Pullup only enabled when HPIENA=0, invalid

HCS I Chip select input. This pin is the select input for the HPI, and must be driven low during accesses.

HDS1
HDS2

HAS I Address strobe input. Address strobe input. Hosts with multiplexed address and data pins require this input,

HR/W I Read/write input. This input controls the direction of an HPI transfer. (Pullup only enabled when HPIENA=0)

HRDY O/Z Ready output. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into

HINT O/Z Interrupt output. This output is used to interrupt the host. When the DSP is in reset, this signal is driven

HPIENA I HPI enable input. This pin must be tied directly to DVDD to enable the HPI. An internal pulldown resistor is

HPI16 I HPI 16-bit Select Pin. This pin must be tied directly to DVDD to enable HPI16 mode. This input pin has an

†

I = Input, O = Output, Z = High-impedance, S = Supply

†

HOST PORT INTERFACE PINS

data pins, D0 to D15, are multiplexed to transfer data between the core CPU and external data/program
memory, I/O devices, or HPI in 16-bit mode. The data bus is placed in the high-impedance state when not
outputting or when RS
OFF

is low.

The data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins.
The bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is
not being driven by the DSP, the bus holders keep the pins at the logic level that was most recently driven.
The data bus holders of the DSP are disabled at reset, and can be enabled/disabled via the BH bit of the
BSCR.

is high. HD0−HD7 is placed in the high-impedance state when not outputting data or when OFF
HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When
the HPI data bus is not being driven by the DSP, the bus holders keep the pins at the logic level that was most
recently driven. The HPI data bus holders are disabled at reset, and can be enabled/disabled via the HBH bit
of the BSCR.

I Control inputs. These inputs select a host access to one of the three HPI registers. (Pullup only enabled when

HPIENA=0, HPI16=1)

when HPI16=1)

(Pullup only enabled when HPIENA=0, or HPI16=1)

I Data strobe inputs. These pins are driven by the host read and write strobes to control transfers.

(Pullup only enabled when HPIENA=0)

to latch the address in the HPIA register. (Pull-up only enabled when HPIENA=0)

the high-impedance state when OFF

high

. HINT can also be used for timer 1 output (TOUT1), when the HPI is disabled. The signal goes into the

high-impedance state when OFF

always active and the HPIENA pin is sampled on the rising edge of RS
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the DSP
is reset.

internal pulldown resistor which is always active. If HPI16 is left open or driven low, HPI16 mode is disabled.
The non-multiplexed mode allows hosts with separate address/data buses to access the HPI address range
via the 16 address pins A0−A15. 16-bit Data is also accessible through pins D0−D15. HOST-to-DSP and
DSP-to-HOST interrupts are not supported. There are no HPIC and HPIA registers in the non-multiplexed
mode since there are HCNTRL0,1 signals available.

or HOLD is asserted. The data bus also goes into the high-impedance state when

is low.

is low. (invalid when HPI16=1)

DESCRIPTIONI/O

is low. The

. If HPIENA is left open or driven low

November 2001 − Revised April 2004 SPRS007D

21

Introduction

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

CV

DD

DV

DD

V

SS

TCK I IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The

TDI I IEEE standard 1149.1 test data input, pin with internal pullup device. TDI is clocked into the selected register

TDO O/Z IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted

TMS I IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into

TRST I IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of

EMU0 I/O/Z Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST

EMU1/OFF I/O/Z Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from

†

I = Input, O = Output, Z = High-impedance, S = Supply

†

DESCRIPTIONI/O

SUPPLY PINS

S +VDD. Dedicated 1.5V power supply for the core CPU.

S +VDD. Dedicated 3.3V power supply for I/O pins.

S Ground.

changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.

(instruction or data) on a rising edge of TCK.

out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is
in progress. TDO also goes into the high-impedance state when OFF is low.

the test access port (TAP) controller on the rising edge of TCK.

the operations of the device. If TRST

is not connected or driven low, the device operates in its functional

mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by
way of IEEE standard 1149.1 scan system. Should be pulled up to DV

with a separate 4.7-kΩ resistor.

DD

the emulator system and is defined as input/output via IEEE standard 1149.1 scan system. When TRST
driven low, EMU1/OFF
into the high-impedance state. Note that OFF
multiprocessing applications). Thus, for the OFF
EMU0=high, EMU1/OFF

is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers

is used exclusively for testing and emulation purposes (not for

feature, the following conditions apply: TRST=low,

= low. Should be pulled up to DVDD with a separate 4.7-kΩ resistor.

is

22

November 2001 − Revised April 2004SPRS007D

3 Functional Overview

The following functional overview is based on the block diagram in Figure 3−1.

P, C, D, E Buses and Control Signals

Cbus

54X cLEAD

TI BUS

Dbus

Ebus

RHEA
Bridge

Pbus

Cbus

Pbus

40K RAM

Dual Access

Program/Data

RHEA Bus

Dbus

†

Ebus

MBus

Pbus

128K Program

‡

ROM

GPIO

McBSP0

Functional Overview

†

16K for 5404

‡

64K for 5404

Figure 3−1. TMS320VC5407/TMS320VC5404 Functional Block Diagram

3.1 Memory

The 5407/5404 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.

3.1.1 Data Memory

XIO

16HPI

Enhanced XIO

16 HPI

xDMA

logic

RHEAbus

RHEA bus

MBus

MBus

Clocks

McBSP1

McBSP2

UART

TIMER

APLL

JTAG

The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip
RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device
automatically generates an external access.

The advantages of operating from on-chip memory are as follows:

• Higher performance because no wait states are required

• Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)

• Lower cost than external memory

• Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

November 2001 − Revised April 2004 SPRS007D

23

Functional Overview

3.1.2 Program Memory

Software can configure their memory cells to reside inside or outside of the program address map. When the
cells are mapped into program space, the device automatically accesses them when their addresses are
within bounds. When the program-address generation (PAGEN) logic generates an address outside its
bounds, the device automatically generates an external access. The advantages of operating from on-chip
memory are as follows:

• Higher performance because no wait states are required

• Lower cost than external memory

• Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

3.1.3 Extended Program Memory

The 5407/5404 uses a paged extended memory scheme in program space to allow access of up to 8192K
of program memory. In order to implement this scheme, the 5407/5404 includes several features which are
also present on C548/549/5410:

• Twenty-three address lines, instead of sixteen

• An extra memory-mapped register, the XPC

• Six extra instructions for addressing extended program space

Program memory in the 5407/5404 is organized into 128 pages that are each 64K in length.

The value of the XPC register defines the page selection. This register is memory-mapped into data space
to address 001Eh. At a hardware reset, the XPC is initialized to 0.

3.2 On-Chip ROM With Bootloader

The 5407 features a 128K-word × 16-bit on-chip maskable ROM that is mapped into program memory space,
but 16K words of which can also optionally be mapped into data memory. The 5404 features a 64K-word
16-bit on-chip maskable ROM that is mapped into program memory space.

Customers can also arrange to have the ROM of the 5407/5404 programmed with contents unique to any
particular application.

A bootloader is available in the standard 5407/5404 on-chip ROM. This bootloader can be used to
automatically transfer user code from an external source to anywhere in the program memory at power up.
If MP/MC
on-chip ROM. This location contains a branch instruction to the start of the bootloader program.

The standard 5407/5404 devices provide different ways to download the code to accommodate various
system requirements:

• Parallel from 8-bit or 16-bit-wide EPROM

• Parallel from I/O space, 8-bit or 16-bit mode

• Serial boot from serial ports, 8-bit or 16-bit mode

• UART boot mode

• Host-port interface boot

• Warm boot

of the device is sampled low during a hardware reset, execution begins at location FF80h of the

×

24

November 2001 − Revised April 2004SPRS007D

The standard on-chip ROM layout is shown in Table 3−1.

ADDRESS RANGE DESCRIPTION

C000h−D4FFh ROM tables for the GSM EFR speech codec

D500h−F7FFh Reserved

F800h−FBFFh Bootloader

FC00h−FCFFh µ-Law expansion table

FD00h−FDFFh A-Law expansion table

FE00h−FEFFh Sine look-up table

FF00h−FF7Fh Reserved

FF80h−FFFFh Interrupt vector table

†

In the 5407/5404 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h−FF7Fh in program space.

3.3 On-Chip RAM

The 5407 device contains 40K-words × 16-bit of on-chip dual-access RAM (DARAM), while the 5404 device
contains 16K-words x 16-bit of DARAM.

The DARAM is composed of five blocks of 8K words each. Each block in the DARAM can support two reads
in one cycle, or a read and a write in one cycle. The five blocks of DARAM on the 5407 are located in the
address range 0080h−9FFFh in data space, and can be mapped into program/data space by setting the OVLY
bit to one.

Table 3−1. Standard On-Chip ROM Layout

†

Functional Overview

†

On the 5404, the two blocks of DARAM are located at 0080h−3FFFh in data space and can also be mapped
into data space by setting OVLY to one.

3.4 On-Chip Memory Security

The 5407/5404 device provides maskable options to protect the contents of on-chip memories. When the
ROM protect option is selected, no externally originating instruction can access the on-chip ROM; when the
RAM protect option is selected, HPI RAM is protected; HPI writes are not restricted, but HPI reads are
restricted to 2000h − 3FFFh.

November 2001 − Revised April 2004 SPRS007D

25

Functional Overview

3.5 Memory Maps

3.5.1 5407 Memory Map

Page 0 Program

Hex

0000

007F
0080

9FFF
A000

FF7F

FF80

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

On-Chip
DARAM0−4
(OVLY = 1)

External

(OVLY = 0)

External

Interrupts
(External)

MP/MC

(Microprocessor Mode)

Page 0 Program

= 1

Hex

0000

007F

0080

5FFF
6000

FEFF

FF00

FF7F

FF80

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

On-Chip
DARAM0−2
(OVLY = 1)

External

(OVLY = 0)

On-Chip ROM

(40K x 16-bit)

Reserved

Interrupts
(On-Chip)

= 0

MP/MC

(Microcomputer Mode)

Hex

0000

005F

0060
007F
0080

9FFF

A000

BFFF

C000

FFFF

Memory-Mapped

Figure 3−2. 5407 Program and Data Memory Map

Data

Registers

Scratch-Pad

RAM

On-Chip

DARAM0−4

(40K x 16-bit)

External

On-Chip

PDROM0−1

(DROM=1)

or

External

(DROM=0)

Hex

010000

017FFF

018000

01FFFF

†

The lower 32K words of pages 1 through 127 are only available when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip memory
is mapped to the lower 32K words of all program space pages.

Program

External

On-Chip

ROM

Page 1
XPC=1

†

Hex

020000

027FFF

028000

02FFFF

Program

External

On-Chip

ROM

Page 2
XPC=2

†

Hex

030000

038000

03DFFF

03E000
03FFFF

Program

External

On-Chip

ROM

External

Page 3
XPC=3

†

Hex

040000

047FFF037FFF

048000

04FFFF

Program

External

External

Page 4
XPC=4

†

......

Hex

7F0000

7F7FFF

7F8000

7FFFFF

Program

External

External

Page 127

XPC=7Fh

†

Figure 3−3. 5407 Extended Program Memory Map

26

November 2001 − Revised April 2004SPRS007D

3.5.2 5404 Memory Map

Page 0 Program

Hex

0000

007F
0080

3FFF

4000

9FFF

A000

FF7F

FF80

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

On-Chip

DARAM0−1

(OVLY = 1)

External

(OVLY = 0)

Reserved

(OVLY = 1)

External

(OVLY = 0)

External

Interrupts
(External)

MP/MC

(Microprocessor Mode)

Page 0 Program

= 1

Hex

0000

007F

0080

3FFF

4000

5FFF

6000

7FFF

8000

FEFF

FF00
FF7F

FF80

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

On-Chip
DARAM0−1
(OVLY = 1)

External

(OVLY = 0)

Reserved

(OVLY = 1)

External

(OVLY = 0)

Reserved

On-Chip ROM

(32K x 16-bit)

Reserved

Interrupts
(On-Chip)

MP/MC

(Microcomputer Mode)

= 0

Hex

0000

005F

0060
007F
0080

3FFF

4000

9FFF

A000

BFFF

C000

FFFF

Memory-Mapped

Figure 3−4. 5404 Program and Data Memory Map

Data

Registers

Scratch-Pad

RAM

On-Chip

DARAM0−1

(32K x 16-bit)

Reserved

External

PDROM0−1
(DROM = 1)

or

External

(DROM = 0)

Functional Overview

November 2001 − Revised April 2004 SPRS007D

27

Functional Overview

Hex

010000

013FFF

014000

017FFF

018000

01FFFF

†

The lower 16K words of pages 1 through 127 are only available when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip memory
is mapped to the lower 16K words of all program space pages.

Program

External

Reserved

(OVLY = 1)

External

(OVLY = 0)

On-Chip

ROM

Page 1
XPC=1

†

Hex

020000

023FFF

024000

027FFF
028000

02FFFF

Program

External

Reserved

(OVLY = 1)

(OVLY = 0)

Reserved

†

External

Page 2
XPC=2

Hex

030000

034000

037FFF

038000

03DFFF

03E000

03FFFF

Program

External

Reserved

(OVLY = 1)

External

(OVLY = 0)

Reserved

External

Page 3
XPC=3

Hex

040000

†

043FFF033FFF

044000

047FFF

048000

04FFFF

Program

External

Reserved

(OVLY = 1)

External

(OVLY = 0)

External

Page 4
XPC=4

†

......

Hex

7F0000

7F3FFF

7F4000

7F7FFF

7F8000

7FFFFF

Program

External

Reserved

(OVLY = 1)

External

(OVLY = 0)

External

Page 127

XPC=7Fh

†

Figure 3−5. 5404 Extended Program Memory Map

3.5.3 Relocatable Interrupt Vector Table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved
at each vector location to accommodate a delayed branch instruction which allows branching to the
appropriate interrupt service routine without the overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.

NOTE: The hardware reset (RS
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

) vector cannot be remapped because the hardware reset loads the IPTR

28

November 2001 − Revised April 2004SPRS007D

15

RESET

Functional Overview

IPTR

R/W-1FF

7

IPTR MP/MC OVLY AVIS DROM CLKOFF SMUL SST

LEGEND: R = Read, W = Write, n = value after reset

654321 0

MP/MC Pin R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Figure 3−6. Processor Mode Status (PMST) Register

Table 3−2. Processor Mode Status (PMST) Register Bit Fields

BIT

NO. NAME

15−7 IPTR 1FFh

6 MP/MC

5 OVLY 0

4 AVIS 0

3 DROM 0

2 CLKOFF 0

1 SMUL N/A

0 SST N/A

RESET
VALUE

MP/MC

pin

FUNCTION

Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt
vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these
bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The
RESET instruction does not affect this field.

Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in
program memory space.

- MP/MC

- MP/MC

MP/MC
pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can
also be set or cleared by software.

RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.
The values for the OVLY bit are:

- OVLY = 0: The on-chip RAM is addressable in data space but not in program space.

- OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (addresses

Address visibility mode. AVIS enables/disables the internal program address to be visible at the
address pins.

- AVIS = 0: The external address lines do not change with the internal program address. Control and

- AVIS = 1: This mode allows the internal program address to appear at the pins of the 5407/5404 so

Data ROM. DROM enables on-chip ROM to be mapped into data space. The DROM bit values are:

- DROM = 0: The on-chip ROM is not mapped into data space.

- DROM = 1: A portion of the on-chip ROM is not mapped into data space.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high
level.

Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before
performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1
and FRCT = 1.

Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before
storing in memory. The saturation is performed after the shift operation.

= 0: The on-chip ROM is enabled and addressable.

= 1: The on-chip ROM is not available.

is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This

0h to 7Fh), however, is not mapped into program space.

data lines are not affected and the address bus is driven with the last address on the bus.

that the internal program address can be traced. Also, it allows the interrupt vector to be decoded
in conjunction with IACK

when the interrupt vectors reside on on-chip memory.

November 2001 − Revised April 2004 SPRS007D

29

Functional Overview

3.6 On-Chip Peripherals

The 5407/5404 device has the following peripherals:

• Software-programmable wait-state generator

• Programmable bank-switching

• A host-port interface (HPI8/16)

• Three multichannel buffered serial ports (McBSPs)

• Two hardware timers

• A clock generator with a multiple phase-locked loop (PLL)

• Enhanced external parallel interface (XIO2)

• A DMA controller (DMA)

• A UART with an integrated baud rate generator

3.6.1 Software-Programmable Wait-State Generator

The software wait-state generator of the 5407/5404 can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.
When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator
are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of
the 5407/5404.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 3−7 and described in Table 3−3.

15

XPA I/O DATA DATA

R/W-0 R/W-111 R/W-111

DATA PROGRAM PROGRAM

R/W-111 R/W-111 R/W-111

LEGEND: R = Read, W = Write, n = value after reset

14 12 11 9 8

65 32 0

Figure 3−7. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

30

November 2001 − Revised April 2004SPRS007D