Texas Instruments TMS320UC5409PGE-80, TMS320UC5409GGU-80 Datasheet

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus

40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation

Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator

Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

T wo Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

Data Bus With a Bus-Holder Feature

Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space

16K x 16-Bit On-Chip ROM

32K x 16-Bit Dual-Access On-Chip RAM

Single-Instruction-Repeat and Block-Repeat Operations for Program Code

Block-Memory-Move Instructions for Better Program and Data Management

Instructions With a 32-Bit Long Word Operand

Instructions With Two- or Three-Operand Reads

Arithmetic Instructions With Parallel Store and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

On-Chip Peripherals – Software-Programmable Wait-State

Generator and Programmable Bank Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or External Clock Source

– Three Multichannel Buffered Serial Ports

(McBSPs)

– Enhanced 8-Bit Parallel Host-Port

Interface With 16-Bit Data/Addressing – One 16-Bit Timer – Six-Channel Direct Memory Access

(DMA) Controller

Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic

12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS)

1.8-V Core Power Supply

1.8-V to 3.6-V I/O Power Supply Enables Operation With a SIngle 1.8-V Supply or With Dual Power Supplies

Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

description

The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5409 unless otherwise specified) is ideal for low-power, high-performance applications. This processor of fers very low power consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems. This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADVANCE INFORMATION

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5409 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory , and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

For detailed information on the architecture of the ’C5000 family of DSPs, see the

TMS320C5000 DSP Family

Functional Overview

(literature number SPRU307).

HDS1

A18 A17 V

A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT V

HPIENA CV

TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT HD2 HPI16 CLKMD3 CLKMD2 CLKMD1 V

BDX1 BFSX1

A22

A10

HD7

A11 A12 A13 A14 A15

HAS V

HCS

HR/W

READY

PS DS

R/W

MSTRB

IOSTRB

MSC

HOLDA

IAQ

HOLD

BIO

MP/MC

BDR1

BFSR1

144

A21

143

142

141A8140A7139A6138A5137A4136

HD6

135A3134A2133A1132A0131DV130

129

128

127

126

125

HD5

124

D15

123

D14

122

D13

121

HD4

120

D12

119

D11

118

117D9116D8115D7114D6113

112

373839404142434445464748495051525354555657585960616263646566676869

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

BCLKR1

HCNTL0SSBCLKR0

BCLKR2

BFSR0

BFSR2

BDR0

HCNTL1

BDR2

BCLKX0

BCLKX2

HD0

BDX0

BDX2

IACK

HBIL

NMI

INT0

INT1

INT2

INT3

HD1

HRDY

HINT

111

110

A19

109

707172

BCLKX1

D10

A20

HDS2SSV

TMS320UC5409 PGE PACKAGE

†‡

(TOP VIEW)

BFSX0

BFSX2

†

NC = No internal connection

‡

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

ADVANCE INFORMATION

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409 GGU PACKAGE

(BOTTOM VIEW)

A B

E F

H J

L M

3456781012 1113 9

The pin assignments table to follow lists each signal quadrant and BGA ball number for the TMS320UC5409GGU (144-pin BGA package).

ADVANCE INFORMATION

TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Assignments TMS320UC5409GGU (144-Pin BGA Package)

†

SIGNAL

QUADRANT 1

BGA BALL #

SIGNAL

QUADRANT 2

BGA BALL #

SIGNAL

QUADRANT 3

BGA BALL #

SIGNAL

QUADRANT 4

BGA BALL #

A1 BFSX1 N13 V

N1 A19 A13 A22 B1 BDX1 M13 BCLKR1 N2 A20 A12 V

C2 DV

L12 HCNTL0 M3 V

B11

C1 V

L13 V

N3 DV

A11 A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10 HD7 D3 CLKMD2 K11 BCLKR2 L4 D7 C10

A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10 A12 D1 HPI16 K13 BFSR2 N4 D9 A10 A13 E4 HD2 J10 BDR0 K5 D10 D9 A14 E3 TOUT J11 HCNTL1 L5 D11 C9 A15 E2 EMU0 J12 BDR2 M5 D12 B9

E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9 HAS F4 TDO H10 BCLKX2 K6 D13 D8 V

F3 TDI H11 V

L6 D14 C8

F2 TRST H12 HINT M6 D15 B8

F1 TCK H13 CV

N6 HD5 A8

HCS G2 TMS G12 BFSX0 M7 CV

HR/W G1 V

G13 BFSX2 N7 V

READY G3 CV

G11 HRDY L7 HDS1 C7

PS G4 HPIENA G10 DV

K7 V

DS H1 V

F13 V

N8 HDS2 A6

IS H2 CLKOUT F12 HD0 M8 DV

R/W H3 HD3 F11 BDX0 L8 A0 C6

MSTRB H4 X1 F10 BDX2 K8 A1 D6

IOSTRB J1 X2/CLKIN E13 IACK N9 A2 A5

MSC J2 RS E12 HBIL M9 A3 B5

XF J3 D0 E11 NMI L9 HD6 C5

HOLDA J4 D1 E10 INT0 K9 A4 D5

IAQ K1 D2 D13 INT1 N10 A5 A4

HOLD K2 D3 D12 INT2 M10 A6 B4

BIO K3 D4 D11 INT3 L10 A7 C4

MP/MC L1 D5 C13 CV

N11 A8 A3

L2 A16 C12 HD1 M11 A9 B3

L3 V

C11 V

L11 CV

BDR1 M1 A17 B13 BCLKX1 N12 A21 A2

BFSR1 M2 A18 B12 V

M12 V

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

ADVANCE INFORMATION

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

terminal functions

The following table lists each signal, function, and operating mode(s) grouped by function.

Terminal Functions

TERMINAL

NAME

I/O

†

DESCRIPTION

DATA SIGNALS

A22 (MSB) A21 A20 A19 A18 A17

O/Z

Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O while the upper seven address pins (A16 to A22) are only used to address external program space. These pins are placed in the high-impedance state when the hold mode is enabled, or when OFF

is low.

A16

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB)

A15 (MSB) A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB)

These pins can be used to address internal memory via the HPI when the HPI16 pin is high (A0 – A15).

D15 (MSB) D14 D13 D12 D11 D10 D9 D8

I/O/Z

D15 (MSB) D14 D13 D12 D11 D10 D9 D8

I/O Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are

multiplexed to transfer data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the high-impedance state when not outputting or when RS

or HOLD is asserted. The data bus also goes into the

high-impedance state when OFF

is low.

The data bus has bus holders to reduce the static power dissipation caused by

floating, unused pins. These bus holders also eliminate the need for external bias D7 D6 D5 D4 D3 D2 D1 D0 (LSB)

D7 D6 D5 D4 D3 D2 D1 D0 (LSB)

resistors on unused pins. When the data bus is not being driven by the ’UC5409, the

bus holders keep the pins at the previous logic level. The data bus holders on the

’UC5409 are disabled at reset and can be enabled/disabled via the BH bit of the

bank-switching control register (BSCR).

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

IACK

O/Z

Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15–A0. IACK

also goes into the high-impedance state when OFF is low.

INT0 INT1 INT2 INT3

External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the interrupt mode bit. INT0

–INT3 can be polled and reset by way of the interrupt flag register.

NMI

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI

is activated, the processor traps to the appropriate vector location.

†

I = Input, O = Output, Z = High-impedance, S = Supply

ADVANCE INFORMATION

TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONI/O

†

TERMINAL

NAME

DESCRIPTIONI/O

†

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU and peripherals. When RS

is brought to a high level, execution begins at location 0FF80h of program memory. RS

affects various registers and status bits.

MP/MC I

Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. MP/MC

is only sampled at reset, and the

MP/MC

bit of the PMST register can override the mode that is selected at reset.

MULTIPROCESSING SIGNALS

BIO I

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. For the XC instruction, the BIO

condition is sampled during the decode phase of the pipeline;

all other instructions sample BIO

during the read phase of the pipeline.

XF O/Z

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF

is low, and is set high

at reset.

MEMORY CONTROL SIGNALS

DS PS IS

O/Z

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing a particular external memory space. Active period corresponds to valid address information. DS

, PS, and IS are placed

into the high-impedance state in the hold mode; the signals also go into the high-impedance state when OFF

is low.

MSTRB O/Z

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB

is placed in the high-impedance state in the hold mode; it also goes into the

high-impedance state when OFF

is low.

READY I

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states.

R/W O/Z

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W

is placed in the

high-impedance state in hold mode; it also goes into the high-impedance state when OFF

is low.

IOSTRB O/Z

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB

is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF

is low.

HOLD I

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the ’C54x, these lines go into the high-impedance state.

HOLDA O/Z

Hold acknowledge. HOLDA indicates that the ’UC5409 is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices. HOLDA also goes into the high-impedance state when OFF is low.

MSC O/Z

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC

pin goes low during the last of these wait states. If connected to the READY input, MSC forces

one external wait state after the last internal wait state is completed. MSC

also goes into the high-impedance state

when OFF

is low.

IAQ O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus. IAQ

goes into the high-impedance state when OFF is low.

OSCILLATOR/TIMER SIGNALS

CLKOUT O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF

is low.

†

I = Input, O = Output, Z = High-impedance, S = Supply

ADVANCE INFORMATION

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONI/O

†

TERMINAL

NAME

DESCRIPTIONI/O

†

OSCILLATOR/TIMER SIGNALS (CONTINUED)

CLKMD1 CLKMD2 CLKMD3

Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized to the selected mode. After reset, the clock mode can be changed through software, but the clock mode select signals have no effect until the device is reset again.

X2/CLKIN I Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. X1 O

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when OFF

is low.

TOUT O/Z

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF

is low.

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

BCLKR0 BCLKR1 BCLKR2

I/O/Z Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0 BDR1 BDR2

I Serial data receive input

BFSR0 BFSR1 BFSR2

I/O/Z Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

BCLKX0 BCLKX1 BCLKX2

I/O/Z

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when OFF

goes

low.

BDX0 BDX1 BDX2

O/Z

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted, or when OFF

is low.

BFSX0 BFSX1 BFSX2

I/O/Z

Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the high-impedance state when OFF

is low.

HOST-PORT INTERFACE SIGNALS

A0 – A15 I These pins can be used to address internal memory via the HPI when the HPI16 pin is high.

D0 – D15 I/O

These pins can be used to read/write internal memory via the HPI when the HPI16 pin is high. The sixteen data pins, D0 to D15, are multiplexed to transfer data between the core CPU and external data/program memory, I/O devices, or HPI in 16-bit mode. The data bus is placed in the high-impedance state when not outputting or when RS

or HOLD

is asserted. The data bus also goes into the high-inmpedance state when OFF is low.

The data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the ’UC5409, the bus holders keep the pins at the logic level that was most recently driven. The data bus holders of the ’UC5409 are disabled at reset, and can be enabled/disabled via the BH bit of the BSCR.

HD0 – HD7 I/O/Z

Parallel bidirectional data bus. These pins can also be used as general-purpose I/O pins when the HPI16 pin is high. HD0–HD7 is placed in the high-impedance state when not outputting data or when OFF

is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the ’UC5409, the bus holders keep the pins at the logic level that was most recently driven. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

†

I = Input, O = Output, Z = High-impedance, S = Supply

ADVANCE INFORMATION

TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONI/O

†

TERMINAL

NAME

DESCRIPTIONI/O

†

HOST-PORT INTERFACE SIGNALS (CONTINUED)

HCNTL0 HCNTL1

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal pullup resistors that are only enabled when HPIENA = 0.

HBIL I

Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup resistor that is only enabled when HPIENA = 0.

HCS I

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input has an internal pullup resistor that is only enabled when HPIENA = 0.

HDS1 HDS2

Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.

HAS I

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register. HAS

has an internal pullup resistor that is only enabled when HPIENA = 0.

HR/W I

Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only enabled when HPIENA = 0.

HRDY O/Z

Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the high-impedance state when OFF

is low.

HINT O/Z

Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. The signal goes into the high-impedance state when OFF

is low.

HPIENA I

HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor is always active and the HPIENA pin is sampled on the rising edge of RS

. If HPIENA is left open or is driven low during reset,

the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’UC5409 is reset.

HPI16 I

HPI 16-bit select pin. HPI16 = 1 selects the non-multiplexed mode. The non-multiplexed mode allows hosts with separate address/data buses to access the HPI address range via the 16 address pins (A0–A15). The 16-bit data is also accessible through pins D0 through D15. Host-to-DSP and DSP-to-Host interrupts are not supported. There are no HPIC and HPIA registers in the non-multiplexed mode since HCNTRL0 and HCNTRL1 signals are available.

SUPPLY PNS

S +VDD. Dedicated 1.8-V power supply for the core CPU

S +VDD. Dedicated 3.3-V power supply for the I/O pins

S Ground

TEST PINS

TCK I

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller , instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.

TDI I

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.

TDO O/Z

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF

is low.

TMS I

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK.

TRST I

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST

is not connected or is driven low, the device operates in its functional mode, and

the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

†

I = Input, O = Output, Z = High-impedance, S = Supply

ADVANCE INFORMATION

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONI/O

†

TERMINAL

NAME

DESCRIPTIONI/O

†

TEST PINS (CONTINUED)

EMU0 I/O/Z

Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system.

EMU1/OFF I/O/Z

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST

driven low, EMU1/OFF

is configured as OFF . The EMU1/OFF signal, when active low , puts all output drivers into the

high-impedance state. Note that OFF

is used exclusively for testing and emulation purposes (not for multiprocessing

applications). Therefore, for the OFF

feature, the following apply:

TRST

= low EMU0 = high EMU1/OFF

= low

†

I = Input, O = Output, Z = High-impedance, S = Supply

memory

The ’UC5409 device provides both on-chip ROM and RAM memories to aid in system performance and integration.

on-chip ROM with bootloader

The ’5409 features a 16K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the ’5409 programmed with contents unique to any particular application. A security option is available to protect a custom ROM. This security option is described in the

TMS320C54x DSP CPU and Peripherals Reference Set,

Volume 1

(literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option,

is available on the ’5409 . A bootloader is available in the standard ’5409 on-chip ROM. This bootloader can be used to automatically

transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard ’5409 bootloader provides different ways to download the code to accomodate various system requirements:

Parallel from 8-bit or 16-bit-wide EPROM

Parallel from I/O space 8-bit or 16-bit mode

Serial boot from serial ports 8-bit or 16-bit mode

Host-port interface boot

SPI serial EEPROM 8-bit boot mode

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SPRS101A – APRIL 1999 – REVISED AUGUST 1999

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on-chip ROM with bootloader (continued)

The standard on-chip ROM layout is shown in Table 1.

Table 1. Standard On-Chip ROM Layout

†

ADDRESS RANGE DESCRIPTION

0x0000h – 0xBFFFh External program space 0xC000h – 0xF7FFh Reserved 0xF800h – 0xFBFFh Bootloader

0xFC00h – 0xFEFFh Reserved

0xFF00h – 0xFF7Fh Reserved

†

0xFF80h – 0xFFFFh Interrupt vector table

†

In the ’VC5409 ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in program space.

on-chip RAM

The ’UC5409 device contains 32K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of four blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h–7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one.

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memory map

Page 0 Program

Hex

Data

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

MP/MC

= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

007F 0080

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

Interrupts (External)

FF80

Memory-

Mapped

Registers

On-Chip DARAM

(32K words)

ROM

(DROM=1)

or External

(DROM=0)

0080

FFFF

Hex

0000

FF7F

FF00

FEFF

BFFF

C000

FFFF

0060

007F

0000

Hex

Page 0 Program

External

Scratch-Pad

RAM

Reserved

(DROM=1)

or External

(DROM=0)

005F

Reserved

(OVLY = 1)

External

(OVLY = 0)

007F 0080

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

FF80

FEFF

BFFF

C000

External

On-Chip ROM

(16K Words)

Interrupts (On-Chip)

7FFF

8000

FF00 FF7F

Reserved

Figure 1. Memory Map

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.

NOTE: The hardware reset (RS

) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

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extended program memory

The ’UC5409 uses a paged extended memory scheme in program space to allow access of up to 8M program memory locations. In order to implement this scheme, the ’UC5409 includes several features that are also present on the ’548/’549 devices:

Twenty-three address lines, instead of sixteen

An extra memory-mapped register, the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

Six extra instructions for addressing extended program space. These six instructions affect the XPC. –

FB[D]

pmad (23 bits) – Far branch

–

FBACC[D]

Accu[22:0] – Far branch to the location specified by the value in accumulator A or

accumulator B

–

FCALL[D]

pmad (23 bits) – Far call

–

FCALA[D]

Accu[22:0] – Far call to the location specified by the value in accumulator A or accumulator B

–

FRET[D]

– Far return

–

FRETE[D]

– Far return with interrupts enabled

In addition to these new instructions, two ’54x instructions are extended to use 23 bits in the ’UC5409: – READA data_memory (using 23-bit accumulator address) – WRITA data_memory (using 23-bit accumulator address)

All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access only memory within the current page.

Program memory in the ’UC5409 is organized into 127 pages that are each 64K in length, as shown in Figure 2.

00 0000

Internal

32K

Page 0

1 0000

1 7FFF

Page 1 Lower

32K

†

External

2 0000

2 7FFF

Page 2

Lower

32K

†

External

. . .

7F 0000

7F 7FFF

Page 127

Lower

32K

†

External

0 FFFF

32K

External

1 8000

1 FFFF

Page 1

Upper

32K

External

2 8000

2 FFFF

Page 2

Upper

32K

External

. . .

7F 8000

7F FFFF

Page 127

Upper

32K

External

†

The lower 32K words of pages 1 through 126 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM is mapped to the lower 32K words of all program space pages.

Figure 2. Extended Program Memory

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on-chip peripherals

The ’UC5409 device has the following peripherals:

Software-programmable wait-state generator with programmable bank-switching wait states

An enhanced 8-bit host-port interface (HPI8/16) with 16-bit data/addressing

Three multichannel buffered serial ports (McBSPs)

One hardware timer

A clock generator with a phase-locked loop (PLL)

A direct memory access (DMA) controller

software-programmable wait-state generator

The software wait-state generator of the ’UC5409 is similar to that of the ’5410 and it can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power comsumption of the ’UC5409.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the system configuration register (SCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3 and described in Table 2.

XPA I/O Data Data Program Program

14 12 11 9 8 6 5 3 2 015

R/W-111R/W-0 R/W-111 R/W-111 R/W-111 R/W-111

LEGEND: R = Read, W = Write

Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

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software-programmable wait-state generator (continued)

Table 2. Software Wait-State Register (SWWSR) Bit Fields

BIT

RESET

NO. NAME

VALUE

FUNCTION

15 XPA 0

Extended program address control bit. XP A is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states.

14–12 I/O 1

I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

11–9 Data 1

Upper data space. The field value (0–7) corresponds to the base number of wait states for external data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

8–6 Data 1

Lower data space. The field value (0–7) corresponds to the base number of wait states for external data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

5–3 Program 1

Upper program space. The field value (0–7) corresponds to the base number of wait states for external program space accesses within the following addresses:

XPA = 0: x8000 – xFFFFh

XPA = 1: The upper program space bit field has no ef fect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

2–0 Program 1

Program space. The field value (0–7) corresponds to the base number of wait states for external program space accesses within the following addresses:

XPA = 0: x0000–x7FFFh

XPA = 1: 00000–FFFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

The software wait-state multiplier bit of the software wait-state configuration register is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described in Table 3.

Reserved

115

R/W-0

SWSM

R/W-0

LEGEND: R = Read, W = Write

Figure 4. Software Wait-State Configuration Register (SWCR) [MMR Address 002Bh]

Table 3. Software Wait-State Configuration Register (SWCR) Bit Fields

RESET

NO. NAME

VALUE

FUNCTION

15–1 Reserved 0

These bits are reserved and are unaffected by writes.

0 SWSM 0

Software wait-state multiplier . Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2.

SWSM = 0: wait-state base values are unchanged (multiplied by 1).

SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.

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programmable bank-switching wait states

The programmable bank-switching logic of the ’UC5409 is functionally equivalent to that of the ’548/’549 devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the data space boundary into program space.

The bank-switching control register (BSCR) defines the bank size for bank-switching wait-states. Figure 5 shows the BSCR and its bits are described in Table 4.

BNKCMP PS-DS Reserved HBH

12 11 3 2 115

R/W-0R-0R/W-1R/W-1111

EXIO

010

R/W-0R/W-0

LEGEND: R = Read, W = Write

Figure 5. Bank-Switching Control Register (BSCR) [MMR Address 0029h]

Table 4. Bank-Switching Control Register Fields

BIT

RESET

NO. NAME

VALUE

FUNCTION

15–12 BNKCMP 1111

Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four MSBs of an address. For example, if BNKCMP = 11 11b, the four MSBs (bits 12–15) are compared, resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.

11 PS - DS 1

Program read – data read access. PS-DS inserts an extra cycle between consecutive accesses of program read and data read or data read and program read. PS-DS = 0 No extra cycles are inserted by this feature. PS-DS = 1 One extra cycle is inserted between consecutive data and program reads.

10–3 Reserved 0 These bits are reserved and are unaffected by writes.

2 HBH 0

HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset. HBH = 0 The bus holder is disabled. HBH = 1 The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the

previous logic level.

1 BH 0

Bus holder. BH controls the data bus holder feature. BH is cleared to 0 at reset. BH = 0 The bus holder is disabled. BH = 1 The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the

previous logic level.

External bus interface off. The EXIO bit controls the external bus-off function.

0 EXIO 0

EXIO

= 0

The external bus interface functions as usual

EXIO = 1 The address bus, data bus, and control signals become inactive after completing the

current bus cycle. Note that the

DROM, MP/MC

, and

OVLY bits in the PMST

and the

bit of ST1 cannot be modified when the interface is disabled.

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parallel I/O ports

The ’UC5409 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS

signal indicates a read/write operation through an I/O port. The ’UC5409 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.

enhanced 8-bit host-port interface (HPI8/16)

The ’UC5409 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI8/16 is an 8-bit parallel port for interprocessor communication. The features of the HPI8/16 include:

Standard features:

Sequential transfers (with autoincrement) or random-access transfers

Host interrupt and ’54x interrupt capability

Multiple data strobes and control pins for interface flexibility

Enhanced features of the ’UC5409 HPI8/16:

Access to entire on-chip RAM through DMA bus

Capability to continue transferring during emulation stop

Capability to transfer 16-bit address and 16-bit data (non-multiplexed mode)

The HPI8/16 functions as a slave and enables the host processor to access the on-chip memory of the ’UC5409. A major enhancement to the ’UC5409 HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The HPI8/16 does not have access to external memory. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority , and the DSP waits for one HPI8/16 cycle. Note that since host accesses are always synchronized to the ’UC5409 clock, an active input clock (CLKIN) is required for HPI8/16 accesses during IDLE states, and host accesses are not allowed while the ’UC5409 reset pin is asserted.

In standard 8-bit mode, the HPI8/16 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8/16 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the ’UC5409.

In 16-bit nonmultiplexed mode (HPI16=1), the HPI8/16 can read and write to internal memory via the external address and data pins, A0 – A15 and D0–D15, respectively. HD0–HD7 can be configured as general-purpose input/output (GPIO). The HPI16 non-multiplexed mode does not support the use of the HPID and HPIA registers. Host-to-DSP and DSP-to-host interrupts are also not supported. See Figure 6 for the HPI memory map.

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enhanced 8-bit host-port interface (HPI8/16) (continued)

0000h 005Fh

Reserved

0060h

007Fh

Scratch-Pad

RAM

0080h

7FFFh

On-Chip RAM

(32K x 16 Bits)

8000h

FFFFh

Reserved

Figure 6. ’UC5409 HPI Memory Map

HPI nonmultiplexed mode

nonmultiplexed

mode, a host with separate address/data buses can access the HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 16-bit HA address bus. The host initiates the access with the strobe signals (HDS1

, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not available in

nonmultiplexed

mode since there are no HCNTL signals available. All host accesses initiate a DMA

read or write access. Figure 7 shows a block diagram of the HPI16 in

nonmultiplexed

mode.

HPID[15:0]

HAS

HDS1, HDS2, HCS

DMA

Internal

Memory

PPD[15:0]

DATA[15:0]

Address[15:0]

R/W

Data Strobes

READY

HPI16

HRDY

’54xx

CPU

HCNTL0 HCNTL1

HR/W

HINT

HBIL

HOST

Figure 7. Host-Port Interface — Nonmultiplexed Mode

host access control

Host accesses are controlled by the data strobes (HDS1 and HDS2), along with chip select (HCS), in exactly the same fashion as documented in the

HPI nonmultiplexed mode

section.

host access type

nonmultiplexed

mode, only one access type (HPID read/write) is available since the HPIA register is not

needed because of direct address inputs, and since the HCNTL pins are not available for access-type selection.

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HPI16 control register (HPIC)

nonmultiplexed

mode, the HPIC register is not accessible via the host. This precludes DSP-to-host or host-to-DSP interrupts, data prefetch via the FETCH bit, and HRDY polling. Extended addressing capability still exists (even without the XHPIA bit) because the HA bus is 16 bits wide.

HPI16 address register (HPIA)

nonmultiplexed

mode, the HPIA register is not needed because direct address inputs A[15:0] are used as HA[15:0]. The DMA address comes directly from the HA pins. Note that the HA bus is still always latched at the end of the host access (on the rising edge of HDS = HDS1 XNOR HDS2) in order to ensure a valid address during the DMA write access.

host data prefetch

Since the HPIA register is not used in

nonmultiplexed

mode, the prefetch mechanism is not supported. Random

address accesses in

nonmultiplexed

mode are still faster than those in

multiplexed

mode because of the

separate address and data buses.

host ready logic (HRDY)

Hardware HRDY logic operation in

nonmultiplexed

mode is the same as that in

multiplexed

mode. HRDY

operation during prefetches and HRDY/FETCH bit interaction are not supported with

nonmultiplexed

mode.

host/DSP interrupts

Host-to-DSP and DSP-to-host interrupts are not supported by HPI16 in

nonmultiplexed

mode.

other HPI system considerations

operation during IDLE2

The HPI can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power . The DSP CPU does not wake up from the IDLE mode during this process.

multichannel buffered serial ports

The ’UC5409 device has three high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:

Full-duplex communication

Double-buffer data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

Direct interface to: – T1/E1 framers – MVIP switching-compatible and ST-BUS compliant devices – IOM-2 compliant devices – AC97-compliant devices – Serial peripheral interface (SPIt) devices

Multichannel transmit and receive of up to 128 channels

A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits

µ-law and A-law companding

Programmable polarity for both frame synchronization and data clocks

Programmable internal clock and frame generation

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multichannel buffered serial ports (continued)

The McBSPs consist of separate transmit and receive channels that operate independently. The external interface of each McBSP consists of the following pins:

BCLKX Transmit reference clock

BDX Transmit data

BFSX Transmit frame synchronization

BCLKR Receive reference clock

BDR Receive data

BFSR Receive frame synchronization

The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.

On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins, respectively . The CPU or DMA can read received data from the data receive register (DRR). Data received on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR). If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR is available. This structure allows storage of the two previous words while the reception of the current word is in progress.

The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP interrupts, event signals, and status flags. The DMA is capable of handling data movement between the McBSPs and memory with no intervention from the CPU.

In addition to the standard serial port functions, the McBSP provides programmable clock and frame sync generation. Among the programmable functions are:

Frame synchronization pulse width

Frame period

Frame synchronization delay

Clock reference (internal vs. external)

Clock division

Clock and frame sync polarity

The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format. When companding is used, transmit data is encoded according to specified companding law and received data is decoded to 2s complement format.

The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to 32 channels in a stream of up to 128 channels can be enabled.

The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI) protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU clock frequency divided by 2.

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sample rate generator external clock options

Although the CLKS pin is not available on the ’5409 PGE and GGU packages, the ’5409 is capable of synchronization to external clock sources. CLKX or CLKR can be used by the sample rate generator for external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to accomodate this option.

15 14 13 12 11 10 9 8

Reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM

RW RW RW RW RW RW RW

76543210

SCLKME CLKS STAT DX STAT DR STAT FSXP FSRP CLKXP CLKRP

RW RW RW RW RW RW RW RW

Legend: R = Read, W = Write

Figure 8. Pin Control Register (PCR)

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sample rate generator external clock options (continued)

Table 5. Pin Control Register (PCR) Bit Field Description

BIT NAME FUNCTION

15 – 14 Reserved Reserved. Pins are not used.

13 XIOEN

Transmit/Receive general-purpose I/O mode ONLY when XRST=0 in the SPCR(1/2)

XIOEN = 0 DX pin is not a general-purpose output. FSX and CLKX are not general-purpose I/Os. XIOEN = 1 DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These

serial port pins do not perform serial port operations.

12 RIOEN

Transmit/Receive general-purpose I/O mode ONLY when RRST=0 in the SPCR(1/2)

RIOEN = 0 DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not

general-purpose I/Os.

RIOEN = 1 DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-purpose

I/Os. These serial port pins do not perform serial port operations. The CLKS pin is affected by a combination of RRST

and RIOEN signals of the receiver.

11 FSXM

Transmit frame synchronization mode

FSRM = 0 Frame synchronization signal derived from an external source. FSRM = 1 Frame synchronization is determined by the sample rate generator frame

synchronization mode bit (FSGM) in the SRGR2.

10 FSRM

Receive frame synchronization mode

FSRM = 0 Frame synchronization pulses generated by an external device. FSR is an input pin. FSRM = 1 Frame synchronization generated internally by the sample rate generator . FSR is an

output pin except when GSYNC=1 in the SRGR.

9 CLKRM

Receiver clock mode

Case 1: Digital loop-back mode is not set (CLB=0) in SPCR1.

CLKRM = 0 Receive clock (CLKR) is an input pin driven by an external clock. CLKRM= 1 CLKR is an output pin and is driven by the internal sample rate generator

Case 2: Digital loop-back mode set (CLB=1) in SPCR1

CLKRM = 0 Receive clock (

Not

the CLKR pin) is driven by transmit clock (CLKX), which is based

on CLKXM bit in the PCR. CLKR pin is in high-impedance mode.

CLKRM= 1 CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived

based on the CLKXM bit in the PCR.

8 CLKXM

Transmitter clock mode

CLKXM = 0 Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input

CLKXM= 1 CLK(R/X) is an output pin and is driven by the internal sample rate generator

During SPI mode (CLKSTP is a non-zero value):

CLKXM = 0 McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR

is internally driven by CLKX.

CLKXM= 1 McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR)

and the shift clock of the SPI-compliant slaves in the system.

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Table 5. Pin Control Register (PCR) Bit Field Description (Continued)

BIT FUNCTIONNAME

7 SCLKME

Sample rate clock mode extended

SCLKME = 0 External clock via CLKS or CPU clock is used as a reference by the sample rate

generator.

SCLKME = 1 External clock via CLKR or CLKX clock is used as a reference by the sample rate

generator.

CLKS

STAT

CLKS pin status. CLKS STAT reflects value on CLKS pin when selected as a general-purpose input.

5 DX STAT DX pin status. DX STA T reflects value on DX pin when it is selected as a general-purpose output. 4 DR STAT DR pin status. DR STAT reflects value on DR pin when it is selected as a general-purpose input.

FSXP

Receive/Transmit frame synchronization polarity.

–

FSRP

FS(R/X)P = 0 Frame synchronization pulse FS(R/X) is active high FS(R/X)P = 1 Frame synchronization pulse FS(R/X) is active low

1 CLKXP

Transmit clock polarity

CLKXP = 0 Transmit data sampled on rising edge of CLKR CLKXP = 1 T ransmit data sampled on falling edge of CLKR

0 CLKRP

Receive clock polarity

CLKRP = 0 Receive data sampled on falling edge of CLKR CLKRP = 1 Receive data sampled on rising edge of CLKR

The ’5409 sample rate generator has four clock input options that are only available when both the PCR and SRGR2 are used. Table 6 shows the sample rate generator clock input options.

Table 6. Sample Rate Generator Clock Input Options

MODE

SCLKME

(PCR.7)

CLKSM

(SRGR2.13)

CLKS pin 0 0

CPU 0 1 CLKR pin 1 0 CLKX pin 1 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GSYNC CLKSP CLKSM

FSGM

FPER

RW RW RW RW RW

Legend: R = Read, W = Write

Figure 9. Sample Rate Generator Register 2 (SRGR2)

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sample rate generator external clock options (continued)

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

sample rate generator external clock options (continued)

Table 7. Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions

BIT NAME FUNCTION

15 GSYNC

Sample rate gnereator clock synchronization. Only used when the external clock (CLKS) drives the sample rate generator clock (CLKSM=0)

GSYNC = 0 The sample rate generator clock (CLKG) is free-running. GSYNC = 1 The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and

frame sync signal (FSG) is generated only after detecting the receive frame synchronization signal (FSR). Also, frame period (FPER) is a don’t care because the period is dictated by the external frame sync pulse.

14 CLKSP

CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate generator clock (CLKSM=0).

CLKSP = 0 Rising edge of CLKS generates CLKG and FSG. CLKSP = 1 Falling edge of CLKS generates CLKG and FSG.

13 CLKSM

McBSP sample rate generator clock mode

SCLKME = 0 CLKSM = 0 Sample rate generator clock derived from the CLKS pin (in PCR) CLKSM = 1 Sample rate generator clock derived from CPU clock

SCLKME = 1 CLKSM = 0 Sample rate generator clock derived from CLKR pin (in PCR) CLKSM = 1 Smaple rate generator clock derived from CLKX pin

12 FSGM

Sample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR.

FSGM = 0 Transmit frame sync signal (FSX) due to DXR(1/2) copy FSGN = 1 Transmit frame sync signal driven by the sample rate generator frame sync signal

(FSG)

11 – 0 FPER

Frame period. This determines when the next frame sycn signal should become active. Range: up to 212; 1 to 4096 CLKG periods.

hardware timer

The ’UC5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.

clock generator

The clock generator provides clocks to the ’UC5409 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the ’UC5409 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’UC5409 device.

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Texas Instruments TMS320UC5409PGE-80, TMS320UC5409GGU-80 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual