Texas Instruments TMS320UC5402PGE-80, TMS320UC5402GGU-80 Datasheet

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and One Program Memory Bus

D 40-Bit Arithmetic Logic Unit (ALU),

Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

D 17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation

D Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi Operator

D Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

D T wo Address Generators With Eight

Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

D Data Bus With a Bus-Holder Feature D Extended Addressing Mode for 1M × 16-Bit

Maximum Addressable External Program Space

D 4K x 16-Bit On-Chip ROM D 16K x 16-Bit Dual-Access On-Chip RAM D Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

D Block-Memory-Move Instructions for

Efficient Program and Data Management

D Instructions With a 32-Bit Long Word

Operand

D Instructions With Two- or Three-Operand

Reads

D Arithmetic Instructions With Parallel Store

and Parallel Load

D Conditional Store Instructions D Fast Return From Interrupt D On-Chip Peripherals

– Software-Programmable Wait-State

Generator and Programmable Bank Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or External Clock Source

– Two Multichannel Buffered Serial Ports

(McBSPs)

– Enhanced 8-Bit Parallel Host-Port

Interface (HPI-8) – Two 16-Bit Timers – Six-Channel Direct Memory Access

(DMA) Controller

D Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With Power-Down Modes

D CLKOUT Off Control to Disable CLKOUT D On-Chip Scan-Based Emulation Logic,

IEEE Std 1149.1† (JTAG) Boundary Scan Logic

D 12.5-ns Single-Cycle Fixed-Point

Instruction Execution Time (80 MIPS)

D 1.8-V Core Power Supply D 1.8-V to 3.6-V I/O Power Supply Enables

Operation With a Single 1.8-V Supply or with Dual Supplies

D Available in a 144-Pin Plastic Thin Quad

Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

description

The TMS320UC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5402 unless otherwise specified) is ideal for low-power, high-performance applications. This processor of fers very low power consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems. This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

T PREVIEW

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

T exas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long term reliability of the device.

System-level concerns such as bus contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to, the I/O buffers and powered down after the I/O buffers.

The ’UC5402 is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory , and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

NOTE: For detailed information on the architecture of the ’C5000 family of DSPs, see the

TMS320C5000 DSP Family

Functional Overview

(literature number SPRU307).

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

HDS1

A18 A17 V

A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT V

HPIENA CV

NC TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT0 HD2 NC CLKMD3 CLKMD2 CLKMD1 V

NC NC

A10

HD7

A11 A12 A13 A14 A15

NC HAS V

HCS

HR/W

READY

R/W

MSTRB

IOSTRB

MSC

HOLDA

IAQ

HOLD

BIO

MP/MC

DD V

144

143

142

141A8140A7139A6138A5137A4136

HD6

135A3134A2133A1132A0131DV130

129

128

127

126

125

HD5

124

D15

123

D14

122

D13

121

HD4

120

D12

119

D11

118

117D9116D8115D7114D6113

112

373839404142434445464748495051525354555657585960616263646566676869

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

HCNTL0SSBCLKR0

BCLKR1

BFSR0

BFSR1

BDR0

HCNTL1

BDR1

BCLKX0

BCLKX1

HD0

BDX0

BDX1

IACK

HBIL

NMI

INT0

INT1

INT2

INT3

HD1

HRDY

HINT/TOUT1

111

110

A19

109

707172

D10

HDS2SSV

PGE PACKAGE

†‡

(TOP VIEW)

BFSX0

BFSX1

†

NC = No connection. These pins should be left unconnected.

‡

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

The TMS320UC5402PGE (144-pin TQFP) package is footprint-compatible with the ’LC548 and ’LC/VC549.

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

GGU PACKAGE

(BOTTOM VIEW)

A B

E F

H J

L M

3456781012 1113 9

The pin assignments table to follow lists each signal name and BGA ball number for the TMS320UC5402GGU (144-pin BGA) package which is footprint compatible with the ’LC548 and ’LC/VC549.

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Assignments for the TMS320UC5402GGU (144-Pin BGA) Package

†

SIGNAL

NAME

BGA BALL #

SIGNAL

NAME

BGA BALL #

SIGNAL

NAME

BGA BALL #

SIGNAL

NAME

BGA BALL #

NC A1 NC N13 NC N1 A19 A13 NC B1 NC M13 NC N2 NC A12

C2 DV

L12 HCNTL0 M3 V

B11

C1 V

L13 V

N3 DV

A11 A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10 HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10 A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10 A12 D1 NC K13 BFSR1 N4 D9 A10 A13 E4 HD2 J10 BDR0 K5 D10 D9 A14 E3 TOUT0 J11 HCNTL1 L5 D11 C9 A15 E2 EMU0 J12 BDR1 M5 D12 B9

NC E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9 HAS F4 TDO H10 BCLKX1 K6 D13 D8 V

F3 TDI H11 V

L6 D14 C8

NC F2 TRST H12 HINT/TOUT1 M6 D15 B8

F1 TCK H13 CV

N6 HD5 A8

HCS G2 TMS G12 BFSX0 M7 CV

HR/W G1 NC G13 BFSX1 N7 NC A7

READY G3 CV

G11 HRDY L7 HDS1 C7

PS G4 HPIENA G10 DV

K7 V

DS H1 V

F13 V

N8 HDS2 A6

IS H2 CLKOUT F12 HD0 M8 DV

R/W H3 HD3 F11 BDX0 L8 A0 C6

MSTRB H4 X1 F10 BDX1 K8 A1 D6

IOSTRB J1 X2/CLKIN

‡

E13 IACK N9 A2 A5

MSC J2 RS E12 HBIL M9 A3 B5

XF J3 D0 E11 NMI L9 HD6 C5

HOLDA J4 D1 E10 INT0 K9 A4 D5

IAQ K1 D2 D13 INT1 N10 A5 A4

HOLD K2 D3 D12 INT2 M10 A6 B4

BIO K3 D4 D11 INT3 L10 A7 C4

MP/MC L1 D5 C13 CV

N11 A8 A3

L2 A16 C12 HD1 M11 A9 B3

L3 V

C11 V

L11 CV

C3 NC M1 A17 B13 NC N12 NC A2 NC M2 A18 B12 NC M12 NC B2

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

terminal functions

The following table lists each signal, function, and operating mode(s) grouped by function.

Terminal Functions

TERMINAL

NAME

TYPE

†

DESCRIPTION

DATA SIGNALS

A19 (MSB) A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB)

O/Z Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen

address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper four address pins (A16 to A19) are only used to address external program space. These pins are placed in the high-impedance state when the hold mode is enabled, or when EMU1/OFF

is low.

D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)

I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer

data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the high-impedance state when not outputting or when RS

or HOLD is asserted. The data bus also goes into the

high-impedance state when EMU1/OFF

is low.

The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the ’UC5402, the bus holders keep the pins at the previous logic level. The data bus holders on the ’UC5402 are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

IACK

O/Z

Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15–A0. IACK

also goes into the high-impedance state when EMU1/OFF

is low.

INT0 INT1 INT2 INT3

External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register (IMR) and the interrupt mode bit. INT0

–INT3 can be polled and reset by way of the interrupt flag register (IFR).

NMI

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI

is activated, the processor traps to the appropriate vector location.

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU and peripherals. When RS

is brought to a high level, execution begins at location 0FF80h of program

memory. RS

affects various registers and status bits.

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONTYPE

†

TERMINAL

NAME

DESCRIPTIONTYPE

†

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)

MP/MC I

Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin is only sampled at reset, and the MP/MC

bit of the processor mode status (PMST) register can override the mode

that is selected at reset.

MULTIPROCESSING SIGNALS

BIO I

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. For the XC instruction, the BIO

condition is sampled during the decode phase of the

pipeline; all other instructions sample BIO

during the read phase of the pipeline.

XF O/Z

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when EMU1/OFF

is low, and is set high at reset.

MEMORY CONTROL SIGNALS

DS PS IS

O/Z

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing a particular external memory space. Active period corresponds to valid address information. DS

, PS, and IS are placed into the high-impedance state in the hold mode; the signals also go into the high-impedance state when EMU1/OFF

is low.

MSTRB O/Z

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB

is placed in the high-impedance state in the hold mode; it also goes into the

high-impedance state when EMU1/OFF

is low.

READY I

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states.

R/W O/Z

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W

is placed in

the high-impedance state in hold mode; it also goes into the high-impedance state when EMU1/OFF

is low.

IOSTRB O/Z

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB

is placed in the high-impedance state in the hold mode; it also goes into the high-impedance

state when EMU1/OFF

is low.

HOLD I

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the ’C54x, these lines go into the high-impedance state.

HOLDA O/Z

Hold acknowledge. HOLDA indicates that the ’UC5402 is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices. HOLDA

also goes into the high-impedance state when EMU1/OFF is low.

MSC O/Z

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC

pin goes active at the beginning of the first software wait state and goes inactive

high at the beginning of the last software wait state. If connected to the READY input, MSC

forces one external

wait state after the last internal wait state is completed. MSC

also goes into the high-impedance state when

EMU1/OFF

is low.

IAQ O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus. IAQ

goes into the high-impedance state whenOFF EMU1/OFF is low.

PLL/TIMER SIGNALS

CLKOUT O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF is low.

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONTYPE

†

TERMINAL

NAME

DESCRIPTIONTYPE

†

PLL/TIMER SIGNALS (CONTINUED)

CLKMD1 CLKMD2 CLKMD3

Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select signals have no effect until the device is reset again.

X2/CLKIN

‡

I Clock/PLL input. If the internal oscillator is not being used, this X2/CLKIN functions as the clock input.

X1 O

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when EMU1/OFF

is low.

TOUT0 O/Z

Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF

is low.

TOUT1 O/Z

Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT

pin of the HPI and is only available when

the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF

is low.

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

BCLKR0 BCLKR1

I/O/Z Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0 BDR1

I Serial data receive input

BFSR0 BFSR1

I/O/Z Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

BCLKX0 BCLKX1

I/O/Z

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter . BCLKX can be configured as an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when EMU1/OFF

goes low.

BDX0 BDX1

O/Z

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted, or when EMU1/OFF

is low.

BFSX0 BFSX1

I/O/Z

Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the high-impedance state when EMU1/OFF

is low.

MISCELLANEOUS SIGNAL

NC No connection

HOST-PORT INTERFACE SIGNALS

HD0–HD7 I/O/Z

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the high-impedance state when not outputting data or when EMU1/OFF

is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the ’UC5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

HCNTL0 HCNTL1

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal pullup resistors that are only enabled when HPIENA = 0.

HBIL I

Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup resistor that is only enabled when HPIENA = 0.

HCS I

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input has an internal pullup resistor that is only enabled when HPIENA = 0.

HDS1 HDS2

Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.

HAS I

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register. HAS

has an internal pullup resistor that is only enabled when HPIENA = 0.

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONTYPE

†

TERMINAL

NAME

DESCRIPTIONTYPE

†

HOST-PORT INTERFACE SIGNALS (CONTINUED)

HR/W I

Read/write. HR/W controls the direction of an HPI transfer. HR/W has an internal pullup resistor that is only enabled when HPIENA = 0.

HRDY O/Z

Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the high-impedance state when EMU1/OFF

is low.

HINT O/Z

Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can also be configured as the timer 1 output (TOUT1) when the HPI is disabled. The signal goes into the high-impedance state when EMU1/OFF

is low.

HPIENA I

HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor is always active and the HPIENA pin is sampled on the rising edge of RS

. If HPIENA is left open or is driven low during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’UC5402 is reset.

SUPPLY PNS

S +VDD. Dedicated power supply for the core CPU

S +VDD. Dedicated power supply for the I/O pins

S Ground

TEST PINS

TCK I

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the T AP output signal (TDO) occur on the falling edge of TCK.

TDI I

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.

TDO O/Z

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when EMU1/OFF

is low.

TMS I

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK.

TRST I

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST

is not connected or is driven low, the device operates in its functional mode,

and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

EMU0 I/O/Z

Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system.

EMU1/OFF I/O/Z

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF

is used exclusively for testing and emulation purposes (not for

multiprocessing applications). Therefore, for the OFF

feature, the following apply:

TRST

= low EMU0 = high EMU1/OFF

= low

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory

The ’UC5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration.

on-chip ROM with bootloader

The ’UC5402 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the ’UC5402 programmed with contents unique to any particular application. A security option is available to protect a custom ROM. This security option is described in the

TMS320C54x DSP CPU and Peripherals

Reference Set, Volume 1

(literature number SPRU131). Note that only the ROM security option, and not the

ROM/RAM option, is available on the ’UC5402 . A bootloader is available in the standard ’UC5402 on-chip ROM. This bootloader can be used to automatically

transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard ’UC5402 bootloader provides different ways to download the code to accomodate various system requirements:

D Parallel from 8-bit or 16-bit-wide EPROM D Parallel from I/O space 8-bit or 16-bit mode D Serial boot from serial ports 8-bit or 16-bit mode D Host-port interface boot

The standard on-chip ROM layout is shown in Table 1.

Table 1. Standard On-Chip ROM Layout

†

ADDRESS RANGE DESCRIPTION

F000h – F7FFh Reserved

F800h – FBFFh Bootloader FC00h – FCFFh µ-law expansion table FD00h – FDFFh A-law expansion table FE00h – FEFFh Sine look-up table

FF00h – FF7Fh Reserved

FF80h – FFFFh Interrupt vector table

†

In the ’UC5402 ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in program space.

on-chip RAM

The ’UC5402 device contains 16K

× 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed

of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h–3FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to 1.

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory map

Page 0 Program

Hex

Data

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

MP/MC

= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

007F 0080

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

Interrupts

(External)

FF80

Memory Mapped

Registers

On-Chip DARAM

(16K x 16-bit)

ROM (DROM=1)

or External

(DROM=0)

0080

FFFF

Hex

0000

FF7F

FF00

FEFF

EFFF

F000

FFFF

3FFF

4000

0060

007F

0000

Hex

Page 0 Program

External

Scratch-Pad

RAM

Reserved

(DROM=1)

or External

(DROM=0)

005F

Reserved

(OVLY = 1)

External

(OVLY = 0)

007F 0080

3FFF

4000

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

FF00

FEFF

EFFF

F000

External

On-Chip ROM

(4K x 16-bit)

Interrupts (On-Chip)

3FFF

4000

Reserved

FF7F FF80

Figure 1. Memory Map

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.

NOTE: The hardware reset (RS

) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

extended program memory

The ’UC5402 uses a paged extended memory scheme in program space to allow access of up to 1024K program memory locations. In order to implement this scheme, the ’UC5402 includes several features that are also present on the ’548/’549 devices:

D Twenty address lines, instead of sixteen D An extra memory-mapped register, the XPC register, defines the page selection. This register is

memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

D Six extra instructions for addressing extended program space. These six instructions affect the XPC.

–

FB[D]

pmad (20 bits) – Far branch

–

FBACC[D]

Accu[19:0] – Far branch to the location specified by the value in accumulator A or

accumulator B

–

FCALL[D]

pmad (20 bits) – Far call

–

FCALA[D]

Accu[19:0] – Far call to the location specified by the value in accumulator A or accumulator B

–

FRET[D]

– Far return

–

FRETE[D]

– Far return with interrupts enabled

D In addition to these new instructions, two ’54x instructions are extended to use 20 bits in the ’UC5402:

– READA data_memory (using 20-bit accumulator address) – WRITA data_memory (using 20-bit accumulator address)

All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access only memory within the current page.

Program memory in the ’UC5402 is organized into 16 pages that are each 64K in length, as shown in Figure 2.

0 0000

1 0000

1 3FFF

Page 1

Lower

16K}

External

2 0000

2 3FFF

Page 2

Lower

16K}

External

. . . . . .

F 0000

F 3FFF

Page 15

Lower

16K}

External

0 FFFF

Page 0

64K

Words{

1 4000

1 FFFF

Page 1

Upper

48K

External

2 4000

2 FFFF

Page 2

Upper

48K

External

. . .

F 4000

F FFFF

Page 15

Upper

48K

External

†

See Figure 1

‡

The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM is mapped to the lower 16K words of all program space pages.

Figure 2. Extended Program Memory

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

on-chip peripherals

The ’UC5402 device has the following peripherals:

D Software-programmable wait-state generator with programmable bank-switching wait states D An enhanced 8-bit host-port interface (HPI-8) D Two multichannel buf fered serial ports (McBSPs) D Two hardware timers D A clock generator with a phase-locked loop (PLL) D A direct memory access (DMA) controller

software-programmable wait-state generator

The software wait-state generator of the ’UC5402 can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power comsumption of the ’UC5402.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 15 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3 and described in Table 2.

XPA I/O Data Data Program Program

14 12 11 9 8 6 5 3 2 015

R/W-111R/W-0 R/W-111 R/W-111 R/W-111 R/W-111

LEGEND: R=Read, W=Write, 0=V alue after reset

Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

software-programmable wait-state generator (continued)

Table 2. Software Wait-State Register (SWWSR) Bit Fields

BIT

RESET

NO. NAME

RESET

VALUE

FUNCTION

15 XPA 0

Extended program address control bit. XP A is used in conjunction with the program space fields (bits 0 through 5) to select the address range for the program space wait states.

14–12 I/O 1

I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

11–9 Data 1

Upper data space. The field value (0–7) corresponds to the base number of wait states for external data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

8–6 Data 1

Lower data space. The field value (0–7) corresponds to the base number of wait states for external data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

5–3 Program 1

Upper program space. The field value (0–7) corresponds to the base number of wait states for external program space accesses within the following addresses:

- XPA = 0: x8000 – xFFFFh

- XPA = 1: The upper program space bit field has no effect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

2–0 Program 1

Program space. The field value (0–7) corresponds to the base number of wait states for external program space accesses within the following addresses:

- XPA = 0: x0000–x7FFFh

- XPA = 1: 00000–FFFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described in Table 3.

Reserved

115

R/W-0

SWSM

R/W-0

LEGEND: R = Read, W = Write

Figure 4. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]

Table 3. Software Wait-State Control Register (SWCR) Bit Fields

BIT

RESET

NO. NAME

RESET

VALUE

FUNCTION

15–1 Reserved 0

These bits are reserved and are unaffected by writes.

0 SWSM 0

Software wait-state multiplier . Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2.

- SWSM = 0: wait-state base values are unchanged (multiplied by 1).

- SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable bank-switching wait states

The programmable bank-switching logic of the ’UC5402 is functionally equivalent to that of the ’548/’549 devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the data space boundary into program space.

The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 5 shows the BSCR and its bits are described in Table 4.

BNKCMP PS-DS Reserved HBH

12 11 3 2 115

R/W-0R-0R/W-1R/W-1111

EXIO

010

R/W-0R/W-0

LEGEND: R = Read, W = Write

Figure 5. Bank-Switching Control Register (BSCR) [MMR Address 0029h]

Table 4. Bank-Switching Control Register (BSCR) Bit Fields

BIT

RESET

NO. NAME

RESET

VALUE

FUNCTION

15–12 BNKCMP 1111

Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared, resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.

11 PS - DS 1

Program read – data read access. Inserts an extra cycle between consecutive accesses of program read and data read or data read and program read. PS-DS = 0 No extra cycles are inserted by this feature. PS-DS = 1 One extra cycle is inserted between consecutive data and program reads.

10–3 Reserved 0 These bits are reserved and are unaffected by writes.

2 HBH 0

HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset. HBH = 0 The bus holder is disabled. HBH = 1 The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the

previous logic level.

1 BH 0

Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset. BH = 0 The bus holder is disabled. BH = 1 The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the

previous logic level.

External bus interface off. The EXIO bit controls the external bus-off function.

0 EXIO 0

EXIO = 0 The external bus interface functions as usual. EXIO = 1 The address bus, data bus, and control signals become inactive after completing the

current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM bit of ST1 cannot be modified when the interface is disabled.

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

parallel I/O ports

The ’UC5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS

signal indicates a read/write operation through an I/O port. The ’UC5402 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.

enhanced 8-bit host-port interface (HPI-8)

The ’UC5402 host-port interface, also referred to as the HPI-8, is an enhanced version of the standard 8-bit HPI found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI-8 is an 8-bit parallel port for interprocessor communication. The features of the HPI-8 include:

Standard features:

D Sequential transfers (with autoincrement) or random-access transfers D Host interrupt and ’54x interrupt capability D Multiple data strobes and control pins for interface flexibility

Enhanced features of the ’UC5402 HPI-8:

D Access to entire on-chip RAM through DMA bus D Capability to continue transferring during emulation stop

FFFF

Reserved

4000

3FFF

Hex

0000

005F

0060

On-Chip DARAM

Scratch-Pad

0080

007F

(16K x 16-bit)

RAM

Reserved

McBSP

Registers

001F

0020

0023 0024

Reserved

Figure 6. ’UC5402 HPI-8 and DMA Memory Map

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

enhanced 8-bit host-port interface (HPI-8) (continued)

The HPI-8 functions as a slave and enables the host processor to access the on-chip memory of the ’UC5402. A major enhancement to the ’UC5402 HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP . The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority , and the DSP waits for one HPI-8 cycle. Note that since host accesses are always synchronized to the ’UC5402 clock, an active input clock (CLKIN) is required for HPI-8 accesses during IDLE states, and host accesses are not allowed while the ’UC5402 reset pin is asserted.

The HPI-8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI-8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the ’UC5402.

multichannel buffered serial ports

The ’UC5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other ’C54x/’LC54x DSPs, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:

D Full-duplex communication D Double-buffered data registers, which allow a continuous data stream D Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

D Direct interface to:

– T1/E1 framers – MVIP switching compatible and ST-BUS compliant devices – IOM-2 compliant devices – Serial peripheral interface devices

D Multichannel transmit and receive of up to 128 channels D A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits D µ-law and A-law companding D Programmable polarity for both frame synchronization and data clocks D Programmable internal clock and frame generation

The McBSPs consist of separate transmit and receive channels that operate independently. The external interface of each McBSP consists of the following pins:

D BCLKX Transmit reference clock D BDX Transmit data D BFSX Transmit frame synchronization D BCLKR Receive reference clock D BDR Receive data D BFSR Receive frame synchronization

The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multichannel buffered serial ports (continued)

On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins, respectively . The CPU or DMA can read received data from the data receive register (DRR). Data received on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR). If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR is available. This structure allows storage of the two previous words while the reception of the current word is in progress.

The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP interrupts, event signals, and status flags. The DMA is capable of handling data movement between the McBSPs and memory with no intervention from the CPU.

In addition to the standard serial port functions, the McBSP provides programmable clock and frame synchronization generation. Among the programmable functions are:

D Frame synchronization pulse width D Frame period D Frame synchronization delay D Clock reference (internal vs. external) D Clock division D Clock and frame synchronization polarity

The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format. When companding is used, transmit data is encoded according to specified companding law and received data is decoded to 2s complement format.

The McBSP allows multiple channels to be independently selected for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to 32 channels in a stream of up to 128 channels can be enabled.

The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI) protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU clock frequency divided by 2.

hardware timer

The ’UC5402 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.

clock generator

The clock generator provides clocks to the ’UC5402 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external reference clock source. The reference clock input is then divided by two or four (DIV mode) to generate clocks for the ’UC5402 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor. This allows the use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed 1.98 V.

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

clock generator (continued)

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’UC5402 device.

This clock generator allows system designers to select the clock source. The sources that drive the clock generator are:

D A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of

the ’UC5402 to enable the internal oscillator.

D An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left

unconnected.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed 1.98 V.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to the PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:

D PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved

using the PLL circuitry.

D DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be

completely disabled to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 – CLKMD3 pins as shown in Table 5.

Table 5. Clock Mode Settings at Reset

CLKMD1 CLKMD2 CLKMD3

CLKMD

CLOCK MODE

CLKMD1

CLKMD2

CLKMD3

RESET VALUE

CLOCK MODE

0 0 0 E007h PLL x 15 0 0 1 9007h PLL x 10

0 1 0 4007h PLL x 5 1 0 0 1007h PLL x 2 1 1 0 F007h PLL x 1 1 1 1 0000h 1/2 (PLL disabled) 1 0 1 F000h 1/4 (PLL disabled) 0 1 1 — Reserved (bypass mode)

T PREVIEW

+ 44 hidden pages

Texas Instruments TMS320UC5402PGE-80, TMS320UC5402GGU-80 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual