Texas Instruments TMS320UC5402PGE-80, TMS320UC5402GGU-80 Datasheet

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TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and One Program Memory Bus

D 40-Bit Arithmetic Logic Unit (ALU),

Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

D 17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation

D Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi Operator

D Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

D T wo Address Generators With Eight

Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

D Data Bus With a Bus-Holder Feature D Extended Addressing Mode for 1M × 16-Bit

Maximum Addressable External Program Space

D 4K x 16-Bit On-Chip ROM D 16K x 16-Bit Dual-Access On-Chip RAM D Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

D Block-Memory-Move Instructions for

Efficient Program and Data Management

D Instructions With a 32-Bit Long Word

Operand

D Instructions With Two- or Three-Operand

Reads

D Arithmetic Instructions With Parallel Store

and Parallel Load

D Conditional Store Instructions D Fast Return From Interrupt D On-Chip Peripherals

– Software-Programmable Wait-State

Generator and Programmable Bank Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or External Clock Source

– Two Multichannel Buffered Serial Ports

(McBSPs)

– Enhanced 8-Bit Parallel Host-Port

Interface (HPI-8) – Two 16-Bit Timers – Six-Channel Direct Memory Access

(DMA) Controller

D Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With Power-Down Modes

D CLKOUT Off Control to Disable CLKOUT D On-Chip Scan-Based Emulation Logic,

IEEE Std 1149.1† (JTAG) Boundary Scan Logic

D 12.5-ns Single-Cycle Fixed-Point

Instruction Execution Time (80 MIPS)

D 1.8-V Core Power Supply D 1.8-V to 3.6-V I/O Power Supply Enables

Operation With a Single 1.8-V Supply or with Dual Supplies

D Available in a 144-Pin Plastic Thin Quad

Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

description

The TMS320UC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5402 unless otherwise specified) is ideal for low-power, high-performance applications. This processor of fers very low power consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems. This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

T PREVIEW

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

T exas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long term reliability of the device.

System-level concerns such as bus contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to, the I/O buffers and powered down after the I/O buffers.

The ’UC5402 is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory , and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

NOTE: For detailed information on the architecture of the ’C5000 family of DSPs, see the

TMS320C5000 DSP Family

Functional Overview

(literature number SPRU307).

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TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

HDS1

A18 A17 V

A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT V

HPIENA CV

NC TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT0 HD2 NC CLKMD3 CLKMD2 CLKMD1 V

NC NC

A10

HD7

A11 A12 A13 A14 A15

NC HAS V

HCS

HR/W

READY

R/W

MSTRB

IOSTRB

MSC

HOLDA

IAQ

HOLD

BIO

MP/MC

DD V

144

143

142

141A8140A7139A6138A5137A4136

HD6

135A3134A2133A1132A0131DV130

129

128

127

126

125

HD5

124

D15

123

D14

122

D13

121

HD4

120

D12

119

D11

118

117D9116D8115D7114D6113

112

373839404142434445464748495051525354555657585960616263646566676869

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

HCNTL0SSBCLKR0

BCLKR1

BFSR0

BFSR1

BDR0

HCNTL1

BDR1

BCLKX0

BCLKX1

HD0

BDX0

BDX1

IACK

HBIL

NMI

INT0

INT1

INT2

INT3

HD1

HRDY

HINT/TOUT1

111

110

A19

109

707172

D10

HDS2SSV

PGE PACKAGE

†‡

(TOP VIEW)

BFSX0

BFSX1

†

NC = No connection. These pins should be left unconnected.

‡

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

The TMS320UC5402PGE (144-pin TQFP) package is footprint-compatible with the ’LC548 and ’LC/VC549.

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TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

GGU PACKAGE

(BOTTOM VIEW)

A B

E F

H J

L M

3456781012 1113 9

The pin assignments table to follow lists each signal name and BGA ball number for the TMS320UC5402GGU (144-pin BGA) package which is footprint compatible with the ’LC548 and ’LC/VC549.

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Assignments for the TMS320UC5402GGU (144-Pin BGA) Package

†

SIGNAL

NAME

BGA BALL #

SIGNAL

NAME

BGA BALL #

SIGNAL

NAME

BGA BALL #

SIGNAL

NAME

BGA BALL #

NC A1 NC N13 NC N1 A19 A13 NC B1 NC M13 NC N2 NC A12

C2 DV

L12 HCNTL0 M3 V

B11

C1 V

L13 V

N3 DV

A11 A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10 HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10 A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10 A12 D1 NC K13 BFSR1 N4 D9 A10 A13 E4 HD2 J10 BDR0 K5 D10 D9 A14 E3 TOUT0 J11 HCNTL1 L5 D11 C9 A15 E2 EMU0 J12 BDR1 M5 D12 B9

NC E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9 HAS F4 TDO H10 BCLKX1 K6 D13 D8 V

F3 TDI H11 V

L6 D14 C8

NC F2 TRST H12 HINT/TOUT1 M6 D15 B8

F1 TCK H13 CV

N6 HD5 A8

HCS G2 TMS G12 BFSX0 M7 CV

HR/W G1 NC G13 BFSX1 N7 NC A7

READY G3 CV

G11 HRDY L7 HDS1 C7

PS G4 HPIENA G10 DV

K7 V

DS H1 V

F13 V

N8 HDS2 A6

IS H2 CLKOUT F12 HD0 M8 DV

R/W H3 HD3 F11 BDX0 L8 A0 C6

MSTRB H4 X1 F10 BDX1 K8 A1 D6

IOSTRB J1 X2/CLKIN

‡

E13 IACK N9 A2 A5

MSC J2 RS E12 HBIL M9 A3 B5

XF J3 D0 E11 NMI L9 HD6 C5

HOLDA J4 D1 E10 INT0 K9 A4 D5

IAQ K1 D2 D13 INT1 N10 A5 A4

HOLD K2 D3 D12 INT2 M10 A6 B4

BIO K3 D4 D11 INT3 L10 A7 C4

MP/MC L1 D5 C13 CV

N11 A8 A3

L2 A16 C12 HD1 M11 A9 B3

L3 V

C11 V

L11 CV

C3 NC M1 A17 B13 NC N12 NC A2 NC M2 A18 B12 NC M12 NC B2

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

terminal functions

The following table lists each signal, function, and operating mode(s) grouped by function.

Terminal Functions

TERMINAL

NAME

TYPE

†

DESCRIPTION

DATA SIGNALS

A19 (MSB) A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB)

O/Z Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen

address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper four address pins (A16 to A19) are only used to address external program space. These pins are placed in the high-impedance state when the hold mode is enabled, or when EMU1/OFF

is low.

D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)

I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer

data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the high-impedance state when not outputting or when RS

or HOLD is asserted. The data bus also goes into the

high-impedance state when EMU1/OFF

is low.

The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the ’UC5402, the bus holders keep the pins at the previous logic level. The data bus holders on the ’UC5402 are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

IACK

O/Z

Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15–A0. IACK

also goes into the high-impedance state when EMU1/OFF

is low.

INT0 INT1 INT2 INT3

External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register (IMR) and the interrupt mode bit. INT0

–INT3 can be polled and reset by way of the interrupt flag register (IFR).

NMI

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI

is activated, the processor traps to the appropriate vector location.

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU and peripherals. When RS

is brought to a high level, execution begins at location 0FF80h of program

memory. RS

affects various registers and status bits.

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONTYPE

†

TERMINAL

NAME

DESCRIPTIONTYPE

†

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)

MP/MC I

Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin is only sampled at reset, and the MP/MC

bit of the processor mode status (PMST) register can override the mode

that is selected at reset.

MULTIPROCESSING SIGNALS

BIO I

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. For the XC instruction, the BIO

condition is sampled during the decode phase of the

pipeline; all other instructions sample BIO

during the read phase of the pipeline.

XF O/Z

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when EMU1/OFF

is low, and is set high at reset.

MEMORY CONTROL SIGNALS

DS PS IS

O/Z

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing a particular external memory space. Active period corresponds to valid address information. DS

, PS, and IS are placed into the high-impedance state in the hold mode; the signals also go into the high-impedance state when EMU1/OFF

is low.

MSTRB O/Z

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB

is placed in the high-impedance state in the hold mode; it also goes into the

high-impedance state when EMU1/OFF

is low.

READY I

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states.

R/W O/Z

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W

is placed in

the high-impedance state in hold mode; it also goes into the high-impedance state when EMU1/OFF

is low.

IOSTRB O/Z

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB

is placed in the high-impedance state in the hold mode; it also goes into the high-impedance

state when EMU1/OFF

is low.

HOLD I

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the ’C54x, these lines go into the high-impedance state.

HOLDA O/Z

Hold acknowledge. HOLDA indicates that the ’UC5402 is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices. HOLDA

also goes into the high-impedance state when EMU1/OFF is low.

MSC O/Z

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC

pin goes active at the beginning of the first software wait state and goes inactive

high at the beginning of the last software wait state. If connected to the READY input, MSC

forces one external

wait state after the last internal wait state is completed. MSC

also goes into the high-impedance state when

EMU1/OFF

is low.

IAQ O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus. IAQ

goes into the high-impedance state whenOFF EMU1/OFF is low.

PLL/TIMER SIGNALS

CLKOUT O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF is low.

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONTYPE

†

TERMINAL

NAME

DESCRIPTIONTYPE

†

PLL/TIMER SIGNALS (CONTINUED)

CLKMD1 CLKMD2 CLKMD3

Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select signals have no effect until the device is reset again.

X2/CLKIN

‡

I Clock/PLL input. If the internal oscillator is not being used, this X2/CLKIN functions as the clock input.

X1 O

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when EMU1/OFF

is low.

TOUT0 O/Z

Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF

is low.

TOUT1 O/Z

Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT

pin of the HPI and is only available when

the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF

is low.

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

BCLKR0 BCLKR1

I/O/Z Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0 BDR1

I Serial data receive input

BFSR0 BFSR1

I/O/Z Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

BCLKX0 BCLKX1

I/O/Z

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter . BCLKX can be configured as an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when EMU1/OFF

goes low.

BDX0 BDX1

O/Z

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted, or when EMU1/OFF

is low.

BFSX0 BFSX1

I/O/Z

Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the high-impedance state when EMU1/OFF

is low.

MISCELLANEOUS SIGNAL

NC No connection

HOST-PORT INTERFACE SIGNALS

HD0–HD7 I/O/Z

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the high-impedance state when not outputting data or when EMU1/OFF

is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the ’UC5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

HCNTL0 HCNTL1

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal pullup resistors that are only enabled when HPIENA = 0.

HBIL I

Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup resistor that is only enabled when HPIENA = 0.

HCS I

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input has an internal pullup resistor that is only enabled when HPIENA = 0.

HDS1 HDS2

Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.

HAS I

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register. HAS

has an internal pullup resistor that is only enabled when HPIENA = 0.

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTIONTYPE

†

TERMINAL

NAME

DESCRIPTIONTYPE

†

HOST-PORT INTERFACE SIGNALS (CONTINUED)

HR/W I

Read/write. HR/W controls the direction of an HPI transfer. HR/W has an internal pullup resistor that is only enabled when HPIENA = 0.

HRDY O/Z

Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the high-impedance state when EMU1/OFF

is low.

HINT O/Z

Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can also be configured as the timer 1 output (TOUT1) when the HPI is disabled. The signal goes into the high-impedance state when EMU1/OFF

is low.

HPIENA I

HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor is always active and the HPIENA pin is sampled on the rising edge of RS

. If HPIENA is left open or is driven low during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’UC5402 is reset.

SUPPLY PNS

S +VDD. Dedicated power supply for the core CPU

S +VDD. Dedicated power supply for the I/O pins

S Ground

TEST PINS

TCK I

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the T AP output signal (TDO) occur on the falling edge of TCK.

TDI I

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.

TDO O/Z

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when EMU1/OFF

is low.

TMS I

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK.

TRST I

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST

is not connected or is driven low, the device operates in its functional mode,

and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

EMU0 I/O/Z

Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system.

EMU1/OFF I/O/Z

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF

is used exclusively for testing and emulation purposes (not for

multiprocessing applications). Therefore, for the OFF

feature, the following apply:

TRST

= low EMU0 = high EMU1/OFF

= low

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory

The ’UC5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration.

on-chip ROM with bootloader

The ’UC5402 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the ’UC5402 programmed with contents unique to any particular application. A security option is available to protect a custom ROM. This security option is described in the

TMS320C54x DSP CPU and Peripherals

Reference Set, Volume 1

(literature number SPRU131). Note that only the ROM security option, and not the

ROM/RAM option, is available on the ’UC5402 . A bootloader is available in the standard ’UC5402 on-chip ROM. This bootloader can be used to automatically

transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard ’UC5402 bootloader provides different ways to download the code to accomodate various system requirements:

D Parallel from 8-bit or 16-bit-wide EPROM D Parallel from I/O space 8-bit or 16-bit mode D Serial boot from serial ports 8-bit or 16-bit mode D Host-port interface boot

The standard on-chip ROM layout is shown in Table 1.

Table 1. Standard On-Chip ROM Layout

†

ADDRESS RANGE DESCRIPTION

F000h – F7FFh Reserved

F800h – FBFFh Bootloader FC00h – FCFFh µ-law expansion table FD00h – FDFFh A-law expansion table FE00h – FEFFh Sine look-up table

FF00h – FF7Fh Reserved

FF80h – FFFFh Interrupt vector table

†

In the ’UC5402 ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in program space.

on-chip RAM

The ’UC5402 device contains 16K

× 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed

of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h–3FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to 1.

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memory map

Page 0 Program

Hex

Data

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

MP/MC

= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

007F 0080

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

Interrupts

(External)

FF80

Memory Mapped

Registers

On-Chip DARAM

(16K x 16-bit)

ROM (DROM=1)

or External

(DROM=0)

0080

FFFF

Hex

0000

FF7F

FF00

FEFF

EFFF

F000

FFFF

3FFF

4000

0060

007F

0000

Hex

Page 0 Program

External

Scratch-Pad

RAM

Reserved

(DROM=1)

or External

(DROM=0)

005F

Reserved

(OVLY = 1)

External

(OVLY = 0)

007F 0080

3FFF

4000

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

FF00

FEFF

EFFF

F000

External

On-Chip ROM

(4K x 16-bit)

Interrupts (On-Chip)

3FFF

4000

Reserved

FF7F FF80

Figure 1. Memory Map

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.

NOTE: The hardware reset (RS

) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

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extended program memory

The ’UC5402 uses a paged extended memory scheme in program space to allow access of up to 1024K program memory locations. In order to implement this scheme, the ’UC5402 includes several features that are also present on the ’548/’549 devices:

D Twenty address lines, instead of sixteen D An extra memory-mapped register, the XPC register, defines the page selection. This register is

memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

D Six extra instructions for addressing extended program space. These six instructions affect the XPC.

–

FB[D]

pmad (20 bits) – Far branch

–

FBACC[D]

Accu[19:0] – Far branch to the location specified by the value in accumulator A or

accumulator B

–

FCALL[D]

pmad (20 bits) – Far call

–

FCALA[D]

Accu[19:0] – Far call to the location specified by the value in accumulator A or accumulator B

–

FRET[D]

– Far return

–

FRETE[D]

– Far return with interrupts enabled

D In addition to these new instructions, two ’54x instructions are extended to use 20 bits in the ’UC5402:

– READA data_memory (using 20-bit accumulator address) – WRITA data_memory (using 20-bit accumulator address)

All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access only memory within the current page.

Program memory in the ’UC5402 is organized into 16 pages that are each 64K in length, as shown in Figure 2.

0 0000

1 0000

1 3FFF

Page 1

Lower

16K}

External

2 0000

2 3FFF

Page 2

Lower

16K}

External

. . . . . .

F 0000

F 3FFF

Page 15

Lower

16K}

External

0 FFFF

Page 0

64K

Words{

1 4000

1 FFFF

Page 1

Upper

48K

External

2 4000

2 FFFF

Page 2

Upper

48K

External

. . .

F 4000

F FFFF

Page 15

Upper

48K

External

†

See Figure 1

‡

The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM is mapped to the lower 16K words of all program space pages.

Figure 2. Extended Program Memory

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on-chip peripherals

The ’UC5402 device has the following peripherals:

D Software-programmable wait-state generator with programmable bank-switching wait states D An enhanced 8-bit host-port interface (HPI-8) D Two multichannel buf fered serial ports (McBSPs) D Two hardware timers D A clock generator with a phase-locked loop (PLL) D A direct memory access (DMA) controller

software-programmable wait-state generator

The software wait-state generator of the ’UC5402 can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power comsumption of the ’UC5402.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 15 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3 and described in Table 2.

XPA I/O Data Data Program Program

14 12 11 9 8 6 5 3 2 015

R/W-111R/W-0 R/W-111 R/W-111 R/W-111 R/W-111

LEGEND: R=Read, W=Write, 0=V alue after reset

Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

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software-programmable wait-state generator (continued)

Table 2. Software Wait-State Register (SWWSR) Bit Fields

BIT

RESET

NO. NAME

RESET

VALUE

FUNCTION

15 XPA 0

Extended program address control bit. XP A is used in conjunction with the program space fields (bits 0 through 5) to select the address range for the program space wait states.

14–12 I/O 1

I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

11–9 Data 1

Upper data space. The field value (0–7) corresponds to the base number of wait states for external data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

8–6 Data 1

Lower data space. The field value (0–7) corresponds to the base number of wait states for external data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

5–3 Program 1

Upper program space. The field value (0–7) corresponds to the base number of wait states for external program space accesses within the following addresses:

- XPA = 0: x8000 – xFFFFh

- XPA = 1: The upper program space bit field has no effect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

2–0 Program 1

Program space. The field value (0–7) corresponds to the base number of wait states for external program space accesses within the following addresses:

- XPA = 0: x0000–x7FFFh

- XPA = 1: 00000–FFFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described in Table 3.

Reserved

115

R/W-0

SWSM

R/W-0

LEGEND: R = Read, W = Write

Figure 4. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]

Table 3. Software Wait-State Control Register (SWCR) Bit Fields

BIT

RESET

NO. NAME

RESET

VALUE

FUNCTION

15–1 Reserved 0

These bits are reserved and are unaffected by writes.

0 SWSM 0

Software wait-state multiplier . Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2.

- SWSM = 0: wait-state base values are unchanged (multiplied by 1).

- SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.

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programmable bank-switching wait states

The programmable bank-switching logic of the ’UC5402 is functionally equivalent to that of the ’548/’549 devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the data space boundary into program space.

The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 5 shows the BSCR and its bits are described in Table 4.

BNKCMP PS-DS Reserved HBH

12 11 3 2 115

R/W-0R-0R/W-1R/W-1111

EXIO

010

R/W-0R/W-0

LEGEND: R = Read, W = Write

Figure 5. Bank-Switching Control Register (BSCR) [MMR Address 0029h]

Table 4. Bank-Switching Control Register (BSCR) Bit Fields

BIT

RESET

NO. NAME

RESET

VALUE

FUNCTION

15–12 BNKCMP 1111

Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared, resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.

11 PS - DS 1

Program read – data read access. Inserts an extra cycle between consecutive accesses of program read and data read or data read and program read. PS-DS = 0 No extra cycles are inserted by this feature. PS-DS = 1 One extra cycle is inserted between consecutive data and program reads.

10–3 Reserved 0 These bits are reserved and are unaffected by writes.

2 HBH 0

HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset. HBH = 0 The bus holder is disabled. HBH = 1 The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the

previous logic level.

1 BH 0

Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset. BH = 0 The bus holder is disabled. BH = 1 The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the

previous logic level.

External bus interface off. The EXIO bit controls the external bus-off function.

0 EXIO 0

EXIO = 0 The external bus interface functions as usual. EXIO = 1 The address bus, data bus, and control signals become inactive after completing the

current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM bit of ST1 cannot be modified when the interface is disabled.

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parallel I/O ports

The ’UC5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS

signal indicates a read/write operation through an I/O port. The ’UC5402 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.

enhanced 8-bit host-port interface (HPI-8)

The ’UC5402 host-port interface, also referred to as the HPI-8, is an enhanced version of the standard 8-bit HPI found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI-8 is an 8-bit parallel port for interprocessor communication. The features of the HPI-8 include:

Standard features:

D Sequential transfers (with autoincrement) or random-access transfers D Host interrupt and ’54x interrupt capability D Multiple data strobes and control pins for interface flexibility

Enhanced features of the ’UC5402 HPI-8:

D Access to entire on-chip RAM through DMA bus D Capability to continue transferring during emulation stop

FFFF

Reserved

4000

3FFF

Hex

0000

005F

0060

On-Chip DARAM

Scratch-Pad

0080

007F

(16K x 16-bit)

RAM

Reserved

McBSP

Registers

001F

0020

0023 0024

Reserved

Figure 6. ’UC5402 HPI-8 and DMA Memory Map

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enhanced 8-bit host-port interface (HPI-8) (continued)

The HPI-8 functions as a slave and enables the host processor to access the on-chip memory of the ’UC5402. A major enhancement to the ’UC5402 HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP . The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority , and the DSP waits for one HPI-8 cycle. Note that since host accesses are always synchronized to the ’UC5402 clock, an active input clock (CLKIN) is required for HPI-8 accesses during IDLE states, and host accesses are not allowed while the ’UC5402 reset pin is asserted.

The HPI-8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI-8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the ’UC5402.

multichannel buffered serial ports

The ’UC5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other ’C54x/’LC54x DSPs, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:

D Full-duplex communication D Double-buffered data registers, which allow a continuous data stream D Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

D Direct interface to:

– T1/E1 framers – MVIP switching compatible and ST-BUS compliant devices – IOM-2 compliant devices – Serial peripheral interface devices

D Multichannel transmit and receive of up to 128 channels D A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits D µ-law and A-law companding D Programmable polarity for both frame synchronization and data clocks D Programmable internal clock and frame generation

The McBSPs consist of separate transmit and receive channels that operate independently. The external interface of each McBSP consists of the following pins:

D BCLKX Transmit reference clock D BDX Transmit data D BFSX Transmit frame synchronization D BCLKR Receive reference clock D BDR Receive data D BFSR Receive frame synchronization

The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.

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multichannel buffered serial ports (continued)

On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins, respectively . The CPU or DMA can read received data from the data receive register (DRR). Data received on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR). If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR is available. This structure allows storage of the two previous words while the reception of the current word is in progress.

The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP interrupts, event signals, and status flags. The DMA is capable of handling data movement between the McBSPs and memory with no intervention from the CPU.

In addition to the standard serial port functions, the McBSP provides programmable clock and frame synchronization generation. Among the programmable functions are:

D Frame synchronization pulse width D Frame period D Frame synchronization delay D Clock reference (internal vs. external) D Clock division D Clock and frame synchronization polarity

The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format. When companding is used, transmit data is encoded according to specified companding law and received data is decoded to 2s complement format.

The McBSP allows multiple channels to be independently selected for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to 32 channels in a stream of up to 128 channels can be enabled.

The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI) protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU clock frequency divided by 2.

hardware timer

The ’UC5402 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.

clock generator

The clock generator provides clocks to the ’UC5402 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external reference clock source. The reference clock input is then divided by two or four (DIV mode) to generate clocks for the ’UC5402 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor. This allows the use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed 1.98 V.

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clock generator (continued)

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’UC5402 device.

This clock generator allows system designers to select the clock source. The sources that drive the clock generator are:

D A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of

the ’UC5402 to enable the internal oscillator.

D An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left

unconnected.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed 1.98 V.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to the PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:

D PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved

using the PLL circuitry.

D DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be

completely disabled to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 – CLKMD3 pins as shown in Table 5.

Table 5. Clock Mode Settings at Reset

CLKMD1 CLKMD2 CLKMD3

CLKMD

CLOCK MODE

CLKMD1

CLKMD2

CLKMD3

RESET VALUE

CLOCK MODE

0 0 0 E007h PLL x 15 0 0 1 9007h PLL x 10

0 1 0 4007h PLL x 5 1 0 0 1007h PLL x 2 1 1 0 F007h PLL x 1 1 1 1 0000h 1/2 (PLL disabled) 1 0 1 F000h 1/4 (PLL disabled) 0 1 1 — Reserved (bypass mode)

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DMA controller

The ’UC5402 direct memory access (DMA) controller transfers data between points in the memory map without intervention by the CPU. The DMA controller allows movements of data to and from internal program/data memory or internal peripherals (such as the McBSPs) to occur in the background of CPU operation. The DMA has six independent programmable channels, allowing six different contexts for DMA operation.

features

The DMA has the following features:

D The DMA operates independently of the CPU. D The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers. D The DMA has higher priority than the CPU for internal accesses. D Each channel has independently programmable priorities. D Each channel’s source and destination address registers can have configurable indexes through memory

on each read and write transfer, respectively. The address may remain constant, be postincremented, postdecremented, or be adjusted by a programmable value.

D Each read or write transfer may be initialized by selected events. D Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to the

CPU.

D The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).

DMA memory map

The DMA memory map allows DMA transfers to be unaffected by the status of the MP/MC, DROM, and OVL Y bits. The DMAmemory map is identical to that of the HPI-8 controller shown in Figure 6.

DMA priority level

Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple DMA channels that are assigned to the same priority level are handled in a round-robin manner.

DMA source/destination address modification

The DMA provides flexible address-indexing modes for easy implementation of data management schemes such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and can be postincremented, postdecremented, or postincremented with a specified index offset.

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DMA in autoinitialization mode

The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and DMGCR). Autoinitialization allows:

D Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the

completion of the current block transfer; but with the global reload registers, it can reinitialize these values for the next block transfer any time after the current block transfer begins.

D Repetitive operation: The CPU does not preload the global reload register with new values for each block

transfer but only loads them on the first block transfer.

DMA transfer counting

The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields that represent the number of frames and the number of elements per frame to be transferred.

D Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number

of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default value) means the block transfer contains a single frame.

D Element count. This 16-bit value defines the number of elements per frame. This counter is decremented

after the read transfer of each element. The maximum number of elements per frame is 65536 (DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded with the DMA global count reload register (DMGCR).

DMA transfers in double-word mode

Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated following each transfer. In this mode, each 32-bit word is considered to be one element.

DMA channel index registers

The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is the last in the current frame. The normal adjustment value (element index) is contained in the element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1.

The element index and the frame index affect address adjustment as follows:

D Element index: For all except the last transfer in the frame, the element index determines the amount to be

added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by the SIND/DIND bits.

D Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as selected

by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.

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DMA interrupts

The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is determined by the IMOD and DINM bits in the DMA mode control register (DMMCRn). The available modes are shown in Table 6.

Table 6. DMA Interrupts

MODE DINM IMOD INTERRUPT

ABU (non-decrement) 1 0 At full buffer only ABU (non-decrement) 1 1 At half buffer and full buffer Multi-Frame 1 0 At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0) Multi-Frame 1 1 At end of frame and end of block (DMCTRn = 0) Either 0 X No interrupt generated Either 0 X No interrupt generated

DMA controller synchronization events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event for a channel. The list of possible events and the DSYN values are shown in Table 7.

Table 7. DMA Synchronization Events

DSYN VALUE DMA SYNCHRONIZATION EVENT

0000b No synchronization used 0001b McBSP0 receive event 0010b McBSP0 transmit event

0011–0100b Reserved

0101b McBSP1 receive event

0110b McBSP1 transmit event

0111b–0110b Reserved

1101b Timer0 interrupt 1110b External interrupt 3 1111b Timer1 interrupt

DMA channel interrupt selection

The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an interrupt line with timer 1 (IMR/IFR bit 7). When the ’UC5402 is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these interrupts, as shown in Table 8.

Table 8. DMA Channel Interrupt Selection

INTSEL Value IMR/IFR[7] IMR/IFR[10] IMR/IFR[11]

00b (reset) TINT1 BRINT1 BXINT1

01b TINT1 DMAC2 DMAC3 10b DMAC1 DMAC2 DMAC3

11b Reserved

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memory-mapped registers

The ’UC5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to 1Fh. Table 9 gives a list of the CPU memory-mapped registers (MMRs) available on ’UC5402. The device also has a set of memory-mapped registers associated with peripherals. T able 10, T able 11, and T able 12 show additional peripheral MMRs associated with the ’UC5402.

Table 9. CPU Memory-Mapped Registers

ADDRESS

NAME

DEC HEX

DESCRIPTION

IMR 0 0 Interrupt mask register IFR 1 1 Interrupt flag register – 2–5 2–5 Reserved for testing ST0 6 6 Status register 0 ST1 7 7 Status register 1 AL 8 8 Accumulator A low word (15–0) AH 9 9 Accumulator A high word (31–16) AG 10 A Accumulator A guard bits (39–32) BL 11 B Accumulator B low word (15–0) BH 12 C Accumulator B high word (31–16) BG 13 D Accumulator B guard bits (39–32) TREG 14 E Temporary register TRN 15 F Transition register AR0 16 10 Auxiliary register 0 AR1 17 11 Auxiliary register 1 AR2 18 12 Auxiliary register 2 AR3 19 13 Auxiliary register 3 AR4 20 14 Auxiliary register 4 AR5 21 15 Auxiliary register 5 AR6 22 16 Auxiliary register 6 AR7 23 17 Auxiliary register 7 SP 24 18 Stack pointer register BK 25 19 Circular buffer size register BRC 26 1A Block-repeat counter RSA 27 1B Block-repeat start address REA 28 1C Block-repeat end address PMST 29 1D Processor mode status (PMST) register XPC 30 1E Extended program page register – 31 1F Reserved

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memory-mapped registers (continued)

Table 10. Peripheral Memory-Mapped Registers

NAME ADDRESS DESCRIPTION TYPE

DRR20 20h

McBSP0 data receive register 2 McBSP #0

DRR10 21h

McBSP0 data receive register 1 McBSP #0

DXR20 22h

McBSP0 data transmit register 2 McBSP #0

DXR10 23h

McBSP0 data transmit register 1 McBSP #0

TIM 24h

Timer0 register Timer0

PRD 25h

Timer0 period counter Timer0

TCR 26h

Timer0 control register Timer0 – 27h Reserved SWWSR 28h

Software wait-state register External Bus BSCR 29h

Bank-switching control register External Bus – 2Ah Reserved SWCR 2Bh

Software wait-state control register External Bus HPIC 2Ch

HPI control register HPI – 2Dh–2Fh Reserved TIM1 30h

Timer1 register Timer1 PRD1 31h

Timer1 period counter Timer1 TCR1 32h

Timer1 control register Timer1 – 33h–37h Reserved SPSA0

38h

McBSP0 subbank address register

†

McBSP #0

SPSD0

39h

McBSP0 subbank data register

†

McBSP #0 – 3Ah–3Bh Reserved GPIOCR

3Ch

General-purpose I/O pins control register

GPIO

GPIOSR

3Dh

General-purpose I/O pins status register

GPIO – 3Eh–3Fh Reserved DRR21 40h

McBSP1 data receive register 2 McBSP #1

DRR11 41h

McBSP1 data receive register 1 McBSP #1

DXR21 42h

McBSP1 data transmit register 2 McBSP #1

DXR11 43h

McBSP1 data transmit register 1 McBSP #1 – 44h–47h Reserved SPSA1 48h

McBSP1 subbank address register

†

McBSP #1

SPSD1

49h

McBSP1 subbank data register

†

McBSP #1 – 4Ah–53h Reserved DMPREC 54h

DMA channel priority and enable control register DMA

DMSA 55h

DMA subbank address register

‡

DMA

DMSDI

56h

DMA subbank data register with autoincrement

‡

DMA

DMSDN

57h

DMA subbank data register

‡

DMA

CLKMD

58h

Clock mode register

PLL

– 59h–5Fh Reserved

†

See Table 11 for a detailed description of the McBSP control registers and their subaddresses.

‡

See Table 12 for a detailed description of the DMA subbank addressed registers.

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McBSP control registers and subaddresses

The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register. Table 11 shows the McBSP control registers and their corresponding subaddresses.

Table 11. McBSP Control Registers and Subaddresses

McBSP0

NAME ADDRESS

McBSP1

NAME ADDRESS

SUB-

ADDRESS

DESCRIPTION

SPCR10

39h

SPCR11

49h

00h

Serial port control register 1

SPCR20

39h

SPCR21

49h

01h

Serial port control register 2

RCR10

39h

RCR11

49h

02h

Receive control register 1

RCR20

39h

RCR21

49h

03h

Receive control register 2

XCR10

39h

XCR11

49h

04h

Transmit control register 1

XCR20

39h

XCR21

49h

05h

Transmit control register 2

SRGR10

39h

SRGR11

49h

06h

Sample rate generator register 1

SRGR20

39h

SRGR21

49h

07h

Sample rate generator register 2

MCR10

39h

MCR11

49h

08h

Multichannel register 1

MCR20

39h

MCR21

49h

09h

Multichannel register 2

RCERA0

39h

RCERA1

49h

0Ah

Receive channel enable register partition A

RCERB0

39h

RCERB1

49h

0Bh

Receive channel enable register partition B

XCERA0

39h

XCERA1

49h

0Ch

Transmit channel enable register partition A

XCERB0

39h

XCERB1

49h

0Dh

Transmit channel enable register partition B

PCR0

39h

PCR1

49h

0Eh

Pin control register

DMA subbank addressed registers

The direct memory access (DMA) controller has several control registers associated with it. The main control register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with autoincrement (DMSDI) is used to access (read or write) the selected register.

When the DMSDI register is used to access the subbank, the subbank address is automatically postincremented so that a subsequent access affects the next register within the subbank. This autoincrement feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature is not required, the DMSDN register should be used to access the subbank. T able 12 shows the DMA controller subbank addressed registers and their corresponding subaddresses.

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DMA subbank addressed registers (continued)

Table 12. DMA Subbank Addressed Registers

NAME ADDRESS

†

SUB-

ADDRESS

DESCRIPTION

DMSRC0 56h/57h 00h DMA channel 0 source address register DMDST0 56h/57h 01h DMA channel 0 destination address register DMCTR0 56h/57h 02h DMA channel 0 element count register DMSFC0 56h/57h 03h DMA channel 0 sync select and frame count register DMMCR0 56h/57h 04h DMA channel 0 transfer mode control register DMSRC1 56h/57h 05h DMA channel 1 source address register DMDST1 56h/57h 06h DMA channel 1 destination address register DMCTR1 56h/57h 07h DMA channel 1 element count register DMSFC1 56h/57h 08h DMA channel 1 sync select and frame count register DMMCR1 56h/57h 09h DMA channel 1 transfer mode control register DMSRC2 56h/57h 0Ah DMA channel 2 source address register DMDST2 56h/57h 0Bh DMA channel 2 destination address register DMCTR2 56h/57h 0Ch DMA channel 2 element count register DMSFC2 56h/57h 0Dh DMA channel 2 sync select and frame count register DMMCR2 56h/57h 0Eh DMA channel 2 transfer mode control register DMSRC3 56h/57h 0Fh DMA channel 3 source address register DMDST3 56h/57h 10h DMA channel 3 destination address register DMCTR3 56h/57h 11h DMA channel 3 element count register DMSFC3 56h/57h 12h DMA channel 3 sync select and frame count register DMMCR3 56h/57h 13h DMA channel 3 transfer mode control register DMSRC4 56h/57h 14h DMA channel 4 source address register DMDST4 56h/57h 15h DMA channel 4 destination address register DMCTR4 56h/57h 16h DMA channel 4 element count register DMSFC4 56h/57h 17h DMA channel 4 sync select and frame count register DMMCR4 56h/57h 18h DMA channel 4 transfer mode control register DMSRC5 56h/57h 19h DMA channel 5 source address register DMDST5 56h/57h 1Ah DMA channel 5 destination address register DMCTR5 56h/57h 1Bh DMA channel 5 element count register DMSFC5 56h/57h 1Ch DMA channel 5 sync select and frame count register DMMCR5 56h/57h 1Dh DMA channel 5 transfer mode control register DMSRCP 56h/57h 1Eh DMA source program page address (common channel) DMDSTP 56h/57h 1Fh DMA destination program page address (common channel) DMIDX0 56h/57h 20h DMA element index address register 0 DMIDX1 56h/57h 21h DMA element index address register 1 DMFRI0 56h/57h 22h DMA frame index register 0 DMFRI1 56h/57h 23h DMA frame index register 1 DMGSA 56h/57h 24h DMA global source address reload register DMGDA 56h/57h 25h DMA global destination address reload register DMGCR 56h/57h 26h DMA global count reload register DMGFR 56h/57h 27h DMA global frame count reload register

†

Address 56h is used to access DMA subbank data registers with autoincrement (DMSDI) while address 57h is used to access DMA subbank data register without autoincrement (DMSDN).

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FIXED-POINT DIGITAL SIGNAL PROCESSOR

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

interrupts

Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13.

Table 13. Interrupt Locations and Priorities

NAME

LOCATION

DECIMAL HEX

PRIORITY FUNCTION

RS, SINTR 0 00 1 Reset (hardware and software reset) NMI, SINT16 4 04 2 Nonmaskable interrupt SINT17 8 08 — Software interrupt #17 SINT18 12 0C — Software interrupt #18 SINT19 16 10 — Software interrupt #19 SINT20 20 14 — Software interrupt #20 SINT21 24 18 — Software interrupt #21 SINT22 28 1C — Software interrupt #22 SINT23 32 20 — Software interrupt #23 SINT24 36 24 — Software interrupt #24 SINT25 40 28 — Software interrupt #25 SINT26 44 2C — Software interrupt #26 SINT27 48 30 — Software interrupt #27 SINT28 52 34 — Software interrupt #28 SINT29 56 38 — Software interrupt #29 SINT30 60 3C — Software interrupt #30 INT0, SINT0 64 40 3 External user interrupt #0 INT1, SINT1 68 44 4 External user interrupt #1 INT2, SINT2 72 48 5 External user interrupt #2 TINT0, SINT3 76 4C 6 Timer0 interrupt BRINT0, SINT4 80 50 7 McBSP #0 receive interrupt BXINT0, SINT5 84 54 8 McBSP #0 transmit interrupt DMAC0, SINT7 88 58 9 DMA channel 0 interrupt

TINT1(DMAC1), SINT7 92 5C 10

Timer1 interrupt (default) or DMA channel 1 interrupt. The selection is made in the

DMPREC register. INT3, SINT8 96 60 11 External user interrupt #3 HPINT, SINT9 100 64 12 HPI interrupt

BRINT1(DMAC2), SINT10 104 68 13

McBSP #1 receive interrupt (default) or DMA

channel 2 interrupt. The selection is made in

the DMPREC register.

BXINT1(DMAC3), SINT11 108 6C 14

McBSP #1 transmit interrupt (default) or DMA

channel 3 interrupt. The selection is made in

the DMPREC register. DMAC4,SINT12 112 70 15 DMA channel 4 interrupt DMAC5,SINT13 116 74 16 DMA channel 5 interrupt Reserved 120–127 78–7F — Reserved

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interrupts (continued)

The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 7.

15–14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RES DMAC5 DMAC4 BXINT1

DMAC3

BRINT1

DMAC2

HPINT INT3 TINT1

DMAC1

DMAC0 BXINT0 BRINT0 TINT0 INT2 INT1 INT0

Figure 7. IFR and IMR Registers

Table 14. IFR and IMR Register Bit Fields

BIT

NUMBER NAME

FUNCTION

15–14 – Reserved for future expansion

13 DMAC5 DMA channel 5 interrupt flag/mask bit 12 DMAC4

DMA channel 4 interrupt flag/mask bit

11 BXINT1/DMAC3

This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.

10 BRINT1/DMAC2

This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.

9 HPINT

Host to ’54x interrupt flag/mask

8 INT3

External interrupt 3 flag/mask

7 TINT1/DMAC1

This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1 interrupt flag/mask bit. The selection is made in the DMPREC register.

6 DMAC0

DMA channel 0 interrupt flag/mask bit

5 BXINT0

McBSP0 transmit interrupt flag/mask bit

4 BRINT0

McBSP0 receive interrupt flag/mask bit

3 TINT0

Timer 0 interrupt flag/mask bit

2 INT2

External interrupt 2 flag/mask bit

1 INT1

External interrupt 1 flag/mask bit

0 INT0

External interrupt 0 flag/mask bit

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FIXED-POINT DIGITAL SIGNAL PROCESSOR

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

documentation support

Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the ’C5000 family of DSPs:

TMS320C5000 DSP Family Functional Overview

(literature number SPRU307)

D Device-specific data sheets (such as this document) D Complete User Guides D Development-support tools D Hardware and software application reports

The five-volume

TMS320C54x DSP Reference Set

(literature number SPRU210) consists of:

Volume 1: CPU and Peripherals

(literature number SPRU131)

Volume 2: Mnemonic Instruction Set

(literature number SPRU172)

Volume 3: Algebraic Instruction Set

(literature number SPRU179)

Volume 4: Applications Guide

(literature number SPRU173)

Volume 5: Enhanced Peripherals

(literature number SPRU302)

The reference set describes in detail the ’54x TMS320 products currently available and the hardware and software applications, including algorithms, for fixed-point TMS320 devices.

For general background information on DSPs and Texas Instruments (TIt) devices, see the three-volume publication

Digital Signal Processing Applications with the TMS320 Family

(literature numbers SPRA012,

SPRA016, and SPRA017). A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal

processing research and education. The TMS320 newsletter,

Details on Signal Processing

, is published

quarterly and distributed to update TMS320 customers on product information. Information regarding TI DSP products is also available on the Worldwide Web at

http://www.ti.com

uniform

resource locator (URL).

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TI is a trademark of Texas Instruments Incorporated.

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

absolute maximum ratings over specified temperature range (unless otherwise noted)

†

Supply voltage I/O range, DVDD‡ –0.3 V to 4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage core range, CV

‡

–0.3 V to 2.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

–0.3 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.3 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating case temperature range, T

–40°C to 100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

DVDDDevice supply voltage, I/O 1.71 3.6 V CVDDDevice supply voltage, core 1.71 1.8 1.98 V

Supply voltage, GND 0 V

X2/CLKIN 1.35 1.98

DVDD = 1.71 V to 1.89 V

All other inputs 1.35 DVDD + 0.3 X2/CLKIN 1.35 1.98

DVDD = 1.90 V to 2.99 V

All other inputs 1.70 DVDD + 0.3

High-level input

X2/CLKIN 1.35 1.98

High level in ut

voltage

DVDD = 3.0 V to 3.6 V

RS, INTn, NMI, BIO, BCLKR0, BCLKR1, BCLKX0, BCLKX1, HCS

, HDS1,

HDS2

, TDI, TMS, CLKMDn

2.2 DVDD + 0.3

TCK, TRST 2.5 DVDD + 0.3 All other inputs 2.0 DVDD + 0.3 X2/CLKIN –0.3 0.6

DVDD = 1.71 V to 1.89 V

All other inputs –0.3 0.6 X2/CLKIN –0.3 0.6

Low-level input voltage

DVDD = 1.90 V to 3.6 V

RS, INTn, NMI, BIO, BCLKR0, BCLKR1, BCLKX0, BCLKX1, HCS

, HDS1,

HDS2

, TCK, CLKMDn

–0.3 0.6

All other inputs –0.3 0.8

High-level output current –300 µA

Low-level output current 1.5 mA

Operating case temperature –40 100 °C

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electrical characteristics over recommended operating case temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

High-level output voltage

IOH = MAX DVDD – 0.3 V

CLKOUT 0.40

Low-level output

VDD

= 1.71 to 1.89 V IOL = MAX

All other outputs 0.35

voltage

VDD

= 1.9 to 3.6 V IOL = MAX All outputs 0.40

Input current for outputs in high

D[15:0], HD[7:0]

Bus holders enabled, DVDD = MAX, VI = VSS to DV

–175 175

µA

out uts in high

impedance

All other inputs

DVDD = MAX, VO = VSS to DV

–5 5

µA

X2/CLKIN –40 40 TRST With internal pulldown –5 300

HPIENA With internal pulldown

–5 300

nput current

TMS, TCK, TDI, HPI

}

With internal pullups, HPIENA = 0

to DVDD)

–300 5

µA

All other input-only

All other in ut only

pins

–5 5

DDC

Supply current, core CPU

CVDD = 1.8 V, f

clock

= 80 MHz,w

TC = 25°C

35 mA

= 80 MHz,w

DVDD = 1.71 to

1.89 V

DDP

Supply current, pins

clock

= 80

MHz

TC = 25°C

DVDD = 1.9 to

3.6 V

Supply current,

IDLE2 PLL × 1 mode, 80 MHz input 1.6 mA

Su ly current,

standby

IDLE3

Divide-by-two mode, CLKIN stopped 20 µA

Input capacitance 5 pF

Output capacitance 5 pF

†

All values are typical unless otherwise specified.

‡

HPI input signals except for HPIENA.

Clock mode: PLL × 1 with external source

Timing parameters provided in this document are measured using the following load circuit on all device output pins.

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PARAMETER MEASUREMENT INFORMATION

Timing parameters provided are measured using the load circuit in Figure 8 on all device output pins.

Tester Pin

Electronics

Load

Output Under Test

50 Ω

Where: I

= 1.5 mA (all outputs)

= 300 µA (all outputs)

Load

= 0.855 V

= 40 pF typical load circuit capacitance

Figure 8. 1.8-V Test Load Circuit

internal oscillator with external crystal

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT is a multiple of the oscillator frequency . The multiply ratio is determined by the bit settings in the CLKMD register. The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance of 30 Ω and power dissipation of 1 mW. The circuit shown in Figure 9 represents fundamental-mode operation.

The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 9. The load capacitors, C

and C2, should be chosen such that the equation below is satisfied. CL in the equation

is the load specified for the crystal.

C1C

(

)

recommended operating conditions of internal oscillator with external crystal (see Figure 9)

MIN NOM MAX UNIT

clock

Input clock frequency 10 20 MHz

X1 X2/CLKIN

C1 C2

Crystal

Figure 9. Internal Oscillator With External Crystal

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divide-by-two clock option (PLL disabled)

The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate the internal machine cycle. The selection of the clock mode is described in the clock generator section.

When an external clock source is used, the external frequency injected must conform to specifications listed in the timing requirements table.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

switching characteristics over recommended operating conditions [H = 0.5t

c(CO)

]† (see Figure 9,

Figure 10, and the recommended operating conditions table)

PARAMETER MIN TYP MAX UNIT

c(CO)

Cycle time, CLKOUT 12.50‡2t

c(CI)

†

d(CIH-CO)

Delay time, X2/CLKIN high to CLKOUT high/low 7 12 20 ns

f(CO)

Fall time, CLKOUT 4 ns

r(CO)

Rise time, CLKOUT 4 ns

w(COL)

Pulse duration, CLKOUT low H–2 H–1 H ns

w(COH)

Pulse duration, CLKOUT high H–2 H–1 H ns

†

This device utilizes a fully static design and therefore can operate with t

c(CI)

approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

‡

It is recommended that the PLL clocking option be used for maximum frequency operation.

timing requirements (see Figure 10)

MIN MAX UNIT

c(CI)

Cycle time, X2/CLKIN 6.25

†

f(CI)

Fall time, X2/CLKIN 8 ns

r(CI)

Rise time, X2/CLKIN 8 ns

†

This device utilizes a fully static design and therefore can operate with t

c(CI)

approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

r(CO)

f(CO)

CLKOUT

X2/CLKIN

w(COL)

d(CIH-CO)

f(CI)

r(CI)

w(COH)

c(CI)

c(CO)

Figure 10. External Divide-by-Two Clock Timing

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multiply-by-N clock option

The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator section.

When an external clock source is used, the external frequency injected must conform to specifications listed in the timing requirements table.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed 1.98 V .

switching characteristics over recommended operating conditions [H = 0.5t

c(CO)

]

(see Figure 9 and Figure 11)

PARAMETER MIN TYP MAX UNIT

c(CO)

Cycle time, CLKOUT 12.5 t

c(CI)/N

†

d(CI-CO)

Delay time, X2/CLKIN high/low to CLKOUT high/low 7 10 20 ns

f(CO)

Fall time, CLKOUT 4 ns

r(CO)

Rise time, CLKOUT 4 ns

w(COL)

Pulse duration, CLKOUT low H–2 H–1 H ns

w(COH)

Pulse duration, CLKOUT high H–2 H–1 H ns

Transitory phase, PLL lock up time 30

†

N = Multiplication factor

timing requirements (see Figure 11)

†

MIN MAX UNIT

Integer PLL multiplier N (N = 1–15) 12.5N 400N

c(CI

)

Cycle time, X2/CLKIN

PLL multiplier N = x.5

12.5N 200N

c(CI)

Cycle time, X2/CLKIN

PLL multiplier N = x.25, x.75 12.5N 100N

f(CI)

Fall time, X2/CLKIN 8 ns

r(CI)

Rise time, X2/CLKIN 8 ns

†

N = Multiplication factor

c(CO)

c(CI)

w(COH)

f(CO)

r(CO)

f(CI)

X2/CLKIN

CLKOUT

d(CI-CO)

w(COL)

r(CI)

Unstable

Figure 11. External Multiply-by-One Clock Timing

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing

switching characteristics over recommended operating conditions for a

memory read

(MSTRB

= 0)

†

(see Figure 12)

PARAMETER MIN MAX UNIT

d(CLKL-A)

Delay time, CLKOUT low to address valid

‡

0 5 ns

d(CLKH-A)

Delay time, CLKOUT high (transition) to address valid

–2 5 ns

d(CLKL-MSL)

Delay time, CLKOUT l ow to MSTRB low 1 5 ns

d(CLKL-MSH)

Delay time, CLKOUT low to MSTRB high 1 5 ns

h(CLKL-A)R

Hold time, address valid after CLKOUT low

‡

0 5 ns

h(CLKH-A)R

Hold time, address valid after CLKOUT high

–2 5 ns

†

Address, PS

, and DS timings are all included in timings referenced as address.

‡

In the case of a memory read preceded by a memory read

In the case of a memory read preceded by a memory write

timing requirements for a

memory read (MSTRB = 0)

[H = 0.5 t

c(CO)

]

†

(see Figure 12)

MIN MAX UNIT

a(A)M

Access time, read data access from address valid 2H–8 ns

a(MSTRBL)

Access time, read data access from MSTRB low 2H–8 ns

su(D)R

Setup time, read data before CLKOUT low 7 ns

h(D)R

Hold time, read data after CLKOUT low –1 ns

h(A-D)R

Hold time, read data after address invalid –3 ns

h(D)MSTRBH

Hold time, read data after MSTRB high –3 ns

†

Address, PS

, and DS timings are all included in timings referenced as address.

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

PS, DS

R/W

MSTRB

D[15:0]

A[19:0]

CLKOUT

h(D)R

h(CLKL-A)R

d(CLKL-MSH)

d(CLKL-A)

d(CLKL-MSL)

su(D)R

a(A)M

a(MSTRBL)

h(A-D)R

h(D)MSTRBH

NOTE A: A[19:16] are always driven low during external data space accesses.

Figure 12. Memory Read (MSTRB = 0)

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a

memory write

(MSTRB

= 0)

[H = 0.5 t

c(CO)

]† (see Figure 13)

PARAMETER MIN MAX UNIT

d(CLKH-A)

Delay time, CLKOUT high to address valid

‡

0 5 ns

d(CLKL-A)

Delay time, CLKOUT l ow to addres s valid

–2 5 ns

d(CLKL-MSL)

Delay time, CLKOUT l ow to MSTRB low 1 5 ns

d(CLKL-D)W

Delay time, CLKOUT l ow to data valid 0 15 ns

d(CLKL-MSH)

Delay time, CLKOUT l ow to MSTRB high 1 5 ns

d(CLKH-RWL)

Delay time, CLKOUT high to R/W low –1 5 ns

d(CLKH-RWH)

Delay time, CLKOUT high to R/W high –2 5 ns

d(RWL-MSTRBL)

Delay time, R/W low to MSTRB low H – 2 H + 1 ns

h(A)W

Hold time, address valid after CLKOUT high

‡

2 4 ns

h(D)MSH

Hold time, write data valid after MSTRB high H–3 H+8

w(SL)MS

Pulse duration, MSTRB low 2H–1 ns

su(A)W

Setup time, address valid before MSTRB low 2H–1 ns

su(D)MSH

Setup time, write data valid before MSTRB high 2H–8 2H+5

en(D–RWL)

Enable time, data bus driven after R/W low H–5 ns

dis(RWH–D)

Disable time, R/W high to data bus high impedance 0 ns

†

Address, PS, and DS timings are all included in timings referenced as address.

‡

In the case of a memory write preceded by a memory write

In the case of a memory write preceded by an I/O cycle

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

PS, DS

R/W

MSTRB

D[15:0]

A[19:0]

CLKOUT

d(CLKH-RWH)

h(A)W

d(CLKL-MSH)

su(D)MSH

d(CLKL-D)W

w(SL)MS

su(A)W

d(CLKL-MSL)

h(D)MSH

d(CLKL-A)

d(CLKH-RWL)

d(RWL-MSTRBL)

d(CLKH-A)

en(D-RWL)

dis(RWH-D)

NOTE A: A[19:16] are always driven low during external data space accesses.

Figure 13. Memory Write (MSTRB = 0)

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a

parallel I/O port read

(IOSTRB

= 0)

†

(see Figure 14)

PARAMETER MIN MAX UNIT

d(CLKL-A)

Delay time, CLKOUT low to address valid 0 5 ns

d(CLKH-ISTRBL)

Delay time, CLKOUT h igh to IOSTR B low –2 4 ns

d(CLKH-ISTRBH)

Delay time, CLKOUT h igh to IOSTR B high –2 4 ns

h(A)IOR

Hold time, address after CLKOUT low 0 5 ns

†

Address and IS timings are included in timings referenced as address.

timing requirements for a

parallel I/O port read (IOSTRB = 0)

[H = 0.5 t

c(CO)

]† (see Figure 14)

MIN MAX UNIT

a(A)IO

Access time, read data access from address valid 3H–9 ns

a(ISTRBL)IO

Access time, read data access from IOSTRB low 3H–9 ns

su(D)IOR

Setup time, read data before CLKOUT high 7 ns

h(D)IOR

Hold time, read data after CLKOUT high –2 ns

h(ISTRBH-D)R

Hold time, read data after IOSTRB high –3 ns

†

Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

D[15:0]

A[19:0]

CLKOUT

h(A)IOR

d(CLKH-ISTRBH)

h(D)IOR

su(D)IOR

a(A)IO

d(CLKH-ISTRBL)

d(CLKL-A)

a(ISTRBL)IO

h(ISTRBH-D)R

NOTE A: A[19:16] are always driven low during I/O accesses.

Figure 14. Parallel I/O Port Read (IOSTRB = 0)

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a

parallel I/O port write

(IOSTRB

= 0)

[H = 0.5 t

c(CO)

]† (see Figure 15)

PARAMETER MIN MAX UNIT

d(CLKL-A)

Delay time, CLKOUT low to address valid 0 5 ns

d(CLKH-ISTRBL)

Delay time, CLKOUT h igh to IOSTR B low –2 4 ns

d(CLKH-D)IOW

Delay time, CLKOUT h i gh to write data valid H–5 H+14 ns

d(CLKH-ISTRBH)

Delay time, CLKOUT h igh to IOSTR B high –2 4 ns

d(CLKL-RWL)

Delay time, CLKOUT low to R/W low 0 6 ns

d(CLKL-RWH)

Delay time, CLKOUT low to R/W high 0 6 ns

h(A)IOW

Hold time, address valid after CLKOUT low 0 5 ns

h(D)IOW

Hold time, write data after IOSTRB high H–3 H+9 ns

su(D)IOSTRBH

Setup time, write data before IOSTRB high H–9 H+1 ns

su(A)IOSTRBL

Setup time, address valid before IOSTRB low H–1 H+1 ns

†

Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

D[15:0]

A[19:0]

CLKOUT

d(CLKH-ISTRBH)

h(A)IOW

h(D)IOW

d(CLKH-D)IOW

d(CLKH-ISTRBL)

d(CLKL-A)

d(CLKL-RWL)

d(CLKL-RWH)

su(A)IOSTRBL

su(D)IOSTRBH

NOTE A: A[19:16] are always driven low during I/O accesses.

Figure 15. Parallel I/O Port Write (IOSTRB = 0)

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ready timing for externally generated wait states

timing requirements for externally generated wait states [H = 0.5 t

c(CO)

]† (see Figure 16, Figure 17,

Figure 18, and Figure 19)

MIN MAX UNIT

su(RDY)

Setup time, READY before CLKOUT low 6 ns

h(RDY)

Hold time, READY after CLKOUT low 0–1 ns

v(RDY)MSTRB

Valid time, READY after MSTRB low

‡

4H–8 ns

h(RDY)MSTRB

Hold time, READY after MSTRB low

‡

4H–3 ns

v(RDY)IOSTRB

Valid time, READY after IOSTRB low

‡

5H–7 ns

h(RDY)IOSTRB

Hold time, READY after IOSTRB low

‡

5H–2 ns

v(MSCL)

Valid time, MSC low after CLKOUT low 0 6 ns

v(MSCH)

Valid time, MSC high after CLKOUT low –1 5 ns

†

The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using READY, at least two software wait states must be programmed.

‡

These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.

MSC

MSTRB

READY

A[19:0]

CLKOUT

v(MSCH)

v(MSCL)

h(RDY)

h(RDY)MSTRB

v(RDY)MSTRB

Wait State Generated by READY

Wait States

Generated Internally

su(RDY)

NOTE A: A[19:16] are always driven low during external data space accesses.

Figure 16. Memory Read With Externally Generated Wait States

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ready timing for externally generated wait states (continued)

MSC

MSTRB

READY

D[15:0]

A[19:0]

CLKOUT

v(MSCH)

h(RDY)

Wait State Generated by READY

Wait States

Generated Internally

h(RDY)MSTRB

v(RDY)MSTRB

v(MSCL)

su(RDY)

NOTE A: A[19:16] are always driven low during external data space accesses.

Figure 17. Memory Write With Externally Generated Wait States

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ready timing for externally generated wait states (continued)

su(RDY)

MSC

IOSTRB

READY

A[19:0]

CLKOUT

v(MSCH)

h(RDY)

Wait State Generated by READY

Wait

States

Generated

Internally

v(RDY)IOSTRB

v(MSCL)

h(RDY)IOSTRB

NOTE A: A[19:16] are always driven low during I/O space accesses.

Figure 18. I/O Read With Externally Generated Wait States

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ready timing for externally generated wait states (continued)

IOSTRB

MSC

READY

D[15:0]

A[19:0]

CLKOUT

h(RDY)

Wait State Generated by READY

Wait States

Generated

Internally

v(RDY)IOSTRB

su(RDY)

v(MSCH)

v(MSCL)

h(RDY)IOSTRB

NOTE A: A[19:16] are always driven low during I/O accesses.

Figure 19. I/O Write With Externally Generated Wait States

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

HOLD and HOLDA timings

switching characteristics over recommended operating conditions for memory control signals and HOLDA

, [H = 0.5 t

c(CO)

] (see Figure 20)

PARAMETER MIN MAX UNIT

dis(CLKL-A)

Disable time, address, PS, DS, IS high impedance from CLKOUT low 3 ns

dis(CLKL-RW)

Disable time, R/W high impedance from CLKOUT low 3 ns

dis(CLKL-S)

Disable time, MSTRB, IOSTRB high impedance from CLKOUT low 3 ns

en(CLKL-A)

Enable time, address, PS, DS, IS from CLKOUT low 2H+7 ns

en(CLKL-RW)

Enable time, R/W enabled from CLKOUT low 2H+7 ns

en(CLKL-S)

Enable time, MSTRB, IOSTRB enabled from CLKOUT low 2H+7 ns Valid time, HOLDA low after CLKOUT low

10 7 ns

v(HOLDA)

Valid time, HOLDA high after CLKOUT low

1 6 ns

w(HOLDA)

Pulse duration, HOLDA low duration 2H ns

timing requirements for memory control signals and HOLDA, [H = 0.5 t

c(CO)

] (see Figure 20)

MIN MAX UNIT

w(HOLD)

Pulse duration, HOLD low 4H+16 ns

su(HOLD)

Setup time, HOLD low/high before CLKOUT low 7 ns

IOSTRB

MSTRB

R/W

D[15:0]

, DS, IS

A[19:0]

HOLDA

HOLD

CLKOUT

en(CLKL-S)

en(CLKL-RW)

dis(CLKL-S)

dis(CLKL-RW)

dis(CLKL-A)

v(HOLDA)

w(HOLDA)

w(HOLD)

su(HOLD)

en(CLKL-A)

Figure 20. HOLD and HOLDA Timings (HM = 1)

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

reset, BIO, interrupt, and MP/MC timings timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 t

c(CO)

] (see Figure 21, Figure 22,

and Figure 23)

MIN MAX UNIT

h(RS)

Hold time, RS after CLKOUT low 0 ns

h(BIO)

Hold time, BIO after CLKOUT low –2 ns

h(INT)

Hold time, INTn, NMI, after CLKOUT low

†

–3 ns

h(MPMC)

Hold time, MP/MC after CLKOUT low 0 ns

w(RSL)

Pulse duration, RS low

‡§

4H+5 ns

w(BIO)S

Pulse duration, BIO low, synchronous 2H+4 ns

w(BIO)A

Pulse duration, BIO low, asynchronous 4H ns

w(INTH)S

Pulse duration, INTn, NMI high (synchronous) 2H–1 ns

w(INTH)A

Pulse duration, INTn, NMI high (asynchronous) 4H ns

w(INTL)S

Pulse duration, INTn, NMI low (synchronous) 2H+1 ns

w(INTL)A

Pulse duration, INTn, NMI low (asynchronous) 4H ns

w(INTL)WKP

Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup 8 ns

su(RS)

Setup time, RS before X2/CLKIN low

5 ns

su(BIO)

Setup time, BIO before CLKOUT low 7 12 ns

su(INT)

Setup time, INTn, NMI, RS before CLKOUT low 8 12 ns

su(MPMC)

Setup time, MP/MC before CLKOUT low 10 ns

†

The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is corresponding to three CLKOUT sampling sequences.

‡

If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS

must be held low for at least 50 µs to ensure

synchronization and lock-in of the PLL.

Note that RS

may cause a change in clock frequency, therefore changing the value of H.

Divide-by-two mode

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

reset, BIO, interrupt, and MP/MC timings (continued)

BIO

CLKOUT

, INTn, NMI

X2/CLKIN

h(BIO)

h(RS)

su(INT)

w(BIO)S

su(BIO)

w(RSL)

su(RS)

Figure 21. Reset and BIO Timings

INTn, NMI

CLKOUT

h(INT)

su(INT)

w(INTL)A

w(INTH)A

Figure 22. Interrupt Timing

MP/MC

CLKOUT

su(MPMC)

h(MPMC)

Figure 23. MP/MC Timing

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings

switching characteristics over recommended operating conditions for IAQ and IACK [H = 0.5 t

c(CO)

] (see Figure 24)

PARAMETER MIN MAX UNIT

d(CLKL-IAQL)

Delay time, CLKOUT low to IAQ low 1 5 ns

d(CLKL-IAQH)

Delay time, CLKOUT low to IAQ high 1 5 ns

d(A)IAQ

Delay time, address valid to IAQ low 2 ns

d(CLKL-IACKL)

Delay time, CLKOUT low to IACK low 0 5 ns

d(CLKL-IACKH)

Delay time , CLKOUT low to IACK high 1 5 ns

d(A)IACK

Delay time, address valid to IACK low 2 ns

h(A)IAQ

Hold time, IAQ high after address invalid –1 ns

h(A)IACK

Hold time, IACK high after address invalid –1 ns

w(IAQL)

Pulse duration, IAQ low 2H–1 ns

w(IACKL)

Pulse duration, IACK low 2H–1 ns

MSTRB

IACK

IAQ

A[19:0]

CLKOUT

d(A)IACK

d(A)IAQ

w(IACKL)

h(A)IACK

d(CLKL-IACKL)

w(IAQL)

h(A)IAQ

d(CLKL-IAQL)

d(CLKL-IACKH)

d(CLKL-IAQH)

Figure 24. IAQ and IACK Timings

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings (continued)

switching characteristics over recommended operating conditions for XF and TOUT [H = 0.5 t

c(CO)

] (see Figure 25 and Figure 26)

PARAMETER MIN MAX UNIT

Delay time, CLKOUT low to XF high –1 5

d(XF)

Delay time, CLKOUT low to XF low –1 5

d(TOUTH)

Delay time, CLKOUT low to TOUT high 2 7 ns

d(TOUTL)

Delay time, CLKOUT low to TOUT low 1 6 ns

w(TOUT)

Pulse duration, TOUT 2H ns

CLKOUT

d(XF)

Figure 25. XF Timing

TOUT

CLKOUT

w(TOUT)

d(TOUTL)

d(TOUTH)

Figure 26. TOUT Timing

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing

timing requirements for McBSP [H=0.5t

c(CO)

]†(see Figure 27 and Figure 28)

MIN MAX UNIT

c(BCKRX)

Cycle time, BCLKR/X BCLKR/X ext 4H ns

w(BCKRX)

Pulse duration, BCLKR/X high or BCLKR/X low BCLKR/X ext 2H–1 ns

BCLKR int 9

su(BFRH-BCKRL)

Setup time, external BFSR high before BCLKR low

BCLKR ext

BCLKR int –1

h(BCKRL-BFRH)

Hold time, external BFSR high after BCLKR low

BCLKR ext

BCLKR int 10

su(BDRV-BCKRL)

Setup time, BDR valid before BCLKR low

BCLKR ext

BCLKR int 0

h(BCKRL-BDRV)

Hold time, BDR valid after BCLKR low

BCLKR ext

BCLKX int 9

su(BFXH-BCKXL)

Setup time, external BFSX high before BCLKX low

BCLKX ext

BCLKX int 1

h(BCKXL-BFXH)

Hold time, external BFSX high after BCLKX low

BCLKX ext

r(BCKRX)

Rise time, BCLKR/X BCLKR/X ext 8 ns

f(BCKRX)

Fall time, BCLKR/X BCLKR/X ext 8 ns

†

CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

switching characteristics for McBSP [H=0.5t

c(CO)

]† (see Figure 27 and Figure 28)

PARAMETER MIN MAX UNIT

c(BCKRX)

Cycle time, BCLKR/X BCLKR/X int 4H ns

w(BCKRXH)

Pulse duration, BCLKR/X high BCLKR/X int D – 1‡D + 1‡ns

w(BCKRXL)

Pulse duration, BCLKR/X low BCLKR/X int C – 1‡C + 1‡ns

BCLKR int –2 4 ns

d(BCKRH-BFRV)

Delay time, BCLKR high to internal BFSR valid

BCLKR ext

7 13 ns

BCLKX int 0 6

d(BCKXH-BFXV)

Delay time, BCLKX high to internal BFSX valid

BCLKX ext

3 14

Disable time, BCLKX high to BDX high impedance following last data

BCLKX int 1 6

dis(BCKXH-BDXHZ)

Disable time, BCLKX high to BDX high im edance following last data

bit of transfer

BCLKX ext

7 13

BCLKX int 0 7

d(BCKXH-BDXV)

Delay time, BCLKX high to BDX valid

DXENA

§ BCLKX ext 3 14

Delay time, BFSX high to BDX valid

BFSX int 1

d(BFXH-BDXV)

ONLY applies when in data delay 0 (XDATDLY = 00b) mode

BFSX ext 7 14

†

CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡

T = BCLKRX period = (1 + CLKGDV) * 2H C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320UC5402.

Minimum delay times also represent minimum output hold times.

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing (continued)

Bit(n-1)

(n-2) (n-3)

BCLKR

BFSR (int)

BFSR (ext)

BDR

w(BCKRXH)

c(BCKRX)

w(BCKRXL)

d(BCKRH-BFRV)

su(BFRH-BCKRL)

h(BCKRL-BFRH)

h(BCKRL-BDRV)

su(BDRV-BCKRL)

r(BCKRX)

f(BCKRX)

Figure 27. McBSP Receive Timings

Bit 0 Bit(n-1) (n-2) (n-3)

BCLKX

BFSX (int)

BFSX (ext)

BFSX

BDX

c(BCKRX)

w(BCKRXH)

w(BCKRXL)

d(BCKXH-BFXV)

su(BFXH-BCKXL)

h(BCKXL-BFXH)

dis(BCKXH-BDXHZ)

d(BFXH-BDXV)

d(BCKXH-BDXV)

(XDATDLY=00b)

r(BCKRX)

f(BCKRX)

d(BCKXH-BFXV)

Figure 28. McBSP Transmit Timings

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing (continued)

timing requirements for McBSP general-purpose I/O (see Figure 29)

MIN MAX UNIT

su(BGPIO-COH)

Setup time, BGPIOx input mode before CLKOUT high

†

13 ns

h(COH-BGPIO)

Hold time, BGPIOx input mode after CLKOUT high

†

0 ns

†

BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.

switching characteristics for McBSP general-purpose I/O (see Figure 29)

PARAMETER MIN MAX UNIT

d(COH-BGPIO)

Delay time, CLKOUT high to BGPIOx output mode

‡

0 7 ns

‡

BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.

su(BGPIO-COH)

h(COH-BGPIO)

d(COH-BGPIO)

CLKOUT

BGPIOx Input

mode

†

BGPIOx Output

mode

‡

†

BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.

‡

BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.

Figure 29. McBSP General-Purpose I/O Timings

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing (continued)

timing requirements for McBSP as SPI master or slave: [H=0.5t

c(CO)

] CLKSTP = 10b, CLKXP = 0

†

(see Figure 30)

MASTER SLAVE

MIN MAX MIN MAX

UNIT

su(BDRV-BCKXL)

Setup time, BDR valid before BCLKX low 16 2 – 12H ns

h(BCKXL-BDRV)

Hold time, BDR valid after BCLKX low 0 5 + 12H ns

su(BFXL-BCKXH)

Setup time, BFSX low before BCLKX high 15 ns

c(BCKX)

Cycle time, BCLKX 12H 32H ns

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

c(CO)

] CLKSTP = 10b,

CLKXP = 0

†

(see Figure 30)

MASTER

‡

SLAVE

PARAMETER

MIN MAX MIN MAX

UNIT

h(BCKXL-BFXL)

Hold time, BFSX low after BCLKX low

T – 4 T + 5 ns

d(BFXL-BCKXH)

Delay time, BFSX low to BCLKX high

C – 6 C + 4 ns

d(BCKXH-BDXV)

Delay time, BCLKX high to BDX valid –3 7 6H + 4 10H + 16 ns

dis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from BCLKX low

C – 2 C + 3 ns

dis(BFXH-BDXHZ)

Disable time, BDX high impedance following last data bit from BFSX high

2H+ 8 6H + 21 ns

d(BFXL-BDXV)

Delay time, BFSX low to BDX valid 4H –3 8H + 21 ns

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡

T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX).

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

BCLKX

BFSX

BDX

BDR

su(BDRV-BCLXL)

d(BCKXH-BDXV)

h(BCKXL-BDRV)

dis(BFXH-BDXHZ)

dis(BCKXL-BDXHZ)

h(BCKXL-BFXL)

d(BFXL-BDXV)

d(BFXL-BCKXH)

LSB

MSB

su(BFXL-BCKXH)

c(BCKX)

Figure 30. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing (continued)

timing requirements for McBSP as SPI master or slave: [H=0.5t

c(CO)

] CLKSTP = 11b, CLKXP = 0

†

(see Figure 31)

MASTER SLAVE

MIN MAX MIN MAX

UNIT

su(BDRV-BCKXH)

Setup time, BDR valid before BCLKX high 16 2 – 12H ns

h(BCKXH-BDRV)

Hold time, BDR valid after BCLKX high 4 5 + 12H ns

su(BFXL-BCKXH)

Setup time, BFSX low before BCLKX high 15 ns

c(BCKX)

Cycle time, BCLKX 12H 32H ns

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

c(CO)

] CLKSTP = 11b,

CLKXP = 0

†

(see Figure 31)

MASTER

‡

SLAVE

PARAMETER

MIN MAX MIN MAX

UNIT

h(BCKXL-BFXL)

Hold time, BFSX low after BCLKX low

C –4 C + 5 ns

d(BFXL-BCKXH)

Delay time, BFSX low to BCLKX high

T – 6 T + 4 ns

d(BCKXL-BDXV)

Delay time, BCLKX low to BDX valid 4 7 6H + 4 10H + 16 ns

dis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from BCLKX low

0 6 6H +7 10H + 21 ns

d(BFXL-BDXV)

Delay time, BFSX low to BDX valid D – 2 D + 4 4H –3 8H + 21 ns

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡

T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX).

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

BCLKX

BFSX

BDX

BDR

d(BFXL-BCKXH)

dis(BCKXL-BDXHZ)

d(BCKXL-BDXV)

h(BCKXH-BDRV)

su(BDRV-BCKXH)

d(BFXL-BDXV)

h(BCKXL-BFXL)

LSB

MSB

su(BFXL-BCKXH)

c(BCKX)

Figure 31. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing (continued)

timing requirements for McBSP as SPI master or slave: [H=0.5t

c(CO)

] CLKSTP = 10b, CLKXP = 1

†

(see Figure 32)

MASTER SLAVE

MIN MAX MIN MAX

UNIT

su(BDRV-BCKXH)

Setup time, BDR valid before BCLKX high 16 2 – 12H ns

h(BCKXH-BDRV)

Hold time, BDR valid after BCLKX high 4 5 + 12H ns

su(BFXL-BCKXL)

Setup time, BFSX low before BCLKX low 10 ns

c(BCKX)

Cycle time, BCLKX 12H 32H ns

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

c(CO)

] CLKSTP = 10b,

CLKXP = 1

†‡

(see Figure 32)

MASTER SLAVE

PARAMETER

MIN MAX MIN MAX

UNIT

h(BCKXH-BFXL)

Hold time, BFSX low after BCLKX high

T – 4 T + 5 ns

d(BFXL-BCKXL)

Delay time, BFSX low to BCLKX low

D – 6 D + 4 ns

d(BCKXL-BDXV)

Delay time, BCLKX low to BDX valid – 3 7 6H + 4 10H + 16 ns

dis(BCKXH-BDXHZ)

Disable time, BDX high impedance following last data bit from BCLKX high

D – 2 D + 3 ns

dis(BFXH-BDXHZ)

Disable time, BDX high impedance following last data bit from BFSX high

2H + 7 6H + 21 ns

d(BFXL-BDXV)

Delay time, BFSX low to BDX valid 4H – 3 8H + 21 ns

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡

T = BCLKX period = (1 + CLKGDV) * 2H D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX).

su(BFXL-BCKXL)

h(BCKXH-BDRV)

dis(BFXH-BDXHZ)

dis(BCKXH-BDXHZ)

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

BCLKX

BFSX

BDX

BDR

d(BFXL-BCKXL)

d(BFXL-BDXV)

d(BCKXL-BDXV)

su(BDRV-BCKXH)

h(BCKXH-BFXL)

LSB

MSB

c(BCKX)

Figure 32. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing (continued)

timing requirements for McBSP as SPI master or slave: [H=0.5t

c(CO)

] CLKSTP = 11b, CLKXP = 1

†

(see Figure 33)

MASTER SLAVE

MIN MAX MIN MAX

UNIT

su(BDRV-BCKXL)

Setup time, BDR valid before BCLKX low 16 – 12H ns

h(BCKXL-BDRV)

Hold time, BDR valid after BCLKX low 0 5 + 12H ns

su(BFXL-BCKXL)

Setup time, BFSX low before BCLKX low 10 ns

c(BCKX)

Cycle time, BCLKX 12H 32H ns

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

c(CO)

] CLKSTP = 11b,

CLKXP = 1

†‡

(see Figure 33)

MASTER

‡

SLAVE

PARAMETER

MIN MAX MIN MAX

UNIT

h(BCKXH-BFXL)

Hold time, BFSX low after BCLKX high

D – 4 D + 5 ns

d(BFXL-BCKXL)

Delay time, BFSX low to BCLKX low

T – 6 T + 4 ns

d(BCKXH-BDXV)

Delay time, BCLKX high to BDX valid – 3 7 6H + 4 10H + 16 ns

dis(BCKXH-BDXHZ)

Disable time, BDX high impedance following last data bit from BCLKX high

0 6 6H +7 10H + 21 ns

d(BFXL-BDXV)

Delay time, BFSX low to BDX valid C – 2 C + 4 4H – 3 8H + 21 ns

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX).

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

BCLKX

BFSX

BDX

BDR

d(BFXL-BCKXL)

su(BDRV-BCKXL)

dis(BCKXH-BDXHZ)

h(BCKXH-BFXL)

d(BCKXH-BDXV)

h(BCKXL-BDRV)

d(BFXL-BDXV)

LSB

MSB

su(BFXL-BCKXL)

c(BCKX)

Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

HPI-8 timing

switching characteristics over recommended operating conditions†‡§¶ [H = 0.5t

c(CO)

]

(see Figure 34, Figure 35, Figure 36, and Figure 37)

PARAMETER MIN MAX UNIT

en(DSL-HD)

Enable time, HD driven from DS low 5 21 ns

Case 1a: Memory accesses when DMAC is active in 16-bit mode and t

w(DSH)

< 18H

18H + 21

Case 1b: Memory accesses when DMAC is active in 16-bit mode and t

w(DSH)

≥ 18H

Delay time, DS low to HDx valid for

Case 1c: Memory access when DMAC is active in 32-bit mode and t

w(DSH)

< 26H

26H + 21

d(DSL-HDV1)

Delay time, DS low to HDx valid for

first byte of an HPI read

Case 1d: Memory access when DMAC is active in 32-bit mode and t

w(DSH)

≥ 26H

Case 2a: Memory accesses when DMAC is inactive and t

w(DSH)

< 10H

10H + 21

Case 2b: Memory accesses when DMAC is inactive and t

w(DSH)

≥ 10H

Case 3: Register accesses 21

d(DSL-HDV2)

Delay time, DS low to HDx valid for second byte of an HPI read 21 ns

h(DSH-HDV)R

Hold time, HDx valid after DS high, for a HPI read 5 9 ns

v(HYH-HDV)

Valid time, HDx valid after HRDY high 17

d(DSH-HYL)

Delay time, DS high to HRDY low (see Note 1) 21 ns

Case 1a: Memory accesses when DMAC is active in 16-bit mode

18H + 21 ns

Case 1b: Memory accesses when DMAC is active in 32-bit mode

26H + 21

d(DSH-HYH)

Delay time, DS high to HRDY high

Case 2: Memory accesses when DMAC is inactive

10H + 21

Case 3: Write accesses to HPIC register (see Note 2)

6H + 21

d(HCS-HRDY)

Delay time, HCS low/high to HRDY low/high

13 ns

d(COH-HYH

) Delay time, CLKOUT high to HRDY high 4 ns

d(COH-HTX)

Delay time, CLKOUT high to HINT change 5 ns

d(COH-GPIO)

Delay time, CLKOUT high to HDx output change. HDx is configured as a general-purpose output.

8 ns

NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.

2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously, and do not cause HRDY to be deasserted.

†

DS refers to the logical OR of HCS

, HDS1, and HDS2.

‡

HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).

DMAC stands for direct memory access (DMA) controller. The HPI-8 shares the internal DMA bus with the DMAC, thus HPI-8 access times are affected by DMAC activity.

GPIO refers to the HD pins when they are configured as general-purpose input/outputs.

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

HPI-8 timing (continued)

timing requirements†‡§ (see Figure 34, Figure 35, Figure 36, and Figure 37)

MIN MAX UNIT

su(HBV-DSL)

Setup time, HBIL valid before DS low 5 ns

h(DSL-HBV)

Hold time, HBIL valid after DS low 5 ns

su(HSL-DSL)

Setup time, HAS low before DS low 5 ns

w(DSL)

Pulse duration, DS low 20 ns

w(DSH)

Pulse duration, DS high 10 ns

su(HDV-DSH)

Setup time, HDx valid before DS high, HPI write 12 ns

h(DSH-HDV)W

Hold time, HDx valid after DS high, HPI write 4 ns

su(GPIO-COH)

Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input 7 ns

h(GPIO-COH)

Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input 0 ns

†

DS refers to the logical OR of HCS, HDS1, and HDS2.

‡

HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).

GPIO refers to the HD pins when they are configured as general-purpose input/outputs.

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

HPI-8 timing (continued)

Valid

su(HSL-DSL)

Valid

su(HBV-DSL)

‡

HAS

HBIL

h(DSL-HBV)

‡

d(DSH-HYH)

w(DSL)

d(DSL-HDV1)

v(HYH-HDV)

Valid Valid

Valid

d(COH-HYH)

Valid

w(DSH)

d(DSH-HYL)

h(DSH-HDV)R

h(DSH-HDV)W

Valid

su(HDV-DSH)

d(DSL-HDV2)

en(DSL-HD)

HCS

HDS

HRDY

HD READ

Valid

HD WRITE

CLKOUT

Second Byte First Byte Second Byte

HAD

†

HAD refers to HCNTL0, HCNTL1, and HR/W.

‡

When HAS

is not used (HAS always high)

Figure 34. Using HDS to Control Accesses (HCS Always Low)

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

HPI-8 timing (continued)

Second Byte

First Byte

Second Byte

d(HCS-HRDY)

HCS

HDS

HRDY

Figure 35. Using HCS to Control Accesses

HINT

CLKOUT

d(COH-HTX)

Figure 36. HINT Timing

GPIOx Input Mode

†

CLKOUT

h(GPIO-COH)

GPIOx Output Mode

†

su(GPIO-COH)

d(COH-GPIO)

†

GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).

Figure 37. GPIOx† Timings

T PREVIEW

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK

4040147/B 10/94

0,27

0,17

0,13 NOM

0,25

0,75 0,45

0,05 MIN

Seating Plane

Gage Plane

108

109

144

22,20 21,80

19,80

17,50 TYP

20,20

1,35

1,45

1,60 MAX

0,08

0°–7°

0,08

0,50

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136

Thermal Resistance Characteristics

PARAMETER

°C/W

ΘJA

ΘJC

T PREVIEW

TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY PACKAGE

0,80

0,10

0,08

0,80

9,60 TYP

12 1310 118967

N M

42 3

C B

Seating Plane

4073221/A 11/96

11,90

12,10

0,95

0,35

0,45

0,55

0,85

0,08

0,12

1,40 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. MicroStar BGA configuration

Thermal Resistance Characteristics

PARAMETER

°C/W

ΘJA

ΘJC

T PREVIEW

MicroStar BGA is a trademark of Texas Instruments Incorporated.

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Texas Instruments TMS320UC5402PGE-80, TMS320UC5402GGU-80 Datasheet

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Frequently Asked Questions

User Manual