TMS320UC5402 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS096C
April 1999 − Revised October 2008
!
!
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS096B device-specific data
sheet to make it an SPRS096C revision.
Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date with the following changes.
PAGE(S)
NO.
5 Table 1−2, Signal Descriptions:
− Updated DESCRIPTION of TRST
− Added footnote about TRST
62 Section 5, Mechanical Data:
− Moved “Package Thermal Resistance Characteristics” section (Section 4.4 in SPRS096B) to this section
− Added Section 5.2, Packaging Information
− Mechanical drawings will be appended to this document via an automated process
ADDITIONS/CHANGES/DELETIONS
April 1999 − Revised October 2008 SPRS096C
iii
Revision History
iv
April 1999 − Revised October 2008SPRS096C
Contents
Contents
Section Page
1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Pin Assignments 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 Terminal Assignments for the GGU Package 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 Pin Assignments for the PGE Package 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Signal Descriptions 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Overview 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Memory 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 On-Chip Dual-Access RAM (DARAM) 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 On-Chip ROM With Bootloader 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Memory Map 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Relocatable Interrupt Vector Table 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 Extended Program Memory 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 On-Chip Peripherals 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Software-Programmable Wait-State Generator 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Parallel I/O Ports 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Hardware Timer 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Clock Generator 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5 DMA Controller 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Memory-Mapped Registers 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 CPU Memory-Mapped Registers 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Peripheral Memory-Mapped Registers 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 McBSP Control Registers and Subaddresses 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 DMA Subbank Addressed Registers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Interrupts 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 IFR and IMR Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Documentation Support 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Electrical Specifications 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Absolute Maximum Ratings 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Recommended Operating Conditions 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Electrical Characteristics Over Recommended Operating Case Temperature Range
(Unless Otherwise Noted) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Timing Parameter Symbology 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Clock Options 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 Internal Oscillator With External Crystal 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 Divide-By-Two Clock Option (PLL disabled) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3 Multiply-By-N Clock Option (PLL Enabled) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Memory and Parallel I/O Interface Timing 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1 Memory Read 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 Memory Write 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.3 I/O Read 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.4 I/O Write 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
April 1999 − Revised October 2008 SPRS096C
v
Contents
Section Page
4.7 Ready Timing for Externally Generated Wait States 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 HOLD
and HOLDA Timings 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Reset, BIO, Interrupt, and MP/MC Timings 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings 48. . . . . . . . . . . . . . . . .
4.11 External Flag (XF) and TOUT Timings 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Multichannel Buffered Serial Port (McBSP) Timing 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.1 McBSP Transmit and Receive Timings 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.2 McBSP General-Purpose I/O Timing 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.3 McBSP as SPI Master or Slave Timing 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Host-Port Interface Timing (HPI8) 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Mechanical Data 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Package Thermal Resistance Characteristics 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Packaging Information 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
April 1999 − Revised October 2008SPRS096C
Figures
List of Figures
Figure Page
1−1 144-Terminal GGU Ball Grid Array (Bottom View) 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 144-Pin PGE Low-Profile Quad Flatpack (Top View) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 Block Diagram of the TMS320UC5402 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 TMS320UC5402 Memory Map 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 Extended Program Memory 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] 13. . .
2−6 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] 14. . . . . . . . . . . . . . . . . . . . . . .
2−7 Bank-Switching Control Register (BSCR) [MMR Address 0029h] 15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 UC5402 HPI8 Memory Map 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 UC5402 DMA Memory Map 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 IFR and IMR Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 1.8-V Test Load Circuit 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Internal Oscillator With External Crystal 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 External Divide-by-Two Clock Timing 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 External Multiply-by-One Clock Timing 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Memory Read (MSTRB = 0) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Memory Write (MSTRB = 0) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Parallel I/O Port Read (IOSTRB = 0) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Parallel I/O Port Write (IOSTRB = 0) 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 Memory Read With Externally Generated Wait States 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 Memory Write With Externally Generated Wait States 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 I/O Read With Externally Generated Wait States 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 I/O Write With Externally Generated Wait States 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 HOLD and HOLDA Timings (HM = 1) 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 Reset and BIO Timings 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 Interrupt Timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 MP/MC Timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 IAQ and IACK Timings 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 XF Timing 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 TOUT Timing 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 McBSP Receive Timings 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 McBSP Transmit Timings 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 McBSP General-Purpose I/O Timings 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−23 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 54. . . . . . . . . . . . . . . . . . . . . . . .
4−24 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 55. . . . . . . . . . . . . . . . . . . . . . . .
4−25 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 56. . . . . . . . . . . . . . . . . . . . . . . .
4−26 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 57. . . . . . . . . . . . . . . . . . . . . . . .
April 1999 − Revised October 2008 SPRS096C
vii
Figures
Figure Page
4−27 Using HDS
to Control Accesses (HCS Always Low) 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−28 Using HCS to Control Accesses 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−29 HINT Timing 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−30 GPIOx Timings 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
April 1999 − Revised October 2008SPRS096C
Tables
List of Tables
Table Page
1−1 Terminal Assignments (144-Terminal GGU Package) 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 Signal Descriptions 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 Standard On-Chip ROM Layout 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Software Wait-State Register (SWWSR) Bit Fields 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 Software Wait-State Control Register (SWCR) Bit Fields 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 Bank-Switching Control Register (BSCR) Bit Fields 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Clock Mode Settings at Reset 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 DMA Interrupts 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 DMA Synchronization Events 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 CPU Memory-Mapped Registers 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 Peripheral Memory-Mapped Registers 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 McBSP Control Registers and Subaddresses 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 DMA Subbank Addressed Registers 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 Interrupt Locations and Priorities 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 IFR and IMR Register Bit Fields 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Divide-By-2 and Divide-by-4 Clock Options Timing Requirements 34. . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics 34. . . . . . . . . . . . . . . . . . . . . . .
4−3 Multiply-By-N Clock Option Timing Requirements 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Multiply-By-N Clock Option Switching Characteristics 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Memory Read Timing Requirements 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Memory Read Switching Characteristics 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Memory Write Switching Characteristics 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 I/O Read Timing Requirements 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 I/O Read Switching Characteristics 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 I/O Write Switching Characteristics 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Ready Timing Requirements for Externally Generated Wait States 42. . . . . . . . . . . . . . . . . . . . . . . . .
4−12 Ready Switching Characteristics for Externally Generated Wait States 42. . . . . . . . . . . . . . . . . . . . . .
4−13 HOLD and HOLDA Timing Requirements 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 HOLD and HOLDA Switching Characteristics 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 Reset, BIO, Interrupt, and MP/MC Timing Requirements 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics 48. . . .
4−17 External Flag (XF) and TOUT Switching Characteristics 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 McBSP Transmit and Receive Timing Requirements 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 McBSP Transmit and Receive Switching Characteristics 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 McBSP General-Purpose I/O Timing Requirements 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 McBSP General-Purpose I/O Switching Characteristics 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 54. . . . . . . . . .
4−23 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 54. . . . . .
4−24 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 55. . . . . . . . . .
4−25 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 55. . . . . . .
4−26 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 56. . . . . . . . . .
4−27 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 56. . . . . .
4−28 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 57. . . . . . . . . .
4−29 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 57. . . . . . .
April 1999 − Revised October 2008 SPRS096C
ix
Tables
Table Page
4−30 HPI8 Mode Timing Requirements 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−31 HPI8 Mode Switching Characteristics 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 Thermal Resistance Characteristics 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
April 1999 − Revised October 2008SPRS096C
1 Introduction
This section describes the main features of the TMS320UC5402, lists the pin assignments, and describes the
function of each pin. This data manual also provides a detailed description section, electrical specifications,
parameter measurement information, and mechanical data about the available packaging.
NOTE: This data manual is designed to be used in conjunction with theTMS320C54x DSP Functional
Overview (literature number SPRU307).
1.1 Features
D
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D 40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
D 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
D Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D Data Bus With a Bus-Holder Feature
D Extended Addressing Mode for 1M × 16-Bit
Maximum Addressable External Program
Space
D 4K x 16-Bit On-Chip ROM
D 16K x 16-Bit On-Chip Dual-Access RAM
D Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
D Block-Memory-Move Instructions for
Efficient Program and Data Management
D Instructions With a 32-Bit-Long Word
Operand
D Instructions With Two- or Three-Operand
Reads
D Arithmetic Instructions With Parallel Store
and Parallel Load
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
D Conditional Store Instructions
D Fast Return From Interrupt
D On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Two Multichannel Buffered Serial Ports
(McBSPs)
− Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
− Two 16-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
D Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D CLKOUT Off Control to Disable CLKOUT
D On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1
Logic
D 12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS)
D 1.8-V Core Power Supply
D 1.8-V to 3.6-V I/O Power Supply Enables
Operation With a Single 1.8-V Supply or
with Dual Supplies
D Available in a 144-Pin Low-Profile Quad
Flatpack (LQFP) (PGE Suffix)
D Available in a 144-Ball MicroStar Ball Grid
Array (BGA) (GGU Suffix)
Introduction
†
(JTAG) Boundary Scan
April 1999 − Revised October 2008 SPRS096C
1
Introduction
1.2 Description
The TMS320UC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the UC5402 unless
otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low
power consumption and the flexibility to support various system voltage configurations. The wide range of I/O
voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage
systems. This feature eliminates the need for external level-shifting and reduces power consumption in
emerging sub-3V systems.
Texas Instrument (TI) DSPs do not require specific power sequencing between the core supply and the I/O
supply. However, systems should be designed to ensure that neither supply is powered up for extended
periods of time if the other supply is below the proper operating voltage. Excessive exposure to these
conditions can adversely affect the long-term reliability of the device.
System-level concerns such as bus contention may require supply sequencing to be implemented. In this
case, the core supply should be powered up at the same time as, or prior to, the I/O buffers and powered down
after the I/O buffers.
The UC5402 is based on an advanced modified Harvard architecture that has one program memory bus and
three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
1.3 Pin Assignments
Figure 1−1 illustrates the ball locations for the 144-terminal ball grid array (BGA) package and is used in
conjunction with Table 1−1 to locate signal names and ball grid numbers. DV
I/O pins while CV
is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core
DD
CPU.
1.3.1 Terminal Assignments for the GGU Package
is the power supply for the
DD
12
3456781012 1113 9
A
B
C
D
E
F
G
H
J
K
L
M
N
Figure 1−1. 144-Terminal GGU Ball Grid Array (Bottom View)
2
April 1999 − Revised October 2008SPRS096C
Table 1−1. Terminal Assignments (144-Terminal GGU Package)†
Introduction
SIGNAL
NAME
NC A1 NC N13 NC N1 A19 A13
NC B1 NC M13 NC N2 NC A12
V
SS
DV
DD
A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10
HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10
A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10
A12 D1 NC K13 BFSR1 N4 D9 A10
A13 E4 HD2 J10 BDR0 K5 D10 D9
A14 E3 TOUT0 J11 HCNTL1 L5 D11 C9
A15 E2 EMU0 J12 BDR1 M5 D12 B9
NC E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9
HAS F4 TDO H10 BCLKX1 K6 D13 D8
V
SS
NC F2 TRST H12 HINT/TOUT1 M6 D15 B8
CV
DD
HCS G2 TMS G12 BFSX0 M7 CV
HR/W G1 NC G13 BFSX1 N7 NC A7
READY G3 CV
PS G4 HPIENA G10 DV
DS H1 V
IS H2 CLKOUT F12 HD0 M8 DV
R/W H3 HD3 F11 BDX0 L8 A0 C6
MSTRB H4 X1 F10 BDX1 K8 A1 D6
IOSTRB J1 X2/CLKIN
MSC J2 RS E12 HBIL M9 A3 B5
XF J3 D0 E11 NMI L9 HD6 C5
HOLDA J4 D1 E10 INT0 K9 A4 D5
IAQ K1 D2 D13 INT1 N10 A5 A4
HOLD K2 D3 D12 INT2 M10 A6 B4
BIO K3 D4 D11 INT3 L10 A7 C4
MP/MC L1 D5 C13 CV
DV
DD
V
SS
NC M1 A17 B13 NC N12 NC A2
NC M2 A18 B12 NC M12 NC B2
†
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core
CPU.
‡
If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
BGA BALL #
C2 DV
C1 V
F3 TDI H11 V
F1 TCK H13 CV
L2 A16 C12 HD1 M11 A9 B3
L3 V
SIGNAL
NAME
DD
SS
DD
SS
SS
‡
BGA BALL #
L12 HCNTL0 M3 V
L13 V
G11 HRDY L7 HDS1 C7
F13 V
E13 IACK N9 A2 A5
C11 V
SIGNAL
NAME
SS
SS
DD
DD
SS
DD
SS
BGA BALL #
N3 DV
L6 D14 C8
N6 HD5 A8
K7 V
N8 HDS2 A6
N11 A8 A3
L11 CV
SIGNAL
NAME
SS
DD
DD
SS
DD
DD
BGA BALL #
B11
A11
B7
D7
B6
C3
April 1999 − Revised October 2008 SPRS096C
3
Introduction
1.3.2 Pin Assignments for the PGE Package
The TMS320UC5402PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in
Figure 1−2. DV
is the ground for both the I/O pins and the core CPU.
is the power supply for the I/O pins while CVDD is the power supply for the core CPU. V
DD
SS
NC
NC
V
SS
DV
DD
A10
HD7
A11
A12
A13
A14
A15
NC
HAS
V
SS
NC
CV
DD
HCS
HR/W
READY
PS
DS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DV
DD
V
SS
NC
NC
DD
A9
NC
CV
NC
144
143
142
141A8140A7139A6138A5137A4136
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
IS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
373839404142434445464748495051525354555657585960616263646566676869
HD6
135A3134A2133A1132A0131DV130
DD
HDS2SSV
129
128
NC
HDS1
127
126
DD
CV
125
HD5
124
D15
123
D14
122
D13
121
HD4
120
D12
119
D11
118
D10
117D9116D8115D7114D6113
DD
V
DV
112
707172
SS
111
NC
110
A19
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
A18
A17
V
SS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
V
SS
HPIENA
CV
DD
NC
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT0
HD2
NC
CLKMD3
CLKMD2
CLKMD1
V
SS
DV
DD
NC
NC
NC
NC
V
HCNTL0SSBCLKR0
BFSR0
BCLKR1
BDR0
BFSR1
HCNTL1
BDR1
BCLKX0
SS
V
BCLKX1
HINT/TOUT1
NOTE A: NC = No connection. These pins should be left unconnected.
Figure 1−2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
4
DD
CV
BFSX0
BFSX1
DD
HRDY
DV
SS
HD0
V
BDX0
IACK
BDX1
HBIL
NMI
INT0
INT1
INT2
INT3
CV
DD
HD1
SS
NC
NC
V
April 1999 − Revised October 2008SPRS096C
1.4 Signal Descriptions
TERMINAL
TYPE
†
DESCRIPTION
Table 1−2 lists each signal, function, and operating mode(s) grouped by function. See Section 1.3 for exact
pin locations based on package type.
Table 1−2. Signal Descriptions
TERMINAL
NAME
DATA SIGNALS
A19 (MSB)
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
IACK
INT0
INT1
INT2
INT3
NMI
†
I = input, O = output, Z = high impedance, S = supply
‡
If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
§
Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST
a buffer is recommended to ensure the VIL and VIH specifications are met.
O/Z Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen
address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper
four address pins (A16 to A19) are only used to address external program space. These pins are placed in the
high-impedance state when the hold mode is enabled, or when EMU1/OFF
I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer
data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the
high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when EMU1/OFF
The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus
holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven
by the UC5402, the bus holders keep the pins at the previous logic level. The data bus holders on the UC5402
are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15−A0. IACK
O/Z
is low.
External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register (IMR) and
I
the interrupt mode bit. INT0
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM bit (in the ST1
I
register) or the IMR. When NMI
−INT3 can be polled and reset by way of the interrupt flag register (IFR).
is low.
also goes into the high-impedance state when EMU1/OFF
is activated, the processor traps to the appropriate vector location.
Introduction
is low.
pin is connected to multiple DSPs,
April 1999 − Revised October 2008 SPRS096C
5
Introduction
Table 1−2. Signal Descriptions (Continued)
TERMINAL
TERMINAL
NAME
NAME
RS
MP/MC I
BIO I
XF O/Z
DS
PS
IS
MSTRB O/Z
READY I
R/W O/Z
IOSTRB O/Z
HOLD I
HOLDA O/Z
MSC O/Z
IAQ O/Z
†
I = input, O = output, Z = high impedance, S = supply
‡
If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
§
Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST
a buffer is recommended to ensure the VIL and VIH specifications are met.
†
†
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS
I
memory. RS
Microprocessor/microcomputer mode select. If active (low) at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC
that is selected at reset.
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. For the XC instruction, the BIO
pipeline; all other instructions sample BIO
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when EMU1/OFF
is low, and is set high at reset.
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing
a particular external memory space. Active period corresponds to valid address information. DS
O/Z
placed in the high-impedance state in the hold mode; the signals also go into the high-impedance state when
EMU1/OFF is low.
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB
high-impedance state when EMU1/OFF
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W
high-impedance state in hold mode; it also goes into the high-impedance state when EMU1/OFF
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB
state when EMU1/OFF
Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the
C54x, these lines go into the high-impedance state.
Hold acknowledge. HOLDA indicates that the UC5402 is in a hold state and that the address, data, and control
lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices.
HOLDA
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC
high at the beginning of the last software wait state. If connected to the READY input, MSC
wait state after the last internal wait state is completed. MSC
EMU1/OFF
Instruction acquisition signal. IAQ is asserted (active-low) when there is an instruction address on the address
bus. IAQ
affects various registers and status bits.
MULTIPROCESSING SIGNALS
MEMORY CONTROL SIGNALS
is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
is low.
also goes into the high-impedance state when EMU1/OFF is low.
is low.
goes into the high-impedance state when EMU1/OFF is low.
is brought to a high level, execution begins at location 0FF80h of program
is placed in the high-impedance state in the hold mode; it also goes into the
pin goes active at the beginning of the first software wait state and goes inactive
DESCRIPTIONTYPE
DESCRIPTIONTYPE
bit of the processor mode status (PMST) register can override the mode
during the read phase of the pipeline.
is low.
condition is sampled during the decode phase of the
also goes into the high-impedance state when
, PS, and IS are
is placed in the
is low.
forces one external
pin is connected to multiple DSPs,
C54x is a trademark of Texas Instruments.
6
April 1999 − Revised October 2008SPRS096C
Table 1−2. Signal Descriptions (Continued)
TERMINAL
TERMINAL
NAME
NAME
CLKOUT O/Z
CLKMD1
CLKMD2
CLKMD3
X2/CLKIN
X1 O
TOUT0 O/Z
HINT/TOUT1 O/Z
BCLKR0
BCLKR1
BDR0
BDR1
BFSR0
BFSR1
BCLKX0
BCLKX1
BDX0
BDX1
BFSX0
BFSX1
HD0−HD7 I/O/Z
HCNTL0
HCNTL1
HBIL I
HCS I
HDS1
HDS2
†
I = input, O = output, Z = high impedance, S = supply
‡
If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
§
Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST
a buffer is recommended to ensure the VIL and VIH specifications are met.
‡
†
†
PLL/TIMER SIGNALS
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF
is low.
Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The
logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized
I
to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select
signals have no effect until the device is reset again.
I Clock/PLL input. If the internal oscillator is not being used, the X2/CLKIN functions as the clock input.
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when EMU1/OFF
Timer0 output. T OUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF
Timer1 output. TOUT1 signals a pulse when the on-chip timer 1 counts down past zero. The pulse is one
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT
the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
I/O/Z Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.
I Serial data receive input
I/O/Z Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
I/O/Z
I/O/Z
an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when
EMU1/OFF
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
O/Z
asserted, or when EMU1/OFF
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX
can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the
high-impedance state when EMU1/OFF is low.
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0−HD7 is placed in the
high-impedance state when not outputting data or when EMU1/OFF
holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not
being driven by the UC5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders
are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have
I
internal pullup resistors that are only enabled when HPIENA = 0.
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup
resistor that is only enabled when HPIENA = 0.
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs
I
have internal pullup resistors that are only enabled when HPIENA = 0.
goes low.
is low.
HOST-PORT INTERFACE SIGNALS
DESCRIPTIONTYPE
DESCRIPTIONTYPE
pin of the HPI and is only available when
Introduction
is low.
is low.
is low.
is low. The HPI data bus includes bus
pin is connected to multiple DSPs,
April 1999 − Revised October 2008 SPRS096C
7
Introduction
Table 1−2. Signal Descriptions (Continued)
TERMINAL
TERMINAL
NAME
NAME
HAS I
HR/W I
HRDY O/Z
HINT/TOUT1 O/Z
HPIENA I
CV
DD
DV
DD
V
SS
NC No connection
TCK I
TDI I
TDO O/Z
TMS I
§
TRST
EMU0 I/O/Z
EMU1/OFF I/O/Z
†
I = input, O = output, Z = high impedance, S = supply
‡
If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
§
Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST
a buffer is recommended to ensure the VIL and VIH specifications are met.
†
†
HOST-PORT INTERFACE SIGNALS (CONTINUED)
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA
register. HAS
Read/write. HR/W controls the direction of an HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when EMU1/OFF
Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can also
be configured as the timer 1 output (TOUT1) when the HPI is disabled. The signal goes into the high-impedance
state when EMU1/OFF
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor
is always active and the HPIENA pin is sampled on the rising edge of RS
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the UC5402
is reset.
S +VDD. Dedicated power supply for the core CPU
S +VDD. Dedicated power supply for the I/O pins
S Ground
IEEE standard 1 149.1 (JTAG) test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The
changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller,
instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal
(TDO) occur on the falling edge of TCK.
IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST
I
1149.1 signals are ignored. Pin with internal pulldown device.
Emulator 0 pin. When TRST is driven low , EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
of the IEEE standard 1149.1 scan system.
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST
is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active (low), puts all output drivers
into the high-impedance state. Note that OFF
multiprocessing applications). Therefore, for the OFF
TRST
EMU0 = high
EMU1/OFF
has an internal pullup resistor that is only enabled when HPIENA = 0.
is low.
SUPPLY PINS
MISCELLANEOUS SIGNAL
TEST PINS
is driven low, the device operates in its functional mode, and the IEEE standard
= low
= low
DESCRIPTIONTYPE
DESCRIPTIONTYPE
is low.
is used exclusively for testing and emulation purposes (not for
feature, the following apply:
. If HPIENA is left open or is driven low
pin is connected to multiple DSPs,
8
April 1999 − Revised October 2008SPRS096C
2 Functional Overview
The following functional overview is based on the block diagram in Figure 2−1.
Functional Overview
P, C, D, E Buses and Control Signals
Pbus
Cbus
54x Core
JTAG
External Memory Interface
HPI8 Module
Ebus
Dbus
DMA Controller
6 Channels
DMA Bus
Pbus
Cbus
Dbus
16K Dual-Access RAM
Program/Data
Peripheral Bus
Ebus
Pbus
4K ROM Program/Data
Figure 2−1. Block Diagram of the TMS320UC5402
Cbus
Dbus
GPIO
McBSP0
McBSP1
Timer0
Timer1
APLL
2.1 Memory
The UC5402 device provides both on-chip ROM and RAM to aid in system performance and integration.
2.1.1 On-Chip Dual-Access RAM (DARAM)
The UC5402 device contains 16K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed
of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and
a write in one cycle. The DARAM is located in the address range 0080h−3FFFh in data space, and can be
mapped into program/data space by setting the OVLY bit to 1.
April 1999 − Revised October 2008 SPRS096C
9
Functional Overview
2.1.2 On-Chip ROM With Bootloader
The UC5402 features 4K × 16-bit of on-chip maskable ROM. Customers can arrange to have the ROM of the
UC5402 programmed with contents unique to any particular application. A security option is available to
protect a custom ROM. This security option is described in the TMS320C54x DSP Reference Set, Volume 1:
CPU and Peripherals (literature number SPRU131). Note that only the ROM security option, and not the
ROM/RAM option, is available on the UC5402 .
A bootloader is available in the standard UC5402 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC
pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program. The standard UC5402 bootloader
provides different ways to download the code to accomodate various system requirements:
• Parallel from 8-bit or 16-bit-wide EPROM
• Parallel from I/O space 8-bit or 16-bit mode
• Serial boot from serial ports 8-bit or 16-bit mode
• Host-port interface boot
The standard on-chip ROM layout is shown in Table 2−1.
Table 2−1. Standard On-Chip ROM Layout
ADDRESS RANGE DESCRIPTION
F000h − F7FFh Reserved
†
F800h − FBFFh Bootloader
FC00h − FCFFh µ-law expansion table
FD00h − FDFFh A-law expansion table
FE00h − FEFFh Sine look-up table
FF00h − FF7Fh Reserved
FF80h − FFFFh Interrupt vector table
†
In the UC5402 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
10
April 1999 − Revised October 2008SPRS096C
2.1.3 Memory Map
Functional Overview
Page 0 Program
Hex
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
3FFF
4000
External
FF7F
FF80
FFFF
Interrupts
(External)
MP/MC= 1
(Microprocessor Mode)
Page 0 Program
Hex
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
3FFF
4000
External
EFFF
F000
FEFF
FF00
FF7F
FF80
FFFF
On-Chip ROM
(4K x 16-bit)
Reserved
Interrupts
(On-Chip)
MP/MC
(Microcomputer Mode)
= 0
Hex
0000
005F
0060
007F
0080
On-Chip DARAM
3FFF
4000
EFFF
F000
ROM (DROM=1)
FEFF
FF00
FFFF
Data
Memory
Mapped
Registers
Scratch-Pad
RAM
(16K x 16-bit)
External
or External
(DROM=0)
Reserved
(DROM=1)
or External
(DROM=0)
Figure 2−2. TMS320UC5402 Memory Map
2.1.4 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see
Figure 2−3) with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or
trap vector is mapped to the new 128-word page.
NOTE: The hardware reset (RS
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
April 1999 − Revised October 2008 SPRS096C
) vector cannot be remapped because a hardware reset loads the IPTR
11
Functional Overview
15 76543210
IPTR MP/MC OVLY AVIS DROM
R/W R/W R/W R R R R/W R/W
LEGEND: R = Read, W = Write
CLK
OFF
SMUL SST
Figure 2−3. Processor Mode Status (PMST) Register
2.1.5 Extended Program Memory
The UC5402 uses a paged extended memory scheme in program space to allow access of up to 1024K
program memory locations. In order to implement this scheme, the UC5402 includes several features that are
also present on the 548/549 devices:
• Twenty address lines, instead of sixteen
• An extra memory-mapped register, the XPC register, defines the page selection. This register is
memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
• Six extra instructions for addressing extended program space. These six instructions affect the XPC.
− FB[D] pmad (20 bits) − Far branch
− FBACC[D] Accu[19:0] − Far branch to the location specified by the value in accumulator A or
accumulator B
− FCALL[D] pmad (20 bits) − Far call
− FCALA[D] Accu[19:0] − Far call to the location specified by the value in accumulator A or
accumulator B
− FRET[D] − Far return
− FRETE[D] − Far return with interrupts enabled
• In addition to these new instructions, two 54x instructions are extended to use 20 bits in the UC5402:
− READA data_memory (using 20-bit accumulator address)
− WRITA data_memory (using 20-bit accumulator address)
All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access
only memory within the current page.
12
April 1999 − Revised October 2008SPRS096C
Functional Overview
Program memory in the UC5402 is organized into 16 pages that are each 64K in length, as shown in
Figure 2−4.
0 0000
Page 0
64K
Words{
0 FFFF
†
See Figure 2−2
‡
The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM
is mapped to the lower 16K words of all program space pages.
1 0000
1 3FFF
1 4000
1 FFFF
Page 1
Lower
16K}
External
Page 1
Upper
48K
External
2 0000
2 3FFF
2 4000
2 FFFF
Page 2
Lower
16K}
External
Page 2
Upper
48K
External
. . .
. . .
. . .
. . .
F 0000
F 3FFF
F 4000
F FFFF
Page 15
Lower
16K}
External
Page 15
Upper
48K
External
Figure 2−4. Extended Program Memory
2.2 On-Chip Peripherals
The UC5402 device supports the following on-chip peripherals:
• Software-programmable wait-state generator with programmable bank-switching wait states
• An enhanced 8-bit host-port interface (HPI8)
• Two multichannel buffered serial ports (McBSPs)
• Two hardware timers
• A clock generator with a phase-locked loop (PLL)
• A direct memory access (DMA) controller
2.2.1 Software-Programmable Wait-State Generator
The software wait-state generator of the UC5402 can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.
When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator
are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the
UC5402.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 15 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 2−5 and described in Table 2−2.
14 12 11 9 8 6 5 3 2 015
XPA I/O Data Data Program Program
R/W-111R/W-0 R/W-111 R/W-111 R/W-111 R/W-111
LEGEND: R=Read, W=Write, 0=Value after reset
Figure 2−5. Software W ait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
April 1999 − Revised October 2008 SPRS096C
13
Functional Overview
RESET
RESET
FUNCTION
RESET
RESET
FUNCTION
BIT
NO. NAME
15 XPA 0
14−12 I/O 1
11−9 Data 1
8−6 Data 1
5−3 Program 1
2−0 Program 1
Table 2−2. Software Wait-State Register (SWWSR) Bit Fields
VALUE
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for the program space wait states.
I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
Upper data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Lower data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
- XPA = 0: x8000 − xFFFFh
- XPA = 1: The upper program space bit field has no effect on wait states.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
- XPA = 0: x0000−x7FFFh
- XPA = 1: 00000−FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
The software wait-state multiplier bit (SWSM) of the software wait-state control register (SWCR) is used to
extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 2−6
and described in Table 2−3.
115
Reserved
R/W-0
LEGEND: R = Read, W = Write
0
SWSM
R/W-0
Figure 2−6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 2−3. Software Wait-State Control Register (SWCR) Bit Fields
BIT
NO. NAME
15−1 Reserved 0
0 SWSM 0
VALUE
These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
- SWSM = 0: wait-state base values are unchanged (multiplied by 1).
- SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.
14
April 1999 − Revised October 2008SPRS096C
2.2.1.1 Programmable Bank-Switching Wait States
RESET
FUNCTION
EXIO = 0 The external bus interface functions as usual.
The programmable bank-switching logic of the UC5402 is functionally equivalent to that of the 548/549
devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within
program or data memory space. A bank-switching wait state can also be automatically inserted when
accesses cross the data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 2−7
shows the BSCR and its bits are described in Table 2−4.
Functional Overview
12 11 3 2 115
BNKCMP PS-DS Reserved HBH
LEGEND: R = Read, W = Write
Figure 2−7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
Table 2−4. Bank-Switching Control Register (BSCR) Bit Fields
BIT
NO. NAME
15−12 BNKCMP 1111
11 PS - DS 1
10−3 Reserved 0 These bits are reserved and are unaffected by writes.
2 HBH 0
1 BH 0
RESET
VALUE
Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of
an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12−15) are compared, resulting in a
bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
Program read − data read access. Inserts an extra cycle between consecutive accesses of program read
and data read or data read and program read.
PS-DS = 0 No extra cycles are inserted by this feature.
PS-DS = 1 One extra cycle is inserted between consecutive data and program reads.
HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset.
HBH = 0 The bus holder is disabled.
HBH = 1 The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the
previous logic level.
Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0 The bus holder is disabled.
BH = 1 The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the
previous logic level.
External bus interface off. The EXIO bit controls the external bus-off function.
010
BH EXIO
R/W-0R-0R/W-1R/W-1111
R/W-0R/W-0
0 EXIO 0
April 1999 − Revised October 2008 SPRS096C
EXIO = 1 The address bus, data bus, and control signals become inactive after completing the
current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM
bit of ST1 cannot be modified when the interface is disabled.
15
Functional Overview
2.2.2 Parallel I/O Ports
The UC5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS
interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding
circuits.
2.2.2.1 Enhanced 8-Bit Host-Port Interface (HPI8)
The UC5402 host-port interface, also referred to as the HPI8, is an enhanced version of the standard 8-bit
HPI found on earlier 54x DSPs (542, 545, 548, and 549). The HPI8 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8 include:
Standard features:
• Sequential transfers (with autoincrement) or random-access transfers
• Host interrupt and 54x interrupt capability
• Multiple data strobes and control pins for interface flexibility
Enhanced features of the UC5402 HPI8:
• Access to entire on-chip RAM through DMA bus
• Capability to continue transferring during emulation stop
signal indicates a read/write operation through an I/O port. The UC5402 can
Hex
0000
001F
0020
0023
0024
005F
0060
007F
0080
Reserved
McBSP
Registers
Reserved
Scratch-Pad
RAM
16
(16K x 16-bit)
On-Chip DARAM
3FFF
4000
Reserved
FFFF
Figure 2−8. UC5402 HPI8 Memory Map
The HPI8 functions as a slave and enables the host processor to access the on-chip memory of the UC5402.
A major enhancement to the UC5402 HPI over previous versions is that it allows host access to the entire
on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times
and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to
the same location, the host has priority, and the DSP waits for one HPI8 cycle. Note that since host accesses
are always synchronized to the UC5402 clock, an active input clock (CLKIN) is required for HPI8 accesses
during IDLE states, and host accesses are not allowed while the UC5402 reset pin is asserted.
April 1999 − Revised October 2008SPRS096C
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an
HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC
register is accessible by both the host and the UC5402.
2.2.2.2 Multichannel Buffered Serial Ports
The UC5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that
allow direct interface to other C54x/LC54x DSPs, codecs, and other devices in a system. The McBSPs are
based on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP
provides:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
• Direct interface to:
− T1/E1 framers
− MVIP switching compatible and ST-BUS compliant devices
− IOM-2 compliant devices
− Serial peripheral interface devices
• Multichannel transmit and receive of up to 128 channels
• A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
•µ-law and A-law companding
• Programmable polarity for both frame synchronization and data clocks
• Programmable internal clock and frame generation
Functional Overview
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
• BCLKX Transmit reference clock
• BDX Transmit data
• BFSX Transmit frame synchronization
• BCLKR Receive reference clock
• BDR Receive data
• BFSR Receive frame synchronization
The six pins listed are functionally equivalent to the previous serial port interface pins in the TMS320C5000
platform of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX
and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit
register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This
structure allows DXR to be loaded with the next word to be sent while the transmission of the current word
is in progress.
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received
on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register
(RBR). If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until
the DRR is available. This structure allows storage of the two previous words while the reception of the current
word is in progress.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
TMS320C5000 is a trademark of Texas Instruments.
April 1999 − Revised October 2008 SPRS096C
17
Functional Overview
In addition to the standard serial port functions, the McBSP provides programmable clock and frame
synchronization generation. Among the programmable functions are:
• Frame synchronization pulse width
• Frame period
• Frame synchronization delay
• Clock reference (internal vs. external)
• Clock division
• Clock and frame synchronization polarity
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received
data is decoded to 2s complement format.
The McBSP allows multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus
bandwidth, multichannel selection allows independent enabling of particular channels for transmission and
reception. Up to 32 channels in a stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes
supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP
is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or
as a slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
2.2.3 Hardware Timer
The UC5402 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer
is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.
2.2.4 Clock Generator
The clock generator provides clocks to the UC5402 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external reference clock source. The
reference clock input is then divided by two or four (DIV mode) to generate clocks for the UC5402 device, or
the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock
frequency by a scale factor. This allows the use of a clock source with a lower frequency than that of the
CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CV
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the
UC5402 device.
DD
+ 0.3 V.
18
April 1999 − Revised October 2008SPRS096C
Functional Overview
CLKMD1
CLKMD2
CLKMD3
RESET VALUE
CLOCK MODE
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
• A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the UC5402 to enable the internal oscillator.
• An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CV
DD
+ 0.3 V.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to the PLL clocking mode of the device until lock is achieved. Devices that have
a built-in software-programmable PLL can be configured in one of two clock modes:
• PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
• DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon
reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the
CLKMD1 − CLKMD3 pins as shown in Table 2−5.
Table 2−5. Clock Mode Settings at Reset
CLKMD1 CLKMD2 CLKMD3
0 0 0 E007h PLL x 15
0 0 1 9007h PLL x 10
0 1 0 4007h PLL x 5
1 0 0 1007h PLL x 2
1 1 0 F007h PLL x 1
1 1 1 0000h 1/2 (PLL disabled)
1 0 1 F000h 1/4 (PLL disabled)
0 1 1 — Reserved (bypass mode)
CLKMD
CLOCK MODE
April 1999 − Revised October 2008 SPRS096C
19
Functional Overview
2.2.5 DMA Controller
The UC5402 direct memory access (DMA) controller transfers data between points in the memory map
without intervention by the CPU. The DMA controller allows movements of data to and from internal
program/data memory or internal peripherals (such as the McBSPs) to occur in the background of CPU
operation. The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.
2.2.5.1 Features
The DMA has the following features:
• The DMA operates independently of the CPU.
• The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
• The DMA has higher priority than the CPU for internal accesses.
• Each channel has independently programmable priorities.
• Each channel ’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be postincremented,
postdecremented, or be adjusted by a programmable value.
• Each read or write transfer may be initialized by selected events.
• Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to
the CPU.
• The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).
2.2.5.2 DMA Memory Map
The DMA memory map allows DMA transfers to be unaffected by the status of the MP/MC, DROM, and OVLY
bits. The DMA memory map (see Figure 2−9) is identical to that of the HPI8 controller .
Hex
0000
001F
0020
0023
0024
005F
0060
007F
0080
3FFF
4000
FFFF
Reserved
McBSP
Registers
Reserved
Scratch-Pad
RAM
(16K x 16-bit)
On-Chip DARAM
Reserved
Figure 2−9. UC5402 DMA Memory Map
2.2.5.3 DMA Priority Level
Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
20
April 1999 − Revised October 2008SPRS096C
2.2.5.4 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately a n d
can be postincremented, postdecremented, or postincremented with a specified index offset.
2.2.5.5 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
• Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfer; but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
• Repetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
2.2.5.6 DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
• Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon
the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter i s
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
• Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is
reloaded with the DMA global count reload register (DMGCR).
Functional Overview
2.2.5.7 DMA Transfers in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
2.2.5.8 DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined
by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
• Element index: For all except the last transfer in the frame, the element index determines the amount to
be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
• Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as
selected by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.
2.2.5.9 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA mode control register (DMMCRx). The available modes
are shown in Table 2−6.
April 1999 − Revised October 2008 SPRS096C
21
Functional Overview
Table 2−6. DMA Interrupts
MODE DINM IMOD INTERRUPT
ABU (non-decrement) 1 0 At full buffer only
ABU (non-decrement) 1 1 At half buffer and full buffer
Multi-Frame 1 0 At block transfer complete (DMCTRx = DMSEFCx[7:0] = 0)
Multi-Frame 1 1 At end of frame and end of block (DMCTRx = 0)
Either 0 X No interrupt generated
Either 0 X No interrupt generated
2.2.5.10 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization
event for a channel. The list of possible events and the DSYN values are shown in Table 2−7.
Table 2−7. DMA Synchronization Events
DSYN VALUE DMA SYNCHRONIZATION EVENT
0000b No synchronization used
0001b McBSP0 receive event
0010b McBSP0 transmit event
0011−0100b Reserved
0101b McBSP1 receive event
0110b McBSP1 transmit event
0111b−0110b Reserved
1101b Timer0 interrupt
1110b External interrupt 3
1111b Timer1 interrupt
2.2.5.11 DMA Channel Interrupt Selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources
for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 1 1), and DMA channel 1 shares an
interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved
interrupt source. When the UC5402 is reset, the interrupts from these four DMA channels are deselected. The
INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these
interrupts, as shown in Table 2−8.
Table 2−8. DMA Channel Interrupt Selection
INTSEL Value IMR/IFR[6] IMR/IFR[7] IMR/IFR[10] IMR/IFR[11]
00b (reset) Reserved TINT1 BRINT1 BXINT1
01b Reserved TINT1 DMAC2 DMAC3
10b DMAC0 DMAC1 DMAC2 DMAC3
11b Reserved
22
April 1999 − Revised October 2008SPRS096C
2.3 Memory-Mapped Registers
NAME
DESCRIPTION
The UC5402 has a set of memory-mapped registers associated with the CPU, on-chip peripherals, the
McBSPs, and the DMA.
2.3.1 CPU Memory-Mapped Registers
The UC5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses
0h to 1Fh. Table 2−9 gives a list of the CPU memory-mapped registers (MMRs) available on UC5402.
Table 2−9. CPU Memory-Mapped Registers
ADDRESS
DEC HEX
IMR 0 0 Interrupt mask register
IFR 1 1 Interrupt flag register
– 2−5 2−5 Reserved for testing
ST0 6 6 Status register 0
ST1 7 7 Status register 1
AL 8 8 Accumulator A low word (15−0)
AH 9 9 Accumulator A high word (31−16)
AG 10 A Accumulator A guard bits (39−32)
BL 11 B Accumulator B low word (15−0)
BH 12 C Accumulator B high word (31−16)
BG 13 D Accumulator B guard bits (39−32)
TREG 14 E Temporary register
TRN 15 F Transition register
AR0 16 10 Auxiliary register 0
AR1 17 11 Auxiliary register 1
AR2 18 12 Auxiliary register 2
AR3 19 13 Auxiliary register 3
AR4 20 14 Auxiliary register 4
AR5 21 15 Auxiliary register 5
AR6 22 16 Auxiliary register 6
AR7 23 17 Auxiliary register 7
SP 24 18 Stack pointer register
BK 25 19 Circular buffer size register
BRC 26 1A Block-repeat counter
RSA 27 1B Block-repeat start address
REA 28 1C Block-repeat end address
PMST 29 1D Processor mode status (PMST) register
XPC 30 1E Extended program page register
– 31 1F Reserved
Functional Overview
April 1999 − Revised October 2008 SPRS096C
23
Functional Overview
2.3.2 Peripheral Memory-Mapped Registers
The UC5402 has a set of memory-mapped registers associated with peripherals as shown in Table 2−10.
Table 2−10. Peripheral Memory-Mapped Registers
NAME ADDRESS DESCRIPTION TYPE
DRR20 20h
DRR10 21h
DXR20 22h
DXR10 23h
TIM 24h
PRD 25h
TCR 26h
– 27h Reserved
SWWSR 28h
BSCR 29h
– 2Ah Reserved
SWCR 2Bh
HPIC 2Ch
– 2Dh−2Fh Reserved
TIM1 30h
PRD1 31h
TCR1 32h
– 33h−37h Reserved
SPSA0
SPSD0
– 3Ah−3Bh Reserved
GPIOCR
GPIOSR
– 3Eh−3Fh Reserved
DRR21 40h
DRR11 41h
DXR21 42h
DXR11 43h
– 44h−47h Reserved
SPSA1 48h
SPSD1
– 4Ah−53h Reserved
DMPREC 54h
DMSA 55h
DMSDI
DMSDN
CLKMD
– 59h−5Fh Reserved
†
See Table 2−11 for a detailed description of the McBSP control registers and their subaddresses.
‡
See Table 2−12 for a detailed description of the DMA subbank addressed registers.
38h
39h
3Ch
3Dh
49h
56h
57h
58h
McBSP0 data receive register 2 McBSP #0
McBSP0 data receive register 1 McBSP #0
McBSP0 data transmit register 2 McBSP #0
McBSP0 data transmit register 1 McBSP #0
Timer0 register Timer0
Timer0 period counter Timer0
Timer0 control register Timer0
Software wait-state register External Bus
Bank-switching control register External Bus
Software wait-state control register External Bus
HPI control register HPI
Timer1 register Timer1
Timer1 period counter Timer1
Timer1 control register Timer1
McBSP0 subbank address register
McBSP0 subbank data register
General-purpose I/O pins control register
General-purpose I/O pins status register
McBSP1 data receive register 2 McBSP #1
McBSP1 data receive register 1 McBSP #1
McBSP1 data transmit register 2 McBSP #1
McBSP1 data transmit register 1 McBSP #1
McBSP1 subbank address register
McBSP1 subbank data register
DMA channel priority and enable control register DMA
DMA subbank address register
DMA subbank data register with autoincrement
DMA subbank data register
Clock mode register
†
†
†
†
‡
‡
‡
McBSP #0
McBSP #0
GPIO
GPIO
McBSP #1
McBSP #1
DMA
DMA
DMA
PLL
24
April 1999 − Revised October 2008SPRS096C
2.3.3 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The serial port subbank address (SPSA) register is used as a pointer to select a particular register
within the subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected
register. Table 2−11 shows the McBSP control registers and their corresponding subaddresses.
Table 2−11. McBSP Control Registers and Subaddresses
McBSP0
NAME ADDRESS
SPCR10
SPCR20
RCR10
RCR20
XCR10
XCR20
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
McBSP1
NAME ADDRESS
SPCR11
SPCR21
RCR11
RCR21
XCR11
XCR21
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
SUB-
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Serial port control register 1
Serial port control register 2
Receive control register 1
Receive control register 2
Transmit control register 1
Transmit control register 2
Sample rate generator register 1
Sample rate generator register 2
Multichannel register 1
Multichannel register 2
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
Functional Overview
DESCRIPTION
2.3.4 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular
register within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register
with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access a ffects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 2−12 shows the DMA
controller subbank addressed registers and their corresponding subaddresses.
April 1999 − Revised October 2008 SPRS096C
25
Functional Overview
Table 2−12. DMA Subbank Addressed Registers
SUB-
NAME ADDRESS
DMSRC0 56h/57h 00h DMA channel 0 source address register
DMDST0 56h/57h 01h DMA channel 0 destination address register
DMCTR0 56h/57h 02h DMA channel 0 element count register
DMSFC0 56h/57h 03h DMA channel 0 sync select and frame count register
DMMCR0 56h/57h 04h DMA channel 0 transfer mode control register
DMSRC1 56h/57h 05h DMA channel 1 source address register
DMDST1 56h/57h 06h DMA channel 1 destination address register
DMCTR1 56h/57h 07h DMA channel 1 element count register
DMSFC1 56h/57h 08h DMA channel 1 sync select and frame count register
DMMCR1 56h/57h 09h DMA channel 1 transfer mode control register
DMSRC2 56h/57h 0Ah DMA channel 2 source address register
DMDST2 56h/57h 0Bh DMA channel 2 destination address register
DMCTR2 56h/57h 0Ch DMA channel 2 element count register
DMSFC2 56h/57h 0Dh DMA channel 2 sync select and frame count register
DMMCR2 56h/57h 0Eh DMA channel 2 transfer mode control register
DMSRC3 56h/57h 0Fh DMA channel 3 source address register
DMDST3 56h/57h 10h DMA channel 3 destination address register
DMCTR3 56h/57h 11h DMA channel 3 element count register
DMSFC3 56h/57h 12h DMA channel 3 sync select and frame count register
DMMCR3 56h/57h 13h DMA channel 3 transfer mode control register
DMSRC4 56h/57h 14h DMA channel 4 source address register
DMDST4 56h/57h 15h DMA channel 4 destination address register
DMCTR4 56h/57h 16h DMA channel 4 element count register
DMSFC4 56h/57h 17h DMA channel 4 sync select and frame count register
DMMCR4 56h/57h 18h DMA channel 4 transfer mode control register
DMSRC5 56h/57h 19h DMA channel 5 source address register
DMDST5 56h/57h 1Ah DMA channel 5 destination address register
DMCTR5 56h/57h 1Bh DMA channel 5 element count register
DMSFC5 56h/57h 1Ch DMA channel 5 sync select and frame count register
DMMCR5 56h/57h 1Dh DMA channel 5 transfer mode control register
DMSRCP 56h/57h 1Eh DMA source program page address (common channel)
DMDSTP 56h/57h 1Fh DMA destination program page address (common channel)
DMIDX0 56h/57h 20h DMA element index address register 0
DMIDX1 56h/57h 21h DMA element index address register 1
DMFRI0 56h/57h 22h DMA frame index register 0
DMFRI1 56h/57h 23h DMA frame index register 1
DMGSA 56h/57h 24h DMA global source address reload register
DMGDA 56h/57h 25h DMA global destination address reload register
DMGCR 56h/57h 26h DMA global count reload register
DMGFR 56h/57h 27h DMA global frame count reload register
†
ADDRESS
DESCRIPTION
†
Address 56h is used to access DMA subbank data registers with autoincrement (DMSDI) while address 57h is used to access DMA subbank
data register without autoincrement (DMSDN).
26
April 1999 − Revised October 2008SPRS096C
Functional Overview
2.4 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 2−13.
Table 2−13. Interrupt Locations and Priorities
NAME
RS, SINTR 0 00 1 Reset (hardware and software reset)
NMI, SINT16 4 04 2 Nonmaskable interrupt
SINT17 8 08 — Software interrupt #17
SINT18 12 0C — Software interrupt #18
SINT19 16 10 — Software interrupt #19
SINT20 20 14 — Software interrupt #20
SINT21 24 18 — Software interrupt #21
SINT22 28 1C — Software interrupt #22
SINT23 32 20 — Software interrupt #23
SINT24 36 24 — Software interrupt #24
SINT25 40 28 — Software interrupt #25
SINT26 44 2C — Software interrupt #26
SINT27 48 30 — Software interrupt #27
SINT28 52 34 — Software interrupt #28
SINT29 56 38 — Software interrupt #29
SINT30 60 3C — Software interrupt #30
INT0, SINT0 64 40 3 External user interrupt #0
INT1, SINT1 68 44 4 External user interrupt #1
INT2, SINT2 72 48 5 External user interrupt #2
TINT0, SINT3 76 4C 6 Timer0 interrupt
BRINT0, SINT4 80 50 7 McBSP #0 receive interrupt
BXINT0, SINT5 84 54 8 McBSP #0 transmit interrupt
Reserved(DMAC0), SINT6 88 58 9
TINT1(DMAC1), SINT7 92 5C 10
INT3, SINT8 96 60 11 External user interrupt #3
HPINT, SINT9 100 64 12 HPI interrupt
BRINT1(DMAC2), SINT10 104 68 13
BXINT1(DMAC3), SINT11 108 6C 14
DMAC4,SINT12 112 70 15 DMA channel 4 interrupt
DMAC5,SINT13 116 74 16 DMA channel 5 interrupt
Reserved 120−127 78−7F — Reserved
LOCATION
DECIMAL HEX
PRIORITY FUNCTION
Reserved (default) or DMA channel 0 interrupt. The selection is made in the DMPREC
register.
Timer1 interrupt (default) or DMA channel 1
interrupt. The selection is made in the
DMPREC register.
McBSP #1 receive interrupt (default) or DMA
channel 2 interrupt. The selection is made in
the DMPREC register.
McBSP #1 transmit interrupt (default) or DMA
channel 3 interrupt. The selection is made in
the DMPREC register.
April 1999 − Revised October 2008 SPRS096C
27
Functional Overview
FUNCTION
2.4.1 IFR and IMR Registers
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in
Figure 2−10.
15−14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES DMAC5 DMAC4
BXINT1
DMAC3
BIT
NUMBER NAME
15−14 − Reserved for future expansion
13 DMAC5 DMA channel 5 interrupt flag/mask bit
12 DMAC4
11 BXINT1/DMAC3
10 BRINT1/DMAC2
9 HPINT
8 INT3
7 TINT1/DMAC1
6 Reserved or DMAC0
5 BXINT0
4 BRINT0
3 TINT0
2 INT2
1 INT1
0 INT0
BRINT1
or
or
DMAC2
HPINT INT3
TINT1
or
DMAC1
RES
or
DMAC0
Figure 2−10. IFR and IMR Registers
Table 2−14. IFR and IMR Register Bit Fields
DMA channel 4 interrupt flag/mask bit
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
Host to C54x interrupt flag/mask
External interrupt 3 flag/mask
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
This bit can be configured either as reserved or as the DMA channel 0 interrupt flag/mask bit. The
selection is made in the DMPREC register.
McBSP0 transmit interrupt flag/mask bit
McBSP0 receive interrupt flag/mask bit
Timer 0 interrupt flag/mask bit
External interrupt 2 flag/mask bit
External interrupt 1 flag/mask bit
External interrupt 0 flag/mask bit
BXINT0 BRINT0 TINT0 INT2 INT1 INT0
28
April 1999 − Revised October 2008SPRS096C
3 Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 platform of DSPs:
• TMS320C54x DSP Functional Overview (literature number SPRU307)
• Device-specific data sheets
• Complete user’s guides
• Development support tools
• Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
• Volume 1: CPU and Peripherals (literature number SPRU131)
• Volume 2: Mnemonic Instruction Set (literature number SPRU172)
• Volume 3: Algebraic Instruction Set (literature number SPRU179)
• Volume 4: Applications Guide (literature number SPRU173)
• Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Documentation Support
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 and C5000 are trademarks of Texas Instruments.
April 1999 − Revised October 2008 SPRS096C
29
Electrical Specifications
DVDD = 1.90 V to 2.99 V
High-level input
V
High-level input
V
4 Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320UC5402 DSP.
4.1 Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 4.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to V
values for a 1.8-V device.
. Figure 4−1 provides the test load circuit
SS
Supply voltage I/O range, DV
Supply voltage core range, CV
Input voltage range, V
I
Output voltage range, V
DD
DD
O
Operating case temperature range, T
Storage temperature range, T
stg
C
−0.3 V to 4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3 V to 2.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−40°C to 100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Recommended Operating Conditions
MIN NOM MAX UNIT
DVDDDevice supply voltage, I/O 1.71 3.6 V
CVDDDevice supply voltage, core 1.71 1.8 1.98 V
V
Supply voltage, GND 0 V
SS
DVDD = 1.71 V to 1.89 V
IH
voltage
DVDD = 3.0 V to 3.6 V
DVDD = 1.71 V to 1.89 V
Low-level input
V
IL
voltage
I
High-level output current −300 µA
OH
I
Low-level output current 1.5 mA
OL
T
Operating case temperature −40 100 °C
C
DVDD = 1.90 V to 3.6 V
X2/CLKIN 1.35 CVDD + 0.3
All other inputs 1.35 DVDD + 0.3
X2/CLKIN 1.35 CVDD + 0.3
All other inputs 1.7 DVDD + 0.3
X2/CLKIN 1.35 CVDD + 0.3
RS, INTn, NMI, BIO,
BCLKR0, BCLKR1, BCLKX0,
BCLKX1, HCS, HDS1,
HDS2
, TDI, TMS, CLKMDn
TCK, TRST 2.5 DVDD + 0.3
All other inputs 2 DVDD + 0.3
X2/CLKIN −0.3 0.6
All other inputs −0.3 0.6
X2/CLKIN −0.3 0.6
RS, INTn, NMI, BIO,
BCLKR0, BCLKR1, BCLKX0,
BCLKX1, HCS, HDS1,
HDS2
, TCK, CLKMDn
All other inputs −0.3 0.8
2.2 DVDD + 0.3
−0.3 0.6
V
30
April 1999 − Revised October 2008SPRS096C
Electrical Specifications
OL
t
DVDD = 1.71 to 1.89 V
IOL = MAX
V
OL
voltage
V
IZ
r
I
IZ
outputs in high
µA
Input current
(VI = V
All other input-only
All other input-only
f
= 80 MHz,w
f
clock
= 80 MHz,w
I
Supply current,
4.3 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
High-level output voltage
OH
Low-level outpu
V
Input current fo
I
outputs in high
impedance
I
I
DVDD = 1.9 to 3.6 V IOL = MAX All outputs 0.4
D[15:0], HD[7:0]
All other inputs
X2/CLKIN −40 40
TRST With internal pulldown −5 300
HPIENA With internal pulldown
TMS, TCK, TDI, HPI
IOH = MAX DVDD − 0.3 V
CLKOUT 0.4
All other outputs 0.35
Bus holders enabled, DVDD = MAX,
VI = VSS to DV
DVDD = MAX, VO = VSS to DV
With internal pullups,
}
HPIENA = 0
DD
DD
SS
to DVDD)
−175 175
−5 5
−5 300
−300 5
V
µA
µA
pins
I
Supply current, core CPU
DDC
I
Supply current, pins
DDP
Supply current,
DD
standby
C
Input capacitance 5 pF
i
C
Output capacitance 5 pF
o
†
All values are typical unless otherwise specified.
‡
HPI input signals except for HPIENA.
§
Clock mode: PLL × 1 with external source
IDLE2 PLL × 1 mode, 80 MHz input 1.6 mA
IDLE3 Divide-by-two mode, CLKIN stopped 20 µA
Tester Pin
Electronics
V
Load
CVDD = 1.8 V, f
TC = 25°C
TC = 25°C
clock
= 80 MHz,w
DVDD = 1.71 to
1.89 V
DVDD = 1.9 to
3.6 V
I
OL
50 Ω
−5 5
35 mA
12
mA
27
Output
Under
C
Test
T
April 1999 − Revised October 2008 SPRS096C
Where: I
= 1.5 mA (all outputs)
OL
I
= 300 µA (all outputs)
OH
V
= 0.855 V
Load
C
= 40 pF typical load circuit capacitance
T
Figure 4−1. 1.8-V Test Load Circuit
I
OH
31
Electrical Specifications
4.4 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings: Letters and symbols and their meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
dis disable time Z High impedance
en enable time
f fall time
h hold time
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
X Unknown, changing, or don’t care level
32
April 1999 − Revised October 2008SPRS096C
4.5 Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
4.5.1 Internal Oscillator With External Crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT
is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD
register. The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω and power dissipation of 1 mW. The circuit shown in Figure 4−2 represents
fundamental-mode operation.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 4−2.
The load capacitors, C
is the load specified for the crystal.
f
clock
Input clock frequency 10 20 MHz
and C2, should be chosen such that the equation below is satisfied. CL in the equation
1
C
+
L
(C1) C2)
Electrical Specifications
C
1C2
MIN MAX UNIT
X1 X2/CLKIN
Crystal
C1 C2
Figure 4−2. Internal Oscillator With External Crystal
April 1999 − Revised October 2008 SPRS096C
33
Electrical Specifications
4.5.2 Divide-By-Two Clock Option (PLL disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate
the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 4−1.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CV
Table 4−1 and Table 4−2 assume testing over recommended operating conditions and H = 0.5t
Figure 4−3).
Table 4−1. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
t
c(CI)
t
f(CI)
t
r(CI)
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
t
c(CO)
t
d(CIH-CO)
t
f(CO)
t
r(CO)
t
w(COL)
t
w(COH)
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
‡
It is recommended that the PLL clocking option be used for maximum frequency operation.
Cycle time, X2/CLKIN 6.25
Fall time, X2/CLKIN 8 ns
Rise time, X2/CLKIN 8 ns
approaching ∞. The device is characterized at frequencies
c(CI)
Table 4−2. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
PARAMETER MIN TYP MAX UNIT
Cycle time, CLKOUT 12.5‡2t
Delay time, X2/CLKIN high to CLKOUT high/low 7 12 20 ns
Fall time, CLKOUT 4 ns
Rise time, CLKOUT 4 ns
Pulse duration, CLKOUT low H−2 H + 2 ns
Pulse duration, CLKOUT high H−2 H + 2 ns
approaching ∞. The device is characterized at frequencies
c(CI)
t
c(CI)
X2/CLKIN
t
r(CI)
+ 0.3 V.
DD
(see
c(CO)
MIN MAX UNIT
†
ns
†
c(CI)
t
f(CI)
ns
34
CLKOUT
t
f(CO)
t
d(CIH-CO)
t
c(CO)
Figure 4−3. External Divide-by-Two Clock Timing
t
r(CO)
t
w(COH)
April 1999 − Revised October 2008SPRS096C
t
w(COL)
4.5.3 Multiply-By-N Clock Option (PLL Enabled)
c(CI)
t
c(CI)
Cycle time, X2/CLKIN
ns
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in the
clock generator section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 4−3.
Electrical Specifications
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CV
Table 4−3 and Table 4−4 assume testing over recommended operating conditions and H = 0.5t
Figure 4−4).
t
t
f(CI)
t
r(CI)
†
N = Multiplication factor
t
c(CO)
t
d(CI-CO)
t
f(CO)
t
r(CO)
t
w(COL)
t
w(COH)
t
p
†
N = Multiplication factor
Cycle time, X2/CLKIN
Fall time, X2/CLKIN 8 ns
Rise time, X2/CLKIN 8 ns
Cycle time, CLKOUT 12.5 t
Delay time, X2/CLKIN high/low to CLKOUT high/low 7 10 20 ns
Fall time, CLKOUT 4 ns
Rise time, CLKOUT 4 ns
Pulse duration, CLKOUT low H−2 H + 2 ns
Pulse duration, CLKOUT high H−2 H + 2 ns
Transitory phase, PLL lock up time 30 ms
Table 4−3. Multiply-By-N Clock Option Timing Requirements
Integer PLL multiplier N (N = 1−15) 12.5N 400N
PLL multiplier N = x.5
PLL multiplier N = x.25, x.75 12.5N 100N
†
Table 4−4. Multiply-By-N Clock Option Switching Characteristics
PARAMETER MIN TYP MAX UNIT
t
t
c(CI)
r(CI)
+ 0.3 V.
DD
MIN MAX UNIT
12.5N 200N
†
c(CI)/N
t
f(CI)
c(CO)
(see
ns
ns
April 1999 − Revised October 2008 SPRS096C
X2/CLKIN
CLKOUT
t
tp
Unstable
d(CI-CO)
t
c(CO)
t
w(COH)
Figure 4−4. External Multiply-by-One Clock Timing
t
f(CO)
t
w(COL)
t
r(CO)
35
Electrical Specifications
4.6 Memory and Parallel I/O Interface Timing
4.6.1 Memory Read
Table 4−5 and Table 4−6 assume testing over recommended operating conditions with MSTRB = 0 and
H = 0.5t
t
a(A)M
t
a(MSTRBL)
t
su(D)R
t
h(D)R
t
h(A-D)R
t
h(D)MSTRBH
†
Address, PS
, and DS timings are all included in timings referenced as address.
(see Figure 4−5).
c(CO)
Table 4−5. Memory Read Timing Requirements
Access time, read data access from address valid 2H−14 ns
Access time, read data access from MSTRB low 2H−14 ns
Setup time, read data before CLKOUT low 7 ns
Hold time, read data after CLKOUT low −2 ns
Hold time, read data after address invalid −3 ns
Hold time, read data after MSTRB high −3 ns
†
MIN MAX UNIT
Table 4−6. Memory Read Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(CLKL-A)
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
h(CLKL-A)R
t
h(CLKH-A)R
†
Address, PS
‡
In the case of a memory read preceded by a memory read
§
In the case of a memory read preceded by a memory write
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low 0 8 ns
Delay time, CLKOUT low to MSTRB high 0 8 ns
Hold time, address valid after CLKOUT low
Hold time, address valid after CLKOUT high
, and DS timings are all included in timings referenced as address.
†
‡
‡
§
0 8 ns
0 7 ns
0 5 ns
36
April 1999 − Revised October 2008SPRS096C
CLKOUT
A[19:0]
D[15:0]
MSTRB
t
d(CLKL-MSL)
t
a(MSTRBL)
t
d(CLKL-A)
t
su(D)R
t
a(A)M
t
h(CLKL-A)R
t
t
h(D)R
t
h(D)MSTRBH
t
d(CLKL-MSH)
Electrical Specifications
h(A-D)R
R/W
PS, DS
NOTE A: A[19:16] are always driven low during external data space accesses.
Figure 4−5. Memory Read (MSTRB = 0)
April 1999 − Revised October 2008 SPRS096C
37
Electrical Specifications
4.6.2 Memory Write
Table 4−7 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
Figure 4−6).
Table 4−7. Memory Write Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(CLKH-A)
t
d(CLKL-A)
t
d(CLKL-MSL)
t
d(CLKL-D)W
t
d(CLKL-MSH)
t
d(CLKH-RWL)
t
d(CLKH-RWH)
t
d(RWL-MSTRBL)
t
h(A)W
t
h(D)MSH
t
w(SL)MS
t
su(A)W
t
su(D)MSH
t
en(D−RWL)
t
dis(RWH−D)
†
Address, PS
‡
In the case of a memory write preceded by a memory write
§
In the case of a memory write preceded by an I/O cycle
Delay time, CLKOUT high to address valid
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low 0 8 ns
Delay time, CLKOUT low to data v alid 0 17 ns
Delay time, CLKOUT low to MSTRB high 0 8 ns
Delay time, CLKOUT high to R/W low −1 5 ns
Delay time, CLKOUT high to R/W high −2 5 ns
Delay time, R/W low to MSTRB low H − 4 H + 2 ns
Hold time, address valid after CLKOUT high
Hold time, write data valid after MSTRB high H−3 H+14 ns
Pulse duration, MSTRB low 2H−5 ns
Setup time, address valid before MSTRB low 2H−4 ns
Setup time, write data valid before MSTRB high 2H−14 2H+5 ns
Enable time, data bus driven after R/W low H−5 ns
Disable time, R/W high to data bus high impedance 0 ns
, and DS timings are all included in timings referenced as address.
(see
c(CO)
†
‡
§
‡
0 5 ns
0 8 ns
0 5 ns
38
April 1999 − Revised October 2008SPRS096C
CLKOUT
A[19:0]
D[15:0]
MSTRB
R/W
t
d(CLKL-A)
t
en(D-RWL)
t
su(A)W
t
d(CLKH-RWL)
t
d(CLKL-D)W
t
su(D)MSH
t
d(CLKL-MSL)
t
w(SL)MS
t
d(RWL-MSTRBL)
t
h(A)W
Electrical Specifications
t
d(CLKH-A)
t
h(D)MSH
t
t
d(CLKL-MSH)
dis(RWH-D)
t
d(CLKH-RWH)
PS, DS
NOTE A: A[19:16] are always driven low during external data space accesses.
Figure 4−6. Memory Write (MSTRB = 0)
April 1999 − Revised October 2008 SPRS096C
39
Electrical Specifications
4.6.3 I/O Read
Table 4−8 and Table 4−9 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5t
t
a(A)IO
t
a(ISTRBL)IO
t
su(D)IOR
t
h(D)IOR
t
h(ISTRBH-D)R
†
Address and IS
t
d(CLKL-A)
t
d(CLKH-ISTRBL)
t
d(CLKH-ISTRBH)
t
h(A)IOR
†
Address and IS
c(CO)
Access time, read data access from address valid
Access time, read data access from IOSTRB low 3H−17 ns
Setup time, read data before CLKOUT high 9 ns
Hold time, read data after CLKOUT high −1 ns
Hold time, read data after IOSTRB high −3 ns
timings are included in timings referenced as address.
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low −2 5 ns
Delay time, CLKOUT high to IOSTRB high −2 5 ns
Hold time, address after CLKOUT low
timings are included in timings referenced as address.
(see Figure 4−7).
Table 4−8. I/O Read Timing Requirements
Table 4−9. I/O Read Switching Characteristics
MIN MAX UNIT
†
PARAMETER MIN MAX UNIT
†
†
3H−17 ns
0 8 ns
0 8 ns
CLKOUT
A[19:0]
D[15:0]
IOSTRB
R/W
t
d(CLKL-A)
t
a(A)IO
t
a(ISTRBL)IO
t
d(CLKH-ISTRBL)
IS
NOTE A: A[19:16] are always driven low during I/O accesses.
t
su(D)IOR
t
t
h(D)IOR
t
h(ISTRBH-D)R
d(CLKH-ISTRBH)
t
h(A)IOR
40
Figure 4−7. Parallel I/O Port Read (IOSTRB = 0)
April 1999 − Revised October 2008SPRS096C
4.6.4 I/O Write
Electrical Specifications
Table 4−10 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
Figure 4−8).
t
d(CLKL-A)
t
d(CLKH-ISTRBL)
t
d(CLKH-D)IOW
t
d(CLKH-ISTRBH)
t
d(CLKL-RWL)
t
d(CLKL-RWH)
t
h(A)IOW
t
h(D)IOW
t
su(D)IOSTRBH
t
su(A)IOSTRBL
†
Address and IS
CLKOUT
A[19:0]
Table 4−10. I/O Write Switching Characteristics
PARAMETER MIN MAX UNIT
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low −2 5 ns
Delay time, CLKOUT high to write data valid H−5 H+14 ns
Delay time, CLKOUT high to IOSTRB high −2 5 ns
Delay time, CLKOUT low to R/W low 0 8 ns
Delay time, CLKOUT low to R/W high 0 8 ns
Hold time, address valid after CLKOUT low
Hold time, write data after IOSTRB high H−3 H+11 ns
Setup time, write data before IOSTRB high H−11 H+1 ns
Setup time, address valid before IOSTRB low
timings are included in timings referenced as address.
t
d(CLKL-A)
†
†
†
t
su(A)IOSTRBL
t
h(A)IOW
H−2 H+2 ns
c(CO)
0 8 ns
0 8 ns
(see
t
d(CLKH-D)IOW
D[15:0]
t
d(CLKH-ISTRBL)
t
d(CLKH-ISTRBH)
IOSTRB
t
d(CLKL-RWL)
R/W
IS
NOTE A: A[19:16] are always driven low during I/O accesses.
Figure 4−8. Parallel I/O Port Write (IOSTRB = 0)
t
h(D)IOW
t
su(D)IOSTRBH
t
d(CLKL-RWH)
April 1999 − Revised October 2008 SPRS096C
41
Electrical Specifications
4.7 Ready Timing for Externally Generated Wait States
Table 4−11 and Table 4−12 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 4−9 through Figure 4−12).
Table 4−11. Ready Timing Requirements for Externally Generated Wait States
t
su(RDY)
t
h(RDY)
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Setup time, READY before CLKOUT low 7 ns
Hold time, READY after CLKOUT low −2 ns
Valid time, READY after MSTRB low
Hold time, READY after MSTRB low
Valid time, READY after IOSTRB low
Hold time, READY after IOSTRB low
‡
‡
‡
‡
Table 4−12. Ready Switching Characteristics for Externally Generated Wait States
PARAMETER MIN MAX UNIT
t
d(MSCL)
t
d(MSCH)
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
CLKOUT
Delay time, CLKOUT low to MSC low 0 8 ns
Delay time, CLKOUT low to MSC high − 1 8 ns
†
MIN MAX UNIT
4H−11 ns
4H−4 ns
5H−11 ns
5H−3 ns
†
A[19:0]
t
su(RDY)
t
h(RDY)
READY
t
v(RDY)MSTRB
t
h(RDY)MSTRB
MSTRB
t
d(MSCH)
t
d(MSCL)
MSC
Wait States
Generated Internally
NOTE A: A[19:16] are always driven low during external data space accesses.
Figure 4−9. Memory Read With Externally Generated Wait States
Wait State
Generated
by READY
42
April 1999 − Revised October 2008SPRS096C
CLKOUT
A[19:0]
D[15:0]
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
d(MSCL)
t
h(RDY)
t
su(RDY)
t
h(RDY)MSTRB
t
d(MSCH)
Electrical Specifications
Wait States
Generated Internally
NOTE A: A[19:16] are always driven low during external data space accesses.
Figure 4−10. Memory Write With Externally Generated Wait States
CLKOUT
A[19:0]
t
h(RDY)
READY
t
v(RDY)IOSTRB
t
IOSTRB
MSC
NOTE A: A[19:16] are always driven low during I/O space accesses.
h(RDY)IOSTRB
t
d(MSCL)
Wait
States
Generated
Internally
Figure 4−11. I/O Read With Externally Generated Wait States
t
su(RDY)
t
d(MSCH)
Wait State Generated
by READY
Wait State Generated
by READY
April 1999 − Revised October 2008 SPRS096C
43
Electrical Specifications
CLKOUT
A[19:0]
D[15:0]
READY
t
v(RDY)IOSTRB
IOSTRB
MSC
NOTE A: A[19:16] are always driven low during I/O accesses.
t
h(RDY)IOSTRB
t
d(MSCL)
t
h(RDY)
t
Wait States
Generated
Internally
su(RDY)
t
d(MSCH)
Wait State Generated
by READY
Figure 4−12. I/O Write With Externally Generated Wait States
44
April 1999 − Revised October 2008SPRS096C
4.8 HOLD and HOLDA Timings
Electrical Specifications
Table 4−13 and Table 4−14 assume testing over recommended operating conditions and H = 0.5t
Figure 4−13).
t
w(HOLD)
t
su(HOLD)
Table 4−13. HOLD
Pulse duration, HOLD low 4H+7 ns
Setup time, HOLD low/high before CLKOUT low 7 ns
and HOLDA Timing Requirements
Table 4−14. HOLD and HOLDA Switching Characteristics
PARAMETER MIN MAX UNIT
t
dis(CLKL-A)
t
dis(CLKL-RW)
t
dis(CLKL-S)
t
en(CLKL-A)
t
en(CLKL-RW)
t
en(CLKL-S)
t
v(HOLDA)
t
w(HOLDA)
Disable time, address, PS, DS, IS high impedance from CLKOUT low 3 ns
Disable time, R/W high impedance from CLKOUT low 3 ns
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low 3 ns
Enable time, address, PS, DS, IS from CLKOUT low 2H+7 ns
Enable time, R/W enabled from CLKOUT low 2H+7 ns
Enable time, MSTRB, IOSTRB enabled from CLKOUT low 2H+7 ns
Valid time, HOLDA low after CLKOUT low
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration 2H ns
(see
c(CO)
MIN MAX UNIT
0 8 ns
0 8 ns
CLKOUT
HOLD
HOLDA
A[19:0]
PS
, DS, IS
D[15:0]
MSTRB
IOSTRB
R/W
t
su(HOLD)
t
w(HOLD)
t
su(HOLD)
t
v(HOLDA)
t
dis(CLKL-A)
t
dis(CLKL-RW)
t
dis(CLKL-S)
t
dis(CLKL-S)
t
w(HOLDA)
t
v(HOLDA)
t
en(CLKL-A)
t
en(CLKL-RW)
t
en(CLKL-S)
t
en(CLKL-S)
Figure 4−13. HOLD and HOLDA Timings (HM = 1)
April 1999 − Revised October 2008 SPRS096C
45
Electrical Specifications
MIN
MAX
UNIT
4.9 Reset, BIO, Interrupt, and MP/MC Timings
Table 4−15 assumes testing over recommended operating conditions and H = 0.5t
(see Figure 4−14,
c(CO)
Figure 4−15, and Figure 4−16).
Table 4−15. Reset, BIO
t
h(RS)
t
h(BIO)
t
h(INT)
t
h(MPMC)
t
w(RSL)
t
w(BIO)S
t
w(BIO)A
t
w(INTH)S
t
w(INTH)A
t
w(INTL)S
t
w(INTL)A
t
w(INTL)WKP
t
su(RS)
t
su(BIO)
t
su(INT)
t
su(MPMC)
†
The external interrupts (INT0
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
‡
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS
and lock-in of the PLL.
§
Note that RS
¶
Divide-by-two mode
Hold time, RS after CLKOUT low 0 ns
Hold time, BIO after CLKOUT low −2 ns
Hold time, INTn, NMI, after CLKOUT low
Hold time, MP/MC after CLKOUT low 0 ns
Pulse duration, RS low
Pulse duration, BIO low, synchronous 2H+4 ns
Pulse duration, BIO low, asynchronous 4H ns
Pulse duration, INTn, NMI high (synchronous) 2H−1 ns
Pulse duration, INTn, NMI high (asynchronous) 4H ns
Pulse duration, INTn, NMI low (synchronous) 2H+1 ns
Pulse duration, INTn, NMI low (asynchronous) 4H ns
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup 8 ns
Setup time, RS before X2/CLKIN low
Setup time, BIO before CLKOUT low 7 12 ns
Setup time, INTn, NMI, RS before CLKOUT low 8 12 ns
Setup time, MP/MC before CLKOUT low 10 ns
−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
may cause a change in clock frequency, therefore changing the value of H.
‡§
, Interrupt, and MP/MC Timing Requirements
†
¶
must be held low for at least 50 µs to ensure synchronization
−3 ns
4H+5 ns
5 ns
46
X2/CLKIN
RS
, INTn, NMI
CLKOUT
BIO
t
su(RS)
t
su(INT)
t
su(BIO)
t
w(BIO)S
Figure 4−14. Reset and BIO Timings
t
w(RSL)
t
h(BIO)
t
h(RS)
April 1999 − Revised October 2008SPRS096C
CLKOUT
Electrical Specifications
, NMI
INTn
CLKOUT
MP/MC
RS
t
su(INT)
t
w(INTH)A
t
su(INT)
Figure 4−15. Interrupt Timing
t
su(MPMC)
Figure 4−16. MP/MC Timing
t
w(INTL)A
t
h(INT)
t
h(MPMC)
April 1999 − Revised October 2008 SPRS096C
47
Electrical Specifications
4.10 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 4−16 assumes testing over recommended operating conditions and H = 0.5t
Table 4−16. Instruction Acquisition (IAQ
t
d(CLKL-IAQL)
t
d(CLKL-IAQH)
t
d(A)IAQ
t
d(CLKL-IACKL)
t
d(CLKL-IACKH)
t
d(A)IACK
t
h(A)IAQ
t
h(A)IACK
t
w(IAQL)
t
w(IACKL)
CLKOUT
Delay time, CLKOUT low to IAQ low 0 9 ns
Delay time, CLKOUT low to IAQ high 0 7 ns
Delay time, address valid to IAQ low 2 ns
Delay time, CLKOUT low to IACK low 0 9 ns
Delay time , CLKOUT low to IACK high 1 6 ns
Delay time, address valid to IACK low 2 ns
Hold time, IAQ high after address invalid −3 ns
Hold time, IACK high after address invalid −2 ns
Pulse duration, IAQ low 2H−2 ns
Pulse duration, IACK low 2H−1 ns
A[19:0]
) and Interrupt Acknowledge (IACK) Switching Characteristics
PARAMETER MIN MAX UNIT
(see Figure 4−17).
c(CO)
IAQ
IACK
MSTRB
t
d(CLKL-IAQL)
t
d(A)IAQ
t
w(IAQL)
t
d(CLKL-IACKL)
t
d(A)IACK
t
w(IACKL)
Figure 4−17. IAQ and IACK Timings
t
d(CLKL-IAQH)
t
h(A)IAQ
t
d(CLKL-IACKH)
t
h(A)IACK
48
April 1999 − Revised October 2008SPRS096C
4.11 External Flag (XF) and TOUT Timings
Electrical Specifications
Table 4−17 assumes testing over recommended operating conditions and H = 0.5t
Figure 4−19).
Table 4−17. External Flag (XF) and TOUT Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(XF)
t
d(TOUTH)
t
d(TOUTL)
t
w(TOUT)
Delay time, CLKOUT low to XF high −1 8
Delay time, CLKOUT low to XF low −1 8
Delay time, CLKOUT low to TOUT high 0 11 ns
Delay time, CLKOUT low to TOUT low 0 9 ns
Pulse duration, TOUT 2H−1 ns
CLKOUT
t
d(XF)
XF
Figure 4−18. XF Timing
(see Figure 4−18 and
c(CO)
ns
CLKOUT
TOUT
t
d(TOUTH)
t
w(TOUT)
Figure 4−19. TOUT Timing
t
d(TOUTL)
April 1999 − Revised October 2008 SPRS096C
49
Electrical Specifications
4.12 Multichannel Buffered Serial Port (McBSP) Timing
4.12.1 McBSP Transmit and Receive Timings
Table 4−18 and Table 4−19 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 4−20 and Figure 4−21).
Table 4−18. McBSP T
t
c(BCKRX)
t
w(BCKRX)
t
su(BFRH-BCKRL)
t
h(BCKRL-BFRH)
t
su(BDRV-BCKRL)
t
h(BCKRL-BDRV)
t
su(BFXH-BCKXL)
t
h(BCKXL-BFXH)
t
r(BCKRX)
t
f(BCKRX)
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Cycle time, BCLKR/X BCLKR/X ext 4H ns
Pulse duration, BCLKR/X high or BCLKR/X low BCLKR/X ext 2H−1 ns
Setup time, external BFSR high before BCLKR low
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
Hold time, BDR valid after BCLKR low
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
Rise time, BCLKR/X BCLKR/X ext 8 ns
Fall time, BCLKR/X BCLKR/X ext 8 ns
ransmit and Receive Timing Requirements
BCLKR int 20
BCLKR ext
BCLKR int −3
BCLKR ext
BCLKR int 17
BCLKR ext
BCLKR int 0
BCLKR ext
BCLKX int 20
BCLKX ext
BCLKX int −4
BCLKX ext
†
MIN MAX UNIT
0
4
0
8
0
5
ns
ns
ns
ns
ns
ns
50
April 1999 − Revised October 2008SPRS096C
Electrical Specifications
Disable time, BCLKX high to BDX high impedance following last data
)
Disable time, BCLKX high to BDX high impedance following last data
§
Table 4−19. McBSP Transmit and Receive Switching Characteristics
PARAMETER MIN MAX UNIT
t
c(BCKRX)
t
w(BCKRXH)
t
w(BCKRXL)
t
d(BCKRH-BFRV)
t
d(BCKXH-BFXV)
t
dis(BCKXH-BDXHZ
t
d(BCKXH-BDXV)
t
d(BFXH-BDXV)
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡
T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§
The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320UC5402.
¶
Minimum delay times also represent minimum output hold times.
Cycle time, BCLKR/X BCLKR/X int 4H ns
Pulse duration, BCLKR/X high BCLKR/X int D − 3‡D + 2‡ns
Pulse duration, BCLKR/X low BCLKR/X int C − 3‡C + 2‡ns
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
bit of transfer
Delay time, BCLKX high to BDX valid
Delay time, BFSX high to BDX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
DXENA = 0
BCLKR int −3 6 ns
BCLKR ext
BCLKX int 0 6
BCLKX ext
BCLKX int 1 6
BCLKX ext
BCLKX int 0
BCLKX ext 5 19
BFSX int 1
BFSX ext 7 18
†
7 13 ns
5 19
7 13
¶
¶
6
2
ns
ns
ns
ns
April 1999 − Revised October 2008 SPRS096C
51
Electrical Specifications
BCLKR
t
d(BCKRH−BFRV)
BFSR (int)
BFSR (ext)
(RDATDLY=00b)
(RDATDLY=01b)
(RDATDLY=10b)
BDR
BDR
BDR
t
su(BFRH−BCKRL)
t
su(BDRV−BCKRL)
t
c(BCKRX)
t
w(BCKRXH)
t
w(BCKRXL)
t
d(BCKRH−BFRV)
t
h(BCKRL−BFRH)
t
h(BCKRL−BDRV)
t
su(BDRV−BCKRL)
t
su(BDRV−BCKRL)
Figure 4−20. McBSP Receive Timings
t
r(BCKRX)
t
h(BCKRL−BDRV)
t
r(BCKRX)
(n−4)(n−3)(n−2)Bit (n−1)
(n−3)(n−2)Bit (n−1)
t
h(BCKRL−BDRV)
(n−2)Bit (n−1)
BCLKX
BFSX (int)
BFSX (ext)
(XDATDLY=00b)
(XDATDLY=01b)
(XDATDLY=10b)
BDX
BDX
BDX
t
d(BCKXH−BFXV)
t
su(BFXH−BCKXL)
Bit 0
Bit 0
t
dis(BCKXH−BDXHZ)
t
c(BCKRX)
t
w(BCKRXH)
t
w(BCKRXL)
t
d(BCKXH−BFXV)
t
h(BCKXL−BFXH)
t
d(BFXH−BDXV)
Figure 4−21. McBSP Transmit Timings
t
r(BCKRX)
t
d(BCKXH−BDXV)
t
d(BCKXH−BDXV)
t
d(BCKXH−BDXV)
t
f(BCKRX)
(n−4)Bit (n−1) (n−3)(n−2)
(n−3)(n−2)Bit (n−1)
(n−2)Bit (n−1)Bit 0
52
April 1999 − Revised October 2008SPRS096C
4.12.2 McBSP General-Purpose I/O Timing
Table 4−20 and Table 4−21 assume testing over recommended operating conditions (see Figure 4−22).
Table 4−20. McBSP General-Purpose I/O Timing Requirements
t
su(BGPIO-COH)
t
h(COH-BGPIO)
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Setup time, BGPIOx input mode before CLKOUT high
Hold time, BGPIOx input mode after CLKOUT high
Table 4−21. McBSP General-Purpose I/O Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(COH-BGPIO)
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Delay time, CLKOUT high to BGPIOx output mode
†
†
‡
Electrical Specifications
MIN MAX UNIT
9 ns
0 ns
0 5 ns
t
su(BGPIO-COH)
CLKOUT
BGPIOx Input
BGPIOx Output
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
mode
mode
†
‡
t
d(COH-BGPIO)
t
h(COH-BGPIO)
Figure 4−22. McBSP General-Purpose I/O Timings
April 1999 − Revised October 2008 SPRS096C
53
Electrical Specifications
UNIT
PARAMETER
UNIT
4.12.3 McBSP as SPI Master or Slave Timing
Table 4−22 to Table 4−29 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 4−23, Figure 4−24, Figure 4−25, and Figure 4−26).
Table 4−22. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER SLAVE
MIN MAX MIN MAX
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
t
su(BFXL-BCKXH)
t
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Setup time, BDR valid before BCLKX low 16 − 12H ns
Hold time, BDR valid after BCLKX low 4 12H + 5 ns
Setup time, BFSX low before BCLKX high 10 ns
Cycle time, BCLKX 12H 32H ns
Table 4−23. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER
MIN MAX MIN MAX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
d(BCKXH-BDXV)
t
dis(BCKXL-BDXHZ)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
Hold time, BFSX low after BCLKX low
Delay time, BFSX low to BCLKX high
Delay time, BCLKX high to BDX valid −3 7 6H + 6 10H + 20 ns
Disable time, BDX high impedance following last data bit from
BCLKX low
Disable time, BDX high impedance following last data bit from
BFSX high
Delay time, BFSX low to BDX valid 4H −3 8H + 21 ns
§
¶
T − 4 T + 5 ns
C − 6 C + 4 ns
C − 2 C + 3 ns
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
‡
SLAVE
2H+ 8 6H + 21 ns
†
†
54
BCLKX
BFSX
BDX
BDR
t
LSB
t
h(BCKXL-BFXL)
t
dis(BFXH-BDXHZ)
t
dis(BCKXL-BDXHZ)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
t
su(BFXL-BCKXH)
t
su(BDRV-BCKXL)
MSB
t
d(BFXL-BCKXH)
t
d(BFXL-BDXV)
t
d(BCKXH-BDXV)
t
h(BCKXL-BDRV)
c(BCKX)
Figure 4−23. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
April 1999 − Revised October 2008SPRS096C
Electrical Specifications
UNIT
PARAMETER
UNIT
Table 4−24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
†
MASTER SLAVE
MIN MAX MIN MAX
t
su(BDRV-BCKXH)
t
h(BCKXH-BDRV)
t
su(BFXL-BCKXH)
t
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
Setup time, BDR valid before BCLKX high 16 − 12H ns
Hold time, BDR valid after BCLKX high 4 12H + 5 ns
Setup time, BFSX low before BCLKX high 10 ns
Cycle time, BCLKX 12H 32H ns
†
MASTER
‡
SLAVE
MIN MAX MIN MAX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
d(BCKXL-BDXV)
t
dis(BCKXL-BDXHZ)
t
d(BFXL-BDXV)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡
T = BCLKX period = (1 + CLKGDV) * 2H
Hold time, BFSX low after BCLKX low
Delay time, BFSX low to BCLKX high
Delay time, BCLKX low to BDX valid −3 7 6H + 6 10H + 20 ns
Disable time, BDX high impedance following last data bit from
BCLKX low
Delay time, BFSX low to BDX valid D − 2 D + 4 4H −3 8H + 21 ns
§
¶
C −4 C + 5 ns
T − 6 T + 4 ns
0 6 6H +7 10H + 21 ns
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
BCLKX
BFSX
t
dis(BCKXL-BDXHZ)
BDX
BDR
Figure 4−24. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
t
LSB
t
h(BCKXL-BFXL)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
su(BFXL-BCKXH)
t
d(BFXL-BDXV)
t
su(BDRV-BCKXH)
MSB
t
d(BFXL-BCKXH)
t
d(BCKXL-BDXV)
t
h(BCKXH-BDRV)
t
c(BCKX)
April 1999 − Revised October 2008 SPRS096C
55
Electrical Specifications
UNIT
PARAMETER
UNIT
Table 4−26. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
†
MASTER SLAVE
MIN MAX MIN MAX
t
su(BDRV-BCKXH)
t
h(BCKXH-BDRV)
t
su(BFXL-BCKXL)
t
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−27. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
Setup time, BDR valid before BCLKX high 16 − 12H ns
Hold time, BDR valid after BCLKX high 4 12H + 5 ns
Setup time, BFSX low before BCLKX low 10 ns
Cycle time, BCLKX 12H 32H ns
†
MASTER
‡
SLAVE
MIN MAX MIN MAX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
t
d(BCKXL-BDXV)
t
dis(BCKXH-BDXHZ)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡
T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
Hold time, BFSX low after BCLKX high
Delay time, BFSX low to BCLKX low
Delay time, BCLKX low to BDX valid − 3 7 6H + 6 10H + 20 ns
Disable time, BDX high impedance following last data bit from
BCLKX high
Disable time, BDX high impedance following last data bit from
BFSX high
Delay time, BFSX low to BDX valid 4H − 3 8H + 21 ns
§
¶
T − 4 T + 5 ns
D − 6 D + 4 ns
D − 2 D + 3 ns
2H + 7 6H + 21 ns
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
56
BCLKX
BFSX
BDX
BDR
LSB
t
h(BCKXH-BFXL)
t
dis(BFXH-BDXHZ)
t
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
t
su(BFXL-BCKXL)
dis(BCKXH-BDXHZ)
t
su(BDRV-BCKXH)
MSB
t
d(BFXL-BCKXL)
t
d(BFXL-BDXV)
t
d(BCKXL-BDXV)
t
h(BCKXH-BDRV)
t
c(BCKX)
Figure 4−25. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
April 1999 − Revised October 2008SPRS096C
Electrical Specifications
UNIT
PARAMETER
UNIT
Table 4−28. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
†
MASTER SLAVE
MIN MAX MIN MAX
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
t
su(BFXL-BCKXL)
t
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−29. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
Setup time, BDR valid before BCLKX low 16 − 12H ns
Hold time, BDR valid after BCLKX low 4 12H + 5 ns
Setup time, BFSX low before BCLKX low 10 ns
Cycle time, BCLKX 12H 32H ns
†
MASTER
‡
SLAVE
MIN MAX MIN MAX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
t
d(BCKXH-BDXV)
t
dis(BCKXH-BDXHZ)
t
d(BFXL-BDXV)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡
T = BCLKX period = (1 + CLKGDV) * 2H
Hold time, BFSX low after BCLKX high
Delay time, BFSX low to BCLKX low
Delay time, BCLKX high to BDX valid − 3 7 6H + 6 10H + 20 ns
Disable time, BDX high impedance following last data bit from
BCLKX high
Delay time, BFSX low to BDX valid C − 2 C + 4 4H − 3 8H + 21 ns
§
¶
D − 4 D + 5 ns
T − 6 T + 4 ns
0 6 6H +7 10H + 21 ns
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
BCLKX
BFSX
t
dis(BCKXH-BDXHZ)
BDX
BDR
Figure 4−26. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
t
LSB
t
h(BCKXH-BFXL)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
su(BFXL-BCKXL)
t
d(BFXL-BDXV)
t
su(BDRV-BCKXL)
MSB
t
d(BFXL-BCKXL)
t
d(BCKXH-BDXV)
t
h(BCKXL-BDRV)
t
c(BCKX)
April 1999 − Revised October 2008 SPRS096C
57
Electrical Specifications
4.13 Host-Port Interface Timing (HPI8)
Table 4−30 and Table 4−31 assume testing over recommended operating conditions and H = 0.5t
Figure 4−27 through Figure 4−30). In the following tables, DS refers to the logical OR of HCS
HDS2
. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0, HCNTL1,
and HR/W
. GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
NOTE: During all cycles, DS should not be driven high to complete the cycle until HRDY is
high. In the case of a read cycle, HDx should also be valid before rising DS.
Table 4−30. HPI8 Mode Timing Requirements
t
su(HBV-DSL)
t
h(DSL-HBV)
t
su(HSL-DSL)
t
w(DSL)
t
w(DSH)
t
su(HDV-DSH)
t
h(DSH-HDV)W
t
su(GPIO-COH)
t
h(GPIO-COH)
Setup time, HBIL valid before DS low 5 ns
Hold time, HBIL valid after DS low 6 ns
Setup time, HAS low before DS low 5 ns
Pulse duration, DS low 20 ns
Pulse duration, DS high 10 ns
Setup time, HDx valid before DS high, HPI write 12 ns
Hold time, HDx valid after DS high, HPI write 8 ns
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input 9 ns
Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input −3 ns
(see
c(CO)
, HDS1, and
MIN MAX UNIT
58
April 1999 − Revised October 2008SPRS096C
Electrical Specifications
t
Delay time, DS low to HDx valid for
ns
ns
Table 4−31. HPI8 Mode Switching Characteristics
PARAMETER MIN MAX UNIT
t
en(DSL-HD)
d(DSL-HDV1)
t
d(DSL-HDV2)
t
h(DSH-HDV)R
t
v(HYH-HDV)
t
d(DSH-HYL)
t
d(DSH-HYH)
t
d(HCS-HRDY)
t
d(COH-HYH
t
d(COH-HTX)
t
d(COH-GPIO)
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
†
DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
2. This timing applies to the first byte of an access, when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes
Enable time, HD driven from DS low 5 21 ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
t
w(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
t
w(DSH)
Case 1c: Memory access when
DMAC is active in 32-bit mode and
Delay time, DS low to HDx valid for
first byte of an HPI read
Delay time, DS low to HDx valid for second byte of an HPI read 21 ns
Hold time, HDx valid after DS high, for a HPI read 5 9 ns
Valid time, HDx valid after HRDY high 12
Delay time, DS high to HRDY low (see Note 1) 21 ns
Delay time, DS high to HRDY high
Delay time, HCS low/high to HRDY low/high
) Delay time, CLKOUT high to HRDY high 5 ns
Delay time, CLKOUT high to HINT change 5 ns
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output.
to the HPIC occur asynchronously, and do not cause HRDY to be deasserted.
t
w(DSH)
Case 1d: Memory access when
DMAC is active in 32-bit mode and
t
w(DSH)
Case 2a: Memory accesses when
DMAC is inactive and t
Case 2b: Memory accesses when
DMAC is inactive and t
Case 3: Register accesses 21
Case 1a: Memory accesses when
DMAC is active in 16-bit mode
Case 1b: Memory accesses when
DMAC is active in 32-bit mode
Case 2: Memory accesses when
DMAC is inactive
Case 3: Write accesses to HPIC
register (see Note 2)
< 18H
≥ 18H
< 26H
≥ 26H
†
†
†
†
†
< 10H
w(DSH)
†
≥ 10H
w(DSH)
†
†
†
18H + 21 − t
26H + 21 − t
10H + 21 − t
w(DSH)
21
w(DSH)
21
w(DSH)
21
18H + 21 ns
26H + 21
10H + 21
6H + 21
19 ns
9 ns
ns
April 1999 − Revised October 2008 SPRS096C
59
Electrical Specifications
H
Second Byte First Byte Second Byte
HAS
t
su(HBV-DSL)
†
HAD
Valid
t
su(HSL-DSL)
t
h(DSL-HBV)
Valid
HBIL
HCS
HDS
HRDY
HD READ
t
su(HBV-DSL)
t
en(DSL-HD)
‡
t
d(DSH-HYL)
t
d(DSL-HDV2)
Valid
t
w(DSH)
t
h(DSH-HDV)R
t
h(DSL-HBV)
t
d(DSH-HYH)
t
d(DSL-HDV1)
‡
t
w(DSL)
Valid Valid
t
su(HDV-DSH)
D WRITE
CLKOUT
†
HAD refers to HCNTL0, HCNTL1, and HR/W
‡
When HAS
is not used (HAS always high)
Valid
t
h(DSH-HDV)W
.
t
v(HYH-HDV)
t
d(COH-HYH)
Valid
Valid
Figure 4−27. Using HDS to Control Accesses (HCS Always Low)
60
April 1999 − Revised October 2008SPRS096C
Second Byte
First Byte
Second Byte
HCS
H
HDS
RDY
CLKOUT
HINT
t
d(HCS-HRDY)
Figure 4−28. Using HCS to Control Accesses
t
d(COH-HTX)
Electrical Specifications
Figure 4−29. HINT Timing
CLKOUT
t
su(GPIO-COH)
t
h(GPIO-COH)
GPIOx Input Mode
GPIOx Output Mode
†
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
†
t
d(COH-GPIO)
†
Figure 4−30. GPIOx† Timings
April 1999 − Revised October 2008 SPRS096C
61
Mechanical Data
5 Mechanical Data
5.1 Package Thermal Resistance Characteristics
Table 5−1 provides the estimated thermal resistance characteristics for the recommended package types
used on the TMS320UC5402 DSP.
Table 5−1. Thermal Resistance Characteristics
PARAMETER
R
ΘJA
R
ΘJC
5.2 Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
GGU
PACKAGE
38 56 °C/W
5 5 °C/W
PGE
PACKAGE
UNIT
62
April 1999 − Revised October 2008SPRS096C
PACKAGE OPTION ADDENDUM
www.ti.com 14-Sep-2009
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
TMS320UC5402GGU-80 ACTIVE BGA MI
Package
Drawing
Pins Package
Qty
Eco Plan
GGU 144 160 TBD SNPB Level-3-220C-168 HR
(2)
Lead/Ball Finish MSL Peak Temp
(3)
CROSTA
R
TMS320UC5402PGE-80 ACTIVE LQFP PGE 144 60 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TMS320UC5402ZGU-80 ACTIVE BGA MI
ZGU 144 160 TBD SNAGCU Level-3-220C-168 HR
CROSTA
R
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK
109
144
1,45
1,35
108
73
72
0,27
0,17
0,50
37
1
17,50 TYP
20,20
SQ
19,80
22,20
SQ
21,80
36
0,05 MIN
0,08
0,25
0,75
0,45
M
0,13 NOM
Gage Plane
0°–7°
1,60 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Seating Plane
0,08
4040147/C 10/96
1
MECHANICAL DATA
MPBG021C – DECEMBER 1996 – REVISED MA Y 2002
GGU (S–PBGA–N144) PLASTIC BALL GRID ARRAY
12,10
11,90
A1 Corner
SQ
N
M
L
K
J
H
G
F
E
D
C
B
A
9,60 TYP
0,80
0,80
0,95
0,85
0,55
0,45
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGAt configuration
0,08
1,40 MAX
0,45
0,35
1
2 4
Seating Plane
0,10
3
5
76 98 1110 1312
Bottom View
4073221-2/C 12/01
MicroStar BGA is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
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