Texas instruments TMS320UC5402 Data Manual

TMS320UC5402 Fixed-Point

Digital Signal Processor

Data Manual

Literature Number: SPRS096C

April 1999 − Revised October 2008

        
         
   !    
!   

Revision History

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS096B device-specific data
sheet to make it an SPRS096C revision.

Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date with the following changes.

PAGE(S)

NO.

5 Table 1−2, Signal Descriptions:

− Updated DESCRIPTION of TRST

− Added footnote about TRST

62 Section 5, Mechanical Data:

− Moved “Package Thermal Resistance Characteristics” section (Section 4.4 in SPRS096B) to this section

− Added Section 5.2, Packaging Information

− Mechanical drawings will be appended to this document via an automated process

ADDITIONS/CHANGES/DELETIONS

April 1999 − Revised October 2008 SPRS096C

iii

Revision History

iv

April 1999 − Revised October 2008SPRS096C

Contents

Contents

Section Page

1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Pin Assignments 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 Terminal Assignments for the GGU Package 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.2 Pin Assignments for the PGE Package 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Signal Descriptions 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Overview 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Memory 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 On-Chip Dual-Access RAM (DARAM) 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 On-Chip ROM With Bootloader 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Memory Map 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 Relocatable Interrupt Vector Table 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 Extended Program Memory 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 On-Chip Peripherals 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Software-Programmable Wait-State Generator 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Parallel I/O Ports 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Hardware Timer 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Clock Generator 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5 DMA Controller 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Memory-Mapped Registers 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 CPU Memory-Mapped Registers 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Peripheral Memory-Mapped Registers 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 McBSP Control Registers and Subaddresses 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 DMA Subbank Addressed Registers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Interrupts 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 IFR and IMR Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Documentation Support 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Electrical Specifications 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Absolute Maximum Ratings 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Recommended Operating Conditions 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Electrical Characteristics Over Recommended Operating Case Temperature Range

(Unless Otherwise Noted) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Timing Parameter Symbology 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Clock Options 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.1 Internal Oscillator With External Crystal 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.2 Divide-By-Two Clock Option (PLL disabled) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.3 Multiply-By-N Clock Option (PLL Enabled) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Memory and Parallel I/O Interface Timing 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.1 Memory Read 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.2 Memory Write 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.3 I/O Read 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.4 I/O Write 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

April 1999 − Revised October 2008 SPRS096C

v

Contents

Section Page

4.7 Ready Timing for Externally Generated Wait States 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 HOLD

and HOLDA Timings 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Reset, BIO, Interrupt, and MP/MC Timings 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings 48. . . . . . . . . . . . . . . . .

4.11 External Flag (XF) and TOUT Timings 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 Multichannel Buffered Serial Port (McBSP) Timing 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12.1 McBSP Transmit and Receive Timings 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12.2 McBSP General-Purpose I/O Timing 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12.3 McBSP as SPI Master or Slave Timing 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.13 Host-Port Interface Timing (HPI8) 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Mechanical Data 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Package Thermal Resistance Characteristics 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Packaging Information 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

April 1999 − Revised October 2008SPRS096C

Figures

List of Figures

Figure Page

1−1 144-Terminal GGU Ball Grid Array (Bottom View) 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2 144-Pin PGE Low-Profile Quad Flatpack (Top View) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 Block Diagram of the TMS320UC5402 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 TMS320UC5402 Memory Map 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 Extended Program Memory 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] 13. . .

2−6 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] 14. . . . . . . . . . . . . . . . . . . . . . .

2−7 Bank-Switching Control Register (BSCR) [MMR Address 0029h] 15. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 UC5402 HPI8 Memory Map 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 UC5402 DMA Memory Map 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 IFR and IMR Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 1.8-V Test Load Circuit 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Internal Oscillator With External Crystal 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 External Divide-by-Two Clock Timing 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 External Multiply-by-One Clock Timing 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 Memory Read (MSTRB = 0) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Memory Write (MSTRB = 0) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Parallel I/O Port Read (IOSTRB = 0) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 Parallel I/O Port Write (IOSTRB = 0) 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−9 Memory Read With Externally Generated Wait States 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−10 Memory Write With Externally Generated Wait States 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−11 I/O Read With Externally Generated Wait States 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−12 I/O Write With Externally Generated Wait States 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−13 HOLD and HOLDA Timings (HM = 1) 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−14 Reset and BIO Timings 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−15 Interrupt Timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−16 MP/MC Timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−17 IAQ and IACK Timings 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−18 XF Timing 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−19 TOUT Timing 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−20 McBSP Receive Timings 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−21 McBSP Transmit Timings 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−22 McBSP General-Purpose I/O Timings 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−23 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 54. . . . . . . . . . . . . . . . . . . . . . . .

4−24 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 55. . . . . . . . . . . . . . . . . . . . . . . .

4−25 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 56. . . . . . . . . . . . . . . . . . . . . . . .

4−26 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 57. . . . . . . . . . . . . . . . . . . . . . . .

April 1999 − Revised October 2008 SPRS096C

vii

Figures

Figure Page

4−27 Using HDS

to Control Accesses (HCS Always Low) 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−28 Using HCS to Control Accesses 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−29 HINT Timing 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−30 GPIOx Timings 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

April 1999 − Revised October 2008SPRS096C

Tables

List of Tables

Table Page

1−1 Terminal Assignments (144-Terminal GGU Package) 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2 Signal Descriptions 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 Standard On-Chip ROM Layout 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Software Wait-State Register (SWWSR) Bit Fields 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Software Wait-State Control Register (SWCR) Bit Fields 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 Bank-Switching Control Register (BSCR) Bit Fields 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Clock Mode Settings at Reset 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 DMA Interrupts 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 DMA Synchronization Events 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 CPU Memory-Mapped Registers 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 Peripheral Memory-Mapped Registers 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 McBSP Control Registers and Subaddresses 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 DMA Subbank Addressed Registers 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−13 Interrupt Locations and Priorities 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−14 IFR and IMR Register Bit Fields 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Divide-By-2 and Divide-by-4 Clock Options Timing Requirements 34. . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics 34. . . . . . . . . . . . . . . . . . . . . . .

4−3 Multiply-By-N Clock Option Timing Requirements 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 Multiply-By-N Clock Option Switching Characteristics 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 Memory Read Timing Requirements 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Memory Read Switching Characteristics 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Memory Write Switching Characteristics 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 I/O Read Timing Requirements 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−9 I/O Read Switching Characteristics 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−10 I/O Write Switching Characteristics 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−11 Ready Timing Requirements for Externally Generated Wait States 42. . . . . . . . . . . . . . . . . . . . . . . . .

4−12 Ready Switching Characteristics for Externally Generated Wait States 42. . . . . . . . . . . . . . . . . . . . . .

4−13 HOLD and HOLDA Timing Requirements 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−14 HOLD and HOLDA Switching Characteristics 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−15 Reset, BIO, Interrupt, and MP/MC Timing Requirements 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−16 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics 48. . . .

4−17 External Flag (XF) and TOUT Switching Characteristics 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−18 McBSP Transmit and Receive Timing Requirements 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−19 McBSP Transmit and Receive Switching Characteristics 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−20 McBSP General-Purpose I/O Timing Requirements 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−21 McBSP General-Purpose I/O Switching Characteristics 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−22 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 54. . . . . . . . . .

4−23 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 54. . . . . .

4−24 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 55. . . . . . . . . .

4−25 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 55. . . . . . .

4−26 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 56. . . . . . . . . .

4−27 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 56. . . . . .

4−28 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 57. . . . . . . . . .

4−29 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 57. . . . . . .

April 1999 − Revised October 2008 SPRS096C

ix

Tables

Table Page

4−30 HPI8 Mode Timing Requirements 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−31 HPI8 Mode Switching Characteristics 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 Thermal Resistance Characteristics 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x

April 1999 − Revised October 2008SPRS096C

1 Introduction

This section describes the main features of the TMS320UC5402, lists the pin assignments, and describes the
function of each pin. This data manual also provides a detailed description section, electrical specifications,
parameter measurement information, and mechanical data about the available packaging.

NOTE: This data manual is designed to be used in conjunction with theTMS320C54x DSP Functional
Overview (literature number SPRU307).

1.1 Features

D

Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus

D 40-Bit Arithmetic Logic Unit (ALU),

Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators

D 17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation

D Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi
Operator

D Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle

D Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)

D Data Bus With a Bus-Holder Feature
D Extended Addressing Mode for 1M × 16-Bit

Maximum Addressable External Program
Space

D 4K x 16-Bit On-Chip ROM
D 16K x 16-Bit On-Chip Dual-Access RAM
D Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

D Block-Memory-Move Instructions for

Efficient Program and Data Management

D Instructions With a 32-Bit-Long Word

Operand

D Instructions With Two- or Three-Operand

Reads

D Arithmetic Instructions With Parallel Store

and Parallel Load

TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

D Conditional Store Instructions
D Fast Return From Interrupt
D On-Chip Peripherals

− Software-Programmable Wait-State
Generator and Programmable Bank
Switching

− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source

− Two Multichannel Buffered Serial Ports
(McBSPs)

− Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)

− Two 16-Bit Timers

− Six-Channel Direct Memory Access
(DMA) Controller

D Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With
Power-Down Modes

D CLKOUT Off Control to Disable CLKOUT
D On-Chip Scan-Based Emulation Logic,

IEEE Std 1149.1
Logic

D 12.5-ns Single-Cycle Fixed-Point

Instruction Execution Time (80 MIPS)

D 1.8-V Core Power Supply
D 1.8-V to 3.6-V I/O Power Supply Enables

Operation With a Single 1.8-V Supply or
with Dual Supplies

D Available in a 144-Pin Low-Profile Quad

Flatpack (LQFP) (PGE Suffix)

D Available in a 144-Ball MicroStar Ball Grid

Array (BGA) (GGU Suffix)

Introduction

†

(JTAG) Boundary Scan

April 1999 − Revised October 2008 SPRS096C

1

Introduction

1.2 Description

The TMS320UC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the UC5402 unless
otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low
power consumption and the flexibility to support various system voltage configurations. The wide range of I/O
voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage
systems. This feature eliminates the need for external level-shifting and reduces power consumption in
emerging sub-3V systems.

Texas Instrument (TI) DSPs do not require specific power sequencing between the core supply and the I/O
supply. However, systems should be designed to ensure that neither supply is powered up for extended
periods of time if the other supply is below the proper operating voltage. Excessive exposure to these
conditions can adversely affect the long-term reliability of the device.

System-level concerns such as bus contention may require supply sequencing to be implemented. In this
case, the core supply should be powered up at the same time as, or prior to, the I/O buffers and powered down
after the I/O buffers.

The UC5402 is based on an advanced modified Harvard architecture that has one program memory bus and
three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

1.3 Pin Assignments

Figure 1−1 illustrates the ball locations for the 144-terminal ball grid array (BGA) package and is used in
conjunction with Table 1−1 to locate signal names and ball grid numbers. DV
I/O pins while CV

is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core

DD

CPU.

1.3.1 Terminal Assignments for the GGU Package

is the power supply for the

DD

12

3456781012 1113 9

A
B
C
D
E
F
G
H
J
K
L
M
N

Figure 1−1. 144-Terminal GGU Ball Grid Array (Bottom View)

2

April 1999 − Revised October 2008SPRS096C

Table 1−1. Terminal Assignments (144-Terminal GGU Package)†

Introduction

SIGNAL

NAME

NC A1 NC N13 NC N1 A19 A13
NC B1 NC M13 NC N2 NC A12

V

SS

DV

DD

A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10

HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10

A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10
A12 D1 NC K13 BFSR1 N4 D9 A10
A13 E4 HD2 J10 BDR0 K5 D10 D9
A14 E3 TOUT0 J11 HCNTL1 L5 D11 C9
A15 E2 EMU0 J12 BDR1 M5 D12 B9

NC E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9
HAS F4 TDO H10 BCLKX1 K6 D13 D8
V

SS

NC F2 TRST H12 HINT/TOUT1 M6 D15 B8

CV

DD

HCS G2 TMS G12 BFSX0 M7 CV

HR/W G1 NC G13 BFSX1 N7 NC A7

READY G3 CV

PS G4 HPIENA G10 DV

DS H1 V

IS H2 CLKOUT F12 HD0 M8 DV

R/W H3 HD3 F11 BDX0 L8 A0 C6

MSTRB H4 X1 F10 BDX1 K8 A1 D6

IOSTRB J1 X2/CLKIN

MSC J2 RS E12 HBIL M9 A3 B5

XF J3 D0 E11 NMI L9 HD6 C5

HOLDA J4 D1 E10 INT0 K9 A4 D5

IAQ K1 D2 D13 INT1 N10 A5 A4

HOLD K2 D3 D12 INT2 M10 A6 B4

BIO K3 D4 D11 INT3 L10 A7 C4

MP/MC L1 D5 C13 CV

DV

DD

V

SS

NC M1 A17 B13 NC N12 NC A2

NC M2 A18 B12 NC M12 NC B2

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core
CPU.

‡

If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.

BGA BALL #

C2 DV
C1 V

F3 TDI H11 V

F1 TCK H13 CV

L2 A16 C12 HD1 M11 A9 B3
L3 V

SIGNAL

NAME

DD

SS

DD

SS

SS

‡

BGA BALL #

L12 HCNTL0 M3 V
L13 V

G11 HRDY L7 HDS1 C7

F13 V

E13 IACK N9 A2 A5

C11 V

SIGNAL

NAME

SS

SS

DD

DD

SS

DD

SS

BGA BALL #

N3 DV

L6 D14 C8

N6 HD5 A8

K7 V
N8 HDS2 A6

N11 A8 A3

L11 CV

SIGNAL

NAME

SS

DD

DD

SS

DD

DD

BGA BALL #

B11
A11

B7

D7

B6

C3

April 1999 − Revised October 2008 SPRS096C

3

Introduction

1.3.2 Pin Assignments for the PGE Package

The TMS320UC5402PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in
Figure 1−2. DV
is the ground for both the I/O pins and the core CPU.

is the power supply for the I/O pins while CVDD is the power supply for the core CPU. V

DD

SS

NC
NC

V

SS

DV

DD

A10

HD7

A11
A12
A13
A14
A15

NC
HAS
V

SS

NC

CV

DD

HCS

HR/W

READY

PS

DS

R/W

MSTRB

IOSTRB

MSC

XF

HOLDA

IAQ

HOLD

BIO

MP/MC

DV

DD
V

SS

NC

NC

DD

A9

NC

CV

NC

144

143

142

141A8140A7139A6138A5137A4136

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

IS

23
24
25
26
27
28
29
30
31
32
33
34
35
36

373839404142434445464748495051525354555657585960616263646566676869

HD6

135A3134A2133A1132A0131DV130

DD

HDS2SSV

129

128

NC

HDS1

127

126

DD

CV

125

HD5

124

D15

123

D14

122

D13

121

HD4

120

D12

119

D11

118

D10

117D9116D8115D7114D6113

DD

V

DV

112

707172

SS

111

NC

110

A19

109

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

A18
A17
V

SS

A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
V

SS

HPIENA
CV

DD

NC
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT0
HD2
NC
CLKMD3
CLKMD2
CLKMD1
V

SS

DV

DD

NC
NC

NC

NC

V

HCNTL0SSBCLKR0

BFSR0

BCLKR1

BDR0

BFSR1

HCNTL1

BDR1

BCLKX0

SS

V

BCLKX1

HINT/TOUT1

NOTE A: NC = No connection. These pins should be left unconnected.

Figure 1−2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)

4

DD

CV

BFSX0

BFSX1

DD

HRDY

DV

SS

HD0

V

BDX0

IACK

BDX1

HBIL

NMI

INT0

INT1

INT2

INT3

CV

DD

HD1

SS

NC

NC

V

April 1999 − Revised October 2008SPRS096C

1.4 Signal Descriptions

TERMINAL

TYPE

†

DESCRIPTION

Table 1−2 lists each signal, function, and operating mode(s) grouped by function. See Section 1.3 for exact
pin locations based on package type.

Table 1−2. Signal Descriptions

TERMINAL

NAME

DATA SIGNALS

A19 (MSB)
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)

D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)

IACK

INT0
INT1
INT2
INT3

NMI
†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.

§

Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST
a buffer is recommended to ensure the VIL and VIH specifications are met.

O/Z Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen

address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper
four address pins (A16 to A19) are only used to address external program space. These pins are placed in the
high-impedance state when the hold mode is enabled, or when EMU1/OFF

I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer

data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the
high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when EMU1/OFF

The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus
holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven
by the UC5402, the bus holders keep the pins at the previous logic level. The data bus holders on the UC5402
are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15−A0. IACK

O/Z

is low.

External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register (IMR) and

I

the interrupt mode bit. INT0

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM bit (in the ST1

I

register) or the IMR. When NMI

−INT3 can be polled and reset by way of the interrupt flag register (IFR).

is low.

also goes into the high-impedance state when EMU1/OFF

is activated, the processor traps to the appropriate vector location.

Introduction

is low.

pin is connected to multiple DSPs,

April 1999 − Revised October 2008 SPRS096C

5

Introduction

Table 1−2. Signal Descriptions (Continued)

TERMINAL

TERMINAL

NAME

NAME

RS

MP/MC I

BIO I

XF O/Z

DS
PS
IS

MSTRB O/Z

READY I

R/W O/Z

IOSTRB O/Z

HOLD I

HOLDA O/Z

MSC O/Z

IAQ O/Z
†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.

§

Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST
a buffer is recommended to ensure the VIL and VIH specifications are met.

†

†

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS

I

memory. RS
Microprocessor/microcomputer mode select. If active (low) at reset, microcomputer mode is selected, and the

internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC
that is selected at reset.

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. For the XC instruction, the BIO
pipeline; all other instructions sample BIO

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when EMU1/OFF
is low, and is set high at reset.

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing
a particular external memory space. Active period corresponds to valid address information. DS

O/Z

placed in the high-impedance state in the hold mode; the signals also go into the high-impedance state when
EMU1/OFF is low.

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB
high-impedance state when EMU1/OFF

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W
high-impedance state in hold mode; it also goes into the high-impedance state when EMU1/OFF

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB
state when EMU1/OFF

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the
C54x, these lines go into the high-impedance state.

Hold acknowledge. HOLDA indicates that the UC5402 is in a hold state and that the address, data, and control
lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices.
HOLDA

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC
high at the beginning of the last software wait state. If connected to the READY input, MSC
wait state after the last internal wait state is completed. MSC
EMU1/OFF

Instruction acquisition signal. IAQ is asserted (active-low) when there is an instruction address on the address
bus. IAQ

affects various registers and status bits.

MULTIPROCESSING SIGNALS

MEMORY CONTROL SIGNALS

is placed in the high-impedance state in the hold mode; it also goes into the high-impedance

is low.

also goes into the high-impedance state when EMU1/OFF is low.

is low.

goes into the high-impedance state when EMU1/OFF is low.

is brought to a high level, execution begins at location 0FF80h of program

is placed in the high-impedance state in the hold mode; it also goes into the

pin goes active at the beginning of the first software wait state and goes inactive

DESCRIPTIONTYPE

DESCRIPTIONTYPE

bit of the processor mode status (PMST) register can override the mode

during the read phase of the pipeline.

is low.

condition is sampled during the decode phase of the

also goes into the high-impedance state when

, PS, and IS are

is placed in the

is low.

forces one external

pin is connected to multiple DSPs,

C54x is a trademark of Texas Instruments.

6

April 1999 − Revised October 2008SPRS096C

Table 1−2. Signal Descriptions (Continued)

TERMINAL

TERMINAL

NAME

NAME

CLKOUT O/Z

CLKMD1
CLKMD2
CLKMD3

X2/CLKIN
X1 O

TOUT0 O/Z

HINT/TOUT1 O/Z

BCLKR0
BCLKR1

BDR0
BDR1

BFSR0
BFSR1

BCLKX0
BCLKX1

BDX0
BDX1

BFSX0
BFSX1

HD0−HD7 I/O/Z

HCNTL0
HCNTL1

HBIL I

HCS I
HDS1

HDS2
†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.

§

Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST
a buffer is recommended to ensure the VIL and VIH specifications are met.

‡

†

†

PLL/TIMER SIGNALS

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF
is low.

Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The
logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized

I

to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select
signals have no effect until the device is reset again.

I Clock/PLL input. If the internal oscillator is not being used, the X2/CLKIN functions as the clock input.

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when EMU1/OFF

Timer0 output. T OUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF

Timer1 output. TOUT1 signals a pulse when the on-chip timer 1 counts down past zero. The pulse is one
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT
the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

I/O/Z Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

I Serial data receive input

I/O/Z Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as

I/O/Z

I/O/Z

an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when
EMU1/OFF

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is

O/Z

asserted, or when EMU1/OFF
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX

can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the
high-impedance state when EMU1/OFF is low.

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0−HD7 is placed in the
high-impedance state when not outputting data or when EMU1/OFF
holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not
being driven by the UC5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders
are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have

I

internal pullup resistors that are only enabled when HPIENA = 0.
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup

resistor that is only enabled when HPIENA = 0.
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input

has an internal pullup resistor that is only enabled when HPIENA = 0.
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs

I

have internal pullup resistors that are only enabled when HPIENA = 0.

goes low.

is low.

HOST-PORT INTERFACE SIGNALS

DESCRIPTIONTYPE

DESCRIPTIONTYPE

pin of the HPI and is only available when

Introduction

is low.

is low.

is low.

is low. The HPI data bus includes bus

pin is connected to multiple DSPs,

April 1999 − Revised October 2008 SPRS096C

7

Introduction

Table 1−2. Signal Descriptions (Continued)

TERMINAL

TERMINAL

NAME

NAME

HAS I

HR/W I

HRDY O/Z

HINT/TOUT1 O/Z

HPIENA I

CV

DD

DV

DD

V

SS

NC No connection

TCK I

TDI I

TDO O/Z

TMS I

§

TRST

EMU0 I/O/Z

EMU1/OFF I/O/Z

†

I = input, O = output, Z = high impedance, S = supply

‡

If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.

§

Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST
a buffer is recommended to ensure the VIL and VIH specifications are met.

†

†

HOST-PORT INTERFACE SIGNALS (CONTINUED)

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA
register. HAS

Read/write. HR/W controls the direction of an HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.

Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when EMU1/OFF

Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can also
be configured as the timer 1 output (TOUT1) when the HPI is disabled. The signal goes into the high-impedance
state when EMU1/OFF

HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor
is always active and the HPIENA pin is sampled on the rising edge of RS
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the UC5402
is reset.

S +VDD. Dedicated power supply for the core CPU
S +VDD. Dedicated power supply for the I/O pins
S Ground

IEEE standard 1 149.1 (JTAG) test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The
changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller,
instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal
(TDO) occur on the falling edge of TCK.

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST

I

1149.1 signals are ignored. Pin with internal pulldown device.
Emulator 0 pin. When TRST is driven low , EMU0 must be high for activation of the OFF condition. When TRST

is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
of the IEEE standard 1149.1 scan system.

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST
is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active (low), puts all output drivers
into the high-impedance state. Note that OFF
multiprocessing applications). Therefore, for the OFF
TRST
EMU0 = high
EMU1/OFF

has an internal pullup resistor that is only enabled when HPIENA = 0.

is low.

SUPPLY PINS

MISCELLANEOUS SIGNAL

TEST PINS

is driven low, the device operates in its functional mode, and the IEEE standard

= low

= low

DESCRIPTIONTYPE

DESCRIPTIONTYPE

is low.

is used exclusively for testing and emulation purposes (not for

feature, the following apply:

. If HPIENA is left open or is driven low

pin is connected to multiple DSPs,

8

April 1999 − Revised October 2008SPRS096C

2 Functional Overview

The following functional overview is based on the block diagram in Figure 2−1.

Functional Overview

P, C, D, E Buses and Control Signals

Pbus

Cbus

54x Core

JTAG

External Memory Interface

HPI8 Module

Ebus

Dbus

DMA Controller

6 Channels

DMA Bus

Pbus

Cbus

Dbus

16K Dual-Access RAM

Program/Data

Peripheral Bus

Ebus

Pbus

4K ROM Program/Data

Figure 2−1. Block Diagram of the TMS320UC5402

Cbus

Dbus

GPIO

McBSP0

McBSP1

Timer0

Timer1

APLL

2.1 Memory

The UC5402 device provides both on-chip ROM and RAM to aid in system performance and integration.

2.1.1 On-Chip Dual-Access RAM (DARAM)

The UC5402 device contains 16K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed
of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and
a write in one cycle. The DARAM is located in the address range 0080h−3FFFh in data space, and can be
mapped into program/data space by setting the OVLY bit to 1.

April 1999 − Revised October 2008 SPRS096C

9

Functional Overview

2.1.2 On-Chip ROM With Bootloader

The UC5402 features 4K × 16-bit of on-chip maskable ROM. Customers can arrange to have the ROM of the
UC5402 programmed with contents unique to any particular application. A security option is available to
protect a custom ROM. This security option is described in the TMS320C54x DSP Reference Set, Volume 1:
CPU and Peripherals (literature number SPRU131). Note that only the ROM security option, and not the
ROM/RAM option, is available on the UC5402 .

A bootloader is available in the standard UC5402 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC
pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program. The standard UC5402 bootloader
provides different ways to download the code to accomodate various system requirements:

• Parallel from 8-bit or 16-bit-wide EPROM

• Parallel from I/O space 8-bit or 16-bit mode

• Serial boot from serial ports 8-bit or 16-bit mode

• Host-port interface boot

The standard on-chip ROM layout is shown in Table 2−1.

Table 2−1. Standard On-Chip ROM Layout

ADDRESS RANGE DESCRIPTION

F000h − F7FFh Reserved

†

F800h − FBFFh Bootloader
FC00h − FCFFh µ-law expansion table
FD00h − FDFFh A-law expansion table
FE00h − FEFFh Sine look-up table

FF00h − FF7Fh Reserved

FF80h − FFFFh Interrupt vector table

†

In the UC5402 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.

10

April 1999 − Revised October 2008SPRS096C

2.1.3 Memory Map

Functional Overview

Page 0 Program

Hex

0000

Reserved

(OVLY = 1)

External

(OVLY = 0)

007F
0080

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

3FFF

4000

External

FF7F
FF80

FFFF

Interrupts
(External)

MP/MC= 1

(Microprocessor Mode)

Page 0 Program

Hex

0000

Reserved

(OVLY = 1)

External

(OVLY = 0)

007F
0080

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

3FFF

4000

External

EFFF

F000

FEFF

FF00

FF7F

FF80

FFFF

On-Chip ROM

(4K x 16-bit)

Reserved

Interrupts
(On-Chip)

MP/MC

(Microcomputer Mode)

= 0

Hex

0000

005F
0060

007F

0080

On-Chip DARAM

3FFF

4000

EFFF

F000

ROM (DROM=1)

FEFF

FF00

FFFF

Data

Memory

Mapped

Registers

Scratch-Pad

RAM

(16K x 16-bit)

External

or External

(DROM=0)

Reserved

(DROM=1)

or External

(DROM=0)

Figure 2−2. TMS320UC5402 Memory Map

2.1.4 Relocatable Interrupt Vector Table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see
Figure 2−3) with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or
trap vector is mapped to the new 128-word page.

NOTE: The hardware reset (RS
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

April 1999 − Revised October 2008 SPRS096C

) vector cannot be remapped because a hardware reset loads the IPTR

11

Functional Overview

15 76543210

IPTR MP/MC OVLY AVIS DROM

R/W R/W R/W R R R R/W R/W

LEGEND: R = Read, W = Write

CLK
OFF

SMUL SST

Figure 2−3. Processor Mode Status (PMST) Register

2.1.5 Extended Program Memory

The UC5402 uses a paged extended memory scheme in program space to allow access of up to 1024K
program memory locations. In order to implement this scheme, the UC5402 includes several features that are
also present on the 548/549 devices:

• Twenty address lines, instead of sixteen

• An extra memory-mapped register, the XPC register, defines the page selection. This register is

memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

• Six extra instructions for addressing extended program space. These six instructions affect the XPC.

− FB[D] pmad (20 bits) − Far branch

− FBACC[D] Accu[19:0] − Far branch to the location specified by the value in accumulator A or
accumulator B

− FCALL[D] pmad (20 bits) − Far call

− FCALA[D] Accu[19:0] − Far call to the location specified by the value in accumulator A or
accumulator B

− FRET[D] − Far return

− FRETE[D] − Far return with interrupts enabled

• In addition to these new instructions, two 54x instructions are extended to use 20 bits in the UC5402:

− READA data_memory (using 20-bit accumulator address)

− WRITA data_memory (using 20-bit accumulator address)

All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access
only memory within the current page.

12

April 1999 − Revised October 2008SPRS096C

Functional Overview

Program memory in the UC5402 is organized into 16 pages that are each 64K in length, as shown in
Figure 2−4.

0 0000

Page 0

64K

Words{

0 FFFF

†

See Figure 2−2

‡

The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM
is mapped to the lower 16K words of all program space pages.

1 0000

1 3FFF

1 4000

1 FFFF

Page 1

Lower

16K}

External

Page 1

Upper

48K

External

2 0000

2 3FFF

2 4000

2 FFFF

Page 2
Lower

16K}

External

Page 2

Upper

48K

External

. . .
. . .

. . .

. . .

F 0000

F 3FFF

F 4000

F FFFF

Page 15

Lower

16K}

External

Page 15

Upper

48K

External

Figure 2−4. Extended Program Memory

2.2 On-Chip Peripherals

The UC5402 device supports the following on-chip peripherals:

• Software-programmable wait-state generator with programmable bank-switching wait states

• An enhanced 8-bit host-port interface (HPI8)

• Two multichannel buffered serial ports (McBSPs)

• Two hardware timers

• A clock generator with a phase-locked loop (PLL)

• A direct memory access (DMA) controller

2.2.1 Software-Programmable Wait-State Generator

The software wait-state generator of the UC5402 can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.
When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator
are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the
UC5402.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 15 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 2−5 and described in Table 2−2.

14 12 11 9 8 6 5 3 2 015

XPA I/O Data Data Program Program

R/W-111R/W-0 R/W-111 R/W-111 R/W-111 R/W-111

LEGEND: R=Read, W=Write, 0=Value after reset

Figure 2−5. Software W ait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

April 1999 − Revised October 2008 SPRS096C

13

Functional Overview

RESET

RESET

FUNCTION

RESET

RESET

FUNCTION

BIT

NO. NAME

15 XPA 0

14−12 I/O 1

11−9 Data 1

8−6 Data 1

5−3 Program 1

2−0 Program 1

Table 2−2. Software Wait-State Register (SWWSR) Bit Fields

VALUE

Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for the program space wait states.

I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.

Upper data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.

Lower data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.

Upper program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:

- XPA = 0: x8000 − xFFFFh

- XPA = 1: The upper program space bit field has no effect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0−7) corresponds to the base number of wait states for external

program space accesses within the following addresses:

- XPA = 0: x0000−x7FFFh

- XPA = 1: 00000−FFFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

The software wait-state multiplier bit (SWSM) of the software wait-state control register (SWCR) is used to
extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 2−6
and described in Table 2−3.

115

Reserved

R/W-0

LEGEND: R = Read, W = Write

0

SWSM

R/W-0

Figure 2−6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]

Table 2−3. Software Wait-State Control Register (SWCR) Bit Fields

BIT

NO. NAME

15−1 Reserved 0

0 SWSM 0

VALUE

These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor

of 1 or 2.

- SWSM = 0: wait-state base values are unchanged (multiplied by 1).

- SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.

14

April 1999 − Revised October 2008SPRS096C