TMS320TCI648x/9x DSP
Viterbi-Decoder Coprocessor 2 (VCP2)
User's Guide
Literature Number: SPRUE09E
May 2006–Revised December 2009
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Preface ....................................................................................................................................... 6
1 Features ............................................................................................................................. 7
2 Introduction ........................................................................................................................ 8
3 Overview .......................................................................................................................... 10
4 Input Data ......................................................................................................................... 11
4.1 Branch Metrics Calculations .......................................................................................... 11
4.2 Soft Input Dynamic Ranges .......................................................................................... 12
5 Decision Data .................................................................................................................... 13
6 Registers .......................................................................................................................... 14
6.1 VCP2 Peripheral Identification Register (VCPPID) ................................................................ 15
6.2 VCP2 Input Configuration Register 0 (VCPIC0) ................................................................... 16
6.3 VCP2 Input Configuration Register 1 (VCPIC1) ................................................................... 17
6.4 VCP2 Input Configuration Register 2 (VCPIC2) ................................................................... 18
6.5 VCP2 Input Configuration Register 3 (VCPIC3) ................................................................... 19
6.6 VCP2 Input Configuration Register 4 (VCPIC4) ................................................................... 20
6.7 VCP2 Input Configuration Register 5 (VCPIC5) ................................................................... 21
6.8 VCP2 Output Register 0 (VCPOUT0) ............................................................................... 22
6.9 VCP2 Output Register 1 (VCPOUT1) ............................................................................... 23
6.10 VCP2 Execution Register (VCPEXE) ............................................................................... 24
6.11 VCP2 Endian Mode Register (VCPEND) ........................................................................... 25
6.12 VCP2 Status Register 0 (VCPSTAT0) .............................................................................. 26
6.13 VCP2 Status Register 1 (VCPSTAT1) .............................................................................. 27
6.14 VCP2 Error Register (VCPERR) ..................................................................................... 28
6.15 VCP2 Emulation Control Register (VCPEMU) ..................................................................... 30
7 Endianness ....................................................................................................................... 31
7.1 Branch Metrics ......................................................................................................... 31
8 Architecture ...................................................................................................................... 34
8.1 Sliding-Windows Processing ......................................................................................... 34
8.2 Yamamoto Parameters ................................................................................................ 37
8.3 Input FIFO (Branch Metrics) .......................................................................................... 37
8.4 Output FIFO (Decisions) .............................................................................................. 37
9 Programming .................................................................................................................... 39
9.1 EDMA3 Resources .................................................................................................... 39
9.2 Input Configuration Words ............................................................................................ 43
10 Output Parameters ............................................................................................................ 43
11 Event Generation ............................................................................................................... 44
11.1 VCPXEVT Generation ................................................................................................. 44
11.2 VCPREVT Generation ................................................................................................ 44
12 Operational Modes ............................................................................................................ 45
12.1 Debugging Features ................................................................................................... 45
13 Errors and Status .............................................................................................................. 46
Appendix A Revision History ...................................................................................................... 47
SPRUE09E–May 2006–Revised December 2009 Table of Contents
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List of Figures
1 Convolutional Encoder Example Block Diagram........................................................................ 8
2 Trellis Diagram for Convolutional Encoder Example................................................................... 9
3 VCP2 Block Diagram...................................................................................................... 10
4 VCP2 Peripheral ID Register (VCPPID)................................................................................ 15
5 VCP2 Input Configuration Register 0 (VCPIC0)....................................................................... 16
6 VCP2 Input Configuration Register 1 (VCPIC1)....................................................................... 17
7 VCP2 Input Configuration Register 2 (VCPIC2)....................................................................... 18
8 VCP2 Input Configuration Register 3 (VCPIC3)....................................................................... 19
9 VCP2 Input Configuration Register 4 (VCPIC4)....................................................................... 20
10 VCP2 Input Configuration Register 5 (VCPIC5)....................................................................... 21
11 VCP2 Output Register 0 (VCPOUT0) .................................................................................. 22
12 VCP2 Output Register 1 (VCPOUT1) .................................................................................. 23
13 VCP2 Execution Register (VCPEXE)................................................................................... 24
14 VCP2 Endian Mode Register (VCPEND) .............................................................................. 25
15 VCP2 Status Register 0 (VCPSTAT0).................................................................................. 26
16 VCP2 Status Register 1 (VCPSTAT1).................................................................................. 27
17 VCP2 Error Register (VCPERR) ........................................................................................ 28
18 VCP2 Emulation Control Register (VCPEMU)......................................................................... 30
19 Data Source - VBUSP/DMA (BM = 1).................................................................................. 31
20 Data Destination - Kernel for Processing Unit (BM = 1).............................................................. 31
21 Data Source - VBUSP/DMA (BM = 0).................................................................................. 32
22 Data Destination - Kernel for Processing Unit (BM = 0).............................................................. 32
23 Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0) .................................... 33
24 Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) .................................... 33
25 Processing Unit............................................................................................................ 34
26 Tailed Traceback Mode................................................................................................... 34
27 Mixed Traceback Mode-Example With Five Sliding Windows....................................................... 35
28 Convergent Traceback Mode-Example With Five Sliding Windows................................................ 35
29 EDMA3 Parameters Structure ........................................................................................... 39
4
List of Figures SPRUE09E–May 2006–Revised December 2009
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1 Branch Metrics for Rate 1/2.............................................................................................. 11
2 Branch Metrics for Rate 1/3.............................................................................................. 12
3 Branch Metrics for Rate 1/4.............................................................................................. 12
4 VCP2 Soft Inputs Quantization .......................................................................................... 12
5 VCP2 Registers............................................................................................................ 14
6 VCP2 Memories ........................................................................................................... 14
7 VCP2 Peripheral ID Register (VCPPID) Field Descriptions ......................................................... 15
8 VCP2 Input Configuration Register 0 (VCPIC0) Field Descriptions ................................................ 16
9 VCP2 Input Configuration Register 1 (VCPIC1) Field Descriptions ................................................ 17
10 VCP2 Input Configuration Register 2 (VCPIC2) Field Descriptions ................................................ 18
11 VCP2 Input Configuration Register 3 (VCPIC3) Field Descriptions ................................................ 19
12 VCP2 Input Configuration Register 4 (VCPIC4) Field Descriptions ................................................ 20
13 VCP2 Input Configuration Register 5 (VCPIC5) Field Descriptions ................................................ 21
14 VCP2 Output Register 0 (VCPOUT0) Field Descriptions............................................................ 22
15 VCP2 Output Register 1 (VCPOUT1) Field Descriptions............................................................ 23
16 VCP2 Execution Register (VCPEXE) Field Descriptions............................................................. 24
17 VCP2 Endian Mode Register (VCPEND) Field Descriptions........................................................ 25
18 VCP2 Status Register 0 (VCPSTAT0) Field Descriptions ........................................................... 26
19 VCP2 Status Register 1 (VCPSTAT1) Field Descriptions ........................................................... 27
20 VCP2 Error Register (VCPERR) Field Descriptions .................................................................. 28
21 VCP2 Emulation Control Register (VCPEMU) Field Descriptions .................................................. 30
22 Branch Metrics............................................................................................................. 31
23 Branch Metrics in DSP Memory (BM = 1).............................................................................. 31
24 Branch Metrics in DSP Memory (BM = 0).............................................................................. 32
25 Soft Decision Organization............................................................................................... 33
26 Traceback Soft Decision Sliding Window Limits ...................................................................... 36
27 Traceback Hard Decision Sliding Window Limits ..................................................................... 36
28 Code Rate versus SYMX................................................................................................. 37
29 Required EDMA3 Links Per User Channel ............................................................................ 39
30 TCI648x/9x Revision History............................................................................................. 47
List of Tables
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About This Manual
Channel decoding of voice and low bit-rate data channels found in third generation (3G) cellular standards
requires decoding of convolutional encoded data. The Viterbi-decoder coprocessor 2 (VCP2) provided in
the TCI648x/9x devices has been designed to perform Viterbi decoding for IS2000 and 3GPP wireless
standards. The VCP2 coprocessor has been designed to perform forward-error correction for 2G and 3G
wireless systems. The VCP2 coprocessor offers a very cost effective and synergistic solution when
combined with Texas Instruments (TI) DSPs. The VCP2 supports 762 12.2 Kbps 3G AMR channels when
running at 333 MHz. This document describes the operation and programming of the VCP2.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
• The term "word" describes a 32-bit value.
Preface
SPRUE09E–May 2006–Revised December 2009
Read This First
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
SPRU189 — TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors
(DSPs).
SPRU198 — TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for
the TMS320C6000™ DSPs and includes application program examples.
SPRU301 — TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™
integrated development environment and software tools.
SPRU321 — Code Composer Studio Application Programming Interface Reference Guide.
Describes the Code Composer Studio™ application programming interface (API), which allows you
to program custom plug-ins for Code Composer.
SPRU871 — TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal
processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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Preface SPRUE09E–May 2006–Revised December 2009
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Channel decoding of voice and low bit-rate data channels found in cellular standards such as 2.5G, 3G,
and WiMAX requires the decoding of convolutional encoded data. The Viterbi-decoder coprocessor 2
(VCP2) provided in the TCI648x/9x devices performs Viterbi decoding for IS2000 and 3GPP wireless
standards. The VCP2 coprocessor also performs forward-error correction for 2G and 3G wireless systems.
The VCP2 coprocessor offers a very cost effective and synergistic solution when combined with Texas
Instruments (TI) DSPs. The VCP2 supports 762 12.2 Kbps 3G AMR channels when running at 333 MHz.
1 Features
The VCP2 provides:
• High flexibility:
– Variable constraint length, K = 5, 6, 7, 8, or 9
– User-supplied code coefficients
– Code rates (1/2, 1/3, or 1/4)
– Configurable trace back settings (convergence distance, frame structure)
– Branch metrics calculation and depuncturing done in software by the DSP
• System and development cost optimization:
– The VCP2 releases DSP resources for other processing
– Reduces board space and power consumption by performing on-chip decoding
– Communication between the DSP and the VCP2 is performed through the high-performance
EDMA3 engine
– Uses its own optimized working memories
– Provides debug capabilities during frame processing
– Libraries are provided for reduced development time
User's Guide
SPRUE09E–May 2006–Revised December 2009
TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2
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output 2
output 0
output 1
input
z
-1
z
-1
Introduction
2 Introduction
A convolutional code is generated by passing the information sequence to be transmitted through a linear
finite-state shift register. The VCP2 is able to decode only a subset of those codes known as a single-shift
register, nonrecursive convolutional code (an example is given in Figure 1). Important parameters for this
type of codes are:
• The constraint length K (length of the delay line, the VCP2 supports K values from 5 to 9).
• The rate R given by R = k/n where k is the number of information bits needed to produce n output bits
also known as codewords (the VCP2 supports 1/2, 1/3, and 1/4 codes with rates).
• The generator polynomials Gn describe how the outputs are generated from the inputs.
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Figure 1. Convolutional Encoder Example Block Diagram
NOTE: K = 3, R = k/n = 1/3, G0= (100)8, G1= (101)8, G2= (111)80/000 means input is 0, output0 is
0, output1 is 0, output2 is 0.There are 2
(K-1)
states and 2kincoming branches per state.
From the parameters, we can derive a trellis diagram providing a useful representation of the code, but
whose complexity grows exponentially with the constraint length K. Figure 2 shows the trellis diagram of
the code from Figure 1. The fact that there is a limited number of possible transitions from one state to
another makes the code powerful and will be used in the decoding process.
As a maximum-likelihood sequence estimation (MLSE) decoder, the Viterbi decoder identifies the code
sequence with the highest probability of matching the transmitted sequence based on the received
sequence.
The Viterbi algorithm is composed of a metric update and a traceback routine. The metric update performs
a forward recursion in the trellis over a finite number of symbol periods where probabilities are
accumulated (the VCP2 accumulates on 13 bits) for each individual state based on the current input
symbol (branch metric information). The accumulated metric is known as path metrics or state metrics.
Once a path through the trellis is identified, the traceback routine performs a backward recursion in the
trellis and outputs hard decisions or soft decisions.
8
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0/000
1/111
00
01
10
11
State
1/101
0/010
1/110
0/011
0/001
1/100
Time t Time t+T
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Introduction
Figure 2. Trellis Diagram for Convolutional Encoder Example
NOTE: K = 3, R = k/n = 1/3, G0= (100)8, G1= (101)8, G2= (111)80/000 means input is 0, output1 is
0, output2 is 0, output3 is 0. There are 2
(K-1)
states and 2kincoming branches per state.
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Configuration bus
EDMA3 bus
Viterbi-decoder coprocessor 2 (VCP2)
REVT/XEVT
generation
CPU
interrupt
generation
VCP Control
EDMA3 I/F unit Memory block Processing unit
VCP2_INT VCPXEVT VCPREVT
Overview
3 Overview
The DSP controls the operation of the VCP2 (Figure 3) using memory-mapped registers. The DSP
typically sends and receives data using synchronized EDMA3 transfers through the EDMA3 bus. The
VCP2 sends two synchronization events to the EDMA3: a receive event (VCPREVT) and a transmit event
(VCPXEVT). The VCP2 input data corresponds to the branch metrics and the output data to the hard
decisions or soft decisions.
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Figure 3. VCP2 Block Diagram
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4 Input Data
4.1 Branch Metrics Calculations
Input Data
The branch metrics (BM) are calculated by the DSP and stored in the DSP memory subsystem as 8-bit
signed values. Per symbol interval T, for a rate R = k/n and a constraint length K, there are a total of 2
branches in the trellis. For rate 1/n codes, only 2
n-1
branch metrics need to be computed per symbol period
K-1+k
and passed to the VCP2. Moreover, n soft inputs are required to calculate 1 branch metric.
Assuming BSPK modulated bits (0 → 1, 1 → -1), the branch metrics are calculated as follows:
• Rate 1/2: there are 2 branch metrics per symbol period
– BM0(t) = r0(t) + r1(t)
– BM1(t) = r0(t) - r1(t)
where r(t) is the received codeword at time t (2 symbols, r0(t) is the symbol corresponding to the encoder
upper branch, see Figure 1).
• Rate 1/3: there are 4 branch metrics per symbol period
– BM0(t) = r0(t) + r1(t) + r2(t)
– BM1(t) = r0(t) + r1(t) - r2(t)
– BM2(t) = r0(t) - r1(t) + r2(t)
– BM3(t) = r0(t) - r1(t) - r2(t)
where r(t) is the received codeword (3 symbols, r0(t) is the symbol corresponding to the encoder upper
branch, see Figure 1).
• Rate 1/4: there are 8 branch metrics per symbol period
– BM0(t) = r0(t) + r1(t) + r2(t) + r3(t)
– BM1(t) = r0(t) + r1(t) + r2(t) - r3(t)
– BM2(t) = r0(t) + r1(t) - r2(t) + r3(t)
– BM3(t) = r0(t) + r1(t) - r2(t) - r3(t)
– BM4(t) = r0(t) - r1(t) + r2(t) + r3(t)
– BM5(t) = r0(t) - r1(t) + r2(t) - r3(t)
– BM6(t) = r0(t) - r1(t) - r2(t) + r3(t)
– BM7(t) = r0(t) - r1(t) - r2(t) - r3(t)
where r(t) is the received codeword (4 symbols, r0(t) is the symbol corresponding to the encoder upper
branch, see Figure 1).
The data must be sent to the VCP2 as described in Table 1, Table 2, and Table 3 for rates 1/2, 1/3, and
1/4, respectively (the base address must be double-word aligned).
The branch metrics can be saved in the DSP memory subsystem in either their native format or packed in
words (user implementation). When working in big-endian mode, the VCP2 endian mode register
(VCPEND) indicates if the data is 32-bit word packed or native 8-bit format and the VCP2 will handle the
endianness byte swapping accordingly (see Section 7).
Table 1. Branch Metrics for Rate 1/2
Data
Address (hex) MSB LSB
Base BM1(t=T) BM0(t=T) BM1(t=0) BM0(t=0)
Base + 4h BM1(t=3T) BM0(t=3T) BM1(t=2T) BM0(t=2T)
Base + 8h ...
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Input Data
Address (hex) MSB LSB
Base BM3(t=0) BM2(t=0) BM1(t=0) BM0(t=0)
Base + 4h BM3(t=T) BM2(t=T) BM1(t=T) BM0(t=T)
Base + 8h ...
Address (hex) MSB LSB
Base BM3(t=0) BM2(t=0) BM1(t=0) BM0(t=0)
Base + 4h BM7(t=0) BM6(t=0) BM5(t=0) BM4(t=0)
Base + 8h BM3(t=T) BM2(t=T) BM1(t=T) BM0(t=T)
Base + Ch BM7(t=T) BM6(t=T) BM5(t=T) BM4(t=T)
Base + 10h ...
The state metric accumulation resolution is 13 bits on the VCP2. Consequently, full 8-bit dynamic range is
available for branch metrics on the TCI648x/9x VCP2, for all constraint lengths and all code rates.
4.2 Soft Input Dynamic Ranges
The VCP2 implementation implies that the soft inputs need to be quantized so that the branch metrics
satisfy the following bound B1 (branch metrics upper bound - absolute value):
(C - 1)
2
- 1 ≥ (2 × (K - 1) + 2) × B
K is the constraint length and C determines the truncation of state metrics that can be performed without
loss of decoding performance.
The VCP2 is designed with C = 13. The branch metrics can have a maximum dynamic range of 7 + 1 sign
bits [-128; +127]. This gives another branch metrics upper bound B2≤ 128.
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Table 2. Branch Metrics for Rate 1/3
Data
Table 3. Branch Metrics for Rate 1/4
Data
1
So for a given constraint length, min (B1, B2) gives the final branch metrics maximum bound B.
To satisfy B in the branch metrics calculation, the soft input values, delivered as 8-bit-signed equalized
values, are linearly scaled with the following formula where 1/n is the rate.
Scaled = min (B1, B2)/n × SoftValue/128
Example
K = 9, then B1≤ 227.5 and the branch metrics range B2is [-128; +127]. So the branch metrics need to be
in [-128;+127] range.
If rate 1/3, 128/3 42, so the soft inputs need to be scaled by a factor of 0.333333 and saturated within
the range [-42; +42].
Table 4 summarizes the calculations for the different constraint length and rate:
Table 4. VCP2 Soft Inputs Quantization
1/Rate K Scaling Factor Range
2 5, 6, 7, 8, 9 0.5 [-64; +63]
3 5, 6, 7, 8, 9 0.333333 [-42; +42]
4 5, 6, 7, 8, 9 0.25 [-31; +31]
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5 Decision Data
The VCP2 can be configured to generate either hard decisions (one bit per decision), or soft decisions
(8-bit value per decision). Ordering of the VCP2 decisions depends on the OUT_ORDER field of VCPIC3
and the SD field of VCPEND. If the DSP is set to work in big-endian mode and the results are soft
decisions (see the VCP2 endian mode register, Section 6.3). The decisions buffer start address must be
double-word aligned and the buffer size must be a multiple of 8 bytes.
The soft decisions in the VCP2 are initially computed with the path metrics at 13-bit values. The results
are then clipped to 8-bit signed integer values before being stored in the traceback soft decision memory.
Decision Data
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Registers
6 Registers
The VCP2 contains several memory-mapped registers accessible by the CPU, the IDMA, the QDMA, and
the EDMA3. A configuration-bus access is faster than an EDMA3-bus access for isolated accesses
(typically when accessing control registers). EDMA3-bus accesses are used for EDMA3 transfers and
provide maximum throughput to/from the VCP2. The registers are listed in Table 5. For the memory map
and full register addresses, see the device-specific data manual.
The branch metric and traceback decision memories contents are not accessible and the memories can
be regarded as FIFOs by the DSP, meaning you do not have to perform any indexing on the addresses.
EDMA3 Bus Configuration Bus
Offsets Offsets Acronym Register Name See
0000h VCPIC0 VCP input configuration register 0 Section 6.2
0004h VCPIC1 VCP input configuration register 1 Section 6.3
0008h VCPIC2 VCP input configuration register 2 Section 6.4
000Ch VCPIC3 VCP input configuration register 3 Section 6.5
0010h VCPIC4 VCP input configuration register 4 Section 6.6
0014h VCPIC5 VCP input configuration register 5 Section 6.7
0048h VCPOUT0 VCP output register 0 Section 6.8
004Ch VCPOUT1 VCP output register 1 Section 6.9
0080h VCPWBM VCP branch metrics write FIFO register
00C0h VCPRDECS VCP decisions read FIFO register
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Table 5. VCP2 Registers
0000h VCPPID VCP peripheral ID register Section 6.1
0018h VCPEXE VCP execution register Section 6.10
0020h VCPEND VCP endian mode register Section 6.11
0040h VCPSTAT0 VCP status register 0 Section 6.12
0044h VCPSTAT1 VCP status register 1 Section 6.13
0050h VCPERR VCP error register Section 6.14
0060h VCPEMU VCP emulation control register Section 6.15
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Table 6. VCP2 Memories
EDMA3 Bus Offsets Acronym Name Size
1000h BM Branch Metrics (BM) 256 Bytes
2000h SM State Metric (SM) 448 Bytes
3000h TBHD Traceback Hard Decision 4K Bytes
6000h TBSD Traceback Soft Decision 16K Bytes
F000h IO Decoded Bits (IO) 512 Bytes
NOTE: Register and Memory Access
• Data Transfer Alignment: Normal (non-emulation) mode data transfers to/from the VCP2
must be aligned on a double-word (64-bit) boundary. Alignment can be forced in C using
the 'DATA_ALIGN' pragma. Non-alignment results in data transfer failure.
Example:
#pragma DATA_ALIGN(configIc, 8) // Should be double-word aligned
VCP_ConfigIc configIc; // VCP Input Configuration Reg
• Data Transfer Size: Normal (non-emulation) mode data transfers to/from the VCP2 must
be of a length that is an 8-byte (double-word) multiple.
• Emulation mode transfers are performed on 32-bit boundaries and are 4 bytes in length.
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Registers
6.1 VCP2 Peripheral Identification Register (VCPPID)
The VCP2 peripheral identification register (VCPPID) is a constant register that contains the ID and ID
revision number for the peripheral. The PID stores version information used to identify the peripheral. All
bits within this register are read-only (writes have no effect), meaning that the values within this register
should be hard-coded with the appropriate values and must not change from their reset state.
The VCPPID register is shown in Figure 4 and described in Table 7.
Figure 4. VCP2 Peripheral ID Register (VCPPID)
TCI648x DSP
31 24 23 16 15 8 7 0
Reserved TYPE CLASS REV
R-0 R-0x01 R-0x11 R-rev
TCI649x DSP
31 30 29 28 27 16 15 11 10 8 7 6 5 0
SCHEME Reserved PID RTL MAJOR CUSTOM MINOR
R-1 R-0 R-0x80A R-<rtl> R-<major> R- R-<minor>
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. VCP2 Peripheral ID Register (VCPPID) Field Descriptions
Bit Field Value Description
TCI648x DSP
31-24 Reserved 0 Reserved
23-16 TYPE 01h Peripheral Type. Identifies the type of the peripheral.
15-8 CLASS 11h Peripheral Class. Identifies the class.
7-0 REV <rev> Peripheral Revision. Identifies the revision level of the specific instance of the peripheral. This
value should begin at 0x01 and be incremented each time the design is revised.
TCI649x DSP
31-30 SCHEME 1 Current scheme.
29-28 Reserved 0 Reserved.
27-16 PID 80Ah Peripheral ID.
15-11 RTL <rtl> RTL revision code.
10-8 MAJOR <major> Major revision code.
7-6 CUSTOM <custom> Custom revision code.
5-0 MINOR <minor> Minor revision code.
<custom>
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