TMS320TCI648x Serial RapidIO (SRIO)
User's Guide
Literature Number: SPRUE13A
September 2006
2 SPRUE13A – September 2006
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Contents
Preface .............................................................................................................................. 14
1 Overview .................................................................................................................. 16
1.1 General RapidIO System ...................................................................................... 16
1.2 RapidIO Feature Support in SRIO............................................................................ 19
1.3 Standards ........................................................................................................ 20
1.4 External Devices Requirements .............................................................................. 20
1.5 TI Devices Supported By This Document ................................................................... 20
2 SRIO Functional Description ....................................................................................... 21
2.1 Overview ......................................................................................................... 21
2.2 SRIO Pins ....................................................................................................... 25
2.3 Functional Operation ........................................................................................... 26
3 Logical/Transport Error Handling and Logging ............................................................. 83
4 Interrupt Conditions ................................................................................................... 85
4.1 CPU Interrupts .................................................................................................. 85
4.2 General Description ............................................................................................ 85
4.3 Interrupt Condition Status and Clear Registers ............................................................. 86
4.4 Interrupt Condition Routing Registers........................................................................ 93
4.5 Interrupt Status Decode Registers ........................................................................... 97
4.6 Interrupt Generation ............................................................................................ 99
4.7 Interrupt Pacing ................................................................................................. 99
4.8 Interrupt Handling ............................................................................................. 100
5 SRIO Registers ........................................................................................................ 102
5.1 Introduction .................................................................................................... 102
5.2 Peripheral Identification Register (PID) .................................................................... 111
5.3 Peripheral Control Register (PCR) .......................................................................... 112
5.4 Peripheral Settings Control Register (PER_SET_CNTL) ................................................ 113
5.5 Peripheral Global Enable Register (GBL_EN) ............................................................ 116
5.6 Peripheral Global Enable Status Register (GBL_EN_STAT)............................................ 117
5.7 Block n Enable Register (BLK n_EN) ....................................................................... 119
5.8 Block n Enable Status Register (BLK n_EN_STAT) ...................................................... 120
5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) ....................................................... 121
5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) ....................................................... 122
5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTL n) ............................... 123
5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n) .................................. 124
5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) ................. 125
5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) ................. 128
5.15 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL) .................................. 130
5.16 DOORBELL n Interrupt Condition Status Register (DOORBELL n_ICSR) ............................. 132
5.17 DOORBELL n Interrupt Condition Clear Register (DOORBELL n_ICCR) .............................. 133
5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ................................................... 134
5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)..................................................... 135
5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) .................................................... 136
5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ..................................................... 137
5.22 LSU Interrupt Condition Status Register (LSU_ICSR) ................................................... 138
SPRUE13A – September 2006 Table of Contents 3
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5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) .................................................... 141
5.24 Error, Reset, and Special Event Interrupt Condition Status Register
(ERR_RST_EVNT_ICSR) .................................................................................... 142
5.25 Error, Reset, and Special Event Interrupt Condition Clear Register
(ERR_RST_EVNT_ICCR) ................................................................................... 143
5.26 DOORBELL n Interrupt Condition Routing Registers (DOORBELL n_ICRR and
DOORBELL n_ICRR2) ........................................................................................ 144
5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) ......... 145
5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) .......... 146
5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3) .............................. 147
5.30 Error, Reset, and Special Event Interrupt Condition Routing Registers
(ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) ............. 149
5.31 Interrupt Status Decode Register (INTDST n_DECODE) ................................................ 150
5.32 INTDST n Interrupt Rate Control Register (INTDST n_RATE_CNTL)................................... 154
5.33 LSU n Control Register 0 (LSU n_REG0) ................................................................... 155
5.34 LSU n Control Register 1 (LSU n_REG1) ................................................................... 156
5.35 LSU n Control Register 2 (LSU n_REG2) ................................................................... 157
5.36 LSU n Control Register 3 (LSU n_REG3) ................................................................... 158
5.37 LSU n Control Register 4 (LSU n_REG4) ................................................................... 159
5.38 LSU n Control Register 5 (LSU n_REG5) ................................................................... 160
5.39 LSU n Control Register 6 (LSU n_REG6) ................................................................... 161
5.40 LSU n Congestion Control Flow Mask Register (LSU n_FLOW_MASKS).............................. 162
5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUE n_TXDMA_HDP) .............. 164
5.42 Queue n Transmit DMA Completion Pointer Register (QUEUE n_TXDMA_CP)...................... 165
5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUE n_RXDMA_HDP) .............. 166
5.44 Queue n Receive DMA Completion Pointer Register (QUEUE n_RXDMA_CP) ...................... 167
5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) .................................... 168
5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7]) .................. 169
5.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) .................................... 172
5.48 Receive CPPI Control Register (RX_CPPI_CNTL) ....................................................... 173
5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3]) ............... 174
5.50 Mailbox to Queue Mapping Registers (RXU_MAP_L n and RXU_MAP_H n) .......................... 177
5.51 Flow Control Table Entry Register n (FLOW_CNTL n) ................................................... 181
5.52 Device Identity CAR (DEV_ID) .............................................................................. 182
5.53 Device Information CAR (DEV_INFO) ..................................................................... 183
5.54 Assembly Identity CAR (ASBLY_ID) ....................................................................... 184
5.55 Assembly Information CAR (ASBLY_INFO) ............................................................... 185
5.56 Processing Element Features CAR (PE_FEAT) .......................................................... 186
5.57 Source Operations CAR (SRC_OP) ........................................................................ 188
5.58 Destination Operations CAR (DEST_OP) ................................................................. 189
5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL) ........................................ 190
5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ................................. 191
5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) ................................... 192
5.62 Base Device ID CSR (BASE_ID) ........................................................................... 193
5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) ............................................. 194
5.64 Component Tag CSR (COMP_TAG) ....................................................................... 195
5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD) .......................... 196
5.66 Port Link Time-Out Control CSR (SP_LT_CTL) .......................................................... 197
5.67 Port Response Time-Out Control CSR (SP_RT_CTL) ................................................... 198
5.68 Port General Control CSR (SP_GEN_CTL) ............................................................... 199
4 Contents SPRUE13A – September 2006
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5.69 Port Link Maintenance Request CSR n (SP n_LM_REQ) ................................................ 200
5.70 Port Link Maintenance Response CSR n (SP n_LM_RESP) ............................................ 201
5.71 Port Local AckID Status CSR n (SP n_ACKID_STAT) ................................................... 202
5.72 Port Error and Status CSR n (SP n_ERR_STAT) ......................................................... 203
5.73 Port Control CSR n (SP n_CTL) ............................................................................. 206
5.74 Error Reporting Block Header Register (ERR_RPT_BH) ................................................ 209
5.75 Logical/Transport Layer Error Detect CSR (ERR_DET) ................................................. 210
5.76 Logical/Transport Layer Error Enable CSR (ERR_EN) .................................................. 212
5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) .............................. 214
5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) ........................................ 215
5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) ........................................... 216
5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) ......................................... 217
5.81 Port-Write Target Device ID CSR (PW_TGT_ID) ......................................................... 218
5.82 Port Error Detect CSR n (SP n_ERR_DET) ................................................................ 219
5.83 Port Error Rate Enable CSR n (SP n_RATE_EN) ......................................................... 221
5.84 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) ............................ 223
5.85 Port n Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) ................................................. 224
5.86 Port n Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) ................................................. 225
5.87 Port n Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) ................................................. 226
5.88 Port n Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) ................................................. 227
5.89 Port Error Rate CSR n (SP n_ERR_RATE) ................................................................ 228
5.90 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) ............................................... 229
5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) ...................... 230
5.92 Port IP Mode CSR (SP_IP_MODE) ........................................................................ 231
5.93 Port IP Prescaler Register (IP_PRESCAL) ................................................................ 233
5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3]) .............................................. 234
5.95 Port Reset Option CSR n (SP n_RST_OPT) ............................................................... 235
5.96 Port Control Independent Register n (SP n_CTL_INDEP) ............................................... 236
5.97 Port Silence Timer n Register (SP n_SILENCE_TIMER) ................................................ 238
5.98 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) ................. 239
5.99 Port Control Symbol Transmit n Register (SP n_CS_TX) ................................................ 240
Index ............................................................................................................................... 241
SPRUE13A – September 2006 Contents 5
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List of Figures
1 RapidIO Architectural Hierarchy .......................................................................................... 17
2 RapidIO Interconnect Architecture ....................................................................................... 18
3 Serial RapidIO Device to Device Interface Diagrams ................................................................. 19
4 SRIO Peripheral Block Diagram .......................................................................................... 22
5 Operation Sequence ....................................................................................................... 23
6 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) ........................................................ 24
7 Serial RapidIO Control Symbol Format.................................................................................. 24
8 SRIO Component Block Diagram ........................................................................................ 27
9 SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) ............................................... 28
10 SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) ............................... 31
11 SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) .............................. 33
12 Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h, LSU2 420h–438h, LSU3
440h–458h, LSU4 460h-478h) ........................................................................................... 36
13 LSU Registers Timing ..................................................................................................... 38
14 Example Burst NWRITE_R ............................................................................................... 39
15 Load/Store Module Data Flow Diagram ................................................................................. 40
16 CPPI RX Scheme for RapidIO ............................................................................................ 44
17 Message Request Packet ................................................................................................. 45
18 Mailbox to Queue Mapping Register Pair ............................................................................... 46
19 RX Buffer Descriptor Fields ............................................................................................... 47
20 RX CPPI Mode Explanation .............................................................................................. 49
21 CPPI Boundary Diagram .................................................................................................. 51
22 TX Buffer Descriptor Fields ............................................................................................... 52
23 Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) ................................... 56
24 RX Buffer Descriptors ...................................................................................................... 62
25 TX Buffer Descriptors ...................................................................................................... 63
26 Doorbell Operation ......................................................................................................... 64
27 Flow Control Table Entry Registers (Address Offset 0900h–093Ch) ............................................... 66
28 Transmit Source Flow Control Masks ................................................................................... 67
29 Fields Within Each Flow Mask ............................................................................................ 67
30 Configuration Bus Example ............................................................................................... 69
31 DMA Example .............................................................................................................. 69
32 GBL_EN (Address 0030h) ................................................................................................ 71
33 GBL_EN_STAT (Address 0034h) ........................................................................................ 71
34 BLK0_EN (Address 0038h) ............................................................................................... 72
35 BLK0_EN_STAT (Address 003Ch) ...................................................................................... 73
36 BLK1_EN (Address 0040h) ............................................................................................... 73
37 BLK1_EN_STAT (Address 0044h) ....................................................................................... 73
38 BLK8_EN (Address 0078h) ............................................................................................... 73
39 BLK8_EN_STAT (Address 007Ch) ...................................................................................... 73
40 Peripheral Control Register (PCR) - Address Offset 0004h .......................................................... 74
41 Bootload Operation ........................................................................................................ 80
42 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTL n) Offsets 0x0090, 0x0098, 0x00A0,
0x00A8 ....................................................................................................................... 81
43 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n) Offsets 0x0094, 0x009C, 0x00A4,
0x00AC ...................................................................................................................... 82
44 Logical/Transport Layer Error Detect CSR (ERR_DET) .............................................................. 83
45 RapidIO DOORBELL Packet for Interrupt Use ......................................................................... 85
46 Doorbell 0 Interrupt Condition Status and Clear Registers ........................................................... 87
47 Doorbell 1 Interrupt Condition Status and Clear Registers ........................................................... 87
48 Doorbell 2 Interrupt Condition Status and Clear Registers ........................................................... 88
49 Doorbell 3 Interrupt Condition Status and Clear Registers ........................................................... 88
6 List of Figures SPRUE13A – September 2006
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50 RX CPPI Interrupt Condition Status and Clear Registers ............................................................. 89
51 TX CPPI Interrupt Condition Status and Clear Registers ............................................................. 89
52 LSU Interrupt Condition Status and Clear Registers .................................................................. 90
53 Error, Reset, and Special Event Interrupt Condition Status and Clear Registers ................................. 91
54 Doorbell 0 Interrupt Condition Routing Registers ...................................................................... 94
55 RX CPPI Interrupt Condition Routing Registers ........................................................................ 94
56 TX CPPI Interrupt Condition Routing Registers ........................................................................ 95
57 LSU Interrupt Condition Routing Registers ............................................................................. 96
58 Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 97
59 Interrupt Status Decode Register (INTDST n_DECODE) ............................................................. 98
60 Interrupt Sources Assigned to ISDR Bits ............................................................................... 98
61 Example Diagram of Interrupt Status Decode Register Mapping .................................................... 99
62 INTDST n_RATE_CNTL Interrupt Rate Control Register ............................................................ 100
63 Peripheral ID Register (PID) - Address Offset 0000h ................................................................ 111
64 Peripheral Control Register (PCR) - Address Offset 0004h ......................................................... 112
65 Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020h) ............................... 113
66 Peripheral Global Enable Register (GBL_EN) (Address Offset 0030h) ........................................... 116
67 Peripheral Global Enable Status Register (GBL_EN_STAT) - Address 0034h .................................. 117
68 Block n Enable Register (BLK n_EN) ................................................................................... 119
69 Block n Enable Status Register (BLK n_EN) .......................................................................... 120
70 RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h) ................................................ 121
71 RapidIO DEVICEID2 Register (DEVICEID_REG2) (Offset 0x0084) ............................................... 122
72 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTL n) .......................................... 123
73 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n) ............................................. 124
74 SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) ............................. 125
75 SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) ............................. 128
76 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL) .............................................. 130
77 Doorbell n Interrupt Condition Status Register (DOORBELL n_ICSR) ............................................. 132
78 Doorbell n Interrupt Condition Clear Register (DOORBELL n_ICCR) .............................................. 133
79 RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) - Address Offset 0240h ...................... 134
80 RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) - Address Offset 0248h ....................... 135
81 TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h ....................... 136
82 TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258h ........................ 137
83 LSU Interrupt Condition Status Register (LSU_ICSR) - Address Offset 0260h .................................. 138
84 LSU Interrupt Condition Clear Register (LSU_ICCR) - Address Offset 0268h ................................... 141
85 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) - Address
Offset 0270h ............................................................................................................... 142
86 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) - Address
Offset 0278h ............................................................................................................... 143
87 Doorbell n Interrupt Condition Routing Registers ..................................................................... 144
88 RX CPPI Interrupt Condition Routing Registers ...................................................................... 145
89 TX CPPI Interrupt Condition Routing Registers ...................................................................... 146
90 LSU Interrupt Condition Routing Registers ............................................................................ 147
91 Error, Reset, and Special Event Interrupt Condition Routing Registers ........................................... 149
92 Interrupt Status Decode Register (INTDST n_DECODE) ............................................................ 150
93 INTDST n Interrupt Rate Control Register (INTDST n_RATE_CNTL) .............................................. 154
94 LSU n Control Register 0 (LSU n_REG0) ............................................................................... 155
95 LSU n Control Register 1 (LSU n_REG1) ............................................................................... 156
96 LSU n Control Register 2 (LSU n_REG2) ............................................................................... 157
97 LSU n Control Register 3 (LSU n_REG3) ............................................................................... 158
98 LSU n Control Register 4 (LSU n_REG4) ............................................................................... 159
99 LSU n Control Register 5 (LSU n_REG5) ............................................................................... 160
100 LSU n Control Register 6 (LSU n_REG6) ............................................................................... 161
101 LSU n Congestion Control Flow Mask Register (LSU n_FLOW_MASKS) ......................................... 162
SPRUE13A – September 2006 List of Figures 7
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102 LSU n FLOW_MASK Fields .............................................................................................. 162
103 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUE n_TXDMA_HDP) ......................... 164
104 Queue n Transmit DMA Completion Pointer Register (QUEUE n_TXDMA_CP) ................................. 165
105 Queue n Receive DMA Head Descriptor Pointer Register (QUEUE n_RXDMA_HDP) .......................... 166
106 Queue n Receive DMA Completion Pointer Register (QUEUE n_RXDMA_CP) .................................. 167
107 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) - Address Offset 0700h ................... 168
108 Transmit CPPI Supported Flow Mask Registers ..................................................................... 170
109 TX Queue n FLOW_MASK Fields ...................................................................................... 170
110 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) (Address Offset 0740h) ................... 172
111 Receive CPPI Control Register (RX_CPPI_CNTL) (Address Offset 0744h) ...................................... 173
112 Transmit CPPI Weighted Round Robin Control Registers .......................................................... 174
113 Mailbox to Queue Mapping Register Pair ............................................................................. 179
114 Flow Control Table Entry Register n (FLOW_CNTL n) ............................................................... 181
115 Device Identity CAR (DEV_ID) - Address Offset 1000h ............................................................. 182
116 Device Information CAR (DEV_INFO) - Address Offset 1004h .................................................... 183
117 Assembly Identity CAR (ASBLY_ID) - Address Offset 1008h ...................................................... 184
118 Assembly Information CAR (ASBLY_INFO) - Address Offset 100Ch ............................................. 185
119 Processing Element Features CAR (PE_FEAT) - Address Offset 1010h ......................................... 186
120 Source Operations CAR (SRC_OP) - Address Offset 1018h ....................................................... 188
121 Destination Operations CAR (DEST_OP) - Address Offset 101Ch ................................................ 189
122 Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch ....................... 190
123 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) - Address Offset 1058h ................ 191
124 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) - Address Offset 105Ch ................. 192
125 Base Device ID CSR (BASE_ID) - Address Offset 1060h .......................................................... 193
126 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) - Address Offset 1068h ............................ 194
127 Component Tag CSR (COMP_TAG) - Address Offset 106Ch ..................................................... 195
128 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) - Address Offset 1100h ........ 196
129 Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120h ......................................... 197
130 Port Response Time-Out Control CSR (SP_RT_CTL) - Address Offset 1124h .................................. 198
131 Port General Control CSR (SP_GEN_CTL) - Address Offset 113Ch .............................................. 199
132 Port Link Maintenance Request CSR n (SP n_LM_REQ) ........................................................... 200
133 Port Link Maintenance Response CSR n (SP n_LM_RESP) ........................................................ 201
134 Port Local AckID Status CSR n (SP n_ACKID_STAT) ............................................................... 202
135 Port Error and Status CSR n (SP n_ERR_STAT) ..................................................................... 203
136 Port Control CSR n (SP n_CTL) ......................................................................................... 206
137 Error Reporting Block Header Register (ERR_RPT_BH) - Address Offset 2000h ............................... 209
138 Logical/Transport Layer Error Detect CSR (ERR_DET) - Address Offset 2008h ................................ 210
139 Logical/Transport Layer Error Enable CSR (ERR_EN) - Address Offset 200Ch ................................. 212
140 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) - Address Offset 2010h ............. 214
141 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h ....................... 215
142 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) - Address Offset 2018h .......................... 216
143 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) - Address Offset 201Ch ........................ 217
144 Port-Write Target Device ID CSR (PW_TGT_ID) - Address Offset 2028h ........................................ 218
145 Port Error Detect CSR n (SP n_ERR_DET) ........................................................................... 219
146 Port Error Rate Enable CSR n (SP n_RATE_EN) .................................................................... 221
147 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) ........................................ 223
148 Port n Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) ............................................................. 224
149 Port n Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) ............................................................. 225
150 Port n Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) ............................................................. 226
151 Port n Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) ............................................................. 227
152 Port Error Rate CSR n (SP n_ERR_RATE) ............................................................................ 228
153 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) ........................................................... 229
154 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) - Address Offset 12000h .... 230
8 List of Figures SPRUE13A – September 2006
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155 Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h ...................................................... 231
156 Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008h ............................................. 233
157 Port-Write-In Capture CSRs ............................................................................................. 234
158 Port Reset Option CSR n (SP n_RST_OPT) .......................................................................... 235
159 Port Control Independent Register n (SP n_CTL_INDEP) ........................................................... 236
160 Port Silence Timer n Register (SP n_SILENCE_TIMER) ............................................................ 238
161 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) ............................ 239
162 Port Control Symbol Transmit n Register (SP n_CS_TX) ............................................................ 240
SPRUE13A – September 2006 List of Figures 9
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List of Tables
1 TI Devices Supported By This Document ............................................................................... 20
2 Registers Checked for Multicast DeviceID .............................................................................. 21
3 Packet Types ............................................................................................................... 25
4 Pin Description .............................................................................................................. 26
5 SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions ......................... 29
6 Line Rate versus PLL Output Clock Frequency ........................................................................ 30
7 Effect of the RATE Bits .................................................................................................... 30
8 Frequency Range versus MPY Value ................................................................................... 30
9 SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) Field Descriptions ........ 31
10 EQ Bits ....................................................................................................................... 33
11 SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) Field Descriptions ........ 33
12 DE Bits of SERDES_CFGTX n_CNTL ................................................................................... 34
13 SWING Bits of SERDES_CFGTX n_CNTL .............................................................................. 35
14 LSU Control/Command Register Fields ................................................................................. 36
15 LSU Status Register Fields ............................................................................................... 37
16 RX DMA State Head Descriptor Pointer (HDP) (Address Offset 600h–63Ch) ..................................... 46
17 RX DMA State Completion Pointer (CP) (Address Offset 680h–6BCh) ............................................ 46
18 RX Buffer Descriptor Field Descriptions ................................................................................. 47
19 TX DMA State Head Descriptor Pointer (HDP) (Address Offset 500h–53Ch) ..................................... 51
20 TX DMA State Completion Pointer (CP) (Address Offset 58h–5BCh) .............................................. 52
21 TX Buffer Descriptor Field Definitions ................................................................................... 52
22 Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) ................................... 56
23 Examples of DOORBELL_INFO Designations (See Figure 26 ) ..................................................... 64
24 Flow Control Table Entry Register n (FLOW_CNTL n) Field Descriptions .......................................... 67
25 Fields Within Each Flow Mask ............................................................................................ 68
26 Reset Hierarchy ............................................................................................................ 70
27 Global Enable and Global Enable Status Field Descriptions ......................................................... 72
28 Block Enable and Block Enable Status Field Descriptions ........................................................... 73
29 Peripheral Control Register (PCR) Field Descriptions................................................................. 74
30 Port Mode Register Settings .............................................................................................. 77
31 Multicast DeviceID Operation ............................................................................................. 81
32 Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTL n) Field Descriptions ...................... 81
33 Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTL n) Field Descriptions ......................... 82
34 Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ........................................ 83
35 Interrupt Condition Status and Clear Bits ............................................................................... 87
36 Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR .......................................... 90
37 Interrupt Conditions Shown in ERR_RST_EVNT_ICSR and Cleared With ERR_RST_EVNT_ICCR .......... 91
38 Interrupt Clearing Sequence for Special Event Interrupts ............................................................ 92
39 Interrupt Condition Routing Options ..................................................................................... 93
40 Serial RapidIO (SRIO) Registers ....................................................................................... 102
41 Peripheral ID Register (PID) Field Descriptions ...................................................................... 111
42 Peripheral Control Register (PCR) Field Descriptions ............................................................... 112
43 Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions ..................................... 113
44 Peripheral Global Enable Register (GBL_EN) Field Descriptions .................................................. 116
45 Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions ................................. 117
46 Block n Enable Registers and the Associated Blocks ............................................................... 119
47 Block n Enable Register (BLK n_EN) Field Descriptions ............................................................. 119
48 Block n Enable Status Registers and the Associated Blocks ....................................................... 120
49 Block n Enable Status Register (BLK n_EN_STAT) Field Descriptions ............................................ 120
10 List of Tables SPRUE13A – September 2006
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50 RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions ............................................ 121
51 RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions ............................................ 122
52 PF_16B_CNTL Registers ................................................................................................ 123
53 Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTL n) Field Descriptions ..................... 123
54 PF_8B_CNTL Registers ................................................................................................. 124
55 Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTL n) Field Descriptions ........................ 124
56 SERDES_CFGRX n_CNTL Registers and the Associated Ports ................................................... 125
57 SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) Field Descriptions ....... 125
58 EQ Bits ..................................................................................................................... 126
59 SERDES_CFGTX n_CNTL Registers and the Associated Ports ................................................... 128
60 SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) Field Descriptions ...... 128
61 DE Bits of SERDES_CFGTX n_CNTL .................................................................................. 129
62 SWING Bits of SERDES_CFGTX n_CNTL ............................................................................ 129
63 SERDES_CFG n_CNTL Registers and the Associated Ports ....................................................... 130
64 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL) Field Descriptions ........................ 130
65 DOORBELL n_ICSR Registers .......................................................................................... 132
66 DOORBELL n Interrupt Condition Status Register (DOORBELL n_ICSR) Field Descriptions ................... 132
67 DOORBELL n_ICCR Registers .......................................................................................... 133
68 DOORBELL n Interrupt Condition Clear Register (DOORBELL n_ICCR) Field Descriptions .................... 133
69 RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) Field Descriptions ............................. 134
70 RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) Field Descriptions .............................. 135
71 TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) Field Descriptions ............................. 136
72 TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) Field Descriptions .............................. 137
73 LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions ......................................... 138
74 LSU Interrupt Condition Clear Register (LSU_ICCR) Field Descriptions .......................................... 141
75 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) Field
Descriptions ............................................................................................................... 142
76 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) Field
Descriptions ............................................................................................................... 143
77 DOORBELL n_ICRR Registers .......................................................................................... 144
78 DOORBELL n Interrupt Condition Routing Register Field Descriptions ............................................ 144
79 RX CPPI Interrupt Condition Routing Register Field Descriptions ................................................. 145
80 TX CPPI Interrupt Condition Routing Register Field Descriptions ................................................. 146
81 LSU Interrupt Condition Routing Register Field Descriptions ....................................................... 148
82 Error, Reset, and Special Event Interrupt Condition Routing Register Field Descriptions ...................... 149
83 INTDST n_DECODE Registers and the Associated Interrupt Destinations ....................................... 150
84 Interrupt Status Decode Register (INTDST n_DECODE) Field Descriptions ...................................... 150
85 INTDST n_RATE_CNTL Registers and the Associated Interrupt Destinations ................................... 154
86 INTDST n Interrupt Rate Control Register (INTDST n_RATE_CNTL) Field Descriptions ........................ 154
87 LSU n_REG0 Registers and the Associated LSUs ................................................................... 155
88 LSU n Control Register 0 (LSU n_REG0) Field Descriptions ........................................................ 155
89 LSU n_REG1 Registers and the Associated LSUs ................................................................... 156
90 LSU n Control Register 1 (LSU n_REG1) Field Descriptions ........................................................ 156
91 LSU n_REG2 Registers and the Associated LSUs ................................................................... 157
92 LSU n Control Register 2 (LSU n_REG2) Field Descriptions ........................................................ 157
93 LSU n_REG3 Registers and the Associated LSUs ................................................................... 158
94 LSU n Control Register 3 (LSU n_REG3) Field Descriptions ........................................................ 158
95 LSU n_REG4 Registers and the Associated LSUs ................................................................... 159
96 LSU n Control Register 4 (LSU n_REG4) Field Descriptions ........................................................ 159
97 LSU n_REG5 Registers and the Associated LSUs ................................................................... 160
98 LSU n Control Register 5 (LSU n_REG5) Field Descriptions ........................................................ 160
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99 LSU n_REG6 Registers and the Associated LSUs ................................................................... 161
100 LSU n Control Register 6 (LSU n_REG6) Field Descriptions ........................................................ 161
101 LSU n_FLOW_MASKS Registers and the Associated LSUs ........................................................ 162
102 LSU n Congestion Control Flow Mask Register (LSU n_FLOW_MASKS) Field Descriptions ................... 162
103 LSU n FLOW_MASK Fields .............................................................................................. 162
104 QUEUE n_TXDMA_HDP Registers ..................................................................................... 164
105 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUE n_TXDMA_HDP) Field Descriptions ... 164
106 QUEUE n_TXDMA_CP Registers ....................................................................................... 165
107 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) Field Descriptions ............ 165
108 QUEUE n_RXDMA_HDP Registers ..................................................................................... 166
109 Queue n Receive DMA Head Descriptor Pointer Register (QUEUE n_RXDMA_HDP) Field Descriptions ... 166
110 QUEUE n_RXDMA_CP Registers ...................................................................................... 167
111 Queue n Receive DMA Completion Pointer Register (QUEUE n_RXDMA_CP) Field Descriptions ........... 167
112 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 168
113 TX_CPPI_FLOW_MASKS Registers and the Associated TX Queues ............................................ 169
114 TX Queue n FLOW_MASK Field Descriptions ........................................................................ 170
115 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 172
116 Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions ............................................ 173
117 Transmit CPPI Weighted Round Robin Control Register Field Descriptions ..................................... 175
118 Mailbox to Queue Mapping Registers and the Associated RX Mappers .......................................... 177
119 Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n) Field Descriptions ..................................... 179
120 Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n) Field Descriptions .................................... 179
121 FLOW_CNTL n Registers ................................................................................................ 181
122 Flow Control Table Entry Register n (FLOW_CNTL n) Field Descriptions ........................................ 181
123 Device Identity CAR (DEV_ID) Field Descriptions ................................................................... 182
124 Device Information CAR (DEV_INFO) Field Descriptions ........................................................... 183
125 Assembly Identity CAR (ASBLY_ID) Field Descriptions ............................................................. 184
126 Assembly Information CAR (ASBLY_INFO) Field Descriptions .................................................... 185
127 Processing Element Features CAR (PE_FEAT) Field Descriptions ............................................... 186
128 Source Operations CAR (SRC_OP) Field Descriptions ............................................................. 188
129 Destination Operations CAR (DEST_OP) Field Descriptions ....................................................... 189
130 Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions .............................. 190
131 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions ...................... 191
132 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions ........................ 192
133 Base Device ID CSR (BASE_ID) Field Descriptions ................................................................. 193
134 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions .................................. 194
135 Component Tag CSR (COMP_TAG) Field Descriptions ............................................................ 195
136 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Field Descriptions .............. 196
137 Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions ................................................. 197
138 Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions ........................................ 198
139 Port General Control CSR (SP_GEN_CTL) Field Descriptions .................................................... 199
140 SPn_LM_REQ Registers and the Associated Ports ................................................................. 200
141 Port Link Maintenance Request CSR n (SP n_LM_REQ) Field Descriptions ..................................... 200
142 SPn_LM_RESP Registers and the Associated Ports ................................................................ 201
143 Port Link Maintenance Response CSR n (SP n_LM_RESP) Field Descriptions ................................. 201
144 SP n_ACKID_STAT Registers and the Associated Ports ............................................................ 202
145 Port Local AckID Status CSR n (SP n_ACKID_STAT) Field Descriptions ......................................... 202
146 SP n_ERR_STAT Registers and the Associated Ports .............................................................. 203
147 Port Error and Status CSR n (SP n_ERR_STAT) Field Descriptions .............................................. 203
148 SP n_CTL Registers and the Associated Ports ....................................................................... 206
149 Port Control CSR n (SP n_CTL) Field Descriptions .................................................................. 206
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150 Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions ..................................... 209
151 Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ...................................... 210
152 Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions ....................................... 212
153 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions ................... 214
154 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions ............................. 215
155 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions ................................ 216
156 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions ............................... 217
157 Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions .............................................. 218
158 SP n_ERR_DET Registers and the Associated Ports ................................................................ 219
159 Port Error Detect CSR n (SP n_ERR_DET) Field Descriptions ..................................................... 219
160 SP n_RATE_EN Registers and the Associated Ports ................................................................ 221
161 Port Error Rate Enable CSR n (SP n_RATE_EN) Field Descriptions .............................................. 221
162 SP n_ERR_ATTR_CAPT_DBG0 Registers and the Associated Ports ............................................. 223
163 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) Field Descriptions ................. 223
164 SP n_ERR_CAPT_DBG1 Registers and the Associated Ports ..................................................... 224
165 Port n Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) Field Descriptions ...................................... 224
166 SP n_ERR_CAPT_DBG2 Registers and the Associated Ports ..................................................... 225
167 Port n Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) Field Descriptions ...................................... 225
168 SP n_ERR_CAPT_DBG3 Registers and the Associated Ports ..................................................... 226
169 Port n Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) Field Descriptions ...................................... 226
170 SP n_ERR_CAPT_DBG4 Registers and the Associated Ports ..................................................... 227
171 Port n Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) Field Descriptions ...................................... 227
172 SP n_ERR_RATE Registers and the Associated Ports .............................................................. 228
173 Port Error Rate CSR n (SP n_ERR_RATE) Field Descriptions ..................................................... 228
174 SP n_ERR_THRESH Registers and the Associated Ports .......................................................... 229
175 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) Field Descriptions ..................................... 229
176 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) Field Descriptions ............ 230
177 Port IP Mode CSR (SP_IP_MODE) Field Descriptions .............................................................. 231
178 Port IP Prescaler Register (IP_PRESCAL) Field Descriptions ..................................................... 233
179 Port-Write-In Capture CSR Field Descriptions ........................................................................ 234
180 SP n_RST_OPT Registers and the Associated Ports ................................................................ 235
181 Port Reset Option CSR n (SP n_RST_OPT) Field Descriptions .................................................... 235
182 SP n_CTL_INDEP Registers and the Associated Ports .............................................................. 236
183 Port Control Independent Register n (SP n_CTL_INDEP) Field Descriptions .................................... 236
184 SP n_SILENCE_TIMER Registers and the Associated Ports ....................................................... 238
185 Port Silence Timer n Register (SP n_SILENCE_TIMER) Field Descriptions ...................................... 238
186 SP n_MULT_EVNT_CS Registers and the Associated Ports ....................................................... 239
187 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) Field Descriptions ...... 239
188 SP n_CS_TX Registers and the Associated Ports .................................................................... 240
189 Port Control Symbol Transmit n Register (SP n_CS_TX) Field Descriptions ..................................... 240
SPRUE13A – September 2006 List of Tables 13
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About This Manual
This document describes the Serial RapidIO
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number represents 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com .
Implementing Serial RapidIO (SRIO) PCB Layout on a TMS320TCI6482 Hardware Design (literature
number SPRAAB0 ) specifies a complete printed circuit board (PCB) solution for the TCI6482 as well as a
list of compatible SRIO devices showing two DSPs connected via a 4x SRIO link. TI has performed the
simulation and system characterization to ensure all SRIO interface timings in this solution are met;
therefore, no electrical data/timing information is supplied here for this interface.
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189 ) gives an
introduction to the TMS320C62x™ and TMS320C67x™ DSPs, development tools, and third-party support.
TMS320C6000 Programmer's Guide (literature number SPRU198 ) describes ways to optimize C and
assembly code for the TMS320C6000™ DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301 ) introduces the Code
Composer Studio™ integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference Guide (literature number
SPRU321 ) describes the Code Composer Studio™ application programming interface (API), which allows
you to program custom plug-ins for Code Composer.
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 ) describes the
TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct
memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,
bandwidth management, and the memory and cache.
TMS320TCI648x Bootloader User's Guide(literature number SPRUEC7 ) describes the features of the
on-chip Bootloader provided with the TMS320TCI648x Digital Signal Processor (DSP). Included are
descriptions of the available boot modes and any interfacing requirements associated with them,
instructions on generating the boot table, and information on the different versions of the Bootloader.
Read This First
®
(SRIO) peripheral on the TMS320TCI648x™ devices.
Preface
SPRUE13A – September 2006
Preface14 SPRUE13A – September 2006
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Related Documentation From Texas Instruments
Trademarks
TMS320TCI648x, C6000, TMS320C62x, TMS320C67x, TMS320C6000, Code Composer Studio are
trademarks of Texas Instruments.
RapidIO is a registered trademark of RapidIO Trade Association.
InfiniBand is a trademark of the InfiniBand Trade Association.
SPRUE13A – September 2006 Read This First 15
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1 Overview
The RapidIO peripheral used in the TMS320TCI648x is called a serial RapidIO (SRIO). This chapter
describes the general operation of a RapidIO system, how this module is connected to the outside world,
the definitions of terms used within this document, and the features supported and not supported for
SRIO.
1.1 General RapidIO System
RapidIO
interconnect intended primarily as an intra-system interface for chip-to-chip and board-to-board
communications at Gigabyte-per-second performance levels. Uses for the architecture can be found in
connected microprocessors, memory, and memory mapped I/O devices that operate in networking
equipment, memory subsystems, and general purpose computing. Principle features of RapidIO include:
• Flexible system architecture allowing peer-to-peer communication
• Robust communication with error detection features
• Frequency and port width scalability
• Operation that is not software intensive
• High bandwidth interconnect with low overhead
• Low pin count
• Low power
• Low latency
®
is a non-proprietary high-bandwidth system level interconnect. It is a packet-switched
User's Guide
SPRUE13A – September 2006
Serial RapidIO (SRIO)
1.1.1 RapidIO Architectural Hierarchy
RapidIO is defined as a 3-layer architectural hierarchy.
• Logical layer: Specifies the protocols, including packet formats, which are needed by endpoints to
process transactions
• Transport layer: Defines addressing schemes to correctly route information packets within a system
• Physical layer: Contains the device level interface information such as the electrical characteristics,
error management data, and basic flow control data
In the RapidIO architecture, a single specification for the transport layer is compatible with differing
specifications for the logical and physical layers (see Figure 1 ).
16 Serial RapidIO (SRIO) SPRUE13A – September 2006
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Globally
shared
memory spec
logical
Future
Message
passingsystem
I/O
Logicalspecification
Informationnecessaryfortheendpoint
toprocessthetransaction(i.e.,transaction
type,size,physicaladdress)
toendinthesystem(i.e.,routingaddress)
Informationtotransportpacketfromend
Transportspecification
spec
transport
Common
betweentwophysicaldevices(i.e.,electrical
Informationnecessarytomovepacket
interface,flowcontrol)
Physicalspecification
1x/4x
LP serialLP-LVDS
8/16
Future
spec
physical
checklist
Compliance
Inter-
operability
specification
Figure 1. RapidIO Architectural Hierarchy
Overview
SPRUE13A – September 2006 Serial RapidIO (SRIO) 17
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HostSubsystem
I/OControlSubsystem
DSP Farm
TDM,GMII,Utopia
CommunicationsSubsystem PCISubsystem
InfiniBand HCA™
ToSystemArea
Network
Memory
Memory
Memory
Memory
RapidIO
RapidIO RapidIO
RapidIO
RapidIO
Backplane
PCI
RapidIO
RapidIO
RapidIO
RapidIO
Switch
Control
Processor
IO
Processor
RapidIOto
InfiniBand
RapidIO
Switch
RapidIO
Switch
Legacy
Comm
Processor
RapidIO
Switch
RapidIOto
PCIBridge
ASIC/FPGA
Memory
Memory
Host
Processor
Host
Processor
DSP DSP DSP DSP
Comm
Processor
Overview
1.1.2 RapidIO Interconnect Architecture
The interconnect architecture is defined as a packet switched protocol independent of a physical layer
implementation. Figure 2 illustrates the interconnection system.
Figure 2. RapidIO Interconnect Architecture
(1) InfiniBand™ is a trademark of the InfiniBand Trade Association.
1.1.3 Physical Layer 1x/4x LP-Serial Specification
Currently, there are two physical layer specifications recognized by the RapidIO Trade Association: 8/16
LP-LVDS and 1x/4x LP-Serial. The 8/16 LP-LVDS specification is a point-to-point synchronous clock
sourcing DDR interface. The 1x/4x LP-Serial specification is a point-to-point, AC coupled, clock recovery
interface. The two physical layer specifications are not compatible.
SRIO complies with the 1x/4x LP-Serial specification. The serializer/deserializer (SERDES) technology in
SRIO also aligns with that specification.
The RapidIO Physical Layer 1x/4x LP-Serial Specification currently covers three frequency points: 1.25,
2.5, and 3.125 Gbps. This defines the total bandwidth of each differential pair of I/O signals. An 8-bit/10-bit
encoding scheme ensures ample data transitions for the clock recovery circuits. Due to the 8-bit/10-bit
encoding overhead, the effective data bandwidth per differential pair is 1.0, 2.0, and 2.5 Gbps
respectively. Serial RapidIO only specifies these rates for both the 1x and 4x ports. A 1x port is defined as
1 TX and 1 RX differential pair. A 4x port is a combination of four of these pairs. This document describes
a 4x RapidIO port that can also be configured as four 1x ports, thus providing a scalable interface capable
of supporting a data bandwidth of 1 to 10 Gbps.
Figure 3 shows how to interface two 1x devices and two 4x devices. Each positive transmit data line (TDx)
on one device is connected to a positive receive data line (RDx) on the other device. Likewise, each
negative transmit data line ( TDx) is connected to a negative receive data line ( RDx).
18 Serial RapidIO (SRIO) SPRUE13A – September 2006
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SerialRapidIO1xDeviceto1xDeviceInterfaceDiagram
SerialRapidIO4xDeviceto4xDeviceInterfaceDiagram
1xDevice
TD[0]
TD[0]
RD[0]
RD[0] TD[0]
TD[0]
1xDevice
RD[0]
RD[0]
RD[0-3]
RD[0-3]
4xDevice
TD[0-3]
RD[0-3]
RD[0-3]
TD[0-3]
4xDevice
TD[0-3]
TD[0-3]
Figure 3. Serial RapidIO Device to Device Interface Diagrams
1.2 RapidIO Feature Support in SRIO
Features Supported in SRIO Peripheral:
• RapidIO Interconnect Specification V1.2 compliance, Errata 1.2
• Physical Layer 1x/4x LP-Serial Specification V1.2 compliance
• 4x Serial RapidIO with auto-negotiation to 1x port, optional operation for four 1x ports
• Integrated clock recovery with TI SERDES
• Hardware error handling including Cyclic Redundancy Code (CRC)
• Differential CML signaling supporting AC coupling
• Support for 1.25, 2.5, and 3.125 Gbps rates
• Power-down option for unused ports
• Read, write, write with response, streaming write, outgoing Atomic, and maintenance operations
• Generates interrupts to the CPU (Doorbell packets and internal scheduling)
• Support for 8-bit and 16-bit device ID
• Support for receiving 34-bit addresses
• Support for generating 34-bit, 50-bit, and 66-bit addresses
• Support for the following data sizes: byte, half-word, word, double-word
• Big endian data transfers
• Direct I/O transfers
• Message passing transfers
• Data payloads of up to 256 bytes
• Single messages consisting of up to 16 packets
• Elastic storage FIFOs for clock domain handoff
• Short run and long run compliance
• Support for Error Management Extensions
• Support for Congestion Control Extensions
• Support for one multi-cast ID
Overview
SPRUE13A – September 2006 Serial RapidIO (SRIO) 19
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Overview
Features Not Supported:
• Compliance with the Global Shared Memory specification (GSM)
• 8/16 LP-LVDS compatible
• Destination support of RapidIO Atomic Operations
• Simultaneous mixing of frequencies between 1x ports (all ports must be the same frequency)
• Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal
L2 memory and registers
1.3 Standards
The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specification and V1.2 of the
RapidIO Physical Layer 1x/4x LP-Serial Specification. These and the various associated documents listed
herein can be found at the official RapidIO website: www.RapidIO.org .
1.4 External Devices Requirements
SRIO provides a seamless interface to all devices which are compliant to V1.2 of the RapidIO Physical
Layer 1x/4x LP-Serial Specification. This includes ASIC, microprocessor, DSP, and switch fabric devices
from multiple vendors. Compliance to the specification can be verified with bus-functional models available
through the RapidIO Trade Association, as well as test suites currently available for licensing.
1.5 TI Devices Supported By This Document
Table 1. TI Devices Supported By This Document
Device DSP Cores (CPUs) Ports Lanes Configurations Frequency
TMS320TCI6482 1 4 4 1x/4x, 1x/1x DSP frequency ÷ 4
Number of Number of Number of SRIO Module
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2 SRIO Functional Description
2.1 Overview
2.1.1 Peripheral Data Flow
This peripheral is designed to be an externally driven slave module that is capable of acting as a master in
the DSP system. This means that an external device can push (burst write) data to the DSP as needed,
without having to generate an interrupt to the CPU or without relying on the DSP EDMA. This has several
benefits. It cuts down on the total number of interrupts, it reduces handshaking (latency) associated with
read-only peripherals, and it frees up the EDMA for other tasks.
SRIO specifies data packets with payloads up to 256 bytes. Many times, transactions will span across
multiple packets. RapidIO specifies a maximum of 16 transactions per message. Although a request is
generated for each packet transaction so that the DMA can transfer the data to L2 memory, an interrupt is
only generated after the final packet of the message. This interrupt notifies the CPU that data is available
in L2 Memory for processing.
As an endpoint device, the peripheral accepts packets based on the destination ID. Two options exist for
packet acceptance and are mode selectable. The first option is to only accept packets whose DestIDs
match the local deviceID in 0x0080. This provides a level of security. The second option is is system
multicast operation. When multicast is enabled in SP_IP_MODE (offset 12004h) bit 5, incoming packets
matching the deviceID in the registers shown in are accepted.
TMS320TCI6482 Local DeviceID Register 0080h
SRIO Functional Description
Table 2. Registers Checked for Multicast DeviceID
Registers Checked For Multicast DeviceID
Device Name Address Offset
Multicast DeviceID Register 0084h
Data flow through the peripheral can be explained using the high-level block diagram shown in Figure 4 .
High-speed data enters from the device pins into the RX block of the SERDES macro. The RX block is a
differential receiver expecting a minimum of 175mV peak-to-peak differential input voltage (Vid). Level
shifting is performed in the RX block, such that the output is single ended CMOS. The serial data is then
fed to the SERDES clock recovery block. The sole purpose of this block is to extract a clock signal from
the data stream. To do this, a low-frequency reference clock is required. Typically, this clock comes from
an off-chip stable crystal oscillator and is a LVDS device input separate to the SERDES. This clock is
distributed to the SERDES PLL block which multiplies that frequency up to that of the data rate. Multiple
high-speed clock phases are created and routed to the clock recovery blocks. The clock recovery blocks
further interpolate between these clocks to provide maximum Unit Interval (UI) resolution on the recovered
clock. The clock recovery block samples the incoming data and monitors the relative positions of the data
edges. With this information, it can provide the data and a center-aligned clock to the S2P block. The S2P
block uses the newly recovered clock to de-multiplex the data into 10-bit words. At this point, the data
leaves the SERDES macro at 1/10th the pin data rate, accompanied by an aligned byte clock.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 21
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1.25to3.125Gbps
differentialdata
RX
Clock
recovery
S2P
10b
Clk
8b/10b
decode
8b
Clock
recovery
RX
8b8b/10b
decode
10b
ClkS2P
Clock
recovery
RX
8b8b/10b
decode
10b
ClkS2P
Clock
recovery
RX
8b8b/10b
decode
10b
ClkS2P
PLL
TX
TX
TX
TX
P2S
P2S
P2S
P2S
8b
8b
8b
8b
10b
8b/10b
coding
Clk
8b/10b
coding
8b/10b
coding
8b/10b
coding
10b
Clk
10b
Clk
10b
Clk
FIFO
FIFO
FIFO
FIFO
System
clock
Capability
registers
Control
Command
andstatus
registers
SERDES
Clockdomain2
Clockdomain3
Clockdomain1
DMA
bus
PacketGeneration
Lanestriping
Lanede-skew
CRCerrordetection
CRCgeneration
Buf
feringaddressanddatahandoff
FIFO
FIFO
FIFO
FIFO
SRIO Functional Description
Figure 4. SRIO Peripheral Block Diagram
Within the physical layer, the data next goes to the 8-bit/10-bit (8b/10b) decode block. 8b/10b encoding is
used by RapidIO to ensure adequate data transitions for the clock recovery circuits. Here the 20%
encoding overhead is removed as the 10-bit data is decoded to the raw 8-bit data. At this point, the
recovered byte clock is still being used.
The next step is clock synchronization and data alignment. These functions are handled by the FIFO and
lane de-skewing blocks. In the RapidIO Interconnect Specification, a "lane" is one serial differential pair.
The FIFO provides an elastic store mechanism used to hand off between the recovered clock domains
and a common system clock. After the FIFO, the four lanes are synchronized in frequency and phase,
whether 1X or 4X mode is being used. The FIFO is 8 words deep. The lane de-skew is only meaningful in
the 4X mode, where it aligns each channel’s word boundaries, such that the resulting 32-bit word is
correctly aligned.
The CRC error detection block keeps a running tally of the incoming data and computes the expected
CRC value for the 1X or 4X mode. The expected value is compared against the CRC value at the end of
the received packet.
After the packet reaches the logical layer, the packet fields are decoded and the payload is buffered.
Depending on the type of received packet, the packet routing is handled by functional blocks which control
the DMA access.
2.1.2 SRIO Packets
2.1.2.1 Operation Sequence
22 Serial RapidIO (SRIO) SPRUE13A – September 2006
The SRIO data stream consists of data fields pertaining to the logical layer, the transport layer, and the
physical layer.
• The logical layer consists of the header (defining the type of access) and the payload (if present).
• The transport layer is partially dependent on the physical topology in the system, and consists of
source and destination IDs for the sending and receiving devices.
• The physical layer is dependent on the physical interface (i.e., serial versus parallel RapidIO) and
includes priority, acknowledgment, and error checking fields.
SRIO transactions are based on request and response packets. Packets are the communication element
between endpoint devices in the system. A master or initiator generates a request packet which is
transmitted to a target. The target then generates a response packet back to the initiator to complete the
transaction.
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Initiator
Request
PacketIssued
Operation
Completedfor
Master
Acknowledge
Symbol
Acknowledge
Symbol
Response
Packet
Forwarded
RequestPacket
Forwarded
Acknowledge
Symbol
Acknowledge
Symbol
ResponsePacket
Issued
Fabric
Target
Target
Completes
Operation
Operation
IssuedBy
Master
SRIO Functional Description
SRIO endpoints are typically not connected directly to each other but instead have intervening connection
fabric devices. Control symbols are used to manage the flow of transactions in the SRIO physical
interconnect. Control symbols are used for packet acknowledgment, flow control information, and
maintenance functions. Figure 5 shows how a packet progresses through the system.
Figure 5. Operation Sequence
2.1.2.2 Example Packet – Streaming Write
An example packet is shown as two data streams in Figure 6 . The first is for payload sizes of 80 bytes or
less, while the second applies to payload sizes of 80 to 256 bytes. SRIO packets must have a length that
is an even integer of 32 bits. If the combination of physical, logical and transport layers has a length that is
an integer of 16 bits, a 16-bit pad of value 0000h is added to the end of the packet, after the CRC (not
shown). Bit fields that are defined as reserved are assigned to logic 0s when generated and ignored when
received. All request and response packet formats are described in the RapidIO Input/Output Logical
Specification and MIessage Passing Logical Specification.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 23
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double-word0
4
double-wordn-1
acklD rsv
prio
tt ftype
destID
sourcelD
address
rsrv
xamsbs
double-word1
...
double-wordn-2
CRC
PHY
LOG
TRA
LOG
TRA
PHY
5
3
2
2
8
8
29
1
2
64 64
(n-4)*64
64
64
16
16
n*64+32
16
4
2
10
LOG
PHY10TRA
2 4
9 * 6 4 + 32
LOG
TRA
16
PHY
16
double-word0
5
ac kl D sourcelD
rsv
3
prio
2
ftype
tt
2 4
destID
8
1
rsrvaddress
8 29
xamsbs
2
64
double-word8
double-word1
64
5*64
...
64
double-word9
64
CRC
16
LOG
(n-9)*64
16
PHY
double-word10
64
double-wordn-2double-word11
64
(n-13)*64
...
double-wordn-1
6464 16
CRC
n*64+96
n*64+80
PHY =Physicallayer
TRA = Transportlayer
LOG=Logicallayer
SCorPD parameter1stype0 stype1Parameter0 cmd CRC
533553
Delimiter 1stByte 2ndByte 3rdByte
8
SRIO Functional Description
Figure 6. 1x/4x RapidIO Packet Data Stream (Streaming-Write Class)
Note: Figure 6 assumes that addresses are 32-bit and device IDs are 8-bit.
The device ID, being an 8-bit field, will address up to 256 nodes in the system. If 16-bit addresses were
used, the system could accommodate up to 64k nodes.
The data stream includes a Cyclic Redundancy Code (CRC) field to ensure the data was correctly
received. The CRC value protects the entire packet except the ackID and one bit of the reserved PHY
field. The peripheral checks the CRC automatically in hardware. If the CRC is correct, a Packet-Accepted
control symbol is sent by the receiving device. If the CRC is incorrect, a Packet-Not-Accepted control
symbol is sent so that transmission may be retried.
2.1.2.3 Control Symbols
Control symbols are physical layer message elements used to manage link maintenance, packet
delimiting, packet acknowledgment, error reporting, and error recovery. All transmitted data packets are
delimited by start-of-packet and end-of-packet delimiters. SRIO control symbols are 24 bits long and are
protected by their own CRC (see Figure 7 ). Control symbols provide two functions: stype0 symbols
convey the status of the port transmitting the symbol, and stype1 symbols are requests to the receiving
port or transmission delimiters. They have the following format, which is detailed in Section 3 of the
RapidIO Physical Layer 1x/4x LP-Serial Specification.
Figure 7. Serial RapidIO Control Symbol Format
Control symbols are delimited by special characters at the beginning of the symbol. If the control symbol
contains a packet delimiter(start-of-packet, end-of-packet, etc.), the special character PD (K28.3) is used.
If the control symbol does not contain a packet delimiter, the special character SC (K28.0) is used. This
use of special characters provides an early warning of the contents of the control symbol. The CRC does
not protect the special characters, but an illegal or invalid character is recognized and flagged as
Packet-Not-Accepted. Since control symbols are known length, they do not need end delimiters.
24 Serial RapidIO (SRIO) SPRUE13A – September 2006
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The type of received packet determines how the packet routing is handled. Reserved or undefined packet
types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous
allocation of resources to them. Unsupported packet types are responded to with an error response
packet. Section 2.1.2.4 details the handling of such packets.
2.1.2.4 SRIO Packet Type
The type of SRIO packet is determined by the combination of Ftype and Ttype fields in the packet. Table 3
lists all supported combinations of Ftype/Ttype and the corresponding decoded actions on the packets.
Ftype Ttype Packet Type
Ftype = 0 Ttype = don't care
Ftype = 2 Ttype = 0100b NREAD
Ftype = 5 Ttype = 0100b NWRITE
Ftype = 6 Ttype = don't care SWRITE
Ftype = 7 Ttype = don't care Congestion control
Ftype = 8 Ttype = 0000b Maintenance read
Ftype = 10 Ttype = don't care Doorbell
Ftype = 11 Ttype = don't care Message
Ftype = 13 Ttype = 0000b Response(+Doorbell Resp)
Undefined Ftypes: 1,3,4,9,12,14,15
SRIO Functional Description
Table 3. Packet Types
Ttype = 1100b Atomic increment
Ttype = 1101b Atomic decrement
Ttype = 1110b Atomic set
Ttype = 1111b Atomic clear
Ttype = others
Ttype = 0101b NWRITE_R
Ttype = 1110b Atomic test and swap
Ttype = others
Ttype = 0001b Maintenance write
Ttype = 0010b Maintenance read response
Ttype = 0011b Maintenance write response
Ttype = 0100b Maintenance port-write
Ttype = others
Ttype = 0001b Message Response
Ttype = 1000b Response w/payload
Ttype = other
2.2 SRIO Pins
The SRIO device pins are high-speed differential signals based on Current-Mode Logic (CML) switching
levels. The transmit and receive buffers are self-contained within the clock recovery blocks. The reference
clock input is not incorporated into the SERDES macro. It uses a differential input buffer that is compatible
with the LVDS and LVPECL interfaces available from crystal oscillator manufacturers. Table 4 describes
the device pins for the SRIO peripheral.
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SRIO Functional Description
Table 4. Pin Description
Pin Signal
Pin Name Count Direction Description
RIOTX3/ RIOTX3 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Most significant bits in 1
port 4X device. Used in 4 port 1X device.
RIOTX2/ RIOTX2 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Bit used in 4 port 1x
device and 1 port 4X device.
RIOTX1/ RIOTX1 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Bit used in 4 port 1x
device and 1 port 4X device.
RIOTX0/ RIOTX0 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Bit used in 1 port 1X
device, 4 port 1x device, and 1 port 4X device.
RIORX3/ RIORX3 2 Input Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Most significant bits in
1 port 4X device. Used in 4 port 1X device.
RIORX2/ RIORX2 2 Input Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Bit used in 4 port 1x
device and 1 port 4X device.
RIORX1/ RIORX1 2 Input Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Bit used in 4 port 1x
device and 1 port 4X device.
RIORX0/ RIORX0 2 Input Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Bit used in 1 port 1X
device, 4 port 1x device, and 1 port 4X device.
RIOCLK/ RIOCLK 2 Input Reference Clock Input Buffer for peripheral clock recovery circuitry.
2.3 Functional Operation
2.3.1 Component Block Diagram
Figure 8 shows a component block diagram of the SRIO peripheral. The load/store unit (LSU) controls the
transmission of direct I/O packets, and the memory access unit (MAU) controls the reception of direct I/O
packets. The LSU also controls the transmission of maintenance packets. Message packets are
transmitted by the TXU and received by the RXU. These four units use the internal DMA to communicate
with internal memory, and they use buffers and receive/transmit ports to communicate with external
devices. Serializer/deserializer (SERDES) macros support the ports by performing the parallel-to-serial
coding for transmission and serial-to-parallel decoding for reception.
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Port0
8x276 TX
8x276RX
8x276RX
8x276 TX
Port1
8x276 TX
8x276RX
Port2
8x276RX
8x276 TX
Port3
Physical
layer
buffers
SERDES0 SERDES1 SERDES2 SERDES3
SERDES
differential
signals
4xmode
datapath
TXbuffering
32x276B
8buffersper1Xport-allpriorities
32buffersper4Xport-8perpriority
Transaction
mapping
layer
buffers
Logical
Load/Store
units(LSUs)
TXdirectI/O
Maintenance
Messaging
TXU
RXdirectI/O
(MAU)
Memory
accessunit
RXU
Messaging
buffer
4.5KB TX
shared
buffer
shared
4.5KBRX
handle
Queue
DMA bus
UDI
Figure 8. SRIO Component Block Diagram
SRIO Functional Description
SPRUE13A – September 2006 Serial RapidIO (SRIO) 27
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SRIO Functional Description
2.3.2 SERDES Macro and its Configurations
SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of
TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can
be used for all three frequency nodes specified in V1.2 of the RapidIO Interconnect Specification (1.25,
2.5, and 3.125 Gbps). This allows you to design to only one protocol throughout the system and
selectively choose the bandwidth, thus eliminating the need for user’s proprietary protocols in many
instances, and providing a faster design turn and production ramp. Since this interface is serial, the
application space is not limited to a single board. It will propagate into backplane applications as well.
Integration of these macros on an ASIC or DSP allows you to reduce the number of discrete components
on the board and eliminates the need for bus driver chips.
Additionally, there are some valuable features built into TI SERDES. System optimization can be uniquely
managed to meet individual customer applications. For example, control registers within the SERDES
allow you to adjust the TX differential output voltage (Vod) on a per driver basis. This allows power
savings on short trace links (on the same board) by reducing the TX swing. Similarly, data edge rates can
be adjusted through the control registers to help reduce any EMI affects. Unused links can be individually
powered down without affecting the working links.
The SERDES macro is a self-contained macro which includes transmitter (TX), receiver (RX),
phase-locked-loop (PLL), clock recovery, serial-to-parallel (S2P), and parallel-to-serial (P2S) blocks. The
internal PLL multiplies a user-supplied reference clock. All loop filter components of the PLL are onchip.
Likewise, the differential TX and RX buffers contain on-chip termination resistors. The only off-chip
component requirement is for DC blocking capacitors.
2.3.2.1 Enabling the PLL
The Physical layer SERDES has a built-in PLL, which is used for the clock recovery circuitry. The PLL is
responsible for clock multiplication of a slow speed reference clock. This reference clock has no timing
relationship to the serial data and is asynchronous to any CPU system clock. The multiplied high-speed
clock is only routed within the SERDES block; it is not distributed to the remaining blocks of the peripheral,
nor is it a boundary signal to the core of the device. It is extremely important to have a good quality
reference clock, and to isolate it and the PLL from all noise sources. Since RapidIO requires 8-bit/10-bit
encoded data, the 8-bit mode of the SERDES PLL is not be used.
The SERDES macro is configured with the register SERDES_CFG0_CNTL, SERDES_CFGRX n_CNTL,
and SERDES_CFGTX n_CNTL, where n is the number of the macro. To enable the internal PLL, the
ENPLL bit of SERDES_CFG0_CNTL (see Figure 9 and Table 5 ) must be set. After setting this bit, it is
necessary to allow 1µs for the regulator to stabilize. Thereafter, the PLL will take no longer than 200
reference clock cycles to lock to the required frequency, provided RIOCLK and RIOCLK are stable.
Registers SERDES_CFG1_CNTL, SERDES_CFG2_CNTL, and SERDES_CFG3_CNTL are not used.
Figure 9. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL)
31 16
Reserved
R-0000h
15 10 9 8 7 6 5 1 0
Reserved LB Reserved MPY ENPLL
R-00h R/W-0 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
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SRIO Functional Description
Table 5. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions
Bit Field Value Description
31–10 Reserved 0000h Reserved
9–8 LB Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock will
00b Frequency dependent bandwidth. The PLL bandwidth is set to a twelfth of the
01b Reserved
10b Low bandwidth. The PLL bandwidth is set to a twentieth of the frequency of
11b High bandwidth. The PLL bandwidth is set to a eighth of the frequency of
7–6 Reserved 00h Reserved
5–1 MPY PLL multiply. Select PLL multiply factors between 4 and 60.
00000b 4x
00001b 5x
00010b 6x
00011b Reserved
00100b 8x
00101b 10x
00110b 12x
00111b 12.5x
01000b 15x
01001b 20x
01010b 25x
01011b Reserved
01100b Reserved
01111b Reserved
1xxxxb Reserved
0 ENPLL Enable PLL
0 PLL disabled
1 PLL enabled
degrade both the transmit eye and receiver jitter tolerance thereby impairing system
performance. Performance of the integrated PLL can be optimized according to the
jitter characteristics of the reference clock via the LB field.
frequency of RIOCLK/ RIOCLK. This setting is suitable for most systems that input the
reference clock via a low jitter input cell, and is required for standards compliance
RIOCLK/ RIOCLK, or 3MHz (whichever is larger). In systems where the reference
clock is directly input via a low jitter input cell, but is of lower quality, this setting may
offer better performance. It will reduce the amount of reference clock jitter transferred
through the PLL. However, it also increases the susceptibility to loop noise generated
within the PLL itself. It is difficult to predict whether the improvement in the former will
more than offset the degradation in the latter.
RIOCLK/ RIOCLK. This is the setting appropriate for systems where the reference
clock is cleaned through an ultra low jitter LC-based PLL. Standards compliance will
be achieved even if the reference clock input to the cleaner PLL is outside the
specification for the standard.
Based on the MPY value, the line rate versus PLL output clock frequency can be calculated. This is
summarized in Table 6 .
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SRIO Functional Description
Table 6. Line Rate versus PLL Output Clock Frequency
Rate Line Rate PLL Output Frequency RATESCALE
Full x Gbps 0.5x GHz 0.5
Half x Gbps x GHz 1
Quarter x Gbps 2x GHz 2
RIOCLK and RIOCLK
FREQ
= LINERATE × RATESCALE
MPY
The rate is defined by the RATE bits of the SERDES_CFGRX n_CNTL register and the
SERDES_CFGTX n_CNTL register, respectively.
The primary operating frequency of the SERDES macro is determined by the reference clock frequency
and PLL multiplication factor. However, to support lower frequency applications, each receiver and
transmitter can also be configured to operate at a half or quarter of this rate via the RATE bits of the
SERDES_CFGRX n_CNTL and SERDES_CFGTX n_CNTL registers as described in Table 7 .
Table 7. Effect of the RATE Bits
RATE Description
00b Full rate. Two data samples taken per PLL output clock cycle.
01b Half rate. One data sample taken per PLL output clock cycle.
10b Quarter rate. One data sample taken every two PLL output clock cycles.
11b Reserved.
Table 8 shows the frequency range versus the multiplication factor (MPY).
Table 8. Frequency Range versus MPY Value
RIOCLK and RIOCLK Line Rate Range (Gbps)
MPY Range (MHz) Full Half Quarter
4x 250 - 425 2 - 3.4 1 - 1.7 0.5 - 0.85
5x 200 - 425 2 - 4.25 1 - 2.125 0.5 - 1.0625
6x 167 - 354.167 2 - 4.25 1 - 2.125 0.5 - 1.0625
8x 125 - 265.625 2 - 4.25 1 - 2.125 0.5 - 1.0625
10x 100 - 212.5 2 - 4.25 1 - 2.125 0.5 - 1.0625
12x 83.33 - 177.08 2 - 4.25 1 - 2.125 0.5 - 1.0625
12.5x 80 - 170 2 - 4.25 1 - 2.125 0.5 - 1.0625
15x 66.67 - 141.67 2 - 4.25 1 - 2.125 0.5 - 1.0625
20x 50 - 106.25 2 - 4.25 1 - 2.125 0.5 - 1.0625
25x 40 - 85 2 - 4.25 1 - 2.125 0.5 - 1.0625
2.3.2.2 Enabling the Receiver
To enable a receiver for deserialization, the ENRX bit of the associated SERDES_CFGRX n_CNTL
registers (100h–10Ch) must be set high. The fields of SERDES_CFGRX n_CNTL are shown in Figure 10
and described in Table 9 .
When ENRX is low, all digital circuitry within the receiver will be disabled, and clocks will be gated off. All
current sources within the receiver will be fully powered down, with the exception of those associated with
the loss of signal detector and IEEE1149.6 boundary scan comparators. Loss of signal power down is
independently controlled via the LOS bits of SERDES_CFGRX n_CNTL. When enabled, the differential
signal amplitude of the received signal is monitored. Whenever loss of signal is detected, the clock
recovery algorithm is frozen to prevent the phase and frequency of the recovered clock from being
modified by low level signal noise.
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SRIO Functional Description
The clock recovery algorithms listed in the CDR bits operate to adjust the clocks used to sample the
received message so that the data samples are taken midway between data transitions. The second order
algorithm can be optionally disabled, and both can be configured to optimize their dynamics. Both
algorithms use the same basic technique for determining whether the sampling clock is ideally placed, and
if not whether it needs to be moved earlier or later. When two contiguous data samples are different, the
phase sample between the two is examined. Eight data samples and nine phase samples are taken with
each result counted as a vote to move the sample point either earlier or later. These eight data bits
constitute the voting window. The eight votes are then counted, and an action to adjust the position of the
sampling clock occurs if there is a majority of early or late votes. The first order algorithm makes a single
phase adjustment per majority vote. The second order algorithm acts repeatedly according to the net
difference between early and late majority votes, thereby adjusting for the rate of change of phase.
Setting the ALIGN field to 01 enables alignment to the K28 comma symbols included in the 8b:10b data
encoding scheme defined by the IEEE and employed by numerous transmission standards. For systems
which cannot use comma based symbol alignment, the single bit alignment jog capability provides a
means to control the symbol realignment features of the receiver directly from logic implemented in the
ASIC core. This logic can be designed to support whatever alignment detection protocol is required.
The EQ bits allow for enabling and configuring the adaptive equalizer incorporated in all of the receive
channels, which can compensate for channel insertion loss by attenuating the low frequency components
with respect to the high frequency components of the signal, thereby reducing inter-symbol interference.
Above the zero frequency, the gain increases at 6dB/octave until it reaches the high frequency gain. When
enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether
the low frequency gain of the equalizer should be increased or decreased. For the fully adaptive setting
(EQ = 0001), if the low frequency gain reaches the minimum value, the zero frequency is then reduced.
Likewise, if it reaches the maximum value, the zero frequency is then increased. This decision logic is
implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that
results reduces the probability of incorrect decisions but allows the equalizer to compensate for the
relatively stable response of the channel.
• No adaptive equalization. The equalizer provides a flat response at the maximum gain. This setting
may be appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than
frequency dependent loss.
• Fully adaptive equalization. Both the low frequency gain and zero position of the equalizer are
determined algorithmically by analysing the data patterns and transition positions in the received data.
This setting should be used for most applications.
• Partially adaptive equalisation. The low frequency gain of the equalizer is determined algorithmically by
analysing the data patterns and transition positions in the received data. The zero position is fixed in
one of eight zero positions. For any given application, the optimal setting is a function of the loss
characteristics of the channel and the spectral density of the signal as well as the data rate, which
means it is not possible to identify the best setting by data rate alone, although generally speaking, the
lower the line rate, the lower the zero frequency that will be required.
Figure 10. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL)
31 26 25 24 23 22 19 18 16
Reserved — EQ CDR
R-0 R/W-0 R-0 R/W-0 R/W-0
15 14 13 12 11 10 8 7 6 5 4 2 1 0
LOS ALIGN — INVPAIR RATE BUSWIDTH ENRX
R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
(write 001b) (write 0)
Reserved
(write 0s)
TERM —
Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) Field
Descriptions
Bit Field Value Description
31–26 Reserved 000000b These read-only bits return 0s when read.
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SRIO Functional Description
Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) Field
Descriptions (continued)
Bit Field Value Description
25–24 Reserved 00b Always write 0s to these reserved bits.
23 Reserved 0 This read-only bit returns 0 when read.
22–19 EQ 0000b–1111b Equalizer. Enables and configures the adaptive equalizer to compensate for loss
in the transmission media. For the selectable values, see Table 10 .
18–16 CDR Clock/data recovery. Configures the clock/data recovery algorithm.
000b First order. Phase offset tracking up to ± 488 ppm.
001b Second order. Highest precision frequency offset matching but poorest response
to changes in frequency offset, and longest lock time. Suitable for use in systems
with fixed frequency offset.
010b Second order. Medium precision frequency offset matching, frequency offset
change response, and lock time.
011b Second order. Best response to changes in frequency offset and fastest lock time,
but lowest precision frequency offset matching. Suitable for use in systems with
spread spectrum clocking.
100b First order with fast lock. Phase offset tracking up to ± 1953 ppm in the presence of
..10101010.. training pattern, and ± 448 ppm otherwise.
101b Second order with fast lock. As per setting 001, but with improved response to
changes in frequency offset when not close to lock.
110b Second order with fast lock. As per setting 010, but with improved response to
changes in frequency offset when not close to lock.
111b Second order with fast lock. As per setting 011, but with improved response to
changes in frequency offset when not close to lock.
15–14 LOS Loss of signal. Enables loss of signal detection with 2 selectable thresholds.
00b Disabled. Loss of signal detection disabled.
01b High threshold. Loss of signal detection threshold in the range 85 to 195mV
This setting is suitable for Infiniband.
10b Low threshold. Loss of signal detection threshold in the range 65 to 175mV
This setting is suitable for PCI-E and S-ATA.
11b Reserved
13–12 ALIGN Symbol alignment. Enables internal or external symbol alignment.
00b Alignment disabled. No symbol alignment will be performed while this setting is
selected, or when switching to this selection from another.
01b Comma alignment enabled. Symbol alignment will be performed whenever a
misaligned comma symbol is received.
10b Alignment jog. The symbol alignment will be adjusted by one bit position when this
mode is selected (that is, the ALIGN value changes from 0xb to 1xb).
11b Reserved
11 Reserved 0 This read-only bit returns 0 when read.
10–8 TERM 001b Input termination. The only valid value for this field is 001b; all other values are
reserved. The value 001b sets the common point to 0.8 VDDT and supports AC
coupled systems using CML transmitters. The transmitter has no effect on the
receiver common mode, which is set to optimize the input sensitivity of the
receiver. Common mode termination is via a 50 pF capacitor to VSSA.
7 INVPAIR Invert polarity. Inverts polarity of RIORXn and RIORXn.
0 Normal polarity. RIORXn is considered to be positive data and RIORXn negative.
1 Inverted polarity. RIORXn is considered to be negative data and RIORXn positive.
6–5 RATE Operating rate. Selects full, half, or quarter rate operation.
00b Full rate. Two data samples taken per PLL output clock cycle.
01b Half rate. One data sample taken per PLL output clock cycle.
10b Quarter rate. One data sample taken every two PLL output clock cycles.
11b Reserved
.
dfpp
.
dfpp
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SRIO Functional Description
Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) Field
Descriptions (continued)
Bit Field Value Description
4–2 BUSWIDTH 000b Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to
1 Reserved 0 Always write 0 to this reserved bit.
0 ENRX Enable receiver
0 Disable this receiver.
1 Enable this receiver.
the clock. All other values are reserved. See Section 2.3.2.1 for an explanation of
the bus.
Table 10. EQ Bits
CFGRX[22–19] Low Freq Gain Zero Freq (at e28(min))
0000b Maximum –
0001b Adaptive Adaptive
001xb Reserved
01xxb Reserved
1000b Adaptive 1084MHz
1001b 805MHz
1010b 573MHz
1011b 402MHz
1100b 304MHz
1101b 216MHz
1110b 156MHz
1111b 135MHz
2.3.2.3 Enabling the Transmitter
To enable a transmitter for serialization, the ENTX bit of the associated SERDES_CFGTX n_CNTL
registers (110h–10Ch) must be set high. When ENTX is low, all digital circuitry within the transmitter will
be disabled, and clocks will be gated off, with the exception of the transmit clock (TXBCLK[ n]) output,
which will continue to operate normally. All current sources within the transmitter will be fully powered
down, with the exception of the current mode logic (CML) driver, which will remain powered up if boundary
scan is selected. Figure 11 shows the fields of SERDES_CFGTX n_CNTL and Table 11 describes them.
Figure 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL)
31 17 16
Reserved ENFTP
R-0 R/W-1
15 12 11 9 8 7 6 5 4 2 1 0
DE SWING CM INVPAIR RATE BUSWIDTH (write 0) ENTX
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
Table 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) Field
Descriptions
Bit Field Value Description
31–17 Reserved 0 These read-only bits return 0s when read.
16 ENFTP 1 Enables fixed phase relationship of transmit input clock with respect to transmit output
clock. The only valid value for this field is 1b; all other values are reserved.
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SRIO Functional Description
Table 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) Field
Descriptions (continued)
Bit Field Value Description
15–12 DE 0000b–1111b De-emphasis. Selects one of 15 output de-emphasis settings from 4.76 to 71.42%.
11–9 SWING 000b–111b Output swing. Selects one of 8 outputs amplitude settings between 125 and
8 CM Common mode. Adjusts the common mode to suit the termination at the attached
0 Normal common mode. Common mode not adjusted.
1 Raised common mode. Common mode raised by 5% of difference between RIOTXn
7 INVPAIR Invert polarity. Inverts the polarity of RIOTXn and RIOTXn.
0 Normal polarity. RIOTXn is considered to be positive data and RIOTXn negative.
1 Inverted polarity. RIOTXn is considered to be negative data and RIOTXn positive.
6–5 RATE Operating rate. Selects full, half, or quarter rate operation.
00b Full rate. Two data samples taken per PLL output clock cycle.
01b Half rate. One data sample taken per PLL output clock cycle.
10b Quarter rate. One data sample taken every two PLL output clock cycles.
11b Reserved
4–2 BUSWIDTH 000b Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to the
1 Reserved 0 Always write 0 to this reserved bit.
0 ENTX Enable transmitter
0 Disable this transmitter.
1 Enable this transmitter.
De-emphasis provides a means to compensate for high frequency attenuation in the
attached media. It causes the output amplitude to be smaller for bits which are not
preceded by a transition than for bits which are. See Table 12 .
1250mV
receiver. For output swing settings above 750mV, this reduced common mode can
cause distortion of the waveform. Under these conditions, this bit should be set high to
offset some of the common mode reduction.
and RIOTXn
clock. All other values are reserved. See Section 2.3.2.1 for an explanation of the bus.
. See Table 13 .
dfpp
Table 12. DE Bits of SERDES_CFGTX n_CNTL
Amplitude Reduction
DE Bits % dB
0000b 0 0
0001b 4.76 –0.42
0010b 9.52 –0.87
0011b 14.28 –1.34
0100b 19.04 –1.83
0101b 23.8 –2.36
0110b 28.56 –2.92
0111b 33.32 –3.52
1000b 38.08 –4.16
1001b 42.85 –4.86
1010b 47.61 –5.61
1011b 52.38 –6.44
1100b 57.14 –7.35
1101b 61.9 –8.38
1110b 66.66 –9.54
1111b 71.42 –10.87
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2.3.2.4 SERDES Configuration Example
//full sample rate at 3.125 Gbps
//SERDES reference clock (RIOCLK) 125 MHz
//MPY = 12.5 125MHz = ((3.125 Gbps)(.5))/MPY
SRIO_REGS->SERDES_CFG0_CNTL = 0x0000000F;
SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000;
// SRIO_REGS->SERDES_CFG1_CNTL not used
// SRIO_REGS->SERDES_CFG2_CNTL not used
// SRIO_REGS->SERDES_CFG3_CNTL not used
Table 13. SWING Bits of SERDES_CFGTX n_CNTL
SWING Bits Amplitude (mV
000b 125
001b 250
010b 500
011b 625
100b 750
101b 1000
110b 1125
111b 1250
SRIO Functional Description
)
dfpp
//four ports enabled
SRIO_REGS->SERDES_CFGRX0_CNTL = 0x00081101 ;
SRIO_REGS->SERDES_CFGRX1_CNTL = 0x00081101 ;
SRIO_REGS->SERDES_CFGRX2_CNTL = 0x00081101 ;
SRIO_REGS->SERDES_CFGRX3_CNTL = 0x00081101 ;
SRIO_REGS->SERDES_CFGTX0_CNTL = 0x00010801 ;
SRIO_REGS->SERDES_CFGTX1_CNTL = 0x00010801 ;
SRIO_REGS->SERDES_CFGTX2_CNTL = 0x00010801 ;
SRIO_REGS->SERDES_CFGTX3_CNTL = 0x00010801 ;
2.3.3 Direct I/O Operation
The direct I/O (Load/Store) module serves as the source of all outgoing direct I/O packets. With direct I/O,
the RapidIO packet contains the specific address where the data should be stored or read in the
destination device. Direct I/O requires that a RapidIO source device keep a local table of addresses for
memory within the destination device. Once these tables are established, the RapidIO source controller
uses this data to compute the destination address and insert it into the packet header. The RapidIO
destination peripheral extracts the destination address from the received packet header and transfers the
payload to memory via the DMA.
When a CPU wants to send data from memory to an external processing element (PE) or read data from
an external PE, it provides the RIO peripheral vital information about the transfer such as DSP memory
address, target device ID, target destination address, packet priority, etc. Essentially, a means must exist
to fill all the header fields of the RapidIO packet. The Load/Store module provides a mechanism to handle
this information exchange via a set of MMRs acting as transfer descriptors. These registers, shown in
Figure 12 , are addressable by the CPU through the configuration bus. Upon completion of a write to
LSU n_REG5, a data transfer is initiated for either an NREAD, NWRITE, NWRITE_R, SWRITE, ATOMIC,
or MAINTENANCE RapidIO transaction. Some fields, such as the RapidIO srcTID/targetTID field, are
assigned by hardware and do not have a corresponding command register field.
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LSU _REG0n RapidIO AddressMSB Control
31
RapidIO AddressLSB/Config_offset Control
31 0
LSU _REG1n
DSP Address Control
31 0
LSU _REG2n
RSV Control
31 0
LSU _REG3n
12 11
Byte_count
OutPortID Control
31 0
LSU _REG4n
1
7
InterruptReq
30
Priority
29 28
xambs
27 26
IDSize
25 24
DestID
23 8
RSV
DrbllInfo Command
31 0
LSU _REG5n
8 7
Packet Type
16
HopCount
15
RSV
31
LSU _REG6n
1
Bsy
5
CompletionCode
4
Status
0
0
SRIO Functional Description
Figure 12. Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h, LSU2 420h–438h, LSU3
440h–458h, LSU4 460h-478h)
The mapping of LSU register fields to RapidIO packet header fields is explained in Table 14 and Table 15 .
Table 14 has the fields of the control and command registers (LSU n_REG0 through LSU n_REG5), and
Table 15 has the fields of the status register (LSU n_REG6).
Table 14. LSU Control/Command Register Fields
LSU Register Field RapidIO Packet Header Field
RapidIO Address MSB 32-bit Extended Address Fields – Packet Types 2, 5, and 6
RapidIO Address
LSB/Config_offset
DSP Address 32-bit DSP byte address. Not available in RapidIO Header.
Byte_Count Number of data bytes to Read/Write - up to 4K bytes. (Used in conjunction with RapidIO address
ID Size RapidIO tt field specifying 8- or 16-bit DeviceIDs.
Priority RapidIO prio field specifying packet priority (0 = lowest, 3 = highest). Request packets should not
Xamsbs RapidIO xamsb field specifying the extended address MSBs.
1. 32-bit Address– Packet Types 2, 5, and 6 (Will be used in conjunction with BYTE_COUNT to
create 64-bit aligned RapidIO packet header address)
2. 24-bit Config_offset Field – Maintenance Packets Type 8 (Will be used in conjunction with
BYTE_COUNT to create 64-bit aligned RapidIO packet header Config_offset). The 2 LSBs of
this field must be zero since the smallest configuration access is 4 bytes.
to create WRSIZE/RDSIZE and WDPTR in RapidIO packet header.)
000000000000b – 4K bytes
000000000001b – 1 byte
000000000010b – 2 bytes
. . .
111111111111b – 4095 bytes
(Maintenance requests are limited to 4 bytes)
00b – 8-bit deviceIDs
01b – 16-bit deviceIDs
10b - reserved
11b - reserved
be sent at a priority level of 3 to avoid system deadlock. It is the responsibility of the software to
assign the appropriate outgoing priority.
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SRIO Functional Description
Table 14. LSU Control/Command Register Fields (continued)
LSU Register Field RapidIO Packet Header Field
DestID RapidIO destinationID field specifying the target device.
Packet Type 4 MSBs: 4-bit ftype field for all packets
4 LSBs: 4-bit trans field for packet types 2, 5, and 8
OutPortID Not available in RapidIO header.
Indicates the output port number for the packet to be transmitted from. Specified by the CPU
along with NodeID.
Drbll Info RapidIO doorbell info field for type 10 packets. (see Table 23 )
Hop Count RapidIO hop_count field specified for Type 8 Maintenance packets.
Interrupt Req Not available in RapidIO header.
CPU controlled request bit used for interrupt generation. Typically used in conjunction with
non-posted commands to alert the CPU when the requested data/status is present.
0 - An interrupt is not requested upon completion of command
1- An interrupt is requested upon completion of command
Table 15. LSU Status Register Fields
LSU Register Field Function
BSY Indicates status of the command registers.
0 - Command registers are available (writable) for next set of transfer descriptors
1 - Command registers are busy with current transfer
Completion Code Indicates the status of the pending command.
000b – Transaction complete, no errors (Posted/Non-posted)
001b – Transaction timeout occurred on Non-posted transaction
010b – Transaction complete, packet not sent due to flow control blockade (Xoff)
011b – Transaction complete, non-posted response packet (type 8 and 13) contained ERROR status, or
response payload length was in error
100b – Transaction complete, packet not sent due to unsupported transaction type or invalid programming
encoding for one or more LSU register fields
101b – DMA data transfer error
110b – Retry DOORBELL response received, or Atomic Test-and-swap was not allowed (semaphore in
use)
111b – Transaction complete, packet not sent due to unavailable outbound credit at given priority
(1)
Status available only when busy (BSY) signal = 0.
(1)
Four LSU register sets exist. This allows four outstanding requests for all transaction types that require a
response (i.e., non-posted). For multi-core devices, software manages the usage of the registers. A
shared configuration bus accesses all register sets. A single core device can utilize all four LSU blocks.
Figure 13 shows the timing diagram for accessing the LSU registers. The busy (BSY) signal is deasserted.
LSU n_REG1 is written on configuration bus clock cycle T0, LSU n_REG2 is written on cycle T1,
LSU n_REG3 is written on cycle T2, and LSU n_REG4 is written on cycle T3. The command register
LSU n_REG5 is written on cycle T4. The extended address field in LSU n_REG0 is assumed to be constant
in this example. Upon completion of the write to the command register (next clock cycle T5), the BSY
signal is asserted, at which point the preceding completion code is invalid and accesses to the LSU
registers are not allowed. Once the transaction completes (either as a successful transmission, or
unsuccessfully, such as flow control prevention or response timeout) and any required interrupt service
routine is completed, the BSY signal is deasserted and the completion code becomes valid and the
registers are accessible again.
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LSU _REG1n
T0
T1 T2
T3
T4 T5
Tn
Valid
LSU _REG2n
Valid
LSU _REG3n
Valid
LSU _REG4n
Valid
LSU _REG5n
Valid
Rdy/BSY
Completion
Valid Valid
After TransactionCompletes
SRIO Functional Description
Figure 13. LSU Registers Timing
The following code illustrates an LSU registers programming example.
SRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 );
SRIO_REGS->LSU1_REG1 = CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET,(int)&rcvBuff1[0] );
SRIO_REGS->LSU1_REG2 = CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, (int)&xmtBuff1[0]);
SRIO_REGS->LSU1_REG3 = CSL_FMK( SRIO_LSU1_REG3_BYTE_COUNT,byte_count );
SRIO_REGS->LSU1_REG4 = CSL_FMK( SRIO_LSU1_REG4_OUTPORTID,0 ) |
CSL_FMK( SRIO_LSU1_REG4_PRIORITY,0 ) |
CSL_FMK( SRIO_LSU1_REG4_XAMSB,0 ) |
CSL_FMK( SRIO_LSU1_REG4_ID_SIZE,1 ) |
CSL_FMK( SRIO_LSU1_REG4_DESTID,0xBEEF )|
CSL_FMK( SRIO_LSU1_REG4_INTERRUPT_REQ,1 );
SRIO_REGS->LSU1_REG5 = CSL_FMK( SRIO_LSU1_REG5_DRBLL_INFO,0x0000 )|
CSL_FMK( SRIO_LSU1_REG5_HOP_COUNT,0x00 ) |
CSL_FMK( SRIO_LSU1_REG5_PACKET_TYPE,type );
Figure 14 gives an example of the data flow and field mappings for a burst NWRITE_R transaction.
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Source Address
DMA Read
Destination Address
Count
ByteCount
DSP Address
RSV
InterruptReq
001723 8
DestID
25 24
IDSize
27 26
xambs
29 28
Priority
OutPortID
31 30
HopCount
Drbll
31 16 15
Packet
8 7 0
RapioIO Address/Config_offset
NodeID
CRC
16
Count*8
payload
2
xamsbs
1
wrptr
29
address
32
extaddr
8
srcTID
4
wrsize
4
trans
8
sourceID
8
destID
4
ftype
2
tt
2
prio
3
rsv
5
ackID
TXSharedBufferPool
rdsize/
wsize
rdptr/
wptr
Count
translator
LSU _REG4n
LSU _REG2n
LSU _REG3n
LSU _REG0
LSU _REG1nn
LSU _REG5n
SRIO Functional Description
Figure 14. Example Burst NWRITE_R
For WRITE commands, the payload is combined with the header information from the control/command
registers and buffered in the shared TX buffer resource pool. Finally, it is forwarded to the TX FIFO for
transmission. READ commands have no payload. In this case, only the control/command register fields
are buffered and used to create a RapidIO NREAD packet, which is forwarded to the TX FIFO.
Corresponding response packet payloads from READ transactions are buffered in the shared RX buffer
resource pool when forwarded from the receive ports. Both posted and non-posted operations rely on the
OutPortID command register field to specify the appropriate output port/FIFO.
The data is burst internally to the Load/Store module at the DMA clock rate.
2.3.3.1 Detailed Data Path Description
The Load/Store module is for generating all outgoing RapidIO direct I/O packets. Any read or write
transaction, other than the messaging protocol, uses this interface. In addition, outgoing DOORBELL
packets are generated through this interface.
The data path for this module uses DMA bus as the DMA interface. The configuration bus is used by the
CPU to access the control/command registers. The registers contain transfer descriptors that are needed
to initiate READ and WRITE packet generation. After the transfer descriptors are written, flow control
status is queried. The unit examines the DESTID and PRIORITY fields of LSU n_REG4 to determine if that
flow has been Xoffd. Additionally, the free buffer status of the TX FIFO is checked (based on the
OutPortID register field). Only after the flow control access is granted, and a TX FIFO buffer has been
allocated, can a DMA bus read command be issued for payload data to be moved into the shared TX
buffer. Data is moved from the shared TX buffer to the appropriate output TX FIFO in simple sequential
order based on completion of the DMA bus transaction. However, if fabric congestion occurs, priority can
affect the order in which the data leaves the TX FIFOs.
Here a reordering mechanism exists, which transmits the highest priority packets first if RETRY
acknowledges. Once in the FIFO, the data is guaranteed to be transmitted through the pins. Alternatively,
if an intended flow has been shut down, the peripheral signals the CPU with an interrupt to notify that the
packet was not sent and sets the completion code to 010b in the status register. The registers are held
until the interrupt service routine is complete before the BSY signal is released (BSY=0 in LSU n_REG6)
and the CPU can then rewrite or overwrite the transfer descriptors with new data. Figure 15 illustrates the
data path and buffering that is required to support the Load/Store module.
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LSU2
LSU4
LSU3
LSU1
MMRcommand
UDI
Load/Storemodule
RapidIOtransport
andphysicallayers
Portxtransmission
FIFOqueues
TX
FIFO
RX
FIFO
Peripheralboundary
Configbus
access
Writetransfer
descriptors
CPU
I/O
pins
L2memory
=SharedresourceforCPPIandMAU
Shared
TX
buffer
Shared
RX
buffer
Response
timer
Control
and
arbitrator
DMA
request
DMA
response
SRIO Functional Description
Figure 15. Load/Store Module Data Flow Diagram
2.3.3.2 Direct I/O TX Operation
WRITE Transactions:
The TX buffers are implemented in a single SRAM and shared between multiple cores. A state machine
arbitrates and assigns available buffers between the LSUs. When the DMA bus read request is
transmitted, the appropriate TX buffer address is specified within it. The data payload is written to that
buffer through the DMA bus response transaction. Depending on the architecture of the device,
interleaving of multi-segmented DMA bus responses from the DMA is possible. Upon receipt of a DMA
bus read response segment, the unit checks the completion status of the payload. Note that only one
payload can be completed in any single DMA bus cycle. The Load/Store module can only forward the
packet to the TX FIFO after the final payload byte from the DMA bus response has been written into the
shared TX buffer. Once the packet is forwarded to the TX FIFO, the shared TX buffer can be released and
made available for a new transaction.
The TX buffer space is dynamically shared among all outgoing sources, including the Load/Store module
and the TX CPPI, as well as the response packets from RX CPPI and the memory access unit (MAU).
Thus, the buffer space memory is partitioned to handle packets with and without payloads. A 4.5K-byte
buffer space is configured to support 16 packets with payloads up to 256 bytes, in addition to 16 packets
without payloads. The SRAM is configured as a 128-bit wide two port, which matches the UDI width of the
TX FIFOs.
Note: The "UDI" ("User Defined Interface") is a reference to the interface between (a) the
SERDES and the FIFO queues and (b) the logical buffers, shared buffers, LSU and MAU
modules, response timer, and controllers (together known as the "User Application"). UDI
could also be known as the "logical/physical interface". No action is required to "define"
this interface.
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SRIO Functional Description
Data leaves the shared TX buffer sequentially in order of receipt, not based on the packet priority.
However, if fabric congestion occurs, priority can affect the order in which the data leaves the TX FIFOs. A
reordering mechanism exists here, which transmits the highest priority packets first if RETRY
acknowledges.
For posted WRITE operations, which do not require a RapidIO response packet, a core may submit
multiple outstanding requests. For instance, a single core may have many streaming write packets
buffered at any given time, given outgoing resources. In this application, the control/command registers
can be released (BSY = 0) to the CPU as soon as the header info is written into the shared TX buffer. If
the request has been flow controlled, the peripheral will set the completion code status register and
appropriate interrupt bit of the ICSR. The control/command registers can be released after the interrupt
service routine completes.
For non-posted WRITE operations, which do require a RapidIO response packet, there can be only one
outstanding request per core at any given time. The payload data and header information is written to the
shared TX buffer as described above; however, the command registers cannot be released (BSY = 1) until
the response packet is routed back to the module and the appropriate completion code is set in the status
register. One special case exists for outgoing test-and-swap packets (Ftype 5, Transaction 1110b). This is
the only WRITE class packet that expects a response with payload. This response payload is routed to the
LSU, where it is examined to verify whether the semaphore was accepted, and then the appropriate
completion code is set. The payload is not transferred out of the peripheral via the DMA bus.
So the general flow is as follows:
• LSU registers are written using the configuration bus
• Flow control is determined
• TX FIFO free buffer availability is determined
• DMA bus read request for data payload
• DMA bus response writes data to specified module buffer in the shared TX buffer space
• DMA bus read response is monitored for last byte of payload
• Header data in the LSU registers is written to the shared TX buffer space
• Payload and header are transferred to the TX FIFO
• The LSU registers are released if no RapidIO response is needed
• Transfer from the TX FIFO to external device based on priority
READ Transactions:
The flow for generating READ transactions is similar to non-posted WRITE with response transactions.
There are two main differences: READ packets contain no data payload, and READ responses have a
payload. So READ commands simply require a non-payload shared TX buffer. In addition, they require a
shared RX buffer. This buffer is not pre-allocated before transmitting the READ request packet, since
doing so could cause traffic congestion of other in-bound packets destined to other functional blocks.
Again, the control/command registers cannot be released (BSY = 1) until the response packet is routed
back to the module and appropriate completion code is set in the status register.
So the general flow would be:
• LSU registers are written using the configuration bus
• Flow control is determined
• TX FIFO free buffer availability is determined
• Header data in the LSU registers is written to the shared TX buffer
• Payload and header are transferred to the TX FIFO
• The LSU registers are released if no RapidIO response is needed
• Transfer from the TX FIFO to external device based on priority
For all transactions, the shared TX buffers are released as soon as the packet is forwarded to the TX
FIFOs. If an ERROR or RETRY response is received for a non-posted transaction, the CPU must either
reinitiate the process by writing to the LSU register, or initiate a new transaction altogether.
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SRIO Functional Description
Segmentation:
The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count
of Read/Write requests exceeds 256 bytes (up to 4K bytes). The second type is when Read/Write request
RapidIO address is non-64-bit aligned. In both cases, the outgoing request is broken up into multiple
RapidIO request packets. For example, assume that the CPU wants to perform a 1K-byte store operation
to an external RapidIO device. After setting up the LSU registers, the CPU performs one write to the
LSU n_REG5 register. The peripheral hardware then segments the store operation into four RapidIO write
packets of 256 bytes each, and calculates the 64-bit-aligned RapidIO address, WRSIZE, and WDPTR as
required for each packet. This example requires four outbound handles to be assigned and four DMA
transmit requests. The LSU registers cannot be released until all posted request packets are passed to
the TX FIFOs. Alternatively, for non-posted operations, such as CPU loads, all packet responses must be
received before the LSU registers are released.
2.3.3.3 Direct I/O RX Operation
Response packets are always type 13 RapidIO packets. All response packets with transaction types not
equal to 0001b are routed to the LSU block sequentially in order of reception. These packets may have a
payload, depending on the type of corresponding request packet that was originally sent. Due to the
nature of RapidIO switch fabric systems, response packets can arrive in any order. The data payload, if
any, and header data is moved from the RX FIFO to the shared RX buffer. The targetTID field of the
packet is examined to determine which core and corresponding set of registers are waiting for the
response. Remember, there can be only one outstanding request per core. Any payload data is moved
from the shared RX buffer into memory through normal DMA bus operations.
Registers for all non-posted operations should only be held for a finite amount of time to avoid blocking
resources when a request or response packet is somehow lost in the switch fabric. This time correlates to
the 24-bit Port Response Time-out Control CSR value discussed in sections 5.10.1 and 6.1.2.4 of the
RapidIO Physical Layer 1x/4x LP-Serial Specification. If the time expires, control/command register
resources should be released, and an error is logged in the error-management RapidIO registers. The
RapidIO Interconnect Specification states that the maximum time interval (all 1s) is between 3 and 6
seconds. A logical layer timeout occurs if the response packet is not received before a countdown timer
(initialized to this CSR value) reaches zero.
Each outstanding packet response timer requires a 4-bit register. The register is loaded with the current
timecode when the transaction is sent. The timecode comes from a 4 bit counter associated with the 24 bit
down counter that continually counts down and is re-loaded with the value of SP_RT_CTL (Address offset
1124h) when it reaches 0. Each time the timecode changes, a 4-bit compare is done to the register. If the
register becomes equal to the timecode again, without a response being seen, then the transaction has
timed out. Essentially, instead of the 24-bit value representing the period of the response timer, the period
is now defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 –
89.5Mhz for a 6 – 3 second response timeout. Because the needed timer frequency is derived from the
DMA bus clock (which is device dependent), the hardware supports a programmable configuration register
field to properly scale the clock frequency. This configuration register field is described in the Peripheral
Setting Control register (Address offset 0020h).
If a response packet indicates ERROR status, the Load/Store module notifies the CPU by generating an
error interrupt for the pending non-posted transaction. If the response has completed successfully, and the
Interrupt Req bit is set in the control register, the module generates a CPU servicing interrupt to notify the
CPU that the response is available. The control/command registers can be released as soon as the
response packet is received by the logical layer. The hardware is not responsible for attempting a
retransmission of the non-posted transaction.
If a Doorbell response packet indicates Retry status, the Load/Store module notifies the CPU by
generating an interrupt. The control/command registers can be released as soon as the response packet
is received by the logical layer. The hardware is not responsible for attempting retransmission of the
Doorbell transaction.
42 Serial RapidIO (SRIO) SPRUE13A – September 2006
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So the general flow is as follows:
• Previously, the control/command registers were written and the request packet was sent
• Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not
based on priority)
• The argetTID is examined to determine routing of a response to the appropriate core
• The status field of the response packet is checked for ERROR, RETRY or DONE
• If the field is DONE, it submits DMA bus request and transmits the payload (if any) to DSP address. If
the field is ERROR/RETRY, it sets an interrupt
• Command registers are released (BSY = 0)
• Optional Interrupt to CPU notifying packet reception
2.3.3.4 Reset and Power Down State
Upon reset, the Load/Store module clears the command register fields and wait for a write by the CPU.
The Load/Store module can be powered down if the direct I/O protocol is not being supported in the
application. For example, if the messaging protocol is being used for data transfers, powering down the
Load/Store module will save power. In this situation, the command registers should be powered down and
inaccessible. Clocks should be gated to these blocks while in the power down state.
2.3.4 Message Passing
The Communications Port Programming Interface (CPPI) module is the incoming and outgoing
message-passing protocol engine of the RapidIO peripheral. Messages contain application specific data
that is pushed to the receiving device comparable to a streaming write. Messages do not contain read
operations, but do have response packets.
With message passing, a destination address is not specified. Instead, a mailbox identifier is used within
the RapidIO packet. The mailbox is controlled and mapped to memory by the local (destination) device.
For RapidIO message passing, four mailbox locations are specified. Each mailbox can contain 4 separate
transactions (or letters), effectively providing 16 messages. Single packet messages provide 64 mailboxes
with 4 letters, effectively providing 256 messages. Mailboxes can be defined for different data types or
priorities. The advantage of message passing is that the source device does not require any knowledge of
the destination device’s memory map. The DSP contains buffer description tables for each mailbox. These
tables define a memory map and pointers for each mailbox. Messages are transferred to the appropriate
memory locations via the DMA.
The data path for this module uses the DMA bus as the DMA interface. The ftype header field of the
received RapidIO message packets are decoded by the logical layer of the peripheral. Only Type 11 and
Type 13 (transaction type 1) packets are routed to this module. Data is routed from the priority-based RX
FIFOs to the CPPI module’s data buffer within the shared buffer pool. The mbox (mailbox) header fields
are examined by the mailbox mapper block of the CPPI module. Based on the mailbox and message
length, the data is assigned memory addresses within memory. Data is transferred via DMA bus
commands to memory from the buffer space of the peripheral. The maximum buffer space should
accommodate 256 bytes of data, as that is the maximum payload size of a RapidIO packet. Each
message in memory will be represented by a buffer descriptor in the queue.
The following rules exist for all CPPI traffic:
• One buffer descriptor is provided per message (each buffer descriptor consists of 4 words or 16 bytes).
• Contiguous memory space is required for multi-segment read and write operations.
– There are fixed buffer sizes (configured to handle the application's maximum message size).
• An ERROR response is sent if the RX message is too big for the allotted buffer space.
– ERROR responses are sent for all subsequent segments of that message.
• An ERROR response is sent if the mailbox is not mapped, or if it is mapped to a non-existent queue.
• An ERROR response is sent if the mailbox is mapped but the queue is not initialized (the head
descriptor pointer is not written), or if the queue is disabled (due to a teardown).
• An ERROR response is sent if the RX buffer descriptor queue has no empty buffers (there is an
overflow) .
SRIO Functional Description
SPRUE13A – September 2006 Serial RapidIO (SRIO) 43
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Mailbox1...64
fromRapidIOpacket
Header-Receivedonany
inputport
Mailboxmapper
Q15
Q2 Q1
Q0
Queueassignabletoanycore
Packetsequence
Message
n A
Packet
manager
n+1 B
n+2 B
n+ 3 C
n+4 D
n+5 B
n+6 E
Bufferdescriptor
queues:
Descriptorpermessage
Allpriorities
Dedicatedsingle-segment
messagedescriptorqueue
A
C
E
D
null
null
B
Multi-segmentmessage
descriptorqueue
Multi-segmentmessage
descriptorqueueN
L2memory
databuffer,upto256B
ndatapacket
n+3datapacket
n+4datapacket
n+6datapacket
256Bfreebuffer
L2memory
databuffer,upto4K
n+5datapacket
n+2datapacket
n+1datapacket
4KBfreebuffer
SRIO Functional Description
2.3.4.1 RX Operation
• Out-of-order responses are allowed.
• A RETRY response is issued to the first received segment of a multi-segment message when the RX
queue is busy servicing another request.
– Subsequent RETRY responses may have to be sent for received pipeline segments or additional
pipelined messages to the same queue.
• In-order message reception for dedicated flows is mode programmable.
• A queue is needed for each supported simultaneous multi-segment RX message.
• A minimum of 1.25K bytes of SRAM (64 buffer descriptors) is supported.
• The transmit source must be able to retry any given segment of a message.
• DestID is equal to port for TX operations, and the same DestID is not accessible from multiple ports.
As message packets are received by the RapidIO ports, the data is written into memory while maintaining
accurate state information that is needed for future processing. For instance, if a message spans multiple
packets, information is saved that allows re-assembly of those packets by the CPU. The CPPI module
provides a scheme for tracking single and multi-packet messages, linking messages in queues, and
generating interrupts. Figure 16 illustrates the scheme.
Figure 16. CPPI RX Scheme for RapidIO
44 Serial RapidIO (SRIO) SPRUE13A – September 2006
Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO ports
simultaneously. Packets are handled sequentially in order of receipt. The function of the mailbox mapper
block is to direct the inbound messages to the appropriate queue and finally to the correct core. The
queue mapping is programmable and must be configured after device reset. RapidIO originally supported
only 4 mailboxes with 4 letters/mailbox. Letters allow concurrent message traffic between sender and
receiver. However, for messages that consist of only single packets, the unused 4-bit packet field normally
indicating the message segment extends the available number of mailboxes. Figure 17 shows the packet
header fields for message requests.
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acklD rsv prio tt ftype
ftype=1011
destID
sourcelD msglen ssize msgseg/xmbox double-word0 double-word1 ...
double-wordn-2 double-wordn-1 CRC
PHY
LOG
TRA
LOG
TRAPHY
5 3 2 2 4 8 8 4 4 4 64 64
(n-4)*64
64 64 16
16n*64+16164210
n*64+64
letter
2
mbox
2
SRIO Functional Description
Figure 17. Message Request Packet
This enables the letter and mailbox fields to instead allow four concurrent single-segment messages to
sixty-four possible mailboxes (256 total locations) for a source and destination pair. The mailbox mapper
directs the inbound messages to the appropriate queue based on a pre-programmed routing table. It
bases the decision on the SOURCEID, MSGLEN (the size indicates whether the message is segmented),
MBOX, LETTER, and XMBOX fields of the RapidIO packet.
There are 32 programmable look-up table entries for mapping mailboxes to queues. Each entry consists
of two registers, RXU_MAP_L n and RXU_MAP_H n, which are shown in Figure 18 . A detailed summary of
these register's field is in Section 5.50 . In total, there are 64 registers, at address offsets 0800h–08FCh.
Each entry stores the queue number associated with the message’s intended mailbox/letter. If a
mailbox/letter is not supported or does not have a mapping table entry, the message is discarded and an
ERROR response sent. The mapping entries can explicitly call out a mailbox and letter combination, or
alternatively, the mask fields can be used to grant multiple mailbox/letter combinations access to a queue
using the same table entry. A masking value of 0 in the mailbox or letter mask fields indicates that the
corresponding bit in the mailbox or letter field will not be used to match for this queue mapping entry. For
example, a mailbox mask of all zeros would allow a mapping entry to be used for all incoming mailboxes.
The mapping table entry also provides a security feature to enable or disable access from specific external
devices to local mailboxes. The sourceID field indicates which external device has access to the mapping
entry and corresponding queue. A compare is performed between the sourceID of the incoming message
packet and each relevant mailbox/letter table mapping entry SOURCEID field. If they do not match, an
ERROR response is sent back to the sender, and the transaction is logged in the logical layer error
management capture registers, which sets an interrupt. A PROMISCUOUS bit allows this security feature
to be disabled. When the PROMISCUOUS bit is set, full access to the mapping entry from any sourceID is
allowed. Note that when the PROMISCUOUS bit is set, the mailbox/letter and corresponding mask bits
are still in effect. When the PROMISCUOUS bit is cleared, it equals a mask value of FFFFh, and only a
request with the matching sourceID is allowed access to the mailbox.
Each table entry also indicates if it used for single or multi-segment message mapping. Single segment
message mapping entries utilize all six bits of the mailbox and corresponding mask fields. Multi-segment
entries uses only the 2 LSBs. The number of simultaneous supported multi-segment messages is
determined by the number of dedicated RX queues as discussed further below. It is recommended to
dedicate a multi-segment mapping entry for each supported simultaneous letter. Essentially, letter masks
should be avoided for multi-segment mapping to reduce excessive retries. Note that it is possible to
configure the table entries such that incoming single segment and multi-segment messages are directed
to the same queue. To avoid this condition, properly program the mapping table entries.
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SRIO Functional Description
Figure 18. Mailbox to Queue Mapping Register Pair
Mailbox to Queue Mapping Register L n (RXU_MAP_L n )
31 30 29 24 23 22 21 16
LETTER_MASK MAILBOX_MASK LETTER MAILBOX
R/W-11 R/W-111111 R/W-00 R/W-000000
15 0
SOURCEID
R/W-0000h
Mailbox to Queue Mapping Register H n (RXU_MAP_H n )
31
Reserved
R-0
10 9 8 7 6 5 2 1 0
Reserved TT Reserved QUEUE_ID PROMISCUOUS
R-0 R/W-01 R-00 R/W-0000 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
SEGMENT
MAPPING
The packet manager maintains the RX DMA state of free and used data buffers within the memory space.
It directs the data to specific addresses within the memory and maintains and updates the buffer
descriptor queues. There is a single buffer descriptor per RapidIO message. For example, single segment
messages have one buffer descriptor, as do multi-segment messages with up to 4K-byte payloads.
There can be multiple RX buffer descriptor queues per core. It is suggested that one queue be dedicated
to single segment messages and additional queues be dedicated to multi-segment messages. Each
multi-segment message queue can support only one incoming message at a time. Depending on the
application, it may be necessary to support multiple simultaneous segmentation and reassembly (SAR)
operations per core. In this case, a buffer descriptor queue is allocated for each desired simultaneous
message. The peripheral supports a total of 16 assignable RX queues and their associated RX DMA state
registers. Each of the queues can be assigned to single or multi-segment messages.
Table 16 and Table 17 describe the RX DMA State Registers.
Table 16. RX DMA State Head Descriptor Pointer (HDP) (Address Offset 600h–63Ch)
Bit Name Description
31–0 RX Queue Head RX Queue Head Descriptor Pointer: This field is the memory address for the first buffer descriptor
Descriptor Pointer in the channel receive queue. This field is written by the DSP core to initiate queue receive
operations and is zeroed by the port when all free buffers have been used. An error condition
results if the DSP core writes this field when the current field value is nonzero. The address must
be 32-bit word aligned.
Table 17. RX DMA State Completion Pointer (CP) (Address Offset 680h–6BCh)
Bit Name Description
31–0 RX Queue RX Queue Completion Pointer: This field is the memory address for the receive queue completion
Completion Pointer pointer. This register is written by the DSP core with the buffer descriptor address for the last buffer
processed by the DSP core during interrupt processing. The port uses the value written to
determine if the interrupt should be deasserted.
If a multi-segment buffer descriptor queue is not currently free, and an RX port receives another
multi-segment message that is destined for that queue, the RX CPPI sends a RETRY RESPONSE packet
(type 13) to the sender, indicating that an internal buffering problem exists. If a multi-segment buffer
descriptor queue is busy and there is another incoming multi-segment message with the same
SOURCEID, MAILBOX, and LETTER, an ERROR response is sent. This usually indicates that a TX
programming error has occurred, where duplicate segments or segments outside the MSGLEN were sent.
Upon successful reception of any message segment, the RX CPPI is responsible for sending a DONE
response to the sender.
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31
0
1
2
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19
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message_length
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BitFields
next_descriptor_pointer
buffer_pointer
src_id pri
tt
reserved mailbox
Word
Offset
SRIO Functional Description
If a RX message’s length is greater than that of the targeted buffer descriptor, an ERROR response is
sent back to the source device. In addition, the DSP is notified with the use of the CC field of the RX CPPI
buffer descriptor, described as follows. This situation can result from a DSP software error (misallocating a
buffer for the queue), or as a result of sender error (sending to a wrong mailbox).
An RX transaction timeout is used by all multi-segment queues, in order to not hang receive mailbox
resources in the event that a message segment is lost in the fabric. This response-to-request timer
controls the time-out period for sending a response packet and receiving the next request packet of a
given multi-segment message. It has the same value and is analogous to the request-to-response timer
discussed in the TX CPPI and LSU sections, which is defined by the 24-bit value in the port response
time-out CSR (See Section 2.3.3.3 ). The RapidIO Interconnect Specification states that the maximum time
interval (all 1s) is between 3 and 6 seconds. Each multi-segment receive timer requires a 4-bit register.
The register is loaded with the current timecode when the response is sent. Each time the timecode
changes, a 4-bit compare is done to the register. If the register becomes equal to the timecode again,
without the next message segment being seen, then the transaction has timed out. If this happens, the RX
buffer resources can be released.
The buffer descriptor points to the corresponding data buffer in memory and also points to the next buffer
descriptor in the queue. As segments of a received message arrive, the msgseg field of each segment is
monitored to detect the completion of the received message. Once a full message is received, the
OWNERSHIP bit is cleared in the packet’s buffer descriptor to give control to the host. At this point, a host
interrupt is issued. This interface works with programmable interrupt rate control. There is an ICSR bit for
each supported queue. On interrupt, the CPU processes the RX buffer queue, detecting received packets
by the status of the OWNERSHIP bit in each buffer descriptor. The host processes the RX queue until it
reaches a buffer descriptor with a set OWNERSHIP bit, or set EOQ bit. Once processing is complete, the
host updates the RX DMA State Completion Pointer, allowing the peripheral to reuse the buffer.
Figure 19 shows the RX buffer descriptor fields and Table 18 describes them. A RX buffer descriptor is a
contiguous block of four 32-bit data words aligned on a 32-bit boundary. Accesses to these registers are
restricted to 32-bit boundaries.
Figure 19. RX Buffer Descriptor Fields
Table 18. RX Buffer Descriptor Field Descriptions
Field Description
next_descriptor_pointer Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer
buffer_pointer Buffer Pointer: The byte aligned memory address of the buffer associated with the
sop = 1 Start of Message: Indicates that the descriptor buffer is the first buffer in the message.
eop = 1 End of Message: Indicates that the descriptor buffer is the last buffer in the message.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 47
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descriptor in the RX queue. This references the next buffer descriptor from the current
buffer descriptor. If the value of this pointer is zero, then the current buffer is the last
buffer in the queue. The DSP core sets the next_descriptor_pointer.
buffer descriptor. The DSP core sets the buffer_pointer.
• This bit will always be set, as this device only supports one buffer per message.
• This bit will always be set, as this device only supports one buffer per message.
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SRIO Functional Description
Table 18. RX Buffer Descriptor Field Descriptions (continued)
Field Description
ownership Ownership: Indicates ownership of the message and is valid only on sop. This bit is set
by the DSP core and cleared by the port when the message has been transmitted. The
DSP core uses this bit to reclaim buffers.
0: The message is owned by the DSP core
1: The message is owned by the port
eoq End Of Queue: Set by the port to indicate that the RX queue empty condition exists.
This bit is valid only on eop. The port determines the end of queue condition by a zero
next_descriptor_pointer.
0: The RX queue has more buffers available for reception.
1: The Descriptor buffer is the last buffer in the last message in the queue.
teardown_complete Teardown Complete: Set by the port to indicate that the host commanded teardown
process is complete, and the channel buffers may be reclaimed by the host.
0: The port has not completed the teardown process.
1: The port has completed the commanded teardown process.
message_length Message Length: Initially written by the DSP core to specify the maximum number of
double-words the buffer can receive. Updated by the peripheral (after receiving a
message) to indicate the actual number of double-words in the entire message.
Message payloads are limited to a maximum size of 512 double-words (4096 bytes).
000000000b: 512 double words
000000001b: 1 double word
000000010b: 2 double words
. . .
111111111b: 511 double words
src_id Source Node ID: Unique node identifier of the source of the message. Written by the
DSP core.
tt RapidIO tt field specifying 8- or 16-bit DeviceIDs. Written by the DSP core.
00b: 8-bit deviceIDs
01b: 16-bit deviceIDs
10: reserved
11: reserved
pri Message Priority: Specifies the SRIO priority at which the message was sent. Written
by the DSP core.
cc Completion Code: Written by the port.
000: Good completion. Message received.
001: Error, RX message length greater than supported buffer descriptor
message_length
010: Error, TimeOut on receiving one of the segments
011: DMA transfer error on one or more segments
100: Queue teardown completed, data invalid
101: 111 Reserved
mailbox Destination Mailbox: Specifies the mailbox to which the message was sent. Written by
the DSP core.
000000b: Mailbox 0
000001b: Mailbox 1
. . .
000100b: Mailbox 4
. . .
111111b: Mailbox 63
For multi-segment messages, only the two LSBs of this mailbox are valid. Hardware
ignores the four MSBs if the incoming message has multiple segments.
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Switch
Switch
Endpoint
Endpoint
C0
C0
B0
B0
B2
B2
A1
A1
B1
B1
A0
A0
Open
Open
Open
Open
Open
Open
Open
Full
Open
Open
Full
Full
Retry
Retry
Retry
Retry
Retry
Retry
Accept
Retry
Retry
Retry
Action
Action
Retry
Retry
Scenario A -Default
ScenarioB-Inordermode
Dataflowdestinedforthe
sameRXqueue
RXqueuestatuswhen
packetarrives
RXqueuestatuswhen
packetarrives
RecordsSourceID/letterof
firstretrypacket
SRIO Functional Description
Although the switch fabric delivers the segments of multi-packet messages in the order they were sent,
buffer resources at the receiving endpoint may only become available after the initial segment(s) of a
message have had to be retried. The peripheral can accept out-of-order segments and track completion of
the overall message. Scenario A in Figure 20 shows this concept.
For applications that are set up for specific message flows between a single source and destination, it may
require in-order delivery of messages. This is described in scenario B of Figure 20 . This scenario is similar
to scenario A, although one message may be retried due to a lack of receiver resources, subsequent
pipelined messages may arrive just as resources are freed up. This is a problem for systems requiring
in-order message delivery. In this case, the peripheral needs to record the Src_id/mailbox/letter of the first
retried message and retry all subsequent new requests until resources are available and a segment for
that Src_id/mailbox/letter is received. As long as all messages are from the same source and that source
sends (and retries) packets in order, then all messages will be received in order. Note that this solution is
less effective when multiple sources share an RX queue. The RX CPPI Control register (Address offset
0744h) sets this mode of operation on all receive queues. Once this mode is set and a retry is issued, the
queue will continue to wait for an incoming message that matches the Src_id/mailbox/letter combination. If
no such packet arrives, the RX queue is unusable in a locked state. To reenable the queue, the in-order
bit in the RX CPPI Control register must be disabled by software for that queue, after which it may be
enabled again if desired. The in-order mode of operation is only valid on multi-segment queues because
single-segment messages will never generate RETRY responses.
Figure 20. RX CPPI Mode Explanation
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SRIO Functional Description
In addition, multiple messages can be interleaved at the receive port due to ordering within a connected
switch’s output queue. This can occur when using a single or multiple priorities. The RX CPPI block can
handle simultaneous interleaved multi-segment messages. This implies that state information (write
pointers and sourceID) is maintained on each simultaneous message to properly store the segments in
memory. The number of simultaneous transactions supported directly impacts the number of states to be
stored, and the size of the buffer descriptor memory outside the peripheral. With this in mind, the
peripheral’s supported buffer descriptor SRAM is parameterizable. A minimum size of 1.25K bytes is
recommended, which will allow up to 64 buffer descriptors to be stored at any given time for one core.
These buffer descriptors can be configured to support any combination of single and multi-segment
messages. For example, if the application only handles single-segment messages, all 64 buffers can be
allotted to that queue. Note that a given RX queue can contain packets of all priorities which have been
directed from any of the receive ports.
A CPU may wish to stop receiving messages and reclaim buffers belonging to a specific queue. This is
called queue teardown. The CPU initiates a RX queue teardown by writing to the RX Queue Teardown
command register (Address Offset 0740h).
Teardown of an RX queue causes the following actions:
• If teardown is issued by software during the time when the RX state machine is idle, then the state
machine will immediately start the teardown procedure:
– If the queue to be torn down is in-message (waiting for one or more segments), then the queue will
be torn down and reported with the current buffer descriptor (teardown bit set, ownership bit
cleared, CC = 100b). All other fields of the buffer descriptor are invalid. The peripheral completes
the teardown procedure by clearing the HDP register, setting the CP register to FFFFFFFCh, and
issuing an interrupt for the given queue. The teardown command register bit is automatically
cleared by the peripheral.
– If the queue is not in-message, and active (next descriptor available), then the next descriptor will
be fetched and updated to report teardown (teardown bit set, ownership bit cleared, CC = 100b). All
other fields of the buffer descriptor are invalid. The peripheral completes the teardown procedure by
clearing the HDP register, setting the CP register to FFFFFFFCh, and issuing an interrupt for the
given queue. The teardown command register bit is automatically cleared by the peripheral.
– If the queue is not in-message, but inactive (next descriptor unavailable), then no additional buffer
descriptor will be written. The HDP register and the CP register remain unchanged. An interrupt is
not issued. The teardown command register bit is automatically cleared by the peripheral.
• If teardown is issued by software during the time when the RXU state machine is busy, the teardown
procedure will be postponed until the state machine is idle.
After the teardown process is complete and the interrupt is serviced by the CPU, the software must
re-initialize the RX queue to restart normal operation.
The buffer descriptor queues are maintained in local SRAM just outside of the peripheral, as shown in
Figure 21 . This allows the quickest access time, while maintaining a level of configurability for device
implementation. The SRAM is accessible by the CPU through the configuration bus. Alternatively, the
buffer descriptors could use L2 memory as well.
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CPPIblock
CPU
DMA
Configbusaccess
L2memory
Buffer
descriptor
dual-port
SRAM
(Nx20B)
Data buffer
Peripheralboundary
32
32
32
128
CPPI cont ro l
re gis ter s
Figure 21. CPPI Boundary Diagram
SRIO Functional Description
2.3.4.2 TX Operation
Outgoing messages are handled similarly, with buffer descriptor queues that are assigned by the CPUs.
The queues are configured and initialized upon reset. When a CPU wants to send a message to an
external RapidIO device, it writes the buffer descriptor information via the configuration bus into the
SRAM. Again, there is a single buffer descriptor per RapidIO message. Upon completion of writing the
buffer descriptor, the OWNERSHIP bit is set to give control to the peripheral. The CPU then writes the TX
DMA State HDP register to initiate the queue transmit. For TX operation, PortID is specified to direct the
outgoing packet to the appropriate port. Table 19 and Table 20 describe the TX DMA state registers.
Figure 22 shows the TX buffer descriptor fields and Table 21 describes them. A TX buffer descriptor is a
contiguous block of four 32-bit data words aligned on a 32-bit boundary.
Bit Name Description
31–0 TX Queue Head TX Queue Head Descriptor Pointer: This field is the DSP core memory address for the first buffer
Table 19. TX DMA State Head Descriptor Pointer (HDP) (Address Offset 500h–53Ch)
Descriptor Pointer descriptor in the transmit queue. This field is written by the DSP core to initiate queue transmit
operations and is zeroed by the port when all packets in the queue have been transmitted. An error
condition results if the DSP core writes this field when the current field value is nonzero. The
address must be 32-bit word aligned.
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31
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retry_count
cc
message_length
13
21
5
25
9
17 1
30
1422
626 10
18
2
28
12
20
424
8
16 0
BitFields
next_descriptor_pointer
buffer_pointer
dest_id pri
tt
ssize mailbox
port_id
Word
Offset
SRIO Functional Description
Table 20. TX DMA State Completion Pointer (CP) (Address Offset 58h–5BCh)
Bit Name Description
31–0 TX Queue TX Queue Completion Pointer: This field is the DSP core memory address for the transmit queue
Completion Pointer completion pointer. This register is written by the DSP core with the buffer descriptor address for
the last buffer processed by the DSP core during interrupt processing. The port uses the value
written to determine if the interrupt should be deasserted.
Figure 22. TX Buffer Descriptor Fields
Table 21. TX Buffer Descriptor Field Definitions
Field Description
next_descriptor_pointer Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer
descriptor in the TX queue. This is the mechanism used to reference the next buffer
descriptor from the current buffer descriptor. If the value of this pointer is zero then the
current buffer is the last buffer in the queue. The DSP core sets the
next_descriptor_pointer.
buffer_pointer Buffer Pointer: The byte aligned memory address of the buffer associated with the
buffer descriptor. The DSP core sets the buffer_pointer.
sop = 1 Start of Message: Indicates that the descriptor buffer is the first buffer in the message.
• This bit will always be set as this device only supports one buffer per message.
eop = 1 End of Message: Indicates that the descriptor buffer is the last buffer in the message.
• This bit will always be set as this device only supports one buffer per message.
ownership Ownership: Indicates ownership of the message and is valid only on sop. This bit is set
by the DSP core and cleared by the port when the message has been transmitted. The
DSP core uses this bit to reclaim buffers.
0: The message is owned by the DSP core
1: The message is owned by the port
eoq End Of Queue: Set by the port to indicate that all messages in the queue have been
transmitted and the TX queue is empty. End of queue is determined by the port when
the next_descriptor_pointer is zero on an eop buffer. This bit is valid only on eop.
0: The TX queue has more messages to transfer.
1: The Descriptor buffer is the last buffer in the last message in the queue.
teardown_complete Teardown Complete: Set by the port to indicate that the DSP core commanded
teardown process is complete, and the channel buffers may be reclaimed by the DSP
core.
0: The port has not completed the teardown process.
1: The port has completed the commanded teardown process.
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SRIO Functional Description
Table 21. TX Buffer Descriptor Field Definitions (continued)
Field Description
retry_count Message Retry Count: Set by the DSP core to indicate the total number of retries
cc Completion Code: Set by the port.
message_length Message Length: Message Length – Written by the DSP core to specify the number of
dest_id Destination Node Id: Unique Node identifier for the Destination of the message. Written
pri Message Priority: Specifies the SRIO priority at which the message will be sent.
tt RapidIO tt field specifying 8- or 16-bit DeviceIDs. Written by the host.
port_id Port number for routing outgoing packet. Written by the DSP core.
allowed for this message, including all segments. Decremented by the port each time a
message is retried.
000000b: Infinite Retries
000001b: Retry Message 1 time
000002b: Retry Message 2 times
. . .
111111b: Retry Message 63 times
000: Good Completion. Message received a done response.
001: Transaction error. Message received an error response. *
010: Excessive Retries. Message received more than retry_count retry responses.
011: Transaction timeout. Transaction timer elapsed without any message response
being received.
100: DMA data transfer error
101: Descriptor Programming error
110: TX Queue Teardown Complete
111: Outbound Credit not available.
* An ERROR transfer completion code indicates an error in one or more segments of a
transmitted multi-segment message.
double-words to transmit. Message payloads are limited to a maximum size of 512
double-words (4096 bytes).
000000000b: 512 double words
000000001b: 1 double word
000000010b: 2 double words
. . .
111111111b: 511 double words
by the DSP core.
Messages should not be sent at a priority level of 3 because the message response is
required to promote the priority to avoid system deadlock. It is the responsibility of the
software to assign the appropriate outgoing priority.
00: 8-bit deviceIDs
01: 16-bit deviceIDs
10: reserved
11: reserved
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SRIO Functional Description
Table 21. TX Buffer Descriptor Field Definitions (continued)
Field Description
ssize RIO standard message payload size. Indicates how the hardware should segment the
outgoing message by specifying the maximum number of double-words per packet. If
the message is a multi-segment message, this field remains the same for all outgoing
segments. All segments of the message, except for the last segment, have payloads
equal to this size. The last message segment may be equal or less than this size.
Maximum message size for a 16 segment message is shown below.
Message_length/16 must be less than or equal to Ssize, if not, the message is not sent
and CC 101b is set. Written by the DSP core.
0000b - 1000b: Reserved
1001b: 1 Double-word payload (Supports up to a 128-byte message)
1010b: 2 Double-word payload (Supports up to a 256-byte message)
1011b: 4 Double-word payload (Supports up to a 512-byte message)
1100b: 8 Double-word payload (Supports up to a 1024-byte message)
1101b: 16 Double-word payload (Supports up to a 2048-byte message)
1110b: 32 Double-word payload (Supports up to a 4096-byte message)
1111b: Reserved
mailbox Destination Mailbox: Specifies the mailbox to which the message will be sent. Written
by the DSP core.
000000b: Mailbox 0
000001b: Mailbox 1
. . .
000100b: Mailbox 4
. . .
111111b: Mailbox 63
For multi-segment messages, only the 2 LSBs of this mailbox field are valid. Hardware
will ignore the 4 MSBs of this field if the outgoing message is multi-segment.
Once the port controls the buffer descriptor, the DEST_ID field can be queried to determine flow control. If
the transaction has been flow controlled, the DMA bus READ request is postponed so that the TX buffer
space is not wasted. Because buffer descriptors cannot be reordered in the link list, if the transaction at
the head of the buffer descriptor queue is flow controlled, head-of-line (HOL) blocking will occur on that
queue. When this occurs, all transactions located in that queue are stalled. To counter the effects and
reduce back-up of more TX packets, multiple queues are available. The peripheral supports a total of 16
assignable TX queues and their associated TX DMA state registers. The transmission order between
queues is based on a programmable weighted round-robin scheme at the message level. The
programmable control registers are shown in Figure 23 . This scheme allows configurability of the queue
transmission order, as well as the weight of each queue within the round robin.
The TX state machine begins by processing the current TX_Queue_Map(n). It will attempt to process the
queue and number of buffer descriptors from that queue programmed in this mapping entry. Then it will
move to TX_Queue_Map(n+1), followed by TX_Queue_Map(n+2) and so forth. It is important to note that
this mapping order is fixed in a circular pattern. Each mapper can point to any queue and multiple
mappers can point to a single queue. If a mapper points to an inactive queue, the peripheral recognizes
this and moves to the next mapper. In order for an active queue to transmit packets, at least one mapper
must be pointing to that queue. The default settings dictate an equally weighted round-robin that starts on
queue0 and increments by one until reaching queue15.
The round-robin scheme does not provide precise control over the order of data sent out of the device.
The ordering of the messages provided by the entries in the Weighted Round Robin Programming
Registers is not an absolute guarantee of the actual transmission order or receive order of the messages.
For example, take a case where there are two active queues and the TX_Queue_Map registers are setup
to continuously send 2 messages from Queue 0, followed by 1 message from Queue 1. If the first
message from Queue 0 attempts to reuse a mailbox/letter combination already in use (Content
Addressable Memory (CAM) violation), or fails to gain outbound credit due to buffer congestion at a given
priority, then the state machine will re-evaluate the TX_Queue_Map to decide on the next step. Since the
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SRIO Functional Description
TX_Queue_Map has been programmed to send two messages from Queue 0 before moving to Queue 1,
it will re-attempt to send the same message from Queue 0 before moving on. Whether it is successful or
not, the next attempt will come from Queue 1. Within a given queue, the hardware will always try to send
the head buffer descriptor and can not move to the next buffer descriptor in the queue until a completion
code is written. The weighted round robin control advocates, that statistically over many transmissions, the
messages will be transmitted in accordance with the percentages programmed into the registers .
Network traffic can also affect the packet delivery order. The physical layer of the RapidIO peripheral can
re-order packets of different priorities when fabric congestion occurs.
If message ordering is needed, the following must be obeyed:
• Multi Segmented Messages
– If there are only two devices A sending to B where ordering has to be guaranteed:
• - Use one TX queue
• - Use the same priority
• - Map all messages to the same RX queue
– If there are multiple devices A and B both sending to C, and ordering has to be guaranteed for
both:
• - Use one TX queue in each sending device
• - Use the same priority within each TX queue
• - Map all A messages to the same RX queue and all B messages to another queue by disabling
the promiscuous mode and programming allowable sourceIDs.
• Single Segmented Messages
– There will never be a retry so even if there are multiple senders:
• - Use one TX queue in each sending device
• - Use the same priority within each TX queue
• - Map all messages to the same RX queue
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SRIO Functional Description
Figure 23. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)
TX_QUEUE_CNTL0 - Address Offset 7E0h
<-------------------------------- TX_Queue_Map3 -----------------------------> <-------------------------------- TX_Queue_Map2 ----------------------------->
31 28 27 24 23 20 19 16
Number of Msgs Queue Pointer Number of Msgs Queue Pointer
R/W-0h R/W-3h R/W-0 R/W-2h
<-------------------------------- TX_Queue_Map1 -----------------------------> <-------------------------------- TX_Queue_Map0 ----------------------------->
15 12 11 8 7 4 3 0
Number of Msgs Queue Pointer Number of Msgs Queue Pointer
R/W-0h R/W-1h R/W-0h R/W-0h
TX_QUEUE_CNTL1 - Address Offset 7E4h
<-------------------------------- TX_Queue_Map7 -----------------------------> <-------------------------------- TX_Queue_Map6 ----------------------------->
31 28 27 24 23 20 19 16
Number of Msgs Queue Pointer Number of Msgs Queue Pointer
R/W-0 R/W-7h R/W-0h R/W-6h
<-------------------------------- TX_Queue_Map5 -----------------------------> <-------------------------------- TX_Queue_Map4 ----------------------------->
15 12 11 8 7 4 3 0
Number of Msgs Queue Pointer Number of Msgs Queue Pointer
R/W-0h R/W-5h R/W-0h R/W-4h
TX_QUEUE_CNTL2 - Address Offset 7E8h
<-------------------------------- TX_Queue_Map11 -----------------------------> <-------------------------------- TX_Queue_Map10 ----------------------------->
31 28 27 24 23 20 19 16
Number of Msgs Queue Pointer Number of Msgs Queue Pointer
R/W-0h R/W-Bh R/W-0h R/W-Ah
<-------------------------------- TX_Queue_Map9 -----------------------------> <-------------------------------- TX_Queue_Map8 ----------------------------->
15 12 11 8 7 4 3 0
Number of Msgs Queue Pointer Number of Msgs Queue Pointer
R/W-0h R/W-9h R/W-0h R/W-8h
TX_QUEUE_CNTL3 - Address Offset 7ECh
<-------------------------------- TX_Queue_Map15 -----------------------------> <-------------------------------- TX_Queue_Map14 ----------------------------->
31 28 27 24 23 20 19 16
Number of Msgs Queue Pointer Number of Msgs Queue Pointer
R/W-0h R/W-Fh R/W-0h R/W-Eh
<-------------------------------- TX_Queue_Map13 -----------------------------> <-------------------------------- TX_Queue_Map12 ----------------------------->
15 12 11 8 7 4 3 0
Number of Msgs Queue Pointer Number of Msgs Queue Pointer
R/W-0h R/W-Dh R/W-0h R/W-Ch
Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)
Field Pair Register[Bits] Field Value Description
TX_Queue_Map0 TX_QUEUE_CNTL0[3–0] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL0[7–4] Number of Msgs 0h to Fh Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map1.
TX_Queue_Map1 TX_QUEUE_CNTL0[11–8] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL0[15–12] Number of Msgs 0h to Fh Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map2.
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SRIO Functional Description
Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued)
Field Pair Register[Bits] Field Value Description
TX_Queue_Map2 TX_QUEUE_CNTL0[19–16] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL0[23–20] Number of Msgs 0h to Fh Number of contiguous messages
TX_Queue_Map3 TX_QUEUE_CNTL0[27–24] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL0[31–28] Number of Msgs 0h to Fh Number of contiguous messages
TX_Queue_Map4 TX_QUEUE_CNTL1[3–0] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL1[7–4] Number of Msgs 0h to Fh Number of contiguous messages
TX_Queue_Map5 TX_QUEUE_CNTL1[11–8] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL1[15–12] Number of Msgs 0h to Fh Number of contiguous messages
TX_Queue_Map6 TX_QUEUE_CNTL1[19–16] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL1[23–20] Number of Msgs 0h to Fh Number of contiguous messages
TX_Queue_Map7 TX_QUEUE_CNTL1[27–24] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL1[31–28] Number of Msgs 0h to Fh Number of contiguous messages
TX_Queue_Map8 TX_QUEUE_CNTL2[3–0] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL2[7–4] Number of Msgs 0h to Fh Number of contiguous messages
TX_Queue_Map9 TX_QUEUE_CNTL2[11–8] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL2[15–12] Number of Msgs 0h to Fh Number of contiguous messages
TX_Queue_Map10 TX_QUEUE_CNTL2[19–16] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
TX_QUEUE_CNTL2[23–20] Number of Msgs 0h to Fh Number of contiguous messages
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map3.
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map4.
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map5.
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map6.
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map7.
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map8.
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map9.
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map10.
programmed to point to any one of the 16
TX buffer descriptor queues.
(descriptors) to process before moving to
TX_Queue_Map11.
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SRIO Functional Description
Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued)
Field Pair Register[Bits] Field Value Description
TX_Queue_Map11 TX_QUEUE_CNTL2[27–24] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL2[31–28] Number of Msgs 0h to Fh Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map12.
TX_Queue_Map12 TX_QUEUE_CNTL3[3–0] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL3[7–4] Number of Msgs 0h to Fh Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map13.
TX_Queue_Map13 TX_QUEUE_CNTL3[11–8] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL3[15–12] Number of Msgs 0h to Fh Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map14.
TX_Queue_Map14 TX_QUEUE_CNTL3[19–16] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL3[23–20] Number of Msgs 0h to Fh Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map15.
TX_Queue_Map15 TX_QUEUE_CNTL3[27–24] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL3[31–28] Number of Msgs 0h to Fh Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map0.
The TX queues are treated differently than the RX queues. A TX queue can mix single and multi-segment
message buffer descriptors. The software manages the queue usage.
All outgoing message segments have responses that indicate the status of the transaction. Responses
may indicate DONE, ERROR or RETRY. A buffer descriptor may be released back to CPU control
(OWNERSHIP = 0), only after all segment responses are received, or alternatively if a response timeout
occurs. Timeouts and response evaluation have high priority in the state-machine since they are the only
means to release TX packet resources. The CC is set in the buffer descriptor to indicate the response
status to the CPU. If there is a RETRY response, the TX CPPI module will immediately retry the packet
before continuing to the next queue in the round-robin loop, as long as the RETRY_COUNT is not
exceeded. Once this limit is exceeded, the buffer can be released back to CPU control with the
appropriate CC set. Retry of a message segment does not imply retrying a whole message. Only
segments for which a RETRY response is received should be re-transmitted. This will involve calculating
the correct starting point within the TX data buffer based on the failed segment number and message
length. To achieve respectable performance, the peripheral must not wait for a message/segment
response before sending out the next packet.
Since RapidIO allows for out-of-order responses, the TX CPPI hardware must support this functionality. As
responses are received, the hardware updates the corresponding TX buffer descriptor to reflect the status.
However, if the response is out-of-order, the hardware does not update the CP or set the corresponding
interrupt. Only after all preceding outstanding message responses are received, will the CP and interrupt
be updated. This ensures that a contiguous block of buffer descriptors, starting at the oldest outstanding
descriptor, has been processed by the hardware and is ready for the CPU to reclaim the buffers.
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SRIO Functional Description
A transaction timeout is used by all outgoing message and direct I/O packets. It has the same value and is
analogous to the request-to-response timer discussed in the RX CPPI and LSU sections, which is defined
by the 24-bit value in the port response time-out CSR (See Section 2.3.3.3 ). The RapidIO Interconnect
Specification states that the maximum time interval (all 1s) is between 3 and 6 seconds. A logical layer
timeout occurs if the response packet is not received before a countdown timer (initialized to this CSR
value) reaches zero. Since transaction responses can be acknowledged out-of-order, a timer is needed for
each supported outstanding packet in the TX queue. Each outstanding packet response timer requires a
4-bit register. The register is loaded with the current timecode when the transaction is sent. Each time the
timecode changes, a 4-bit compare is done to the 16 outstanding packet registers. If the register becomes
equal to the timecode again, without a response being seen, then the transaction has timed out and the
buffer descriptor is written.
Essentially, instead of the 24-bit value representing the period of the response timer, the period is now
defined as P = (2
24
x 16)/F. This means the countdown timer frequency needs to be 44.7–89.5 MHz for a
6–3 second response timeout. Since the needed timer frequency is derived from the DMA bus clock
(which is device dependent), the hardware supports a programmable configuration register field to
properly scale the clock frequency. This configuration register field is described in the Peripheral Setting
Control register (Address offset 0020h).
The CPU initiates a TX queue teardown by writing to the TX Queue Teardown command register.
Teardown of a TX queue will cause the following actions:
• No new messages will be sent.
• All messages (single and multi-segment) already started will be completed.
– Failing to complete the message TX would leave an active receiver blocked waiting for the final
segments until the transaction eventually times-out.
– Note that normal TX State Machine operation is to not send any more segments once an error
response has been received on any segment. So if the receiver has also been torn-down (and is
receiving error responses) multi-segment transmit will complete as soon as all in-transit segments
have been responded to.
• When all in-transit messages/segments have been responded to, teardown will be completed as
follows:
– If the queue is active, the teardown bit will be set in the next buffer descriptor in the queue. The
peripheral completes the teardown procedure by clearing the HDP register, setting the CP register
to FFFFFFFCh, and issuing an interrupt for the given queue. The teardown command register bit is
automatically cleared by the peripheral.
– If the queue is in-active (no additional buffer descriptors available), or becomes inactive after a
message in transmission is completed, no buffer descriptor fields are written. The HDP register and
the CP register remain unchanged. An interrupt is not issued. The teardown command register bit
is automatically cleared by the peripheral.
– Because of topology differences between flow's response, packets may arrive in a different order to
the order of requests.
After the teardown process is complete and the interrupt is serviced by the CPU, software must
re-initialize the TX queue to restart normal operation.
2.3.4.3 Reset and Power Down State
Upon reset, the CPPI module must be configured by the CPU. The CPU sets up the receive and transmit
queues in memory. Then the CPU updates the CPPI module with the appropriate RX/TX DMA state head
descriptor pointer, so the peripheral knows with which buffer descriptor address to start. Additionally, the
CPU must provide the CPPI module with initial buffer descriptor values for each data buffer.
The CPPI module can be powered down if the message passing protocol is not being supported in the
application. For example, if the direct I/O protocol is being used for data transfers, powering down the
CPPI module will save power. In this situation, the buffer descriptor queue SRAMs and mailbox mapper
logic should be powered down. Clocks should be gated to these blocks while in the power down state.
Section 2.3.10 describes this in detail.
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SRIO Functional Description
2.3.4.4 Message Passing Software Requirements
Software performs the following functions for messaging:
RX Operation
• Assigns Mailbox-to-queue mapping and allowable SourceIDs/mailbox- Queue Mapping
• Sets up associated buffer descriptor memory – CPPI RAM or L2 RAM
• Link-lists the buffer descriptors, next_descriptor_pointer
• Assigns single segment (256-byte payload) and multi-segment (4K-byte payload) buffers to queues
buffer_length
• Assigns buffer descriptor to data buffer, buffer_pointer
• Gives control of the buffer to the peripheral, ownership = 1
Configures and initiates RX queues
• Assigns Head Descriptor Pointer, HDP, for up to 16 queues: RX DMA State HDP
• Port begins to consume buffers beginning with HDP descriptor and sets ownership = 0 for each buffer
descriptor used. Writes Completion Pointer, CP, RX DMA State CP and moves to next buffer.
• Port hardware generates pending interrupt when CP is written. Physical interrupt generated when
Interrupt Pacing Count down timer = 0.
Processes interrupt
• Determines ICSR bit and process corresponding queue until ownership = 1 or eoq = 1
• Sets processed buffer descriptor ownership = 1
• Writes CP value of last buffer descriptor processed
• Port hardware clears ICSR bit only if the CP value written by CPU equals port written value in the RX
DMA State CP register
• Resets interrupt pacing value
TX Operation
Sets up associated buffer descriptor memory – CPPI RAM or L2 RAM
• Link-lists the buffer descriptors, next_descriptor_pointer
• Assigns buffer descriptor to data buffer, buffer_pointer
• CPU writes buffer descriptors and sets ownership = 1 for each used.
• Specifies RIO fields: Dest_id, Pri, tt, Mailbox
• Sets parameters: PortID, Message_length
• Port starts queue transmit on CPU write to HDP for up to 16 queues - TX DMA State HDP
• Port processes corresponding queues until ownership = 0 or next_descriptor_pointer = all 0s. Port sets
eoq = 1 and writes all 0s to the HDP.
• When each packet transmission is complete, the port sets ownership = 0 and issues an interrupt to the
CPU by writing the last processed buffer descriptor address to the CP, TX DMA State CP
Processes interrupt
• The CPU processes the buffer queue to reclaim buffers. If ownership = 0, the packet has been
transmitted and the buffer is reclaimed.
• CPU processes the queue until eoq = 1 or ownership = 1
• CPU determines all packets have been transmitted if ownership = 0, eoq = 1, and
next_descriptor_pointer = all 0s in last processed buffer descriptor
• CPU acknowledges the interrupt after re-claiming all available buffer descriptors.
• CPU acknowledges the interrupt by writing the CP value
• This value is compared against the port written value in the TX DMA State CP register, if equal, the
interrupt is deasserted.
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Initialization Example
SRIO_REGS->Queue0_RXDMA_HDP = 0 ;
SRIO_REGS->Queue1_RXDMA_HDP = 0 ;
SRIO_REGS->Queue2_RXDMA_HDP = 0 ;
SRIO_REGS->Queue3_RXDMA_HDP = 0 ;
SRIO_REGS->Queue4_RXDMA_HDP = 0 ;
SRIO_REGS->Queue5_RXDMA_HDP = 0 ;
SRIO_REGS->Queue6_RXDMA_HDP = 0 ;
SRIO_REGS->Queue7_RXDMA_HDP = 0 ;
SRIO_REGS->Queue8_RXDMA_HDP = 0 ;
SRIO_REGS->Queue9_RXDMA_HDP = 0 ;
SRIO_REGS->Queue10_RXDMA_HDP = 0 ;
SRIO_REGS->Queue11_RXDMA_HDP = 0 ;
SRIO_REGS->Queue12_RXDMA_HDP = 0 ;
SRIO_REGS->Queue13_RXDMA_HDP = 0 ;
SRIO_REGS->Queue14_RXDMA_HDP = 0 ;
SRIO_REGS->Queue15_RXDMA_HDP = 0 ;
Queue Mapping
SRIO_REGS->RXU_MAP01_L = CSL_FMK( SRIO_RXU_MAP01_L_LETTER_MASK, 3)|
CSL_FMK( SRIO_RXU_MAP01_L_MAILBOX_MASK, 0x3F) |
CSL_FMK( SRIO_RXU_MAP01_L_LETTER, 0) |
CSL_FMK( SRIO_RXU_MAP01_L_MAILBOX, 1) |
CSL_FMK( SRIO_RXU_MAP01_L_SOURCEID, 0xBEEF);
SRIO_REGS->RXU_MAP01_H = CSL_FMK( SRIO_RXU_MAP01_H_TT, 1) |
CSL_FMK( SRIO_RXU_MAP01_H_QUEUE_ID, 0) |
CSL_FMK( SRIO_RXU_MAP01_H_PROMISCUOUS, 1)|
CSL_FMK( SRIO_RXU_MAP01_H_SEGMENT_MAPPING, 1);
RX Buffer Descriptor
RX_DESCP0_0->RXDESC0 = CSL_FMK( SRIO_RXDESC0_N_POINTER,(int )RX_DESCP0_1 ); //link to RX_DESCP0_1
SRIO Functional Description
RX_DESCP0_0->RXDESC1 = CSL_FMK( SRIO_RXDESC1_B_POINTER,(int )&rcvBuff1[0] );
RX_DESCP0_0->RXDESC2 = CSL_FMK( SRIO_RXDESC2_SRC_ID, 0xBEEF)|
CSL_FMK( SRIO_RXDESC2_PRI, 1) |
CSL_FMK( SRIO_RXDESC2_TT, 1) |
CSL_FMK( SRIO_RXDESC2_MAILBOX, 0);
RX_DESCP0_0->RXDESC3 = CSL_FMK( SRIO_RXDESC3_SOP,1 ) |
CSL_FMK( SRIO_RXDESC3_EOP,1 ) |
CSL_FMK( SRIO_RXDESC3_OWNERSHIP,1 )|
CSL_FMK( SRIO_RXDESC3_EOQ,1 ) |
CSL_FMK( SRIO_RXDESC3_TEARDOWN,0 ) |
CSL_FMK( SRIO_RXDESC3_CC,0 ) |
CSL_FMK( SRIO_RXDESC3_MESSAGE_LENGTH,MLEN_512DW);
RX_DESCP0_1->RXDESC0 = CSL_FMK( SRIO_RXDESC0_N_POINTER, 0); //end of message
RX_DESCP0_1->RXDESC1 = CSL_FMK( SRIO_RXDESC1_B_POINTER,(int )&rcvBuff2[0] );
RX_DESCP0_1->RXDESC2 = CSL_FMK( SRIO_RXDESC2_SRC_ID, 0xBEEF)|
CSL_FMK( SRIO_RXDESC2_PRI, 1) |
CSL_FMK( SRIO_RXDESC2_TT, 1) |
CSL_FMK( SRIO_RXDESC2_MAILBOX, 1);
RX_DESCP0_1->RXDESC3 = CSL_FMK( SRIO_RXDESC3_SOP,1 ) |
CSL_FMK( SRIO_RXDESC3_EOP,1 ) |
CSL_FMK( SRIO_RXDESC3_OWNERSHIP,1 )|
CSL_FMK( SRIO_RXDESC3_EOQ,1 ) |
CSL_FMK( SRIO_RXDESC3_TEARDOWN,0 ) |
CSL_FMK( SRIO_RXDESC3_CC,0 ) |
CSL_FMK( SRIO_RXDESC3_MESSAGE_LENGTH,MLEN_512DW );
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Descriptor
Descriptor
Buffer
Buffer
PortRXDMA
state
RXqueueheaddescriptor
pointer
SRIO Functional Description
Figure 24. RX Buffer Descriptors
TX Buffer Descriptor
TX_DESCP0_0->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER,(int )TX_DESCP0_1 ); //link to
TX_DESCP0_1
TX_DESCP0_0->TXDESC1 = CSL_FMK( SRIO_TXDESC1_B_POINTER,(int )&xmtBuff1[0] ); //Buffer
Pointer
TX_DESCP0_0->TXDESC2 = CSL_FMK( SRIO_TXDESC2_DESTID, 0xBEEF) |
CSL_FMK( SRIO_TXDESC2_PRI, 1) |
CSL_FMK( SRIO_TXDESC2_TT, 1) |
CSL_FMK( SRIO_TXDESC2_PORTID, 3) |
CSL_FMK( SRIO_TXDESC2_SSIZE, SSIZE_256B)|
CSL_FMK( SRIO_TXDESC2_MAILBOX, 0);
TX_DESCP0_0->TXDESC3 = CSL_FMK( SRIO_TXDESC3_SOP,1 ) |
CSL_FMK( SRIO_TXDESC3_EOP,1 ) |
CSL_FMK( SRIO_TXDESC3_OWNERSHIP,1 ) |
CSL_FMK( SRIO_TXDESC3_EOQ,1 ) |
CSL_FMK( SRIO_TXDESC3_TEARDOWN,0 ) |
CSL_FMK( SRIO_TXDESC3_RETRY_COUNT,0 )|
CSL_FMK( SRIO_TXDESC3_MESSAGE_LENGTH,MLEN_512DW );
TX_DESCP0_1->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER, 0); //end of message
TX_DESCP0_1->TXDESC1 = CSL_FMK( SRIO_TXDESC1_B_POINTER,(int )&xmtBuff2[0] );
TX_DESCP0_1->TXDESC2 = CSL_FMK( SRIO_TXDESC2_DESTID, 0xBEEF) |
CSL_FMK( SRIO_TXDESC2_PRI, 1) |
CSL_FMK( SRIO_TXDESC2_TT, 1) |
CSL_FMK( SRIO_TXDESC2_PORTID, 3) |
CSL_FMK( SRIO_TXDESC2_SSIZE, SSIZE_256B)|
CSL_FMK( SRIO_TXDESC2_MAILBOX, 1);
TX_DESCP0_1->TXDESC3 = CSL_FMK( SRIO_TXDESC3_SOP,1 ) |
CSL_FMK( SRIO_TXDESC3_EOP,1 ) |
CSL_FMK( SRIO_TXDESC3_OWNERSHIP,1 ) |
CSL_FMK( SRIO_TXDESC3_EOQ,1 ) |
CSL_FMK( SRIO_TXDESC3_TEARDOWN,0 ) |
CSL_FMK( SRIO_TXDESC3_RETRY_COUNT,0 )|
CSL_FMK( SRIO_TXDESC3_MESSAGE_LENGTH,MLEN_512DW );
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Descriptor
Descriptor
Buffer
Buffer
Port TXDMA
state
TXqueueheaddescriptor
pointer
2.3.5 Maintenance
SRIO Functional Description
Figure 25. TX Buffer Descriptors
Start Message Passing
SRIO_REGS->Queue0_RXDMA_HDP = (int )RX_DESCP0_0 ;
SRIO_REGS->Queue0_TXDMA_HDP = (int )TX_DESCP0_0 ;
The type 8 MAINTENANCE packet format accesses the RapidIO capability registers (CARs), command
and status registers (CSRs), and data structures. Unlike other request formats, the type 8 packet format
serves as both the request and the response format for maintenance operations. Type 8 packets contain
no addresses and only contain data payloads for write requests and read responses. All configuration
register read accesses are word (4-byte) accesses. All configuration register write accesses are also word
(4-byte) accesses.
The wrsize field specifies the maximum size of the data payload for multiple double-word transactions.
The data payload may not exceed that size but may be smaller if desired. Both the maintenance read and
the maintenance write request generate the appropriate maintenance response.
The maintenance port-write operation is a write operation that does not have guaranteed delivery and
does not have an associated response. This maintenance operation is useful for sending messages such
as error indicators or status information from a device that does not contain an endpoint, such as a switch.
The data payload is typically placed in a queue in the targeted endpoint and an interrupt is typically
generated to a local processor. A port-write request to a queue that is full or busy servicing another
request may be discarded.
SRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 );
SRIO_REGS->LSU1_REG1 = CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET, (int )car_csr );
SRIO_REGS->LSU1_REG2 = CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, (int )&xmtBuff[0]);
SRIO_REGS->LSU1_REG3 = CSL_FMK( SRIO_LSU1_REG3_BYTE_COUNT,byte_count );
SRIO_REGS->LSU1_REG4 = CSL_FMK( SRIO_LSU1_REG4_OUTPORTID,0 ) |
CSL_FMK( SRIO_LSU1_REG4_PRIORITY,0 ) |
CSL_FMK( SRIO_LSU1_REG4_XAMSB,0 ) | //no extended address
CSL_FMK( SRIO_LSU1_REG4_ID_SIZE,1 ) |
CSL_FMK( SRIO_LSU1_REG4_DESTID,0xBEEF ) |
CSL_FMK( SRIO_LSU1_REG4_INTERRUPT_REQ,0 );
SRIO_REGS->LSU1_REG5 = CSL_FMK( SRIO_LSU1_REG5_DRBLL_INFO,0x0000 )|
CSL_FMK( SRIO_LSU1_REG5_HOP_COUNT,0x03 ) |
CSL_FMK( SRIO_LSU1_REG5_PACKET_TYPE,type ); //type = REQ_MAINT_RD
2.3.6 Doorbell Operation
The doorbell operation is shown in Figure 26 . It consists of the DOORBELL and RESPONSE transactions
(typically a DONE response), and it is used by a processing element to send a very short message to
another processing element through the interconnect fabric. The DOORBELL transaction contains the info
field to hold information and does not have a data payload. This field is software-defined and can be used
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acklD rsv prio tt 1010 destID sourcelD Reserved srcTID
Reserved DoorbellReg# rsv
Doorbellbit
CRC
PHYLOGTRALOGTRAPHY
5 3 2 2 4 8 8 8 8
9 2
1
4
16
1632
16
4
2
10
info(msb)
8
info(lsb)
8
SRIO Functional Description
for any desired purpose; see the RapidIO Interconnect Specification, Section 3.1.4, Type 10 Packet
Formats (Doorbell Class), for information about the info field. A processing element that receives a
doorbell transaction takes the packet and puts it in a doorbell message queue within the processing
element. This queue may be implemented in hardware or in local memory. This behavior is similar to that
of typical message passing mailbox hardware. The local processor is expected to read the queue to
determine the sending processing element and the info field, and determine what action to take.
The DOORBELL functionality is user-defined, but this packet type is commonly used to initiate DSP core
(CPU) interrupts. A DOORBELL packet is not associated with a particular data packet that was previously
transferred, so the info field of the packet must be configured to reflect the DOORBELL bit to be serviced
for the correct TID (Transfer Information Descriptor) information to be processed.
Figure 26. Doorbell Operation
The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There
are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers
(see Table 23 ). Each bit can be assigned to any core as described below by the Interrupt Condition
Routing Registers. Additionally, each status bit is user-defined for the application. For instance, it may be
desirable to support multiple priorities with multiple TID circular buffers per core if control data uses a high
priority (for example, priority = 2), while data packets are sent on priority 0 or 1. This allows the control
packets to have preference in the switch fabric and arrive as quickly as possible. Since it may be required
to interrupt the CPU for both data and control packet processing separately, separate circular buffers are
used, and DOORBELL packets need to distinguish between them for interrupt servicing. If any reserved
bit in the DOORBELL info field is set, an error response is sent.
Table 23. Examples of DOORBELL_INFO Designations (See Figure 26 )
info Field Segments Value Written To
Reserved Reg # rsv Bit LSUn_REG5 Routing Bits Status Bit
000000000b 00b 0b 0000b 0000h DOORBELL0_ICRR[3:0] DOORBELL0_ICSR[0]
000000000b 00b 0b 1001b 0009h DOORBELL0_ICRR2[7:4] DOORBELL0_ICSR[9]
000000000b 01b 0b 0111b 0027h DOORBELL1_ICRR[31:28] DOORBELL1_ICSR[7]
000000000b 01b 0b 1100b 002Ch DOORBELL1_ICRR2[19:16] DOORBELL1_ICSR[12]
000000000b 10b 0b 0101b 0045h DOORBELL2_ICRR[23:20] DOORBELL2_ICSR[5]
000000000b 10b 0b 1111b 004Fh DOORBELL2_ICRR2[31:28] DOORBELL2_ICSR[15]
000000000b 11b 0b 0110b 0066h DOORBELL3_ICRR[27:24] DOORBELL3_ICSR[6]
000000000b 11b 0b 1011b 006Bh DOORBELL3_ICRR2[15:12] DOORBELL3_ICSR[11]
Doorbell Doorbell Field Of Doorbell Interrupt Doorbell Interrupt
DOORBELL_INFO Associated Mapped To This
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2.3.7 Atomic Operations
SRIO Functional Description
SRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 );
SRIO_REGS->LSU1_REG1 = CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET, 0);
SRIO_REGS->LSU1_REG2 = CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, 0);
SRIO_REGS->LSU1_REG3 = CSL_FMK( SRIO_LSU1_REG3_BYTE_COUNT, 0 );
SRIO_REGS->LSU1_REG4 = CSL_FMK( SRIO_LSU1_REG4_OUTPORTID,1 ) |
CSL_FMK( SRIO_LSU1_REG4_PRIORITY,0 ) |
CSL_FMK( SRIO_LSU1_REG4_XAMSB,0 ) |
CSL_FMK( SRIO_LSU1_REG4_ID_SIZE,1 ) |
CSL_FMK( SRIO_LSU1_REG4_DESTID,0xBEEF )|
CSL_FMK( SRIO_LSU1_REG4_INTERRUPT_REQ,0 );
SRIO_REGS->LSU1_REG5 = CSL_FMK( SRIO_LSU1_REG5_DRBLL_INFO,0x0000 )|
CSL_FMK( SRIO_LSU1_REG5_HOP_COUNT,0x03 ) |
CSL_FMK( SRIO_LSU1_REG5_PACKET_TYPE,type );//type = DOORBELL
The Atomic operation is a combination read and write operation. The destination reads the data at the
specified address, returns the read data to the requestor, performs the required operation to the data, and
then writes the modified data back to the specified address without allowing any intervening activity to that
address. Defined operations are increment, decrement, test-and-swap, set, and clear (see Table 3 , Packet
Type). Of these, only test-and-swap requires the requesting processing element to supply data. Incoming
Atomic operations which target the device are not supported for internal L2 memory or registers. Atomic
request operations to external devices are supported and have a response packet.
Request Atomic operations (Ftype 2) never contain a data payload. These operations are like NREAD
(24h) transactions. The data payload size for the response to an Atomic transaction is 8 bytes. The
addressing scheme defined for the read portion of the Atomic transaction also controls the size of the
atomic operation in memory so that the bytes are contiguous and of size byte, half-word (2 bytes), or word
(4 bytes), and are aligned to that boundary and byte lane as with a regular read transaction. Double-word
(8-byte), 3-byte, 5-byte, 6-byte, and 7-byte Atomic transactions are not allowed.
Atomic test-and-swap operations (Ftype 5) to external devices are limited to a payload of one double-word
(8 bytes). These operations are like NWRITE with response (55h) transactions. The addressing scheme
defined for the write transactions also controls the size of the Atomic operation in memory so that the
bytes are contiguous and of size byte, half-word (2 bytes), or word (4 bytes), and are aligned to that
boundary and byte lane as with a regular write transaction. Double-word (8-byte), 3-byte, 5-byte, 6-byte,
and 7-byte Atomic test-and-swap transactions are not allowed. Upon receipt of the request, the targeted
device swaps the contents of the specified memory location and the payload if the contents of the memory
location are all 0s. The contents of the memory location are returned, and the appropriate completion code
is set in the LSU status register (LSU n_REG6). The completion codes are listed in Table 15 .
2.3.8 Congestion Control
The RapidIO Logical Layer Flow Control Extensions Specification. This section describes the requirements
and implementation of congestion control within the peripheral.
The peripheral is notified of switch fabric congestion through type 7 RapidIO packets. The packets are
referred to as Congestion Control Packets (CCPs). The purpose of these packets is to turn off (Xoff), or
turn on (Xon) specific flows defined by DESTID and PRIORITY of outgoing packets. CCPs are sent at the
highest priority in an attempt to address fabric congestion as quickly as possible. CCPs do not have a
response packet and they do not have guaranteed delivery.
When the peripheral receives an Xoff CCP, the peripheral must block outgoing LSU and CPPI packets
that are destined for that flow. When the peripheral receives an Xon, the flow may be enabled. Since
CCPs may arrive from different switches within the fabric, it is possible to receive multiple Xoff CCPs for
the same flow. For this reason, the peripheral must maintain a table and count of Xoff CCPs for each flow.
For example, if two Xoff CCPs are received for a given flow, two Xon CCPs must be received before the
flow is enabled.
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ReservedFLOW_CNTL0
31-18
R-0x00000
TT
17-16
R/W-01
FLOW_CNTL_ID
15-0
R/W-0x0000
ReservedFLOW_CNTL1
31-18
R-0x00000
TT
17-16
R/W-01
FLOW_CNTL_ID
15-0
R/W-0x0000
ReservedFLOW_CNTL2
31-18
R-0x00000
TT
17-16
R/W-01
FLOW_CNTL_ID
15-0
R/W-0x0000
ReservedFLOW_CNTL15
31-18
R-0x00000
TT
17-16
R/W-01
FLOW_CNTL_ID
15-0
R/W-0x0000
SRIO Functional Description
2.3.8.1 Detailed Description
Since CCPs do not have guaranteed delivery and can be dropped by the fabric, an implicit method of
enabling an Xoff’d flow must exist. A simple timeout method is used. Additionally, flow control checks can
be enabled or disabled through the Transmit Source Flow Control Masks. Received CCPs are not passed
through the DMA bus interface.
To avoid large and complex table management, a basic scheme is implemented for congestion
management. The primary goal is to avoid large parallel searches of a centralized congested route table
for each outgoing packet request. The congested route table requirements and subsequent searches
would be overwhelming if each possible DESTID and PRIORITY combination had its own entry. To
implement a more basic scheme, the following assumptions have been made:
• A small number of flows constitute the majority of traffic, and these flows are most likely to cause
congestion
• HOL blocking is undesired, but allowable for TX CPPI queues
• Flow control will be based on DESTID only, regardless of PRIORITY
The congested route table is therefore more static in nature. Instead of dynamically updating a table with
each CCP’s flow information as it arrives, a small finite-entry table is set up and configured by software to
reflect the more critical flows it is using. Only these flows have a discrete table entry. A 16 entry table
reflects 15 critical flows, leaving the sixteenth entry for general other flows, which are categorized
together. Figure 27 and Table 24 summarize the DESTID table entries that are programmable by the CPU
through dedicated flow control registers. A 3-bit hardware counter is implemented for table entries 0
through 14, to maintain a count of Xoff CCPs for that flow. The other flows table entry counts Xoff CCPs
for all flows other than the discrete entries. The counter for this table entry has 5 bits. All outgoing flows
with non-zero Xoff counts are disabled. The counter value is decremented for each corresponding Xon
CCP that is received, but it is not decrement below zero. Additionally, a hardware timer exists for each
table entry to turn on flows that may have been abandoned by lost Xon CCPs. The timer value is of an
order of magnitude larger than the 32-bit Port Response Time-out CSR value. For this reason, each
transmission source adds 2 bits to its 4-bit response time-out counter. Descriptions of this type of time-out
counter are in Section 2.3.3.3 and Section 2.3.4.2 . The additional 2 bits count three timecode revolutions
and provide an implicit Xon timer equal to 3x the Response time-out counter value.
Figure 27. Flow Control Table Entry Registers (Address Offset 0900h–093Ch)
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
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Reserved
RIO_LSUn_FLOW_MASKS
(AddressOffsets:0x041C,
0x043C,0x045C,0x047C)
31-16
R,0x0000
LSUnFlowMask
15-0
R/W,0xFFFF
TXQueue1
FlowMask
RIO_TX_CPPI_FLOW_MASKS0
(AddressOffsets:0x0704)
31-16
R/W,0xFFFF
TXQueue0
FlowMask
15-0
R/W,0xFFFF
TXQueue3
FlowMask
RIO_TX_CPPI_FLOW_MASKS1
(AddressOffsets:0x0708)
31-16
R/W,0xFFFF
TXQueue2
FlowMask
15-0
R/W,0xFFFF
TXQueue5
FlowMask
RIO_TX_CPPI_FLOW_MASKS2
(AddressOffsets:0x070C)
31-16
R/W,0xFFFF
TXQueue4
FlowMask
15-0
R/W,0xFFFF
TXQueue7
FlowMask
RIO_TX_CPPI_FLOW_MASKS3
(AddressOffsets:0x0710)
31-16
R/W,0xFFFF
TXQueue6
FlowMask
15-0
R/W,0xFFFF
TXQueue9
FlowMask
RIO_TX_CPPI_FLOW_MASKS4
(AddressOffsets:0x0714)
31-16
R/W,0xFFFF
TXQueue8
FlowMask
15-0
R/W,0xFFFF
TXQueue11
FlowMask
RIO_TX_CPPI_FLOW_MASKS5
(AddressOffsets:0x0718)
31-16
R/W,0xFFFF
TXQueue10
FlowMask
15-0
R/W,0xFFFF
TXQueue13
FlowMask
RIO_TX_CPPI_FLOW_MASKS6
(AddressOffsets:0x071C)
31-16
R/W,0xFFFF
TXQueue12
FlowMask
15-0
R/W,0xFFFF
TXQueue15
FlowMask
RIO_TX_CPPI_FLOW_MASKS7
(AddressOffsets:0x0720)
31-16
R/W,0xFFFF
TXQueue14
FlowMask
15-0
R/W,0xFFFF
SRIO Functional Description
Table 24. Flow Control Table Entry Register n (FLOW_CNTL n) Field Descriptions
Bit Field Value Description
31–18 Reserved 0 These read-only bits return 0s when read.
17–16 TT Transfer type for flow n
00b 8-bit destination IDs
01b 16-bit destination IDs
1xb Reserved
15–0 FLOW_CNTL_ID 0000h–FFFFh Destination ID for flow n. When 8-bit destination IDs are used (TT = 00b),
the 8 MSBs of this field are don't care bits.
Each transmit source, including any LSU and any TX CPPI queue, indicates which of the 16 flows it uses
with a 16-bit flow mask. Figure 28 illustrates the registers that contain the flow masks, and Figure 29
illustrates the general form of an individual flow mask. As can be seen from Table 25 , bits 0 through 15 of
the flow mask correspond to flows 0 through 15, respectively.
The CPU must configure the flow masks upon reset. The default setting is all 1s, indicating that the
transmit source supports all flows. If the register is set to all 0s, the transmit source does not support any
flow, and consequently, that source is never flow-controlled. If any of the table entry counters that a
transmit source supports have a corresponding non-zero Xoff count, the transmit source is flow-controlled.
A simple 16-bit bus indicates the Xoff state of all 16 flows and is compared to the transmit source mask
register. Each source interprets this result and performs flow control accordingly. For example, an LSU
module that is flow-controlled can reload its registers and attempt to send a packet to another flow, while a
TX CPPI queue that is flow-controlled may create HOL blocking issues on that queue.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FL15 FL14 FL13 FL12 FL11 FL10 FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; - n = Value after reset
Figure 28. Transmit Source Flow Control Masks
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
Figure 29. Fields Within Each Flow Mask
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SRIO Functional Description
Table 25. Fields Within Each Flow Mask
Bit Field Value Description
15 FL15 0 TX source does not support Flow 15 from table entry
1 TX source supports Flow 15 from table entry
14 FL14 0 TX source does not support Flow 14 from table entry
1 TX source supports Flow 14 from table entry
13 FL13 0 TX source does not support Flow 13 from table entry
1 TX source supports Flow 13 from table entry
12 FL12 0 TX source does not support Flow 12 from table entry
1 TX source supports Flow 12 from table entry
11 FL11 0 TX source does not support Flow 11 from table entry
1 TX source supports Flow 11 from table entry
10 FL10 0 TX source does not support Flow 10 from table entry
1 TX source supports Flow 10 from table entry
9 FL9 0 TX source does not support Flow 9 from table entry
1 TX source supports Flow 9 from table entry
8 FL8 0 TX source does not support Flow 8 from table entry
1 TX source supports Flow 8 from table entry
7 FL7 0 TX source does not support Flow 7 from table entry
1 TX source supports Flow 7 from table entry
6 FL6 0 TX source does not support Flow 6 from table entry
1 TX source supports Flow 6 from table entry
5 FL5 0 TX source does not support Flow 5 from table entry
1 TX source supports Flow 5 from table entry
4 FL4 0 TX source does not support Flow 4 from table entry
1 TX source supports Flow 4 from table entry
3 FL3 0 TX source does not support Flow 3 from table entry
1 TX source supports Flow 3 from table entry
2 FL2 0 TX source does not support Flow 2 from table entry
1 TX source supports Flow 2 from table entry
1 FL1 0 TX source does not support Flow 1 from table entry
1 TX source supports Flow 1 from table entry
0 FL0 0 TX source does not support Flow 0 from table entry
1 TX source supports Flow 0 from table entry
2.3.9 Endianness
RapidIO is based on Big Endian. This is discussed in detail in Section 2.4 of the RapidIO Interconnect
Specification. Essentially, Big Endian specifies the address ordering as the most significant bit/byte first.
For example, in the 29-bit address field of a RapidIO packet (shown in Figure 6 ) the left-most bit that is
transmitted first in the serial bit stream is the MSB of the address. Likewise, the data payload of the packet
is double-word aligned Big Endian, which means the MSB is transmitted first. Bit 0 of all the
RapidIO-defined MMR registers is the MSB.
All Endian-specific conversion is handled within the peripheral. For double-word aligned payloads, the
data should be written contiguously into memory beginning at the specified address. Any unaligned
payloads will be padded and properly aligned within the 8-byte boundary. In this case, WDPTR, RDSIZE,
and WRSIZE RapidIO header fields indicate the byte position of the data within the double-word
boundary. An example of an unaligned transfer is shown in Section 2.4 of the RapidIO Interconnect
Specification.
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2.3.9.1 Translation for MMR space
A0A0A2
A2
A1A1A3
A3
L2offset0x0
DSP definedMMR
offset0x1000
Byte
lane0
31
Byte
lane3
DMA 32b
0
RapidIOdefinedbitpositions
A0 A1 A2 A3
310
MMRoffset0x0000
B0 B1 B2 B3
MMRoffset0x0004
C0
C1 C2 C3
MMRoffset0x0008
D0
D1 D2 D3
MMRoffset0x000C
RapidIO
defined
MMR
offsets
A0A1A2A3B0B1B2B3C0C1C2C3D0D1D2D3
Headerfields
Type8
Response
A0
A1 A2 A3
Byte
address3
Byte
Byte
address0
L2offset0x0
B0 B1 B2 B3
L2offset0x4
C0 C1 C2 C3
L2offset0x8
D0
D1 D2 D3
L2offset0xC
BigEndian
LittleEndian
A3
A2 A1 A0
Byte
address0address3
L2offset0x0
B3 B2 B1 B0
L2offset0x4
C3 C2 C1 C0
L2offset0x8
D3
D2 D1 D0
L2offset0xC
Double-word0 Double-word1
ThedesiredoperationistosendaType8maintenancerequesttoanexternaldevice.
Thegoalistoread16BofRapidIOMMR fromanexternaldevice,startingoffset0x0000.
ThisoperationinvolvestheLSUblockandutilizestheDMA fortransferringtheresponse
packetpayload.
There are no Endian translation requirements for accessing the local MMR space. Regardless of the
device memory Endian configuration, all configuration bus accesses are performed on 32-bit values at a
fixed address position. The bit positions in the 32-bit word are defined by this specification. This means
that a memory image which will be copied to a MMR is identical between Little Endian and Big Endian
configurations. Configuration bus reads are performed in the same manner. Figure 30 illustrates the
concept. The desired operation is to locally update a serial RapidIO MMR (offset 1000h) with a value of
A0A1A2A3h, using the configuration bus.
When accessing RapidIO defined MMR within an external device, RapidIO allows 4 bytes, 8 bytes, or any
multiple of a double-word access (up to 64 bytes) for type 8 (maintenance) packets. The peripheral only
supports 4-byte accesses as the target, but can generate all sizes of request packets. RapidIO is defined
as Big Endian only, and has double-word aligned Big Endian packet payloads.
2.3.9.2 Endian Conversion (TMS320TCI6482)
The DMA, however, supports byte wide accesses. The peripheral performs Endian conversion on the
payload if Little Endian is used on the device. This conversion is not only applicable for type 8 packets, but
is also relevant for all outgoing payloads of NWRITE, NWRITE_R, SWRITE, NREAD, and message
packets. This means that the memory image is different between Little Endian and Big Endian
configurations, as shown in Figure 31 .
SRIO Functional Description
Figure 30. Configuration Bus Example
Figure 31. DMA Example
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SRIO Functional Description
2.3.10 Reset and Power Down
The RapidIO peripheral allows independent software controlled shutdown for the logical blocks listed in
Table 26 . With the exception of BLK0_EN for the memory-mapped registers (MMRs), when the BLK n_EN
signals are deasserted, the clocks are gated to these blocks, effectively providing a shutdown function.
Logical Block Reset _EN _EN _EN _EN _EN _EN _EN _EN _EN _EN
DMA interface √ √
MMRs: √ √
Reset/powerdown control
registers
MMRs: √ √ √
Non-reset/powerdown control
registers
Interrupt handling √ √
unit (IHU)
Traffic flow logic √ √
Congestion √ √
control unit
(CCU)
LSU (Direct I/O √ √ √
initiator)
MAU (Direct I/O √ √ √
target)
TXU (message √ √ √
passing initiator)
RXU (message √ √ √
passing target)
Port 0 datapath √ √ √
Port 1 datapath √ √ √
Port 2 datapath √ √ √
Port 3 datapath √ √ √
Table 26. Reset Hierarchy
Bus GBL BLK0 BLK1 BLK2 BLK3 BLK4 BLK5 BLK6 BLK7 BLK8
Reset of the SERDES macros is handled independently of the registers discussed in this section. The
SERDES can be configured to shutdown unused links or fully shutdown. SERDES TX and RX channels
may be enabled/disabled by writing to bit 0 of the SERDES_CFGTX n_CNTL and
SERDES_CFGRX n_CNTL registers. The PLL and remaining SERDES functional blocks can be controlled
by writing to the ENPLL signal in the SERDES_CFG0_CNTL register. This bit will drive the SERDES
signal input, which will gate the reference clock to these blocks internally. This reference clock is sourced
from a device pin specifically for the SERDES and is not derived from the CPU clock, thus it resets
asynchronously. ENPLL will disable all SERDES high-speed output clocks. Since these clocks are
distributed to all the links, ENPLL should only be used to completely shutdown the peripheral. It should be
noted that shutdown of SERDES links in between normal packet transmissions is not permissible for two
reasons. First, the serial RapidIO sends idle packets between data packets to maintain synchronization
and lane alignment. Without this mechanism, the RapidIO RX logic can be mis-aligned for both 1X and 4X
ports. Second, the lock time of the SERDES PLL would need to reoccur, which would slow down the
operation.
When the SERDES ENTX signal is held low, the corresponding transmitter is powered down. In this state,
both outputs, TXP and TXN, will be pulled high to VDDT.
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2.3.10.1 Reset and Power Down Summary
After reset, the state of the peripheral depends on the default register values.
Software can also perform a hard reset of each logical block within the peripheral via the GBL_EN and
BLK n_EN bits. The GBL_EN bit resets the peripheral, while the rest of the device is not reset. The
BLK n_EN bits shut down unused portions of the peripheral, which minimizes power by resetting the
appropriate logical block(s) and gating off the clock to the appropriate logical block(s). This should be
considered an abrupt reset that is independent of the state of the peripheral and that resets the peripheral
to its original state.
Upon reset of the peripheral, the device must reestablish communication with its link partner. Depending
on the system, this may include a discovery phase in which a host processor reads the peripheral’s
CAR/CSR registers to determine its capabilities. In its simplest form, it involves retraining the SERDES
and going through the initialization phase to synchronize on bit and word boundaries by using idle and
control symbols, as described in Section 5.5.2 of the Part VI of the RapidIO Interconnect Specification.
Until the peripheral and its partner are fully initialized and ready for normal operation, the peripheral will
not send any data packets or non-status control symbols.
• GBL_EN: Resets all MMRs, excluding Reset Ctl Values (0000h–01FCh). Resets all logical blocks
except MMR configuration bus i/f. While asserted, the slave configuration bus is operational.
• BLK_EN0: Resets all MMRs, excluding Reset Ctl Values (0000h–01FCh). Other logical blocks are
unaffected, including MMR configuration bus i/f.
• BLK_EN[n:1]: Single enable/reset per logical block. See Table 26 .
2.3.10.2 Enable and Enable Status Registers
The enable and enable status registers are comprised of two global registers and nine pairs of
block-specific registers. The global registers are summarized by Figure 32 , Figure 33 , Table 26 , and
Table 27 . The GBL_EN register is implemented with a single enable bit. This bit is logically ORed with the
reset input to the module and is fanned out to all logical blocks within the peripheral.
SRIO Functional Description
Figure 32. GBL_EN (Address 0030h)
31 1 0
Reserved EN
R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
Figure 33. GBL_EN_STAT (Address 0034h)
31 24
Reserved
R-0
23 16
Reserved
R-0
15 10 9 8
Reserved BLK8_EN_ BLK7_EN_
R-0 R-1 R-1
7 6 5 4 3 2 1 0
BLK6_EN_ BLK5_EN_ BLK4_EN_ BLK3_EN_ BLK2_EN_ BLK1_EN_ BLK0_EN_ GBL_EN_
STAT STAT STAT STAT STAT STAT STAT STAT
R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1
LEGEND: R = Read only; - n = Value after reset
STAT STAT
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SRIO Functional Description
Table 27. Global Enable and Global Enable Status Field Descriptions
Register (Bit) Field Value Description
GBL_EN(31–1) Reserved 0 These read-only bits return 0s when read.
GBL_EN(0) EN Global enable. This bit controls reset to all clock domains within the
GBL_EN_STAT(31–10) Reserved 0 These read-only bits return 0s when read.
GBL_EN_STAT(9) BLK8_EN_STAT Block 8 enable status. Logical block 8 is SRIO port 3.
GBL_EN_STAT(8) BLK7_EN_STAT Block 7 enable status. Logical block 7 is SRIO port 2.
GBL_EN_STAT(7) BLK6_EN_STAT Block 6 enable status. Logical block 6 is SRIO port 1.
GBL_EN_STAT(6) BLK5_EN_STAT Block 5 enable status. Logical block 5 is SRIO port 0.
GBL_EN_STAT(5) BLK4_EN_STAT Block 4 enable status. Logical block 4 is the message receive unit (RXU).
GBL_EN_STAT(4) BLK3_EN_STAT Block 3 enable status. Logical block 3 is the message transmit unit (TXU).
GBL_EN_STAT(3) BLK2_EN_STAT Block 2 enable status. Logical block 2 is the memory access unit (MAU).
GBL_EN_STAT(2) BLK1_EN_STAT Block 1 enable status. Logical block 1 is the Load/Store module, which is
GBL_EN_STAT(1) BLK0_EN_STAT Block 0 enable status. Logical block 0 is the set of memory-mapped control
GBL_EN_STAT(0) GBL_EN_STAT Global enable status
peripheral.
0 The peripheral is to be disabled (held in reset with clocks disabled).
1 The peripheral is to be enabled.
0 Logical block 8 is in reset with its clock off.
1 Logical block 8 is enabled with its clock running.
0 Logical block 7 is in reset with its clock off.
1 Logical block 7 is enabled with its clock running.
0 Logical block 6 is in reset with its clock off.
1 Logical block 6 is enabled with its clock running.
0 Logical block 5 is in reset with its clock off.
1 Logical block 5 is enabled with its clock running.
0 Logical block 4 is in reset with its clock off.
1 Logical block 4 is enabled with its clock running.
0 Logical block 3 is in reset with its clock off.
1 Logical block 3 is enabled with clock running.
0 Logical block 2 is in reset with its clock off.
1 Logical block 2 is enabled with its clock running.
comprised of the four Load/Store units (LSU1, LSU2, LSU3, and LSU4).
0 Logical block 1 is in reset with its clock off.
1 Logical block 1 is enabled with its clock running.
registers for the SRIO peripheral.
0 Logical block 0 is in reset with its clock off.
1 Logical block 0 is enabled with its clock running.
0 The peripheral is in reset with all its clocks off.
1 The peripheral is enabled with all its clocks running.
The 18 block-specific registers are represented by Figure 34 through Figure 39 . These register pairs have
bits with the same functions, which are described in Table 28 .
Figure 34. BLK0_EN (Address 0038h)
31 1 0
Reserved EN
R-0 R/W-1
LEGEND: R = Read, W = Write, - n = Value after reset
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SRIO Functional Description
Figure 35. BLK0_EN_STAT (Address 003Ch)
31 1 0
Reserved EN_STAT
R-0 R-1
LEGEND: R = Read, W = Write, - n = Value after reset
Figure 36. BLK1_EN (Address 0040h)
31 1 0
Reserved EN
R-0 R/W-1
LEGEND: R = Read, W = Write, - n = Value after reset
Figure 37. BLK1_EN_STAT (Address 0044h)
31 1 0
Reserved EN_STAT
R-0 R-1
LEGEND: R = Read, W = Write, - n = Value after reset
•
•
•
Figure 38. BLK8_EN (Address 0078h)
31 1 0
Reserved EN
R-0 R/W-1
LEGEND: R = Read, W = Write, - n = Value after reset
Figure 39. BLK8_EN_STAT (Address 007Ch)
31 1 0
Reserved EN_STAT
R-0 R-1
LEGEND: R = Read, W = Write, - n = Value after reset
Table 28. Block Enable and Block Enable Status Field Descriptions
Register(Bit) Field Valu Description
BLK n_EN(31–1) Reserved 0 These read-only bits return 0s when read.
BLK n_EN(0) EN Block n enable
BLK n_EN_STAT(31–1) Reserved 0 These read-only bits return 0s when read.
BLK n_EN_STAT(0) EN_STAT Block n enable status
e
0 Logical block n is to be reset with its clock off.
1 Logical block n is to be enabled with its clock running.
0 Logical block n is reset with its clock off.
1 Logical block n is enabled with its clock running.
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SRIO Functional Description
2.3.10.3 Software Shutdown Details
Power consumption is minimized for all logical blocks that are in shutdown. In addition to simply asserting
the appropriate reset signal to each logical block within the peripheral, clocks are gated off to the
corresponding logical block as well. Clocks are allowed to run for 32 clock cycles, which is necessary to
fully reset each logical block. When the appropriate logical block is fully reset, the clock input to that
subblock is gated off. When software asserts GBL_EN/BLKn_EN to release the logical block from reset,
the clocks are un-gated and the GBL_EN_STAT/BLKn_EN_STAT bit(s) indicate a value of 1b.
Note: The BLK_EN bits allow you to shut down and gate clocks to unused portions of the logic,
while other parts of the peripheral continue to operate. When shutting down an individual
block, if TXU and RXU queues are not torn down correctly, the DMA bus could hang. For
example, setting BLK3_EN = 0 (disabling the TXU) before a teardown of the queue could
cause any outstanding DMA request returned to the peripheral for the TXU to hang the
bus.
When using the GBL_EN to shutdown/reset the entire peripheral, it is important to first stop all
master-initiated commands on the DMA bus interface. For example, if the GBL_EN is asserted in the
middle of a DMA transfer from the peripheral, this could hang the bus. The procedure to follow is:
1. Stop all RapidIO source transactions, including LSU and TXU operations. The four LSU blocks should
indiciate a BSY status of 0b (offsets 0418h, 0438h, 0458h, 0478h). If an EDMA channel is used for
driving the LSU, it must be stopped to prevent new/additional transfers. This procedure is outside the
scope of this specification. Teardown of the TXU queues is accomplished by writing 0000FFFFh to
RIO_TX_QUEUE_TEAR_DOWN (offset 0700h). Hardware will then tear down the queues and clear
these bits automatically when the teardown is complete.
2. Stop all RapidIO message receive, RXU, operations. Teardown of the RXU queues is accomplished by
writing 0000FFFFh to RIO_RX_QUEUE_TEAR_DOWN (offset 0740h). Hardware will then tear down
the queues and clear these bits automatically when complete.
3. Once teardown is complete, clear the PEREN bit of the RIO_PCR (offset 0004h) to stop all new logical
layer transactions.
4. Wait 1 second to finish any current DMA transfer.
5. Deassert GBL_EN (offset 0030h).
2.3.11 Emulation
Expected behavior during emulation halt is controlled within the peripheral by the SOFT and FREE bits of
the peripheral control register (PCR). These bits are shown in Figure 40 and described in Table 29 .
Figure 40. Peripheral Control Register (PCR) - Address Offset 0004h
31 16
Reserved
R-0
15 3 2 1 0
Reserved PEREN SOFT FREE
R-0 R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
Table 29. Peripheral Control Register (PCR) Field Descriptions
Bit Field Value Description
31–3 Reserved 0 These read-only bits return 0s when read.
2 PEREN Peripheral enable. Controls the flow of data in the logical layer of the peripheral. As an initiator, it
74 Serial RapidIO (SRIO) SPRUE13A – September 2006
will prevent TX transaction generation; as a target, it will disable incoming requests. This should be
the last enable bit to toggle when bringing the device out of reset to begin normal operation.
0 Data flow control is disabled.
1 Data flow control is enabled.
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SRIO Functional Description
Table 29. Peripheral Control Register (PCR) Field Descriptions (continued)
Bit Field Value Description
1 SOFT Soft stop. This bit and the FREE bit determine how the SRIO peripheral behaves during emulation
0 FREE Free run
halts.
0 Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO
peripheral.)
1 Soft stop
0 The SOFT bit takes effect.
1 Free run. Peripheral ignores the emulation suspend signal and functions normally.
Free Run Mode: (default mode) Peripheral does not respond to an emulation suspend assertion. The
peripheral functions normally, irrespective of the CPU emulation state.
Soft Stop Mode: The peripheral gracefully halts operations. The peripheral halts operation at a point that
makes sense both to the internal DMA/data access operation and to the pin interface as described below,
after finishing packet reception or transmission in progress:
• DMA bus DMA master: DMA bus requests in progress are allowed to complete (DMA bus has no
means to throttle command in progress from the master). DMA bus requests that correspond to the
same network packet are allowed to complete. No new DMA bus requests will be generated on the
next new packet.
• Configuration bus MMR interface: All memory-mapped register (MMR) configuration bus requests
are serviced as normal.
• Events/interrupts: New events/interrupts are not generated to the CPU for newly arriving packets.
Current transactions are allowed to finish and may cause an interrupt upon completion.
• Slave pin interface: The pin interface functions as normal. If buffering is available in the peripheral,
the peripheral services externally generated requests as long as possible. When the internal buffers
are consumed, the peripheral will retry incoming network packets in the physical layer.
• Master pin interface: No new master requests are generated. Master requests in progress are
allowed to complete, including all packets located in the physical layer transmit buffers.
Hard Stop Mode: The peripheral halts immediately. This mode is not supported in the peripheral.
2.3.12 TX Buffers, Credit, and Packet Reordering
Packets to be transmitted by the SRIO peripheral travel to logical layer buffers. The packets are then
moved from the logical layer buffers to physical layer buffers. From the physical layer buffers, the packets
are transmitted through a port to a connected device.
2.3.12.1 Multiple Ports With 1x Operation
With multiple ports in 1x mode, logical layer buffers are grouped per port and contain all priorities. Each
group is 8 buffers deep. A counter is maintained for each port to track available buffer credit across the
UDI. The count is initialized to 8 credits per port. The count is decremented each time a packet is sent
across the UDI for a port. Each port buffer group has a buffer release signal which indicates the release of
a packet from the logical layer buffer to the port's physical buffer, thus indicating the freeing up of space in
the port's logical buffer.
Thresholds are used to govern outbound credit when requested by the protocol units (MAU, RXU, TXU,
and the LSUs). These thresholds are programmable in the peripheral settings control register
(PER_SET_CNTL at address offset 0020h).
The physical layer buffer tries to process all packets in the order they were sent across the UDI. However,
it is also governed by a re-ordering algorithm to decide which packets may be sent to the physical layer
buffer depending on credit availability there.
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SRIO Functional Description
The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device, in
which case a re-ordering algorithm is used. The algorithm searches backward through the buffer group for
the first packet with the highest priority. If there are no higher priority packets in the queue, the current
packet is sent again. As an example of the re-ordering algorithm, suppose a physical layer buffer group
contains packets with the following priorities:
0 0 1 2 3 3 1 0
where the leftmost 0 represents the packet that was the first in, or the head of the queue. If this packet is
retried, the next packet to be sent is the earliest packet with priority 3 (the lefthand 3). If that packet is sent
successfully, the physical layer attempts to send the original retried packet again; otherwise, the physical
layer repeats the re-ordering algorithm.
2.3.12.2 Single Port With 1x or 4x Operation
In the case when only one portis used, logical layer buffers are grouped per priority. Each priority is 8
buffers deep. A counter is maintained for each priority to track available buffer credit across the UDI. The
count is initialized to 8 credits per port. The count is decremented each time a packet is sent across the
UDI for a port. Each port buffer group has a buffer release signal which indicates the release of a packet
from the logical layer buffer to the port's physical buffer, thus indicating the freeing up of space in the
port's logical buffer.
A priority arbiter empties the logical layer buffer with the highest priority available first. For example, it
empties all available priority 3 buffers before priority 2, 1, or 0.
The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device, in
which case a re-ordering algorithm is used.The algorithm searches backward through the buffer group for
the first packet with the highest priority. If there are no higher priority packets in the queue, the current
packet is sent again. As an example of the re-ordering algorithm, suppose a physical layer buffer group
contains packets with the following priorities:
0 0 1 2 3 3 1 0
where the leftmost 0 represents the packet that was the first in, or head of the queue. If this packet is
retried, the next packet to be sent is the earliest packet with priority 3 (the lefthand 3). If that packet is sent
successfully, the physical layer attempts to send the original retried packet again; otherwise, the physical
layer repeats the re-ordering algorithm.
2.3.12.3 Unavailable Outbound Credit
At any time, if one of the credit counters reaches 0, no more buffer credit is available. The following
describes how the protocol units deal with this case.
MAU or RXU.In the case of the MAU or the RXU, all outbound packets are response packets. As a result,
the MAU or RXU is free to promote a packet’s priority level until priority 3 is reached. If priority 3 cannot
warrant a credit, the MAU or RXU keeps retrying on priority 3 until credit is available. The assumption is
that if all priority levels become backed up, the physical layer re-ordering mechanism will be implemented
to send out the highest priority packets first.
LSUs. For single-packet transfers, if the transfer is unsuccessful after 256 times of credit request, a
completion code of 111b is indicated in the LSU status register (LSUn_REG6). After reading this status,
software must determine whether to try again, increase the priority, or try a different control flow.
For transfers (with up to 4K-byte payloads) requiring multiple packets, if the transfer is unsuccessful after
256 times of credit request for the first packet, a completion code of 111b is indicated in LSUn_REG6.
After the first packet is successfully completed, subsequent packets are given more retry attempts. The
LSU makes up to 64K attempts to gain outbound credit for the subsequent packets. If the LSU is
unsuccessful after the 64K attempts, a completion code of 111b is indicated in LSUn_REG6.
TXU. The TXU cannot change state to handle inbound responses while it is requesting outbound credit.
To avoid deadlock situations, the TXU tries for outbound credit in the following manner.
For single-segment messages, if the transfer is unsuccessful after 256 times of credit request, the TXU
moves to the next queue in the round-robin loop of TX buffer descriptor queues. The TXU tries to send the
unsent message again the next time the round-robin scheduler returns to the given queue.
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For multi-segment messages, if the transfer is unsuccessful after 256 times of credit request for the first
segment, the TXU moves to the next queue in the round-robin loop. The TXU tries to send the unsent
message again the next time around the loop. After the first segment is granted outbound credit and is
sent to the physical layer for transmission, all subsequent segments are given 64K attempts to gain
outbound credit. If the TXU is unsuccessful after the 64K attempts, a completion code of 111b is written to
the buffer descriptor, and the message is cancelled with no attempt to resend.
2.3.13 Initialization Example
2.3.13.1 Enabling the SRIO Peripheral
When the device is powered on, the SRIO peripheral is in a disabled state. Before any SRIO specific
initialization can take place, the peripheral needs to be enabled; otherwise, its registers cannot be written,
and the reads will all return a value of zero.
/* Glb enable srio */
SRIO_REGS->GBL_EN = 0x00000001 ;
SRIO_REGS->BLK0_EN = 0x00000001 ; //MMR_EN
SRIO_REGS->BLK5_EN = 0x00000001 ; //PORT0_EN
SRIO_REGS->BLK1_EN = 0x00000001 ; //LSU_EN
SRIO_REGS->BLK2_EN = 0x00000001 ; //MAU_EN
SRIO_REGS->BLK3_EN = 0x00000001 ; //TXU_EN
SRIO_REGS->BLK4_EN = 0x00000001 ; //RXU_EN
SRIO_REGS->BLK6_EN = 0x00000001 ; //PORT1_EN
SRIO_REGS->BLK7_EN = 0x00000001 ; //PORT2_EN
SRIO_REGS->BLK8_EN = 0x00000001 ; //PORT3_EN
SRIO Functional Description
2.3.13.2 PLL, Ports, Device ID and Data Rate Initializations
To change from 1 lane to 4 lanes there are 2 registers that need to be programmed. See Table 30 .
Device SP_IP_MODE (offset 0x12004) PER_SET_CNTL (offset 0x0020) Port Mode
TMS320TCI6482 0x00 0x00 1x/4p
TMS320TCI6482 0x01 0x01 1x/1x
For example, Enable PLL, 333MHz, 1x/4p (srio4p1x_mode = 1), x20, 125MHz ref. clock, 2.5 Gbps, half
rate:
if (srio4p1x_mode){
rdata = SRIO_REGS->PER_SET_CNTL;
wdata = 0x0000014F; //4p1x
mask = 0x000001FF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata ; // enable PLL
}
else{
wdata = 0x0000004F; // enable PLL, 1p4x
rdata = SRIO_REGS->PER_SET_CNTL;
mask = 0x000001FF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata ; // enable PLL, 1p1x/4x
}
Table 30. Port Mode Register Settings
Bits 31-30 Bit 8
//INIT_MAC0
if (srio4p1x_mode){
SRIO_REGS->SP_IP_MODE = 0x4400003F; // Jadis mltc/rst/pw enable, clear
}
else{
SRIO_REGS->SP_IP_MODE = 0x0400003F; // Jadis mltc/rst/pw enable, clear
}
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SRIO Functional Description
2.3.13.3 Peripheral Initializations
SRIO_REGS->SERDES_CFG0_CNTL = 0x00000013;
SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFGRX0_CNTL = 0x00081121 ; // enable rx, half rate
SRIO_REGS->SERDES_CFGRX1_CNTL = 0x00081121 ; // enable rx, half rate
SRIO_REGS->SERDES_CFGRX2_CNTL = 0x00081121 ; // enable rx, half rate
SRIO_REGS->SERDES_CFGRX3_CNTL = 0x00081121 ; // enable rx, half rate
SRIO_REGS->SERDES_CFGTX0_CNTL = 0x00010821 ; // enable tx, half rate
SRIO_REGS->SERDES_CFGTX1_CNTL = 0x00010821 ; // enable tx, half rate
SRIO_REGS->SERDES_CFGTX2_CNTL = 0x00010821 ; // enable tx, half rate
SRIO_REGS->SERDES_CFGTX3_CNTL = 0x00010821 ; // enable tx, half rate
Set Device ID Registers
rdata = SRIO_REGS->DEVICEID_REG1;
wdata = 0x00ABBEEF;
mask = 0x00FFFFFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->DEVICEID_REG1 = mdata ; // id-16b=BEEF, id-08b=AB
rdata = SRIO_REGS->DEVICEID_REG2;
wdata = 0x00ABBEEF;
mask = 0x00FFFFFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->DEVICEID_REG2 = mdata ; // id-16b=BEEF, id-08b=AB
rdata = SRIO_REGS->PER_SET_CNTL;
data = 0x00000000;
mask = 0x01000000;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata; // bootcmpl=0
SRIO_REGS->DEV_ID = 0xBEEF0030 ; // id=BEEF, ti=0x0030
SRIO_REGS->DEV_INFO = 0x00000000 ; // 0
SRIO_REGS->ASBLY_ID = 0x00000030 ; // ti=0x0030
SRIO_REGS->ASBLY_INFO = 0x00000000; // 0x0000, next ext=0x0100
SRIO_REGS->PE_FEAT = 0x20000019 ; // proc, bu ext, 16-bit ID, 34-bit addr
SRIO_REGS->SRC_OP = 0x0000FDF4; // all
SRIO_REGS->DEST_OP = 0x0000FC04; // all except atomic
SRIO_REGS->PE_LL_CTL = 0x00000001; // 34-bit addr
SRIO_REGS->LCL_CFG_HBAR = 0x00000000 ; // 0
SRIO_REGS->LCL_CFG_BAR = 0x00000000; // 0
SRIO_REGS->BASE_ID = 0x00ABBEEF; // 16b-id=BEEF, 08b-id=AB
SRIO_REGS->HOST_BASE_ID_LOCK = 0x0000BEEF; // id=BEEF, lock
SRIO_REGS->COMP_TAG = 0x00000000; // not touched
SRIO_REGS->SP_IP_DISCOVERY_TIMER = 0x90000000;// 0, short cycles for sim
SRIO_REGS->IP_PRESCAL = 0x00000021; // srv_clk prescalar=0x21 (333MHz)
SRIO_REGS->SP0_SILENCE_TIMER = 0x20000000;
SRIO_REGS->SP1_SILENCE_TIMER = 0x20000000;
SRIO_REGS->SP2_SILENCE_TIMER = 0x20000000;
SRIO_REGS->SP3_SILENCE_TIMER = 0x20000000;
rdata = SRIO_REGS->PER_SET_CNTL;
wdata = 0x01000000;
mask = 0x01000000;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata; // bootcmpl=1
RIO_REGS->SP_LT_CTL = 0xFFFFFF00; // long
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SRIO_REGS->SP_RT_CTL = 0xFFFFFF00; // long
SRIO_REGS->SP_GEN_CTL = 0x40000000; // agent, master, undiscovered
SRIO_REGS->SP0_CTL = 0x00600000; // enable i/o
SRIO_REGS->SP1_CTL = 0x00600000; // enable i/o
SRIO_REGS->SP2_CTL = 0x00600000; // enable i/o
SRIO_REGS->SP3_CTL = 0x00600000; // enable i/o
SRIO_REGS->ERR_DET = 0x00000000 ; // clear
SRIO_REGS->ERR_EN = 0x00000000 ; // disable
SRIO_REGS->H_ADDR_CAPT = 0x00000000 ; // clear
SRIO_REGS->ADDR_CAPT = 0x00000000 ; // clear
SRIO_REGS->ID_CAPT = 0x00000000 ; // clear
SRIO_REGS->CTRL_CAPT = 0x00000000 ; // clear
SRIO_REGS->SP_IP_PW_IN_CAPT0 = 0x00000000 ; // clear
SRIO_REGS->SP_IP_PW_IN_CAPT1 = 0x00000000 ; // clear
SRIO_REGS->SP_IP_PW_IN_CAPT2 = 0x00000000 ; // clear
SRIO_REGS->SP_IP_PW_IN_CAPT3 = 0x00000000 ; // clear
//INIT_WAIT wait for lane initialization
Read register to check portx(1-4) OK bit
// polling SRIO_MAC's port_ok bit
rdata = SRIO_REGS->P0_ERR_STAT ;
while ((rdata & 0x00000002) != 0x00000002)
{
rdata = SRIO_REGS->P0_ERR_STAT ;
}
if (srio4p1x_mode){
rdata = SRIO_REGS->P1_ERR_STAT;
while ((rdata & 0x00000002) != 0x00000002)
{
rdata = SRIO_REGS->P1_ERR_STAT;
}
rdata = SRIO_REGS->P2_ERR_STAT;
while ((rdata & 0x00000002) != 0x00000002)
{
rdata = SRIO_REGS->P2_ERR_STAT;
}
rdata = SRIO_REGS->P3_ERR_STAT;
while ((rdata & 0x00000002) != 0x00000002)
{
rdata = SRIO_REGS->P3_ERR_STAT;
}
}
Assert the PEREN bit to enable logical layer data flow
SRIO_REGS->PCR = 0x00000004; // peren
SRIO Functional Description
2.3.14 Bootload Capability
2.3.14.1 Configuration and Operation
Figure 41 illustrates the system components involved in bootload operation. It is assumed that an external
device will initiate the bootload data transfer and master the DMA interface. Upon reset, the following
sequence of events must occur:
1. DSP is placed in SRIO boot mode by HW mode pins.
2. Host takes DSP out of reset ( POR or RST). The peripheral’s state machines and registers are reset.
3. Internal boot-strap ROM configures device registers, including SERDES, and DMA. DSP executes
internal ROM code to initialize SRIO.
• Choice of 4 pin selectable configurations
• Optionally, I2C boot can be used to configure SRIO
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Boot
Program
Host
Controller
Optional
I2C
EEPROM
DSP
ROM
1xRapidIO
SRIO Functional Description
4. DSP executes idle instruction.
5. RapidIO ports send Idle control symbols to train PHYs.
6. Host enabled to explore system with RapidIO Maintenance packets.
7. Host identifies, enumerates and initializes the RapidIO device.
8. Host controller configures DSP peripherals through maintenance packets.
• SRIO Device IDs are set for DSPs (either by pin strapping or by host manipulation)
9. Boot Code sent from host controller to DSP L2 memory base address via NWRITE.
10. DSP CPU is awakened by an interrupt such as a RapidIO DOORBELL packet.
11. Boot Code is executed and normal operation follows.
2.3.14.2 Bootload Data Movement
The system host is responsible for writing the bootload data into the DSP’s L2 memory. As such, bootload
is only supported using the direct I/O model, and not the message passing model. Bootload data must be
sent in packets with explicit L2 memory addresses indicating proper destination within the DSP. As part of
the peripheral’s configuration, it should be set up to transfer the desired bootload program to the DSP's
memory through normal DMA bus commands.
Figure 41. Bootload Operation
2.3.14.3 Device Wakeup
Upon completion of the bootload data transfer, the system host issues a DOORBELL interrupt to the DSP.
The RapidIO peripheral processes this interrupt in a manner similar to that described in Section 4 ,
monitoring the DMA bus write-with-response commands to ensure that the data has been completely
transferred through the DMA. This interrupt wakes up the CPUs by pulling them out of their reset state.
The 16-bit data field of the DOORBELL packet should be configured to interrupt Core 0 by setting a
corresponding ICSR bit as described in Figure 46 .
2.3.15 RX Multicast Support, Daisy Chain Operation and Packet Forwarding
2.3.15.1 RX Multicast Support
Multicast transactions are I/O packets that specify a destination address within the header. This address is
used directly for the internal DSP transfers and is not modified in any way. For this reason, multi-cast
support is limited to groups containing devices with the same memory map, or other devices that can
perform address translation. It is the responsibility of the system designer to pre-determine valid multi-cast
address ranges.
When a packet is received, the packet’s tt field and DestID are checked against the main DeviceID (offset
0x0080) and the MulticastID (see Table 31 ). If there is no match, the packet is destroyed and not
forwarded to the logical layer. If there is a match, it is forwarded to the logical layer. Since multicast
operations are defined to be operations that do not require responses, they are limited to NWRITE and
SWRITE operations and forwarded to the MAU.
As an endpoint device, the peripheral accepts packets based on the destination ID. Two options exist for
packet acceptance and are mode selectable. The first option is to only accept packets whose DestIDs
match the local deviceID in 0x0080. This provides a level of security. The second option is is system
multicast operation.
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Device Register Offset Register Offset Endpoint Device Requirements
TMS320TCI6482 0080h 0084h Accepts discrete multiple DestIDs from
2.3.15.2 Daisy Chain Operation and Packet Forwarding
Some applications may require daisy chaining of devices together versus using a switch fabric. Typically,
these applications are low cost implementations. Daisy chains have variable system latency depending on
device position within the chain. Daisy chain implementations also have reduced bandwidth capabilities,
since the link bandwidth doesn’t change, the bandwidth allocated to each device in the chain is limited
(sum of devices’ individual bandwidth needs can’t exceed link bandwidth).
To support daisy chain or ring topologies, the peripheral features a hardware packet forwarding function.
This feature eliminates the need for software to be involved in routing a packet to the next device in the
chain. The basic idea behind the hardware packet forwarding logic is to provide an input port to output
port path such that the packets never leave the peripheral (no DMA transfer). A simple check of an
in-coming packet’s DestID versus the device’s DeviceID and MulticastID is done to determine if the packet
should be forwarded. If the packet’s DestID matches DeviceID, the packet is accepted and processed by
the device. If the packet’s DestID matches the MulticastID, the packet is accepted by the device and
forwarded based on the rules outlined in Section 2.3.15.1 . If the packet’s DestID doesn’t match either, the
packet is simply destroyed or forwarded, depending on the whether the hardware packet forwarding is
enabled.
Additionally, it is beneficial to be able to only forward a packet if the destination ID is one of the devices in
the chain/ring. Otherwise, a rogue packet may be forwarded endlessly using up valuable bandwidth. The
hardware packet forwarding uses a 4 entry mapping table shown in Table 32 and Table 33 . These
mapping entries allow programmable selection of output port based on the in-coming packets DestID
range. Since the packet forwarding is done at the logical layer and not the physical layer, CRCs will be
regenerated for each forwarded packet.
SRIO Functional Description
Table 31. Multicast DeviceID Operation
Local DeviceID Multicast DeviceID
incoming packet
2.3.15.3 Enabling Multicast and Packet Forwarding
In order to enable multicast support, bit 5 of the SP_IP_MODE (offset 0x12004) must be set to 1.The
multicast mode is disabled by simply writing the same deviceID into the registers listed in Table 31 .
Hardware packet forwarding can be disabled by assigning all the table entry Upper and Lower deviceID
boundaries equal to the local DeviceID value.
Figure 42. Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTL n) Offsets 0x0090,
0x0098, 0x00A0, 0x00A8
31 16 15 0
16BIT_DEVID_UP_BOUND 16BIT_DEVID_LOW_BOUND
R/W-FFFFh R/W-FFFFh
LEGEND: R/W = Read/Write; - n = Value after reset
Table 32. Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTL n) Field Descriptions
Bit Field Value Description
31–16 16BIT_DEVID_UP_BOUND 0000h–FFFFh Upper 16-bit DeviceID boundary. DestID above this range
15–0 16BIT_DEVID_LOW_BOUND 0000h–FFFFh Lower 16-bit DeviceID boundary. DestID lower than this
cannot use the table entry.
number cannot use the table entry.
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SRIO Functional Description
Figure 43. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n) Offsets 0x0094,
0x009C, 0x00A4, 0x00AC
31 18 17 16
Reserved
R-0 R/W-3
15 8
8BIT_DEVID_UP_BOUND
R/W-FFh
7 0
8BIT_DEVID_LOW_BOUND
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
OUT_BOUND_
PORT
Table 33. Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTL n) Field Descriptions
Bit Field Value Description
31–18 Reserved 0 Reserved
17–16 OUT_BOUND_PORT 0–3 Output port number for packets whose DestID falls within the 8-bit or
15–8 8BIT_DEVID_UP_BOUND 00h–FFh Upper 8-bit DeviceID boundary. DestID above this range cannot use
7–0 8BIT_DEVID_LOW_BOUND 00h–FFh Lower 8-bit DeviceID boundary. DestID lower than this number cannot
16-bit range for this table entry.
the table entry.
use the table entry.
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Logical/Transport Error Handling and Logging
3 Logical/Transport Error Handling and Logging
Error management registers allow detection and logging of logical/transport layer errors. The detectable
errors are captured in the logical layer error detect CSR (see Figure 44 ). Table 34 names the functional
block(s) involved for each detectable error condition, and includes brief descriptions of the errors captured.
Figure 44. Logical/Transport Layer Error Detect CSR (ERR_DET)
31 30 29 28 27 26 25 24
IO_ERR_ MSG_ERR_ ERR_MSG_ ILL_TRANS_ MSG_REQ_ PKT_RSPNS_
RSPNS RSPNS FORMAT DECODE TIMEOUT TIMEOUT
R/W-0 R/W-0 R-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0
23 22 21
UNSOLICITED_ UNSUPPORTED_
RSPNS TRANS
R/W-0 R/W-0 R-0
7 6 5 0
RX_CPPI_ RX_IO_DMA_
SECURITY ACCESS
R/W-0 R/W-0 R-0
LEGEND: R = Read; W = Write; - n = Value after reset
Reserved Reserved
Reserved
Reserved
R-0
Reserved
8
Table 34. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions
Bit Field Value Description
31 IO_ERR_RSPNS IO error response (endpoint device only)
0 An LSU did not receive an ERROR response to an IO logical layer request.
1 An LSU received an ERROR response to an IO logical layer request. To clear
30 MSG_ERR_RSPNS Message error response (endpoint device only)
0 The TXU did not receive an ERROR response to a message logical layer
1 The TXU received an ERROR response to a message logical layer request. To
29 Reserved 0 This read-only bit returns 0 when read.
28 ERR_MSG_FORMAT Error in message format (endpoint device only)
0 The RXU did not receive a message data payload with an invalid size or
1 The RXU received a message data payload with an invalid size or segment. To
27 ILL_TRANS_DECODE Illegal transaction decode (switch or endpoint device)
0 The LSU/TXU did not receive illegal fields in the response packet for an
1 The LSU/TXU received illegal fields in the response packet for an IO/message
0 The MAU/RXU did not receive illegal fields in the request packet for an
1 The MAU/RXU received illegal fields in the request packet for an IO/message
26 Reserved 0 This read-only bit returns 0 when read.
this bit, write 0 to it.
request.
clear this bit, write 0 to it.
segment.
clear this bit, write 0 to it.
For an LSU or the TXU:
IO/message transaction.
transaction. To clear this bit, write 0 to it.
For the MAU or the RXU:
IO/message transaction.
transaction. To clear this bit, write 0 to it.
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Logical/Transport Error Handling and Logging
Table 34. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued)
Bit Field Value Description
25 MSG_REQ_TIMEOUT Message request timeout (endpoint device only)
0 A timeout has not been detected by RXU.
1 A timeout has been detected by the RXU. A required message request has not
24 PKT_RSPNS_TIMEOUT Packet response timeout (endpoint device only)
0 A timeout has not been detected by an LSU or the TXU.
1 A timeout has been detected by an LSU or the TXU. A required response has
23 UNSOLICITED_RSPNS Unsolicited response (switch or endpoint device)
0 An unsolicited response packet has not been received by an LSU or the TXU.
1 An unsolicited response packet has been received by an LSU or the TXU. To
22 UNSUPPORTED_TRANS Unsupported transaction (switch or endpoint device)
0 The MAU has not received an unsupported transaction.
1 The MAU has received an unsupported transaction. That is, the MAU received
21–8 Reserved 0 These read-only bits return 0 when read.
7 RX_CPPI_SECURITY RX CPPI security error
0 The RXU has not detected an access block.
1 The RXU has detected an access block. That is, access to one of the RX
6 RX_IO_DMA_ACCESS RX IO DMA access error
0 A DMA access to the MAU has not been blocked.
1 A DMA access to the MAU was blocked. To clear this bit, write 0 to it.
5–0 Reserved 0 These read-only bits return 0 when read.
been received by the RXU within the specified time-out interval. To clear this
bit, write 0 to it.
not been received by the LSU/TXU within the specified timeout interval. To
clear this bit, write 0 to it.
clear this bit, write 0 to it.
a transaction that is not supported in the destination operations CAR. To clear
this bit, write 0 to it.
queues was blocked. To clear this bit, write 0 to it.
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4 Interrupt Conditions
acklD rsv prio tt 1010 destID sourcelD Reserved srcTID
Reserved DoorbellReg# rsv
Doorbellbit
CRC
PHYLOGTRALOGTRAPHY
5 3 2 2 4 8 8 8 8
9 2
1
4
16
1632
16
4
2
10
info(msb)
8
info(lsb)
8
4.1 CPU Interrupts
4.2 General Description
Interrupt Conditions
This section defines the CPU interrupt capabilities and requirements of the peripheral.
The following interrupts are supported by the RIO peripheral.
• Error status: Event indicating that a run-time error was reached. The CPU should reset/resynchronize
the peripheral.
• Critical error: Event indicating that a critical error state was reached. The CPU should reset the system.
• CPU servicing: Event indicating that the CPU should service the peripheral.
The RIO peripheral is capable of generating various types of CPU interrupts. The interrupts serve two
general purposes: error indication and servicing requests.
Since RapidIO is a packet oriented interface, the peripheral must recognize and respond to inbound
signals from the serial interface. There are no GPIO or external pins used to indicate an interrupt request.
Thus, the interrupt requests are signaled either by an external RapidIO device through the packet
protocols discussed as follows, or are generated internally by the RIO peripheral.
CPU servicing interrupts lag behind the corresponding data, which was generally transferred from an
external processing element into local L2 memory. This transfer can use a messaging or direct I/O
protocol. When the single or multi-packet data transfer is complete, the external PE, or the peripheral
itself, must notify the local processor that the data is available for processing. To avoid erroneous data
being processed by the local CPU, the data transfer must complete through the DMA before the CPU
interrupt is serviced. This condition could occur since the data and interrupt queues are independent of
each other, and DMA transfers can stall. To avoid this condition, all data transfers from the peripheral
through the DMA use write-with-response DMA bus commands, allowing the peripheral to always be
aware that outstanding transfers have completed. Interrupts are generated only after all DMA bus
responses are received. Since all RapidIO packets are handled sequentially, and submitted on the same
DMA priority queue, the peripheral must keep track of the number of DMA requests submitted and the
number of responses received. Thus, a simple counter within the peripheral ensures that data packets
have arrived in memory before submitting an interrupt.
The sending device initiates the interrupt by using the RapidIO defined DOORBELL message. The
DOORBELL packet format is shown in Figure 45 . The DOORBELL functionality is user-defined. This
packet type is commonly used to initiate CPU interrupts. A DOORBELL packet is not associated with a
particular data packet that was previously transferred, so the INFO field of the packet must be configured
to reflect the DOORBELL bit to be serviced for the correct TID info to be processed.
Figure 45. RapidIO DOORBELL Packet for Interrupt Use
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Interrupt Conditions
The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There
are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers
(see Table 23 for assignment of the 16 bits of DOORBELL_INFO field). Each bit can be assigned to any
core as described by the Interrupt Condition Routing Registers. Additionally, each status bit is
user-defined for the application. For instance, it may be desirable to support multiple priorities with multiple
TID circular buffers per core if control data uses a high priority (for example, priority = 2), while data
packets are sent on priority 0 or 1. This allows the control packets to have preference in the switch fabric
and arrive as quickly as possible. Since it may be required to interrupt the CPU for both data and control
packet processing separately, separate circular buffers are used, and DOORBELL packets must
distinguish between them for interrupt servicing. If any reserved bit in the DOORBELL info field is set, an
error response is sent.
The interrupt approach to the messaging protocol is somewhat different. Since the source device is
unaware of the data's physical location in the destination device, and since each messaging packet
contains size and segment information, the peripheral can automatically generate the interrupt after it has
successfully received all packet segments comprising the complete message. This DMA interface uses
the Communications Port Programming Interface (CPPI). This interface is a link-listed approach versus a
circular buffer approach. Data buffer descriptors which contain information such as start of Packet (SOP),
end of packet (EOP), end of queue (EOQ), and packet length are built from the RapidIO header fields.
The data buffer descriptors also contain the address of the corresponding data buffer as assigned by the
receive device. The data buffer descriptors are then link-listed together as multiple packets are received.
Interrupts are generated by the peripheral after all segments of the messages are received and
successfully transferred through the DMA bus with the write-with-response commands. Interrupt pacing is
also implemented at the peripheral level to manage the interrupt rate, as described in Section 4.7 .
Error handling on the RapidIO link is handled by the peripheral, and as such, does not require the
intervention of software for recovery. This includes CRC errors due to bit rate errors that may cause
erroneous or invalid operations. The exception to this statement is the use of the RapidIO error
management extended features. This specification monitors and tabulates the errors that occur on a per
port basis. If the number of errors exceeds a pre-determined configurable amount, the peripheral should
interrupt the CPU software and notify that an error condition exits. Alternatively, if a system host is used,
the peripheral may issue a port-write operation to notify the system software of a bad link.
A system reset, or Critical Error interrupt, can be initialized through the RapidIO link. This procedure
allows an external device to reset the local device, causing all state machine and configuration registers to
reset to their original values. This is executed with the Reset-Device command described in Part VI,
Section 3.4.5 of the RapidIO Physical Layer 1x/4x LP-Serial Specification. Four sequential Reset-Device
control symbols are needed to avoid inadvertent resetting of a device.
4.3 Interrupt Condition Status and Clear Registers
Interrupt condition status and clear registers configure which CPU interrupts are to be generated and how,
based on the peripheral activity. All peripheral conditions that result in a CPU interrupt are grouped so that
the interrupt can be accessed in the minimum number of register reads possible.
For each of the three types of interrupts (CPU servicing, error status, and critical error), there are two sets
of registers:
• Interrupt Condition Status Register (ICSR): Status register that reflects the state of each condition that
can trigger the interrupt. The general description of each interrupt condition status bit (ICSx) is given in
Table 35 .
• Interrupt Condition Clear Register (ICCR): Command register that allows each condition to be cleared.
This is typically required prior to enabling a condition, so that spurious interrupts are not generated.
Table 35 shows the general description of an interrupt condition clear bit (ICCx).
These registers are accessible in the memory map of the CPU. The CPU controls the clear register. The
status register is readable by the CPU to determine the peripheral condition.
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Interrupt Conditions
Table 35. Interrupt Condition Status and Clear Bits
Field Access Reset Value Value Function
ICSx R 0 0 Condition not present
1 Condition present
ICCx W 0 0 No effect
1 Clear the condition status bit (ICSx)
4.3.1 Doorbell Interrupt Condition Status and Clear Registers
The interrupt condition status registers (ICSRs) and the interrupt condition clear registers (ICCRs) for the
four doorbells are shown in Figure 46 through Figure 49 . These registers are used when the SRIO
peripheral receives doorbell packets. The 16 ICS bits of each interrupt condition status register (ICSR)
indicate the incoming doorbell information packet. For example, the bits ICS15, ICS8, and ICS0 of
DOORBELL0_ICSR correspond to Doorbell 0 information bits 15, 8, and 0. The 16 ICC bits of each
interrupt condition clear register (ICCR) are used to clear the corresponding bits in the ICSR. For example,
the ICC7 bit of DOORBELL2_ICCR is used to clear the ICS7 bit of DOORBELL2_ICSR.
Figure 46. Doorbell 0 Interrupt Condition Status and Clear Registers
Doorbell 0 Interrupt Condition Status Register (DOORBELL0_ICSR) (Address Offset 0200h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Doorbell 0 Interrupt Condition Clear Register (DOORBELL0_ICCR) (Address Offset 0208h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
Figure 47. Doorbell 1 Interrupt Condition Status and Clear Registers
Doorbell 1 Interrupt Condition Status Register (DOORBELL1_ICSR) (Address Offset 0210h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Doorbell 1 Interrupt Condition Clear Register (DOORBELL1_ICCR) (Address Offset 0218h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
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Interrupt Conditions
Figure 48. Doorbell 2 Interrupt Condition Status and Clear Registers
Doorbell 2 Interrupt Condition Status Register (DOORBELL2_ICSR) (Address Offset 0220h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Doorbell 2 Interrupt Condition Clear Register (DOORBELL2_ICCR) (Address Offset 0228h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
Figure 49. Doorbell 3 Interrupt Condition Status and Clear Registers
Doorbell 3 Interrupt Condition Status Register (DOORBELL3_ICSR) (Address Offset 0230h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Doorbell 3 Interrupt Condition Clear Register (DOORBELL3_ICCR) (Address Offset 0238h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
4.3.2 CPPI Interrupt Condition Status and Clear Registers
The ICSRs and the ICCRs for the RXU and the TXU are shown in Figure 50 and Figure 51 . These
interrupt condition registers are used when the SRIO peripheral receives and transmits data message
packets. Each ICS bit corresponds to the interrupt for one of the buffer descriptor queues. For example,
the bits ICS15, ICS8, and ICS0 of RX_CPPI_ICSR correspond to RX buffer descriptor queues 15, 8, and
0. Similarly, the bits ICS15, ICS8, and ICS0 of TX_CPPI_ICSR support TX buffer descriptor queues 15, 8,
and 0. The 16 ICC bits of each interrupt condition clear register (ICCR) are used to clear the
corresponding bits in the ICSR.
For reception, the clearing of any ICSR bit depends on the CPU writing the value of the last buffer
descriptor processed to the completion pointer (CP) register for the queue (QUEUE n_RXDMA_CP). Port
hardware clears the ICSR bit only if the CP value written by the CPU equals the port written value in the
CP register.
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For transmission, the clearing of any ICSR bit is dependent on the CPU writing to the CP register for the
queue (QUEUE n_TXDMA_CP). The CPU acknowledges the interrupt after reclaiming all available buffer
descriptors by writing the CP value. This value is compared against the port written value in the CP
register. If the values are equal, the interrupt is deasserted.
Figure 50. RX CPPI Interrupt Condition Status and Clear Registers
RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) (Address Offset 0240h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) (Address Offset 0248h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
Figure 51. TX CPPI Interrupt Condition Status and Clear Registers
TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) (Address Offset 0250h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) (Address Offset 0258h)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
4.3.3 LSU Interrupt Condition Status and Clear Registers
The ICSR and the ICCR for the LSUs are shown in Figure 52 . These interrupt condition registers are used
when the SRIO peripheral transmits direct I/O packets. As described in Table 36 , each of the status and
clear bits corresponds to a particular type of transaction interrupt condition for a particular LSU. The ICS
bits of LSU_ICSR indicate the occurrence of the conditions. The ICC bits of LSU_ICCR are used to clear
the corresponding ICS bits.
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Figure 52. LSU Interrupt Condition Status and Clear Registers
LSU Interrupt Condition Status Register (LSU_ICSR) (Address Offset 0260h)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICS31 ICS30 ICS29 ICS28 ICS27 ICS26 ICS25 ICS24 ICS23 ICS22 ICS21 ICS20 ICS19 ICS18 ICS17 ICS16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LSU Interrupt Condition Clear Register (LSU_ICCR) (Address Offset 0268h)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICC31 ICC30 ICC29 ICC28 ICC27 ICC26 ICC25 ICC24 ICC23 ICC22 ICC21 ICC20 ICC19 ICC18 ICC17 ICC16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
Table 36. Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR
Bit Associated LSU Interrupt Condition
31 LSU4 Packet not sent due to unavailable outbound credit at given priority
30 LSU4 Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in
29 LSU4 Transaction was not sent due to DMA data transfer error
28 LSU4 Transaction timeout occurred
27 LSU4 Transaction was not sent due to unsupported transaction type or invalid field encoding
26 LSU4 Transaction was not sent due to Xoff condition
25 LSU4 Non-posted transaction received ERROR response, or error in response payload
24 LSU4 Transaction complete, No errors (posted/non-posted)
23 LSU3 Packet not sent due to unavailable outbound credit at given priority
22 LSU3 Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in
21 LSU3 Transaction was not sent due to DMA data transfer error
20 LSU3 Transaction timeout occurred
19 LSU3 Transaction was not sent due to unsupported transaction type or invalid field encoding
18 LSU3 Transaction was not sent due to Xoff condition
17 LSU3 Non-posted transaction received ERROR response, or error in response payload
16 LSU3 Transaction complete, No errors (posted/non-posted)
15 LSU2 Packet not sent due to unavailable outbound credit at given priority
14 LSU2 Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in
13 LSU2 Transaction was not sent due to DMA data transfer error
12 LSU2 Transaction timeout occurred
11 LSU2 Transaction was not sent due to unsupported transaction type or invalid field encoding
10 LSU2 Transaction was not sent due to Xoff condition
9 LSU2 Non-posted transaction received ERROR response, or error in response payload
8 LSU2 Transaction complete, No errors (posted/non-posted)
7 LSU1 Packet not sent due to unavailable outbound credit at given priority
use)
(1)
use)
(1)
use)
(1)
(1)
Enable for this interrupt is ultimately controlled by the Interrupt Req register bit of LSU n_REG4. This allows enabling/disabling
on a per request basis. For optimum LSU performance, interrupt pacing should not be used on the LSU interrupts. Section 4.7
describes interrupt pacing.
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Table 36. Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR (continued)
Bit Associated LSU Interrupt Condition
6 LSU1 Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in
5 LSU1 Transaction was not sent due to DMA data transfer error
4 LSU1 Transaction timeout occurred
3 LSU1 Transaction was not sent due to unsupported transaction type or invalid field encoding
2 LSU1 Transaction was not sent due to Xoff condition
1 LSU1 Non-posted transaction received ERROR response, or error in response payload
0 LSU1 Transaction complete, No errors (posted/non-posted)
use)
(1)
4.3.4 Error, Reset, and Special Event Interrupt Condition Status and Clear Registers
The ICSR and the ICCR for the SRIO ports are shown in Figure 53 . As described in Table 37 , each of the
nonreserved status and clear bits corresponds to a particular interrupt condition in one or more of the
SRIO ports. The ICS bits of ERR_RST_EVNT_ICSR indicate the occurrence of the conditions. The ICC
bits of ERR_RST_EVNT_ICCR are used to clear the corresponding ICS bits.
Figure 53. Error, Reset, and Special Event Interrupt Condition Status and Clear Registers
Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) (Address Offset 0270h)
31 17 16
Reserved ICS16
R-0 R-0
15 12 11 10 9 8 7 3 2 1 0
Reserved ICS11 ICS10 ICS9 ICS8 Reserved ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) (Address Offset 0278h)
31 17 16
Reserved ICC16
R-0 W-0
15 12 11 10 9 8 7 3 2 1 0
Reserved ICC11 ICC10 ICC9 ICC8 Reserved ICC2 ICC1 ICC0
R-0 W-0 W-0 W-0 W-0 R-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
Table 37. Interrupt Conditions Shown in ERR_RST_EVNT_ICSR and Cleared
With ERR_RST_EVNT_ICCR
Bit Interrupt Condition
31–17 Reserved
16 Device reset interrupt from any port
15–12 Reserved
11 Port 3 error (TMS320TCI6482 Only)
10 Port 2 error (TMS320TCI6482 Only)
9 Port 1 error
8 Port 0 error
7–3 Reserved
2 Logical layer error management event capture
1 Port-write-in request received on any port
0 Multi-cast event control symbol interrupt received on any port
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The interrupt status bits found in the ERR_RST_EVNT (0x0270) can be cleared by writing to the ICCR
register (0x0278) in the same manner as other interrupts. However, in order for new event detection and
interrupt generation to occur for these special interrupts, additional register bits must be cleared. The
following table notes the additional interrupt source register bits that need to be cleared and the
appropriated sequence. These are all the bits that can cause the ERR_RST_EVNT status bits to be set
Table 38. Interrupt Clearing Sequence for Special Event Interrupts
Interrupt Function 1stStep 2
Multicast Event Control Symbol Write 1 to clear: Write 1 to clear:
received on any port
Port Write In Request received Write 1 to clear: Write 1 to clear:
on any port
Port 0 Error Write 1 to clear: Write 1 to clear any of the Write 1 to clear:
Port 1 Error Write 1 to clear: Write 1 to clear any of the Write 1 to clear:
Port 2 Error Write 1 to clear: Write 1 to clear any of the Write 1 to clear:
(TMS320TCI6482 Only) following possible bits:
Offset 0x0278 Offset 0x12004
ERR_RST_EVNT_ICCR[0] SP_IP_MODE[4]
Offset 0x0278 Offset 0x12004
ERR_RST_EVNT_ICCR[1] SP_IP_MODE[0]
Offset 0x0278 Offset 0x2040 Offset 0x14004
ERR_RST_EVNT_ICCR[8] SP0_ERR_STAT[2] – Fatal SP0_CTL_INDEP[6]
Offset 0x0278 Offset 0x2080 Offset 0x14104
ERR_RST_EVNT_ICCR[9] SP1_ERR_STAT[2] – Fatal SP1_CTL_INDEP[6]
Offset 0x0278 Offset 0x20C0 Offset 0x14204
ERR_RST_EVNT_ICCR[10] SP2_ERR_STAT[2] – Fatal SP2_CTL_INDEP[6]
nd
Step 3rdStep
following possible bits:
error
SP0_ERR_STAT[25] – Failed
Threshold
SP0_ERR_STAT[24] –
Degraded Threshold
Offset 0x14004
SP0_CTL_INDEP[20] – Illegal
Transaction
SP0_CTL_INDEP[16] – Max
Retry Error
following possible bits:
error
SP1_ERR_STAT[25] – Failed
Threshold
SP1_ERR_STAT[24] –
Degraded Threshold
Offset 0x14104
SP1_CTL_INDEP[20] – Illegal
Transaction
SP1_CTL_INDEP[16] – Max
Retry Error
error
SP2_ERR_STAT[25] – Failed
Threshold
SP2_ERR_STAT[24] –
Degraded Threshold
Offset 0x14204
SP2_CTL_INDEP[20] – Illegal
Transaction
SP2_CTL_INDEP[16] – Max
Retry Error
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Table 38. Interrupt Clearing Sequence for Special Event Interrupts (continued)
Interrupt Function 1stStep 2
Port 3 Error Write 1 to clear: Write 1 to clear any of the Write 1 to clear:
(TMS320TCI6482 Only) following possible bits:
Device Reset Write 1 to clear: Write 1 to clear:
4.4 Interrupt Condition Routing Registers
The interrupt conditions are programmable to select the interrupt output that will be driven. Using the
interrupt condition routing registers (ICRRs), software can independently route each interrupt request to
any of the interrupt destinations supported by the device. For example, a quad core device may support
four CPU servicing interrupt destinations, one per core (INTDST0 for Core0, INTDST1 for Core1,
INTDST2 for Core2, and INTDST3 for Core3). In addition, INTDST4 may be globally routed to all cores
and provide notification of a change in the one ICSR, while INTDST5 may be globally routed to all cores
and provide notification of a change in a different ICSR. The routing defaults for an interrupt condition
routing bit (ICRx) are given in Table 39 .
nd
Step 3rdStep
Offset 0x0278 Offset 0x2100 Offset 0x14304
ERR_RST_EVNT_ICCR[11] SP3_ERR_STAT[2] – Fatal SP_CTL_INDEP[6]
Offset 0x0278 Offset 0x12004
ERR_RST_EVNT_ICCR[16] SP_IP_MODE[2]
error
SP3_ERR_STAT[25] – Failed
Threshold
SP3_ERR_STAT[24] –
Degraded Threshold
Offset 0x14304
SP3_CTL_INDEP[20] – Illegal
Transaction
SP3_CTL_INDEP[16] – Max
Retry Error
Interrupt Conditions
Table 39. Interrupt Condition Routing Options
Field Access Reset Value Value Function
ICRx R 0000b 0000b Routed to INTDST0
4.4.1 Doorbell Interrupt Condition Routing Registers
Figure 54 shows the interrupt condition routing registers for Doorbell 0. The other doorbell ICRRs have the
same bit field map, with the following addresses:
• DOORBELL1_ICRR and DOORBELL1_ICCR2 (Address offsets 0290h and 0294h)
• DOORBELL2_ICRR and DOORBELL2_ICRR2 (Address offset 02A0h and 02A4h)
• DOORBELL3_ICRR and DOORBELL3_ICRR2 (Address offset 02B0h and 02B4h)
0001b Routed to INTDST1
0010b Routed to INTDST2
0011b Routed to INTDST3
0100b Routed to INTDST4
0101b Routed to INTDST5
0110b Routed to INTDST6
0111b Routed to INTDST7
1111b No interrupt destination, interrupt source disabled
other Reserved
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When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests
to interrupt destinations. For example, if ICS6 = 1 in DOORBELL2_ICSR and ICR6 = 0010b in
DOORBELL2_ICRR, the interrupt request from Doorbell 2, bit 6 is sent to interrupt destination 2.
Figure 54. Doorbell 0 Interrupt Condition Routing Registers
Doorbell 0 Interrupt Condition Routing Register (DOORBELL0_ICRR) (Address Offset 0280h)
31 28 27 24 23 20 19 16
ICR7 ICR6 ICR5 ICR4
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR3 ICR2 ICR1 ICR0
R/W-0000 R/W-0000 R/W-0000 R/W-0000
Doorbell 0 Interrupt Condition Routing Register 2 (DOORBELL0_ICRR2) (Address Offset 0284h)
31 28 27 24 23 20 19 16
ICR15 ICR14 ICR13 ICR12
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR11 ICR10 ICR9 ICR8
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R/W = Read/Write; - n = Value after reset
4.4.1.1 CPPI Interrupt Condition Routing Registers
Figure 55 shows the ICRRs for the RXU, and Figure 56 shows the ICRRs for the TXU. These registers
route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in RX_CPPI_ICSR and ICR6 =
0010b in RX_CPPI_ICRR, the interrupt request from RX buffer descriptor queue 6 is sent to interrupt
destination 2. Similarly, if ICS6 = 1 in TX_CPPI_ICSR and ICR6 = 0011b in TX_CPPI_ICRR, the interrupt
request from TX buffer descriptor queue 6 is sent to interrupt destination 3.
Figure 55. RX CPPI Interrupt Condition Routing Registers
RX CPPI Interrupt Condition Routing Register (RX_CPPI_ICRR) (Address Offset 02C0h)
31 28 27 24 23 20 19 16
ICR7 ICR6 ICR5 ICR4
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR3 ICR2 ICR1 ICR0
R/W-0000 R/W-0000 R/W-0000 R/W-0000
RX CPPI Interrupt Condition Routing Register 2 (RX_CPPI_ICRR2) (Address Offset 02C4h)
31 28 27 24 23 20 19 16
ICR15 ICR14 ICR13 ICR12
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR11 ICR10 ICR9 ICR8
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R/W = Read/Write; - n = Value after reset
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Figure 56. TX CPPI Interrupt Condition Routing Registers
TX CPPI Interrupt Condition Routing Register (TX_CPPI_ICRR) (Address Offset 02D0h)
31 28 27 24 23 20 19 16
ICR7 ICR6 ICR5 ICR4
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR3 ICR2 ICR1 ICR0
R/W-0000 R/W-0000 R/W-0000 R/W-0000
TX CPPI Interrupt Condition Routing Register 2 (TX_CPPI_ICRR2) (Address Offset 02D4h)
31 28 27 24 23 20 19 16
ICR15 ICR14 ICR13 ICR12
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR11 ICR10 ICR9 ICR8
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R/W = Read/Write; - n = Value after reset
4.4.1.2 LSU Interrupt Condition Routing Registers
Figure 57 shows the ICRRs for the LSU interrupt requests. These registers route LSU interrupt requests to
interrupt destinations. For example, if ICS4 = 1 in LSU_ICSR and ICR4 = 0000b in LSU_ICRR0, LSU1
has generated a transaction-timeout interrupt request, and that request is routed to interrupt destination 0.
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Figure 57. LSU Interrupt Condition Routing Registers
LSU Interrupt Condition Routing Register 0 (LSU_ICRR0) (Address Offset 02E0h)
31 28 27 24 23 20 19 16
ICR7 ICR6 ICR5 ICR4
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR3 ICR2 ICR1 ICR0
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LSU Interrupt Condition Routing Register 1 (LSU_ICRR1) (Address Offset 02E4h)
31 28 27 24 23 20 19 16
ICR15 ICR14 ICR13 ICR12
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR11 ICR10 ICR9 ICR8
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LSU Interrupt Condition Routing Register 2 (LSU_ICRR2) (Address Offset 02E8h)
31 28 27 24 23 20 19 16
ICR23 ICR22 ICR21 ICR20
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR19 ICR18 ICR17 ICR16
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LSU Interrupt Condition Routing Register 3 (LSU_ICRR3) (Address Offset 02ECh)
31 28 27 24 23 20 19 16
ICR31 ICR30 ICR29 ICR28
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR27 ICR26 ICR25 ICR24
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R/W = Read/Write; - n = Value after reset
4.4.1.3 Error, Reset, and Special Event Interrupt Condition Routing Registers
The ICRRs shown in Figure 58 route port interrupt requests to interrupt destinations. For example, if
ICS8 = 1 in ERR_RST_EVNT_ICSR and ICR8 = 0001b in ERR_RST_EVNT_ICRR2, port 0 has generated
an error interrupt request, and that request is routed to interrupt destination 1.
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Figure 58. Error, Reset, and Special Event Interrupt Condition Routing Registers
Error, Reset, and Special Event ICRR (ERR_RST_EVNT_ICRR) (Address Offset 02F0h)
31
Reserved
R-0
12 11 8 7 4 3 0
Reserved ICR2 ICR1 ICR0
R-0 R/W-0000 R/W-0000 R/W-0000
Error, Reset, & Special Event ICRR 2 (ERR_RST_EVNT_ICRR2) (Address Offset 02F4h)
31 16
Reserved
R-0
15 12 11 8 7 4 3 0
ICR11 ICR10 ICR9 ICR8
R/W-0000 R/W-0000 R/W-0000 R/W-0000
Error, Reset, and Special Event ICRR 3 (ERR_RST_EVNT_ICRR3) (Address Offset 02F8h)
31
Reserved
R-0
4 3 0
Reserved ICR16
R-0 R/W-0000
LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset
4.5 Interrupt Status Decode Registers
There are 8 blocks of the ICSRs to indicate the source of a pending interrupt.
0x0200: Doorbell0 interrupts
0x0210: Doorbell1 interrupts
0x0220: Doorbell2 interrupts
0x0230: Doorbell3 interrupts
0x0240: RX CPPI interrupts
0x0250: TX CPPI interrupts
0x0260: LSU interrupts
0x0270: Error, Reset, and Special Event interrupts
To reduce the number of reads (up to 5 reads) required to find the source bit, an Interrupt Status Decode
Register (ISDR) is implemented for each supported physical interrupt destination. The device supports up
to eight interrupt destinations, INTDST0–INTDST7. The names of the ISDRs and their address offsets are:
• INTDST0_DECODE (Address offset 0300h)
• INTDST1_DECODE (Address offset 0304h)
• INTDST2_DECODE (Address offset 0308h)
• INTDST3_DECODE (Address offset 030Ch)
• INTDST4_DECODE (Address offset 0310h)
• INTDST5_DECODE (Address offset 0314h)
• INTDST6_DECODE (Address offset 0318h)
• INTDST7_DECODE (Address offset 031Ch)
Aside from supporting different interrupt destinations, the ISDRs are the same in content and functionality.
The register fields are shown in Figure 59 . Figure 60 shows which interrupt sources can be mapped to
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each bit in the ISDR. Bits within the LSU interrupt condition status register (ICSR) are logically grouped for
a given core and ORed together into a single bit (bit 31) of the decode register. Similarly, the bits within
the Error, Reset, and Special Event ICSR are ORed together into bit 30 of the decode register. The TX
CPPI and RX CPPI interrupt sources (one for each buffer descriptor queue) can be mapped to bits 31–16
as shown in Figure 60 . The doorbell interrupt sources can be mapped to bits 15–0.
An interrupt source is mapped to ISDR bits only if the ICRR for that interrupt source routes it to the
corresponding interrupt destination. When multiple interrupt sources are mapped to the same bit, the bit
status is a logical OR of those interrupt sources. The mapping of interrupt source bits to decode bits is
fixed and is not programmable.
Figure 59. Interrupt Status Decode Register (INTDST n_DECODE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISD31 ISD30 ISD29 ISD28 ISD27 ISD26 ISD25 ISD24 ISD23 ISD22 ISD21 ISD20 ISD19 ISD18 ISD17 ISD16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISD15 ISD14 ISD13 ISD12 ISD11 ISD10 ISD9 ISD8 ISD7 ISD6 ISD5 ISD4 ISD3 ISD2 ISD1 ISD0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = Value after reset
Figure 60. Interrupt Sources Assigned to ISDR Bits
A Please note that bits 0 through 15 of this ICSR correspond to bits 31 through 16 of the ISDR. For example, bit 15 of
the ICSR corresponds to bit 31 of the ISDR, and so on.
B Please note that bits 15 through 0 of this ICSR correspond to bits 15 through 0 of the ISDR. For example, bit 15 of
the ICSR corresponds to bit 15 of the ISDR, and so on.
As an example of reading an ISDR, if bit 29 of the ISDR is set, this indicates that there is a pending
interrupt on either the TX CPPI queue 2 or RX CPPI queue 2. Figure 61 illustrates the decode routing for
this example.
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Figure 61. Example Diagram of Interrupt Status Decode Register Mapping
Interrupt Conditions
The following are suggestions for minimizing the number of register reads to identifying the interrupt
source:
• Dedicate each doorbell ICSR to one core. The CPU can then determine the interrupt source from a
single read of the decode register.
• Assign the RX and TX CPPI queues orthogonally to different cores. The CPU can then determine the
interrupt source from a single read of the decode registers. The only exceptions to this are bits 31 and
30, which are also logically ORed with LSU and port interrupt sources.
4.6 Interrupt Generation
Interrupts are triggered on a 0-to-1 logic-signal transition. Regardless of the interrupt sources, the physical
interrupts are set only when the total number of set ICSR bits transitions from none to one or more. The
peripheral is responsible for setting the correct bit within the ICSR. The ICRR register maps the pending
interrupt request to the appropriate physical interrupt line. The corresponding CPU is interrupted and
reads the ISDR and ICSR registers to determine the interrupt source and appropriate action. Interrupt
generation is governed by the interrupt pacing discussed Section 4.7 .
4.7 Interrupt Pacing
The rate at which an interrupt can be generated is controllable for each physical interrupt destination. Rate
control is implemented with a programmable down-counter. The load value of the counter is written by the
CPU into the appropriate interrupt rate control register (see Figure 62 ). The counter reloads and
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Interrupt Conditions
immediately starts down-counting each time the CPU writes these registers. When the rate control counter
register is written, and the counter value reaches zero (note that the CPU may write zero immediately for
a zero count), the interrupt pulse generation logic is allowed to fire a single pulse if any bits in the
corresponding ICSR register bits are set (or become set after the zero count is reached). The counter
remains at zero. When the single pulse is generated, the logic will not generate another pulse, regardless
of interrupt status changes, until the rate control counter register is written again.
An interrupt rate control register (INTDST n_RATE_CNTL) is implemented for each supported physical
interrupt destination. The device supports up to eight interrupt destinations, INTDST0–INTDST7. The
names of the registers and their address offsets are:
• INTDST0_RATE_CNTL (Address offset 0320h)
• INTDST1_RATE_CNTL (Address offset 0324h)
• INTDST2_RATE_CNTL (Address offset 0328h)
• INTDST3_RATE_CNTL (Address offset 032Ch)
• INTDST4_RATE_CNTL (Address offset 0330h)
• INTDST5_RATE_CNTL (Address offset 0334h)
• INTDST6_RATE_CNTL (Address offset 0338h)
• INTDST7_RATE_CNTL (Address offset 033Ch)
If interrupt pacing is not desired for a particular interrupt destination, the CPU must still write 00000000h
into the INTDST n_RATE_CNTL register after clearing the corresponding ICSR bits to acknowledge the
physical interrupt. If an ICSR is not mapped to an interrupt destination, pending interrupt bits within the
ICSR maintain current status. When enabled, the interrupt logic re-evaluates all pending interrupts and
re-pulses the interrupt signal if any interrupt conditions are pending. The down-counter is based on the
DMA clock cycle.
Figure 62. INTDST n_RATE_CNTL Interrupt Rate Control Register
31 0
32-bit Count Down Value
R/W-0
LEGEND: R/W = Read/Write; - n = Value after reset
4.8 Interrupt Handling
Interrupts are either signaled externally through RapidIO packets, or internally by state machines in the
peripheral. CPU servicing interrupts are signaled externally by the DOORBELL RapidIO packet in direct
I/O mode, or internally by the CPPI module in the message passing mode. Error Status interrupts are
signaled when error counting logic within the peripheral have reached their thresholds. In either case, it is
the peripheral that signals the interrupt and sets the corresponding status bits.
When the CPU is interrupted, it reads the ICSR registers to determine the source of the interrupt and
appropriate action to take. For example, if it is a DOORBELL interrupt, the CPU will read from an L2
address that is specified by its circular buffer read pointer that is managed by software. There may be
more than one circular buffer for each core. The correct circular buffer to read from and increment
depends on the bit set in the ICSR register. The CPU then clears the status bit.
For Error Status interrupts, the peripheral must indicate to all the CPUs that one of the link ports has
reached the error threshold. In this case, the peripheral sets the status bit indicating degraded or failed
limits have been reached, and an interrupt is generated to each core through the ICRR mapping. The
cores can then scan the ICSR registers to determine the port with the error problems. Further action can
then be taken as determined by the application.
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