TEXAS INSTRUMENTS TMS320R2811, TMS320R2812 Technical data
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TMS320R2811, TMS320R2812
Digital Signal Processors
Data Manual
Literature Number: SPRS257
June 2004
ADVANCE INFORMATION concerns new
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Contents
Contents
Section Page
1 Features 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Introduction 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Description 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Device Summary 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Pin Assignments 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Terminal Assignments for the GHH and ZHH Packages 14. . . . . . . . . . . . . . . . . . .
2.3.2 Pin Assignments for the PGF Package 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Pin Assignments for the PBK Package 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Signal Descriptions 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Functional Overview 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Memory Map 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Brief Descriptions 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 C28x CPU 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Memory Bus (Harvard Bus Architecture) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Peripheral Bus 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Real-Time JTAG and Analysis 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 External Interface (XINTF) (2812 Only) 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 M0, M1 SARAMs 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7 L0, L1, L2, L3, H0 SARAMs 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 Boot ROM 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9 Security 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.10 Peripheral Interrupt Expansion (PIE) Block 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.11 External Interrupts (XINT1, 2, 13, XNMI) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.12 Oscillator and PLL 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.13 Watchdog 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.14 Peripheral Clocking 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.15 Low-Power Modes 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.16 Peripheral Frames 0, 1, 2 (PFn) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer 34. . . . . . . . . . . . . . . . . . . . . . . .
3.2.18 32-Bit CPU-Timers (0, 1, 2) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.19 Control Peripherals 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.20 Serial Port Peripherals 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Register Map 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Device Emulation Registers 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 External Interface, XINTF (2812 Only) 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Timing Registers 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 XREVISION Register 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Interrupts 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 External Interrupts 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 System Control 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 OSC and PLL Block 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2 Loss of Input Clock 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 PLL-Based Clock Module 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 External Reference Oscillator Clock Option 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 Watchdog Block 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.6 Low-Power Modes Block 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Peripherals 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 32-Bit CPU-Timers 0/1/2 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
June 2004 SPRS257
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Contents
4.2 Event Manager Modules (EVA, EVB) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 General-Purpose (GP) Timers 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Full-Compare Units 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Programmable Deadband Generator 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 PWM Waveform Generation 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 Double Update PWM Mode 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6 PWM Characteristics 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.7 Capture Unit 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.8 Quadrature-Encoder Pulse (QEP) Circuit 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.9 External ADC Start-of-Conversion 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Enhanced Analog-to-Digital Converter (ADC) Module 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Enhanced Controller Area Network (eCAN) Module 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Multichannel Buffered Serial Port (McBSP) Module 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Serial Communications Interface (SCI) Module 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Serial Peripheral Interface (SPI) Module 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 GPIO MUX 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Development Support 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Device and Development Support Tool Nomenclature 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Documentation Support 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Electrical Specifications 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Absolute Maximum Ratings 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Recommended Operating Conditions 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320R281x) 86. . . . . . . . . . . . . . . . . .
6.5 Current Consumption Graphs 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Reducing Current Consumption 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Power Sequencing Requirements 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 Signal Transition Levels 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Timing Parameter Symbology 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 General Notes on Timing Parameters 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Test Load Circuit 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Device Clock Table 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Clock Requirements and Characteristics 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.1 Input Clock Requirements 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.2 Output Clock Characteristics 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Reset Timing 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 Low-Power Mode Wakeup Timing 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16 Event Manager Interface 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.1 PWM Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.2 Interrupt Timing 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17 General-Purpose Input/Output (GPIO) − Output Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18 General-Purpose Input/Output (GPIO) − Input Timing 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19 SPI Master Mode Timing 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20 SPI Slave Mode Timing 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21 External Interface (XINTF) Timing 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22 XINTF Signal Alignment to XCLKOUT 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23 External Interface Read Timing 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24 External Interface Write Timing 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.25 External Interface Ready-on-Read Timing With One External Wait State 118. . . . . . . . . . . . . . . .
6.26 External Interface Ready-on-Write Timing With One External Wait State 121. . . . . . . . . . . . . . . .
6.27 XHOLD
and XHOLDA 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28 XHOLD/XHOLDA Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29 On-Chip Analog-to-Digital Converter 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.1 ADC Absolute Maximum Ratings† 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.2 ADC Electrical Characteristics Over Recommended
Operating Conditions 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.3 Current Consumption for Different ADC Configurations
(at 25-MHz ADCCLK) 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.4 ADC Power-Up Control Bit Timing 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.5 Detailed Description 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0) 131. . . . . . . . . . . . . . .
6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) 133. . . . . . . . . . . . . .
6.29.8 Definitions of Specifications and Terminology 134. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30 Multichannel Buffered Serial Port (McBSP) Timing 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30.1 McBSP Transmit and Receive Timing 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30.2 McBSP as SPI Master or Slave Timing 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Migration From F281x Devices 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Mechanical Data 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Ball Grid Array (BGA) 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Plastic Ball Grid Array 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Low-Profile Quad Flatpacks (LQFPs) 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
June 2004 SPRS257
5
Figures
List of Figures
Figure Page
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View) 14. . . . . . . . . . . . . . . . . . . . . .
Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View) 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2−3. TMS320R2811 128-Pin PBK LQFP (Top View) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−1. Functional Block Diagram 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−2. R2812 Memory Map 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−3. R2811 Memory Map 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−4. External Interface Block Diagram 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−5. Interrupt Sources 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−6. Multiplexing of Interrupts Using the PIE Block 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−7. Clock and Reset Domains 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−8. OSC and PLL Block 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−9. Recommended Crystal/Clock Connection 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3−10. Watchdog Module 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−1. CPU-Timers 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−2. CPU-Timer Interrupts Signals and Output Signal 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−3. Event Manager A Functional Block Diagram 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−4. Block Diagram of the R281x ADC Module 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−5. ADC Pin Connections With Internal Reference 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−6. ADC Pin Connections With External Reference 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−7. eCAN Block Diagram and Interface Circuit 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−8. eCAN Memory Map 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−9. McBSP Module With FIFO 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram 72. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) 76. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−12. Modes of Operation 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5−1. TMS320x28x Device Nomenclature 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−1. R2812/R2811 Typical Current Consumption (With Peripheral Clocks Enabled) 87. . . . . . . . . . . . . . . .
Figure 6−2. Output Levels 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−3. Input Levels 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−4. 3.3-V Test Load Circuit 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−5. Clock Timing 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−6. Power-on Reset in Microcomputer Mode (XMP/MC = 0) 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−7. Power-on Reset in Microprocessor Mode (XMP/MC = 1) 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−8. Warm Reset in Microcomputer Mode 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−9. Effect of Writing Into PLLCR Register 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−10. IDLE Entry and Exit Timing 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−11. STANDBY Entry and Exit Timing 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−12. HALT Wakeup Using XNMI 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−13. PWM Output Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−14. TDIRx Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure 6−15. EVASOC Timing 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−16. EVBSOC Timing 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−17. External Interrupt Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−18. General-Purpose Output Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−19. GPIO Input Qualifier − Example Diagram for QUALPRD = 1 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−20. General-Purpose Input Timing 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−21. SPI Master Mode External Timing (Clock Phase = 0) 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−22. SPI Master External Timing (Clock Phase = 1) 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−23. SPI Slave Mode External Timing (Clock Phase = 0) 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 1) 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−25. Relationship Between XTIMCLK and SYSCLKOUT 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−26. Example Read Access 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−27. Example Write Access 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−28. Example Read With Synchronous XREADY Access 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−29. Example Read With Asynchronous XREADY Access 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−30. Write With Synchronous XREADY Access 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−31. Write With Asynchronous XREADY Access 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−32. External Interface Hold Waveform 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−33. XHOLD
/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 126. . . . . . . . . . . . . . . . . . . . .
Figure 6−34. ADC Analog Input Impedance Model 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−35. ADC Power-Up Control Bit Timing 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−36. Sequential Sampling Mode (Single-Channel) Timing 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−37. Simultaneous Sampling Mode Timing 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−38. McBSP Receive Timing 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−39. McBSP Transmit Timing 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6−40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 138. . . . . . . . . . . . . . . . . . . . . .
Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 139. . . . . . . . . . . . . . . . . . . . . .
Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 140. . . . . . . . . . . . . . . . . . . . . .
Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 141. . . . . . . . . . . . . . . . . . . . . .
Figure 7−1. TMS320R2812 179-Ball GHH MicroStar BGA 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7−2. TMS320R2812 179-Ball ZHH MicroStar BGA 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7−3. TMS320R2812 176-Pin PGF LQFP 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7−4. TMS320R2811 128-Pin PBK LQFP 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
June 2004 SPRS257
7
Tables
List of Tables
Table Page
Table 2−1. Hardware Features 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2−2. Signal Descriptions 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−1. Wait States 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−2. Peripheral Frame 0 Registers 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−3. Peripheral Frame 1 Registers 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−4. Peripheral Frame 2 Registers 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−5. Device Emulation Registers 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−6. XINTF Configuration and Control Register Mappings 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−7. XREVISION Register Bit Definitions 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−8. PIE Peripheral Interrupts 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−9. PIE Configuration and Control Registers 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−10. External Interrupt Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−11. PLL, Clocking, Watchdog, and Low-Power Mode Registers 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−12. PLLCR Register Bit Definitions 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−13. Possible PLL Configuration Modes 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3−14. R281x Low-Power Modes 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−2. Module and Signal Names for EVA and EVB 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−3. EVA Registers 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−4. ADC Registers 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−5. 3.3-V eCAN Transceivers for the R281x DSPs 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−6. CAN Registers Map 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−7. McBSP Register Summary 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−8. SCI-A Registers 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−9. SCI-B Registers 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−10. SPI Registers 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−11. GPIO Mux Registers 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−12. GPIO Data Registers 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz) 87. . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−2. TMS320R281x Clock Table and Nomenclature 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−3. Input Clock Frequency 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−4. XCLKIN Timing Requirements − PLL Bypassed or Enabled 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−5. XCLKIN Timing Requirements − PLL Disabled 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−6. Possible PLL Configuration Modes 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) 92. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−8. Reset (XRS) Timing Requirements 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−9. IDLE Mode Switching Characteristics 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−10. STANDBY Mode Switching Characteristics 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−11. HALT Mode Switching Characteristics 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−12. PWM Switching Characteristics 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−13. Timer and Capture Unit Timing Requirements 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−14. External ADC Start-of-Conversion − EVA − Switching Characteristics 101. . . . . . . . . . . . . . . . . . . . . .
Table 6−15. External ADC Start-of-Conversion − EVB − Switching Characteristics 101. . . . . . . . . . . . . . . . . . . . . .
Table 6−16. Interrupt Switching Characteristics 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−17. Interrupt Timing Requirements 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−18. General-Purpose Output Switching Characteristics 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
June 2004SPRS257
Table 6−19. General-Purpose Input Timing Requirements 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−20. SPI Master Mode External Timing (Clock Phase = 0) 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−21. SPI Master Mode External Timing (Clock Phase = 1) 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−22. SPI Slave Mode External Timing (Clock Phase = 0) 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−23. SPI Slave Mode External Timing (Clock Phase = 1) 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−24. Relationship Between Parameters Configured in XTIMING and Duration of Pulse 112. . . . . . . . . . . .
Table 6−25. XINTF Clock Configurations 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−26. External Memory Interface Read Switching Characteristics 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−27. External Memory Interface Read Timing Requirements 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−28. External Memory Interface Write Switching Characteristics 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−29. External Memory Interface Read Switching Characteristics
(Ready-on-Read, 1 Wait State) 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−30. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) 118. . . . . .
Table 6−31. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) 118. . . . . . . . . . . . . . .
Table 6−32. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) 118. . . . . . . . . . . . . .
Table 6−33. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) 121. . .
Table 6−34. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) 121. . . . . . . . . . . . . . .
Table 6−35. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) 121. . . . . . . . . . . . . .
Table 6−36. XHOLD
/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) 125. . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−37. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 126. . . . . . . . . . . . . . . . . . . . . .
Table 6−38. DC Specifications 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−39. AC Specifications 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−40. ADC Power-Up Delays 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−41. Sequential Sampling Mode Timing 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−42. Simultaneous Sampling Mode Timing 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−43. McBSP Timing Requirements 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−44. McBSP Switching Characteristics 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6−45. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 138. . . . . . . . .
Table 6−46. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 138. . . . . .
Table 6−47. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 139. . . . . . . . . .
Table 6−48. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 139. . . . . .
Table 6−49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 140. . . . . . . . .
Table 6−50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 140. . . . . .
Table 6−51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 141. . . . . . . . . .
Table 6−52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 141. . . . . .
Table 6−53. Feature Comparison Between F281x and R281x Devices 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7−1. Thermal Resistance Characteristics for 179-GHH 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7−2. Thermal Resistance Characteristics for 179-ZHH 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7−3. Thermal Resistance Characteristics for 176-PGF 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7−4. Thermal Resistance Characteristics for 128-PBK 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
June 2004 SPRS257
9
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10
June 2004SPRS257
1 Features
ADVANCE INFORMATION
Features
D High-Performance Static CMOS Technology
− 150 MHz (6.67-ns Cycle Time)
− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design
D JTAG Boundary Scan Support
†
D High-Performance 32-Bit CPU
(TMS320C28x)
− 16 x 16 and 32 x 32 MAC Operations
− 16 x 16 Dual MAC
− Harvard Bus Architecture
− Atomic Operations
− Fast Interrupt Response and Processing
− Unified Memory Programming Model
− 4M Linear Program/Data Address Reach
− Code-Efficient (in C/C++ and Assembly)
− Code and Pin Compatible to F2810,
F2811, and F2812 devices
− TMS320F24x/LF240x Processor Source
Code Compatible
D On-Chip Memory
− 20K x 16 Total Single-Access RAM
(SARAM)
− L0 and L1: 2 Blocks of 4K x 16 Each
SARAM
− L2 and L3: 2 Blocks of 1K X 16 SARAM
− H0: 1 Block of 8K x 16 SARAM
− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
D SPI, SCI, and GPIO Boot Loader Modes to
Support Loading Code From Off-chip
Sources to On-chip RAM. SPI Boot Mode
Supports Loading From an External Serial
EEPROM.
D Boot ROM (4K x 16)
− With Software Boot Modes
− Standard Math Tables
D External Interface (2812)
− Up to 1M Total Memory
− Programmable Wait States
− Programmable Read/Write Strobe Timing
− Three Individual Chip Selects
D Clock and System Control
− Dynamic PLL Ratio Changes Supported
− On-Chip Oscillator
− Watchdog Timer Module
D Three External Interrupts
D Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
D Three 32-Bit CPU-Timers
D Motor Control Peripherals
− Two Event Managers (EVA, EVB)
− Compatible to 240xA Devices
D Serial Port Peripherals
− Serial Peripheral Interface (SPI)
− Two Serial Communications Interfaces
(SCIs), Standard UART
− Enhanced Controller Area Network
(eCAN)
− Multichannel Buffered Serial Port
(McBSP)
D 12-Bit ADC, 16 Channels
− 2 x 8 Channel Input Multiplexer
− Two Sample-and-Hold
− Single/Simultaneous Conversions
− Fast Conversion Rate: 80 ns/12.5 MSPS
D Up to 56 General Purpose I/O (GPIO) Pins
D Advanced Emulation Features
− Analysis and Breakpoint Functions
− Real-Time Debug via Hardware
D Development Tools Include
− ANSI C/C++ Compiler/Assembler/Linker
− Code Composer Studio IDE
− DSP/BIOS
− JTAG Scan Controllers
†
D Low-Power Modes and Power Savings
− IDLE, STANDBY, HALT Modes Supported
− Disable Individual Peripheral Clocks
D Package Options
− 179-Ball MicroStar BGA With External
Memory Interface (GHH), (ZHH) (2812)
− 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Memory Interface
(PGF) (2812)
− 128-Pin LQFP Without External Memory
Interface (PBK) (2811)
D Temperature Options:
− A: −40°C to 85°C (GHH, ZHH, PGF, PBK)
− S/Q: −40°C to 125°C (GHH, ZHH, PGF,
PBK)
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
†
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
June 2004 SPRS257
11
Introduction
ADVANCE INFORMATION
2 Introduction
This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
2.1 Description
The TMS320R2811 and TMS320R2812 devices, members of the TMS320C28x DSP generation, are highly
integrated, high-performance solutions for demanding control applications. The functional blocks and the
memory maps are described in Section 3, Functional Overview.
Throughout this document, TMS320R2811 and TMS320R2812 are abbreviated as R2811 and R2812,
respectively.
TMS320C28x is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12
June 2004SPRS257
2.2 Device Summary
ADVANCE INFORMATION
Table 2−1 provides a summary of each device’s features.
Table 2−1. Hardware Features
Introduction
†
FEATURE
Instruction Cycle (at 150 MHz) 6.67 ns 6.67 ns
Single-Access RAM (SARAM)
(16-bit word)
Boot ROM Yes Yes
External Memory Interface — Yes
Event Managers A and B
(EVA and EVB)
S General-Purpose (GP) Timers 4 4
S Compare (CMP)/PWM 16 16
S Capture (CAP)/QEP Channels 6/2 6/2
Watchdog Timer Yes Ye s
12-Bit ADC Ye s Ye s
S Channels 16 16
32-Bit CPU Timers 3 3
SPI Ye s Ye s
SCIA, SCIB SCIA, SCIB SCIA, SCIB
CAN Ye s Ye s
McBSP Yes Ye s
Digital I/O Pins (Shared) 56 56
External Interrupts 3 3
Supply Voltage 1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O
Packaging 128-pin PBK
Temperature Options
Product Status
†
The S temperature option has been replaced by the Q temperature option (40°C to 125°C) from silicon revision E onwards. Q stands for
−40°C to 125°C Q100 automotive fault grading.
‡
See Section 5.1, Device and Development Support Nomenclature for descriptions of TMS and TMX stages.
†
‡
A: −40°C to 85°C Yes Yes
S/Q: −40°C to 125°C Ye s Ye s
R2811 R2812
20K 20K
EVA, EVB EVA, EVB
179-ball GHH
179-ball ZHH
176-pin PGF
TMX TMX
June 2004 SPRS257
13
Introduction
ADVANCE INFORMATION
2.3 Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages.
Figure 2−2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3
shows the pin assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin.
2.3.1 Terminal Assignments for the GHH and ZHH Packages
See Table 2−2 for a description of each terminal’s function(s).
P
N
M
XZCS0AND1 PWM10
SPISOMIA PWM9 XR/W
SPISIMOA XA[1] XRD
L
K
J
MCLKXA MFSRA XD[3]
H
G
F
E
MDXA MDRA XD[0]
XMP/MC
AVDD-
REFBG
PWM8
PWM7 TEST2
V
DD
V
SPICLKA
SS
V
MCLKRA XD[1] MFSXA XD[2]
DD
RESEXT
ADCREFP
XD[6] PWM11 XD[7] C5TRIP
V
SS
XD[4]
ADC-
V
AVSS-
REFBG
V
PWM12
SPISTEA
V
DDIO
V
V
SSA1
DDA1
ADCREFM ADCINA5
SS
T4PWM
_T4CMP
_QEP3
T3PWM
_T3CMP
SS
ADCINB7 C3TRIP XCLKOUT XA[7] TCLKINA TDIRA
CAP6
V
DD
_QEPI2
C4TRIP
CAP4
CAP5
_QEP4
XD[5] XD[13]
XA[0]
BGREFIN
XD[8]
TEST1 XD[9] X2
V
V
C6TRIP TCLKINB
SS
ADC-
XHOLD
DDIO
V
SS
V
DDIO
TDIRB XD[10]
XNMI
_XINT13
T3CTRIP
V
DD
_PDPINTB
XD[11] XA[2] XWE CANTXA CANRXA
X1/
XCLKIN
V
DDIO
T4CTRIP/
EVBSOC
V
XA[3] PWM1
SS
DDIO
PWM5
T1PWM
_T1CMP
CAP2
_QEP2
/
V
V
V
XHOLDA
CAP1
_QEP1
T2CTRIP
EVASOC
XA[13] C2TRIP XA[8] C1TRIP
V
DD
PWM3 PWM4 XD[12]
SS
V
DD
XA[4]
CAP3
_QEPI1
V
DDIO
DD
XZCS2 SCITXDB
SCIRXDB
V
T2PWM
_T2CMP
XA[5]
SS
V
SS
V
DDIO
PWM2
PWM6
V
SS
T1CTRIP
_PDPINTA
XA[6]
V
SS
14
XINT2
D
C
B
A
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6 XRS XA[18]
ADCINB3 ADCINB0 ADCINB1 ADCINA2
V
ADCINB2
ADCLO ADCINA3 ADCINA7 XREADY XA[17]
DDAIO
V
ADCINA0 ADCINA4 V
SSAIO
V
SSA2VSS1
DDA2VDD1
SCITXDA
SCIRXDA XA[16] XD[15] TESTSEL XA[11]
_ADCSOC
XINT1
_XBIO
V
EMU1
DD
XA[15]
V
SS
V
EMU0 TDO TMS XA[9]
SS
V
XA[12] XA[10] TDI
SS
XD[14] TRST XZCS6AND7
V
DD
XA[14]
XF
_XPLLDIS
TCK
V
DD
V
SS
1412 1310 1189563412 7
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View)
June 2004SPRS257
2.3.2 Pin Assignments for the PGF Package
ADVANCE INFORMATION
The TMS320R2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−2.
See Table 2−2 for a description of each pin’s function(s).
Introduction
XZCS6AND7
TESTSEL
TRST
TCK
EMU0
XA[12]
XD[14]
XF_XPLLDIS
XA[13]
V
V
XA[14]
V
DDIO
EMU1
XD[15]
XA[15]
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
XA[16]
V
V
SCITXDA
XA[17]
SCIRXDA
XA[18]
XHOLD
XRS
XREADY
V
DD1
V
ADCBGREFIN
SS1
V
SSA2
V
DDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
V
SSAIO
SS
VDDV
XA[11]
TDI
XA[10]
TDO
TMS
XA[9]
132 89
133
SS
DD
SS
DD
176
131
130
129
128
127
126
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
23456789101112131415161718192021222324252627282930313233343536373839404142
125
C2TRIP
C3TRIP
124
123
C1TRIP
XA[8]
121
122
SS
V
XCLKOUT
120
119
XA[7]
TCLKINA
118
117
T2CTRIP / EVASOC
TDIRA
116
115
DDIO
114
T1CTRIP_PDPINTA
VDDVSSV
XA[6]
111
113
112
110
SS
CAP3_QEPI1
XA[5]
CAP2_QEP2
CAP1_QEP1
V
109
108
107
106
105
DD
T2PWM_T2CMP
XA[4]
T1PWM_T1CMP
PWM6
VSSV
99989796959493
101
104
103
102
100
PWM5
XD[13]
XD[12]
PWM4
PWM3
PWM2
PWM1
929190
SCIRXDB
SCITXDB
CANRXA
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
43
88
XZCS2
CANTXA
V
SS
XA[3]
XWE
T4CTRIP/EVBSOC
XHOLDA
V
DDIO
XA[2]
T3CTRIP_PDPINTB
V
SS
X1/XCLKIN
X2
V
DD
XD[11]
XD[10]
TCLKINB
TDIRB
V
SS
V
DDIO
XD[9]
TEST1
TEST2
XD[8]
V
DDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
V
SS
CAP4_QEP3
V
DD
T4PWM_T4CMP
XD[7]
T3PWM_T3CMP
V
SS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
45
1
DDAIO
V
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFP
ADCREFM
SSA1
DDA1
V
V
AVSSREFBG
AVDDREFBG
SS
MCXMP/
V
XA[0]
MDRA
ADCRESEXT
XD[0]
MDXA
DD
V
XD[1]
MCLKRA
XD[2]
MFSXA
XD[3]VDDIO
MFSRA
MCLKXA
SS
V
XD[4]
SPICLKA
DD
V
XD[5]
SPISTEA
SS
V
XD[6]
SPISIMOA
XRD
XA[1]
SPISOMIA
44
XZCS0AND1
Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View)
June 2004 SPRS257
15
Introduction
ADVANCE INFORMATION
2.3.3 Pin Assignments for the PBK Package
The TMS320R2811 128-pin PBK low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−3.
See Table 2−2 for a description of each pin’s function(s).
TESTSEL
TRST
TCK
EMU0
XF_XPLLDIS
V
V
V
DDIO
EMU1
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
ADCBGREFIN
V
V
SCITXDA
SCIRXDA
XRS
V
DD1
V
SS1
V
SSA2
V
DDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
V
SSAIO
DD
DD
TCLKINA
TDIRA
T2CTRIP/ EVASOC
84
131415
DDIO
VDDV
83
82
T1CTRIP_PDPINTA
CAP1_QEP1
CAP2_QEP2
CAP3_QEPI1
81
79
78
80
16
18
19
17
DD
T2PWM_T2CMP
T1PWM_T1CMP
76
77
21
20
PWM6
757473
222324
VSSV
PWM5
72
25
PWM4
PWM3
71
70
27
26
PWM1
PWM2
69
68
28
29
SCIRXDB
SCITXDB
CANRXA
66
67
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
31
30
64
CANTXA
V
DD
V
SS
T4CTRIP
T3CTRIP_PDPINTB
V
SS
X1/XCLKIN
X2
V
DD
TCLKINB
TDIRB
V
SS
V
DDIO
TEST1
TEST2
V
DDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3
V
DD
T4PWM_T4CMP
T3PWM_T3CMP
V
SS
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
33
/EVBSOC
SS
TDI
TDO
TMS
VDDV
96 65
97
98
99
100
101
102
SS
SS
128
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
93
9291908988
95
94
2345678
C1TRIP
C2TRIP
C3TRIP
SS
XCLKOUT
V
878685
9
101112
16
1
SS
DD
V
DDAIO
V
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFP
ADCREFM
AVSSREFBG
AVDDREFBG
SSA1
DDA1
V
V
ADCRESEXT
MDRA
MDXA
V
MCLKRA
MFSXA
MCLKXA
Figure 2−3. TMS320R2811 128-Pin PBK LQFP
(Top View)
SS
V
DDIO
V
MFSRA
DD
V
V
SPISTEA
SPICLKA
SS
SPISIMOA
SPISOMIA
32
June 2004SPRS257
Introduction
19 bit XINTF Address Bus
ADVANCE INFORMATION
2.4 Signal Descriptions
Table 2−2 specifies the signals on the R281x devices. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.
Table 2−2. Signal Descriptions
PIN NO.
NAME
XA[18] D7 158 − O/Z −
XA[17] B7 156 − O/Z −
XA[16] A8 152 − O/Z −
XA[15] B9 148 − O/Z −
XA[14] A10 144 − O/Z −
XA[13] E10 141 − O/Z −
XA[12] C11 138 − O/Z −
XA[11] A14 132 − O/Z
XA[10] C12 130 − O/Z −
XA[9] D14 125 − O/Z −
XA[8] E12 121 − O/Z −
XA[7] F12 118 − O/Z −
XA[6] G14 111 − O/Z −
XA[5] H13 108 − O/Z −
XA[4] J12 103 − O/Z −
XA[3] M11 85 − O/Z −
XA[2] N10 80 − O/Z −
XA[1] M2 43 − O/Z −
XA[0] G5 18 − O/Z
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
‡
I/O/Z
XINTF SIGNALS (2812 ONLY)
PU/PD
§
19-bit XINTF Address Bus
†
DESCRIPTION
June 2004 SPRS257
17
Introduction
ADVANCE INFORMATION
Table 2−2. Signal Descriptions
PIN NO.
NAME DESCRIPTIONPU/PD
NAME DESCRIPTIONPU/PD
XD[15] A9 147 − I/O/Z PU
XD[14] B11 139 − I/O/Z PU
XD[13] J10 97 − I/O/Z PU
XD[12] L14 96 − I/O/Z PU
XD[11] N9 74 − I/O/Z PU
XD[10] L9 73 − I/O/Z PU
XD[9] M8 68 − I/O/Z PU
XD[8] P7 65 − I/O/Z PU
XD[7] L5 54 − I/O/Z PU
XD[6] L3 39 − I/O/Z PU
XD[5] J5 36 − I/O/Z PU
XD[4] K3 33 − I/O/Z PU
XD[3] J3 30 − I/O/Z PU
XD[2] H5 27 − I/O/Z PU
XD[1] H3 24 − I/O/Z PU
XD[0] G3 21 − I/O/Z PU
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z
I/O/Z
‡
‡
†
(Continued)
§
§
16-bit XINTF Data Bus
18
June 2004SPRS257
Introduction
ADVANCE INFORMATION
Table 2−2. Signal Descriptions
PIN NO.
NAME DESCRIPTIONPU/PD
NAME DESCRIPTIONPU/PD
XMP/MC F1 17 − I PD
XHOLD E7 159 − I PU
XHOLDA K10 82 − O/Z −
XZCS0AND1 P1 44 − O/Z −
XZCS2 P13 88 − O/Z −
XZCS6AND7 B13 133 − O/Z −
XWE N11 84 − O/Z −
XRD M3 42 − O/Z −
XR/W N4 51 − O/Z −
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
XINTF SIGNALS (2812 ONLY) (CONTINUED)
I/O/Z
I/O/Z
‡
‡
†
(Continued)
§
§
Microprocessor/Microcomputer Mode Select. Switches
between microprocessor and microcomputer mode. When
high, Zone 7 is enabled on the external interface. When low,
Zone 7 is disabled from the external interface, and on-chip
boot ROM may be accessed instead. This signal is latched
into the XINTCNF2 register on a reset and the user can modify
this bit in software. The state of the XMP/MC
after reset.
External Hold Request. XHOLD, when active (low), requests
the XINTF to release the external bus and place all buses and
strobes into a high-impedance state. The XINTF will release
the bus when any current access is complete and there are no
pending accesses on the XINTF.
External Hold Acknowledge. XHOLDA is driven active (low)
when the XINTF has granted a XHOLD
buses and strobe signals will be in a high-impedance state.
XHOLDA
External devices should only drive the external bus when
XHOLDA
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active
(low) when an access to the XINTF Zone 0 or Zone 1 is
performed.
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an
access to the XINTF Zone 2 is performed.
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active
(low) when an access to the XINTF Zone 6 or Zone 7 is
performed.
Write Enable. Active-low write strobe. The write strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers.
Read Enable. Active-low read strobe. The read strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers. NOTE: The XRD
and XWE signals are mutually exclusive.
Read Not Write Strobe. Normally held high. When low, XR/W
indicates write cycle is active; when high, XR/W indicates read
cycle is active.
is released when the XHOLD signal is released.
is active (low).
pin is ignored
request. All XINTF
June 2004 SPRS257
19
Introduction
ADVANCE INFORMATION
Table 2−2. Signal Descriptions
†
(Continued)
PIN NO.
NAME DESCRIPTIONPU/PD
GHH
AND
176-PIN
PGF
128-PIN
PBK
NAME DESCRIPTIONPU/PD
179-PIN
I/O/Z
I/O/Z
‡
‡
§
§
ZHH
XINTF SIGNALS (2812 ONLY) (CONTINUED)
Ready Signal. Indicates peripheral is ready to complete the
XREADY B6 161 − I PU
access when asserted to 1. XREADY can be configured to be
a synchronous or an asynchronous input. See the timing
diagrams for more details.
JTAG AND MISCELLANEOUS SIGNALS
Oscillator Input − input to the internal oscillator. This pin is also
used to feed an external clock. The 28x can be operated with
an external clock source, provided that the proper voltage
levels be driven on the X1/XCLKIN pin. It should be noted that
X1/XCLKIN K9 77 58 I
the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core
digital power supply (V
(V
). A clamping diode may be used to clamp a buffered
DDIO
), rather than the 3.3-V I/O supply
DD
clock signal to ensure that the logic-high level does not
exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
X2 M9 76 57 O Oscillator Output
Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose clock
source. XCLKOUT is either the same frequency, 1/2 the
XCLKOUT F11 119 87 O −
frequency, or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be
turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register
to 1.
TESTSEL A13 134 97 I PD Test Pin. Reserved for TI. Must be connected to ground.
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution.
The PC will point to the address contained at the location
0x3FFFC0. When XRS
is brought to a high level, execution
begins at the location pointed to by the PC. This pin is driven
XRS D6 160 11 3 I/O PU
low by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS
pin will be driven low for the
watchdog reset duration of 512 XCLKIN cycles.
The output buffer of this pin is an open-drain with an internal
pullup (100 µA, typical). It is recommended that this pin be
driven by an open-drain device.
TEST1 M7 67 51 I/O −
TEST2 N7 66 50 I/O −
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
This pin is a “no connect (NC)” (i.e., this pin is not connected
to any circuitry internal to the device).
This pin is a “no connect (NC)” (i.e., this pin is not connected
to any circuitry internal to the device).
20
June 2004SPRS257
Introduction
pins have bee
pins have been fully powered up
ADVANCE INFORMATION
Table 2−2. Signal Descriptions
†
(Continued)
PIN NO.
NAME DESCRIPTIONPU/PD
GHH
AND
176-PIN
PGF
128-PIN
PBK
NAME DESCRIPTIONPU/PD
179-PIN
I/O/Z
I/O/Z
‡
‡
§
§
ZHH
JTAG
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are
ignored.
TRST B12 135 98 I PD
NOTE: Do not use pullup resistors on TRST
pulldown device. In a low-noise environment, TRST
; it has an internal
can be
left floating. In a high-noise environment, an additional
pulldown resistor may be needed. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board is validated for proper
operation of the debugger and the application.
TCK A12 136 99 I PU JTAG test clock with internal pullup
JTAG test-mode select (TMS) with internal pullup. This serial
TMS D13 126 92 I PU
control input is clocked into the TAP controller on the rising
edge of TCK.
JTAG test data input (TDI) with internal pullup. TDI is clocked
TDI C13 131 96 I PU
into the selected register (instruction or data) on a rising edge
of TCK.
JTAG scan out, test data output (TDO). The contents of the
TDO D12 127 93 O/Z −
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
Emulator pin 0. When TRST is driven high, this pin is used
EMU0 D11 137 100 I/O/Z PU
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
Emulator pin 1. When TRST is driven high, this pin is used
EMU1 C9 146 105 I/O/Z PU
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
ADC ANALOG INPUT SIGNALS
ADCINA7 B5 167 11 9 I
ADCINA6 D5 168 120 I
ADCINA5 E5 169 121 I
ADCINA4 A4 170 122 I
ADCINA3 B4 171 123 I
8-Channel analog inputs for Sample-and-Hold A. The ADC
pins should not be driven before V
n fully powered up.
.
DDA1
, V
DDA2
, and V
ADCINA2 C4 172 124 I
ADCINA1 D4 173 125 I
ADCINA0 A3 174 126 I
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
DDAIO
June 2004 SPRS257
21
Introduction
bee
V
pins have been fully powered up
ADVANCE INFORMATION
Table 2−2. Signal Descriptions
†
(Continued)
PIN NO.
NAME DESCRIPTIONPU/PD
GHH
AND
176-PIN
PGF
128-PIN
PBK
NAME DESCRIPTIONPU/PD
179-PIN
I/O/Z
I/O/Z
‡
‡
§
§
ZHH
ADC ANALOG INPUT SIGNALS (CONTINUED)
ADCINB7 F5 9 9 I
ADCINB6 D1 8 8 I
ADCINB5 D2 7 7 I
ADCINB4 D3 6 6 I
ADCINB3 C1 5 5 I
8-Channel Analog Inputs for Sample-and-Hold B. The ADC
pins should not be driven before the V
V
DDAIO
pins have
n fully powered up.
DDA1
.
, V
DDA2
, and
ADCINB2 B1 4 4 I
ADCINB1 C3 3 3 I
ADCINB0 C2 2 2 I
ADC Voltage Reference Output (2 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ADCREFP E2 11 11 I/O
ground. (Can accept external reference input (2 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
ADC Voltage Reference Output (1 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ADCREFM E4 10 10 I/O
ground. (Can accept external reference input (1 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
ADCRESEXT F2 16 16 O ADC External Current Bias Resistor (24.9 kΩ ±5%)
ADCBGREFIN E6 164 11 6 I Test Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG E3 12 12 I ADC Analog GND
AVDDREFBG E1 13 13 I ADC Analog Power (3.3-V)
ADCLO B3 175 127 I Common Low Side Analog Input. Connect to analog ground.
V
SSA1
V
SSA2
V
DDA1
V
DDA2
V
SS1
V
DD1
V
DDAIO
V
SSAIO
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
F3 15 15 I ADC Analog GND
C5 165 117 I ADC Analog GND
F4 14 14 I ADC Analog 3.3-V Supply
A5 166 118 I ADC Analog 3.3-V Supply
C6 163 115 I ADC Digital GND
A6 162 114 I ADC Digital 1.8-V (or 1.9-V) Supply
B2 1 1 3.3-V Analog I/O Power Pin
A2 176 128 Analog I/O Ground Pin
22
June 2004SPRS257
Introduction
equirements
requirements
ADVANCE INFORMATION
Table 2−2. Signal Descriptions
†
(Continued)
PIN NO.
NAME DESCRIPTIONPU/PD
GHH
AND
176-PIN
PGF
128-PIN
PBK
NAME DESCRIPTIONPU/PD
179-PIN
I/O/Z
I/O/Z
‡
‡
§
§
ZHH
POWER SIGNALS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
H1 23 20
L1 37 29
P5 56 42
P9 75 56
P12 − 63
K12 100 74
G12 11 2 82
C14 128 94
B10 143 102
C8 154 110
G4 19 17
K1 32 26
L2 38 30
P4 52 39
K6 58 −
P8 70 53
M10 78 59
L11 86 62
K13 99 73
J14 105 −
G13 11 3 −
E14 120 88
B14 129 95
D10 142 −
C10 − 103
B8 153 109
J4 31 25
L7 64 49
L10 81 −
N14 − −
G11 114 83
E9 145 104
N8 69 52
1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2,
Recommended Operating Conditions, for voltage
.
r
.
Core and Digital I/O Ground Pins
3.3-V I/O Digital Power Pins
June 2004 SPRS257
23
Introduction
ADVANCE INFORMATION
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
GPIO PERIPHERAL SIGNAL
GPIOA0 PWM1 (O) M12 92 68 I/O/Z PU GPIO or PWM Output Pin #1
GPIOA1 PWM2 (O) M14 93 69 I/O/Z PU GPIO or PWM Output Pin #2
GPIOA2 PWM3 (O) L12 94 70 I/O/Z PU GPIO or PWM Output Pin #3
GPIOA3 PWM4 (O) L13 95 71 I/O/Z PU GPIO or PWM Output Pin #4
GPIOA4 PWM5 (O) K11 98 72 I/O/Z PU GPIO or PWM Output Pin #5
GPIOA5 PWM6 (O) K14 101 75 I/O/Z PU GPIO or PWM Output Pin #6
GPIOA6 T1PWM_T1CMP (I) J11 102 76 I/O/Z PU GPIO or Timer 1 Output
GPIOA7 T2PWM_T2CMP (I) J13 104 77 I/O/Z PU GPIO or Timer 2 Output
GPIOA8 CAP1_QEP1 (I) H10 106 78 I/O/Z PU GPIO or Capture Input #1
GPIOA9 CAP2_QEP2 (I) H11 107 79 I/O/Z PU GPIO or Capture Input #2
GPIOA10 CAP3_QEPI1 (I) H12 109 80 I/O/Z PU GPIO or Capture Input #3
GPIOA11 TDIRA (I) F14 116 85 I/O/Z PU GPIO or Timer Direction
GPIOA12 TCLKINA (I) F13 117 86 I/O/Z PU GPIO or Timer Clock Input
GPIOA13 C1TRIP (I) E13 122 89 I/O/Z PU GPIO or Compare 1 Output Trip
GPIOA14 C2TRIP (I) E11 123 90 I/O/Z PU GPIO or Compare 2 Output Trip
GPIOA15 C3TRIP (I) F10 124 91 I/O/Z PU GPIO or Compare 3 Output Trip
GPIOB0 PWM7 (O) N2 45 33 I/O/Z PU GPIO or PWM Output Pin #7
GPIOB1 PWM8 (O) P2 46 34 I/O/Z PU GPIO or PWM Output Pin #8
GPIOB2 PWM9 (O) N3 47 35 I/O/Z PU GPIO or PWM Output Pin #9
GPIOB3 PWM10 (O) P3 48 36 I/O/Z PU GPIO or PWM Output Pin #10
GPIOB4 PWM11 (O) L4 49 37 I/O/Z PU GPIO or PWM Output Pin #11
GPIOB5 PWM12 (O) M4 50 38 I/O/Z PU GPIO or PWM Output Pin #12
GPIOB6 T3PWM_T3CMP (I) K5 53 40 I/O/Z PU GPIO or Timer 3 Output
GPIOB7 T4PWM_T4CMP (I) N5 55 41 I/O/Z PU GPIO or Timer 4 Output
GPIOB8 CAP4_QEP3 (I) M5 57 43 I/O/Z PU GPIO or Capture Input #4
GPIOB9 CAP5_QEP4 (I) M6 59 44 I/O/Z PU GPIO or Capture Input #5
GPIOB10 CAP6_QEPI2 (I) P6 60 45 I/O/Z PU GPIO or Capture Input #6
GPIOB11 TDIRB (I) L8 71 54 I/O/Z PU GPIO or Timer Direction
GPIOB12 TCLKINB (I) K8 72 55 I/O/Z PU GPIO or Timer Clock Input
GPIOB13 C4TRIP (I) N6 61 46 I/O/Z PU GPIO or Compare 4 Output Trip
GPIOB14 C5TRIP (I) L6 62 47 I/O/Z PU GPIO or Compare 5 Output Trip
GPIOB15 C6TRIP (I) K7 63 48 I/O/Z PU GPIO or Compare 6 Output Trip
179-PIN
GHH
AND
ZHH
176-PIN
PGF
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIOB OR EVB SIGNALS
128-PIN
PBK
I/O/Z‡PU/PD
§
DESCRIPTION
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
24
June 2004SPRS257
ADVANCE INFORMATION
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
GPIO PERIPHERAL SIGNAL
GPIOD0 T1CTRIP_PDPINTA (I) H14 110 81 I/O/Z PU Timer 1 Compare Output Trip
GPIOD1 T2CTRIP/EVASOC (I) G10 115 84 I/O/Z PU
GPIOD5 T3CTRIP_PDPINTB (I) P10 79 60 I/O/Z PU Timer 3 Compare Output Trip
GPIOD6 T4CTRIP/EVBSOC (I) P11 83 61 I/O/Z PU
GPIOE0 XINT1_XBIO (I) D9 149 106 I/O/Z − GPIO or XINT1 or XBIO input
GPIOE1 XINT2_ADCSOC (I) D8 151 108 I/O/Z − GPIO or XINT2 or ADC start of conversion
GPIOE2 XNMI_XINT13 (I) E8 150 107 I/O/Z PU GPIO or XNMI or XINT13
GPIOF0 SPISIMOA (O) M1 40 31 I/O/Z − GPIO or SPI slave in, master out
GPIOF1 SPISOMIA (I) N1 41 32 I/O/Z − GPIO or SPI slave out, master in
GPIOF2 SPICLKA (I/O) K2 34 27 I/O/Z − GPIO or SPI clock
GPIOF3 SPISTEA (I/O) K4 35 28 I/O/Z − GPIO or SPI slave transmit enable
GPIOF4 SCITXDA (O) C7 155 111 I/O/Z PU
GPIOF5 SCIRXDA (I) A7 157 11 2 I/O/Z PU
GPIOF6 CANTXA (O) N12 87 64 I/O/Z PU GPIO or eCAN transmit data
GPIOF7 CANRXA (I) N13 89 65 I/O/Z PU GPIO or eCAN receive data
GPIOF8 MCLKXA (I/O) J1 28 23 I/O/Z PU GPIO or transmit clock
GPIOF9 MCLKRA (I/O) H2 25 21 I/O/Z PU GPIO or receive clock
GPIOF10 MFSXA (I/O) H4 26 22 I/O/Z PU GPIO or transmit frame synch
GPIOF11 MFSRA (I/O) J2 29 24 I/O/Z PU GPIO or receive frame synch
GPIOF12 MDXA (O) G1 22 19 I/O/Z − GPIO or transmitted serial data
GPIOF13 MDRA (I) G2 20 18 I/O/Z PU GPIO or received serial data
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
AND
ZHH
176-PIN
PGF
GPIOD OR EVA SIGNALS
GPIOD OR EVB SIGNALS
GPIOE OR INTERRUPT SIGNALS
GPIOF OR SPI SIGNALS
GPIOF OR SCI-A SIGNALS
GPIOF OR CAN SIGNALS
GPIOF OR McBSP SIGNALS
128-PIN
PBK
I/O/Z‡PU/PD
§
Timer 2 Compare Output Trip or External
ADC Start-of-Conversion EV-A
Timer 4 Compare Output Trip or External
ADC Start-of-Conversion EV-B
GPIO or SCI asynchronous serial port TX
data
GPIO or SCI asynchronous serial port RX
data
DESCRIPTION
June 2004 SPRS257
25
Introduction
ADVANCE INFORMATION
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
GPIO PERIPHERAL SIGNAL
GPIOF14 XF_XPLLDIS (O) A11 140 101 I/O/Z PU
GPIOG4 SCITXDB (O) P14 90 66 I/O/Z −
GPIOG5 SCIRXDB (I) M13 91 67 I/O/Z −
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
AND
ZHH
176-PIN
PGF
GPIOF OR XF CPU OUTPUT SIGNAL
GPIOG OR SCI-B SIGNALS
128-PIN
PBK
I/O/Z‡PU/PD
§
This pin has three functions:
1. XF − General-purpose output pin.
2. XPLLDIS − This pin will be sampled
during reset to check if the PLL needs
to be disabled. The PLL will be
disabled if this pin is sensed low. HALT
and STANDBY modes cannot be used
when the PLL is disabled.
3. GPIO − GPIO function
GPIO or SCI asynchronous serial port
transmit data
GPIO or SCI asynchronous serial port
receive data
DESCRIPTION
NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with
the 3.3-V supply.
26
June 2004SPRS257
3 Functional Overview
ADVANCE INFORMATION
Functional Overview
Memory Bus
GPIO Pins
TINT0
TINT1
G
P
I
O
M
U
X
XINT13
XNMI
CPU-Timer 0
CPU-Timer 1
CPU-Timer 2
TINT2
PIE
(96 interrupts)
External Interrupt
Control
(XINT1/2/13, XNMI)
SCIA/SCIB
SPI FIFO
McBSP
eCAN
EVA/EVB
†
FIFO
FIFO
INT14
INT[12:1]
INT13
NMI
C28x CPU
Real-Time JTAG
External
Interface
‡
(XINTF)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
L0 SARAM
4K x 16
L1 SARAM
4K x 16
L2 SARAM
1K X 16
Control
Address(19)
Data(16)
XRS
X1/XCLKIN
X2
XF_XPLLDIS
†
45 of the possible 96 interrupts are used on the devices.
‡
XINTF is available on the R2812 devices only.
16 Channels
12-Bit ADC
System Control
(Oscillator and PLL
+
Peripheral Clocking
+
Low-Power
Modes
+
WatchDog)
Peripheral Bus
RS
CLKIN
Memory Bus
Figure 3−1. Functional Block Diagram
L3 SARAM
1K X 16
H0 SARAM
8K × 16
Boot ROM
4K × 16
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Functional Overview
ADVANCE INFORMATION
3.1 Memory Map
Block
Start Address
On-Chip Memory External Memory XINTF
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
Low 64K
(24x/240x Equivalent Data Space)
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x00 A400
0x00 A800
Data Space Prog Space
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
Peripheral Frame 0
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Peripheral Frame 1
(4K × 16, Protected)
Peripheral Frame 2
(4K × 16, Protected)
L0 SARAM (4K × 16)
L1 SARAM (4K × 16)
L2 SARAM (1K × 16)
L3 SARAM (1K × 16)
Reserved
Reserved
Data Space Prog Space
Reserved
XINTF Zone 0 (8K × 16, XZCS0AND1
XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)
Reserved
XINTF Zone 2 (0.5M × 16, XZCS2
XINTF Zone 6 (0.5M × 16, XZCS6AND7)
)
)
0x00 2000
0x00 4000
0x08 0000
0x10 0000
0x18 0000
NOTES: A. Memory blocks are not to scale.
High 64K
Program Space)
(24x/240x Equivalent
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
H. The passwords are set to all ones.
0x3F7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
Reserved
Reserved
128-bit Password (see Note H)
H0 SARAM (8K × 16)
Reserved
Boot ROM (4K × 16)
(Enabled if MP/MC
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC
= 0)
= 0, ENPIE = 0)
XINTF Zone 7 (16K × 16, XZCS6AND7
(Enabled if MP/MC
XINTF Vector - RAM (32 × 32)
(Enabled if VMAP = 1, MP/MC
Figure 3−2. R2812 Memory Map (See Notes A through H)
0x3F C000
)
= 1)
= 1, ENPIE = 0)
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June 2004SPRS257
Functional Overview
ADVANCE INFORMATION
Block
Start Address
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
Low 64K
(24x/240x Equivalent Data Space)
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x00 A400
0x00 A800
On-Chip Memory
Data Space Prog Space
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
Peripheral Frame 0
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Peripheral Frame 1
(4K × 16, Protected)
Peripheral Frame 2
(4K × 16, Protected)
L0 SARAM (4K × 16,)
L1 SARAM (4K × 16)
L2 SARAM (1K × 16)
L3 SARAM (1K × 16)
Reserved
Reserved
High 64K
Program Space)
(24x/240x Equivalent
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. The passwords are set to all ones.
Figure 3−3. R2811 Memory Map (See Notes A through F)
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
Reserved
128-bit Password (see Note F)
H0 SARAM (8K × 16)
Reserved
Boot ROM (4K × 16)
(Enabled if MP/MC
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC
= 0)
= 0, ENPIE = 0)
June 2004 SPRS257
29
Functional Overview
ADVANCE INFORMATION
The low 64K of the memory-address range maps into the data space of the 240x. The “High 64K” of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will only
execute from the “High 64K” memory area. Hence, the top 32K of H0 SARAM block can be used to run
24x/240x-compatible code (if MP/MC
(if MP/MC
The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones
share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample
or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.
The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select
(XZCS0AND1
a single chip select (XZCS6AND7
for details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks
to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory
locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain
peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports
a block protection mode where a region of memory can be protected so as to make sure that operations occur
as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by
default, it will protect the selected zones.
mode is low) or, on the 2812, code can be executed from XINTF Zone 7
mode is high).
NOTE:
); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into
). See Section 3.5, “External Interface, XINTF (2812 only)”,
On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the
user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC
is stored in an MP/MC
hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by
XMP/MC
I/O space is not supported on the 2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 3−1.
.
mode bit in the XINTCNF2 register. The user can change this mode in software and
pin is pulled high. This signal selects
signal on reset
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June 2004SPRS257
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