TEXAS INSTRUMENTS TMS320LF2407, TMS320LF2406, TMS320LF2402 Technical data

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ADVANCE

INFORMATION

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

D High-Performance Static CMOS Technology

– 33-ns Instruction Cycle Time (30 MHz)
– 30 MIPS Performance
– Low-Power 3.3-V Design

D Based on T320C2xx DSP CPU Core

– Code-Compatible With ’F243/’F241/’C242
– Instruction Set and Module Compatible

With ’F240/’C240

– Source-Code-Compatible With

TMS320C1x/2x

D Flash (LF) and ROM (LC) Device Options

– ’LF240x†: ’LF2407, ’LF2406, ’LF2402
– ’LC240x†: ’LC2406, ’LC2404, ’LC2402

D On-Chip Memory

– Up to 32K Words x 16 Bits of Flash

EEPROM (4 Sectors) or ROM

– Up to 2.5K Words x 16 Bits of

Data/Program RAM
– 544 Words of Dual-Access (DARAM)
– 2K Words of Single-Access (SARAM)

D Boot ROM (’LF240x Devices)

– SCI/SPI Flash Bootloader

D Two Event-Manager (EV) Modules (A and B)

EVA and EVB Each Include:
– Two 16-Bit General-Purpose Timers
– Eight 16-Bit Pulse-Width Modulation

(PWM) Channels Which Enable:
– Three-Phase Inverter Control
– Centered or Edge Alignment of PWM

Channels

– Emergency PWM Channel Shutdown

With External PDPINT

– Programmable Deadband Prevents

Shoot-Through Faults

– Three Capture Units For Time-Stamping

of External Events

– On-Chip Position Encoder Interface

Circuitry

– Synchronized Analog-to-Digital

Conversion

– Suitable for AC Induction, BLDC,

Switched Reluctance, and Stepper Motor
Control

– Applicable for Multiple Motor and/or

Converter Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Pin

D External Memory Interface (’LF2407)

– 192K Words x 16 Bits of Total Memory,

64K Program, 64K Data, 64K I/O

D Watchdog (WD) Timer Module
D 10-Bit Analog-to-Digital Converter (ADC)

– 8 or 16 Multiplexed Input Channels
– 500 ns Minimum Conversion Time
– Selectable Twin 8-Input Sequencers

Triggered by Two Event Managers

D Controller Area Network (CAN) 2.0B Module
D Serial Communications Interface (SCI)
D 16-Bit Serial Peripheral Interface (SPI)

Module (Except ’x2402)

D Phase-Locked-Loop (PLL)-Based Clock

Generation

D Up to 40 Individually Programmable,

Multiplexed General-Purpose Input/Output
(GPIO) Pins

D Five External Interrupts (Power Drive

Protection, Reset, and Two Maskable
Interrupts)

D Power Management:

– Three Power-Down Modes
– Ability to Power-Down Each Peripheral

Independently

D Real-Time JTAG-Compliant Scan-Based

Emulation, IEEE Standard 1149.1

‡

(JTAG)

D Development Tools Include:

– Texas Instruments (TI) ANSI

C Compiler, Assembler/Linker, and
Code Composer Debugger

– Evaluation Modules
– Scan-Based Self-Emulation (XDS510)
– Numerous Third-Party Digital Motor

Control Support

D Package Options

– 144-Pin Thin Quad Flatpack (TQFP) PGE

(’LF2407)

– 100-Pin TQFP PZ (’LC2404, ’LC2406,

’LF2406)

– 64-Pin PQFP PG (’LC2402 and ’LF2402)

D Extended Temperature Options (A and S)

– A: – 40°C to 85°C
– S: – 40°C to 125°C

TI, Code Composer, and XDS510 are trademarks of Texas Instruments Incorporated.
†

Throughout this data sheet, ’240x is used as a generic name for the ’LF240x/’LC240x family of devices.

‡

IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port

ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Copyright  1999, Texas Instruments Incorporated

1

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

Table of Contents

description

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320x240x Device Summary 3. . . . . . . . . . . . . . . . . . .

Functional Block Diagram of the ’2407 DSP Controller 4

Pin Functions 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Maps 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Memory Map of the ’LF240x/’LC240x 21. . . .

Device Reset and Interrupts 22. . . . . . . . . . . . . . . . . . . . .

TMS320x240x Instruction Set 26. . . . . . . . . . . . . . . . . . . .

Functional Block Diagram

Peripherals 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Event Manager Modules (EV A, EVB) 36. . . . . . . . . . . .

Enhanced Analog-to-Digital Converter

(ADC) Module 40. . . . . . . . . . . . . . . . . . . . . . . . . . . .

The TMS320LF240x and TMS320LC240x devices, new members of the ’24x family of digital signal processor
(DSP) controllers, are part of the C2000 platform of fixed-point DSPs. The ’240x devices offer the enhanced
TMS320 architectural design of the ’C2xx core CPU for low-cost, low-power, high-performance processing
capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have
been integrated to provide a true single chip DSP controller. While code-compatible with the existing ’24x DSP
controller devices, the ’240x offers increased processing performance (30 MIPS) and a higher level of peripheral
integration. See the TMS320x240x device summary section for device-specific features.

The ’240x family offers an array of memory sizes and different peripherals tailored to meet the specific
price/performance points required by various applications. Flash-based devices of up to 32K words offer a
reprogrammable solution useful for:

– Applications requiring field programmability upgrades
– Development and initial prototyping of applications that migrate to ROM-based devices

Flash devices and corresponding ROM devices are fully pin-to-pin compatible. Note that flash-based devices
contain a 256-word boot ROM to facilitate in-circuit programming.

All ’240x devices offer at least one event manager module which has been optimized for digital motor control
and power conversion applications. Capabilities of this module include centered- and/or edge-aligned PWM
generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital
conversion. Devices with dual event managers enable multiple motor and/or converter control with a single
’240x DSP controller.

of the ’240x DSP CPU 27. . .

Controller Area Network (CAN) Module 41. . . . . . . . . .

Serial Communications Interface (SCI) Module 44. . . .

Serial Peripheral Interface (SPI) Module 46. . . . . . . . . .

PLL-Based Clock Module 48. . . . . . . . . . . . . . . . . . . . . .

Digital I/O and Shared Pin Functions 51. . . . . . . . . . . . .

External Memory Interface (’LF2407) 54. . . . . . . . . . . .

Watchdog (WD) Timer Module 55. . . . . . . . . . . . . . . . . .

Development Support 58. . . . . . . . . . . . . . . . . . . . . . . . . . .

Documentation Support 61. . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 62. . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 62. . . . . . . . . . . . .

Peripheral Register Description 90. . . . . . . . . . . . . . . . . . .

Mechanical Data 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

The high performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and
offers up to 16 channels of analog input. The auto sequencing capability of the ADC allows a maximum of
16 conversions to take place in a single conversion session without any CPU overhead.

A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication
to other devices in the system. For systems requiring additional communication interfaces; the ’2407, ’2406,
and ’2404 offer a 16-bit synchronous serial peripheral interface (SPI). The ’2407 and ’2406 offer a controller area
network (CAN) communications module that meets 2.0B specifications. To maximize device flexibility,
functional pins are also configurable as general purpose inputs/outputs (GPIO).

To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices.
This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite
of code generation tools from C compilers to the industry-standard Code Composer debugger supports this
family. Numerous third party developers not only offer device-level development tools, but also system-level
design and development support.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADVANCE

INFORMATION

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

TMS320x240x device summary

Note that throughout this data sheet, ’240x is used as a generic name for the ’LF240x/’LC240x family of devices.

Table 1. Hardware Features of ’240x Devices

FEATURE ’LF2407

’C2xx DSP Core Yes Yes Yes Yes Yes Yes
Instruction Cycle 33 ns 33 ns 33 ns 33 ns 33 ns 33 ns
MIPS (30 MHz) 30 MIPS 30 MIPS 30 MIPS 30 MIPS 30 MIPS 30 MIPS

RAM (16-bit word)
On-chip Flash (16-bit word)

(4 sectors: 4K, 12K, 12K, 4K)
On-chip ROM (16-bit word) — — — 32K 16K 4K
Boot ROM (16-bit word) 256 256 256 — — —
External Memory Interface Yes — — — — —
Event Managers A and B

(EVA and EVB)

S General-Purpose (GP) Timers 4 4 2 4 4 2
S Compare (CMP)/PWM 10/16 10/16 5/8 10/16 10/16 5/8
S Capture (CAP)/QEP 6/4 6/4 3/2 6/4 6/4 3/2

Watchdog Timer Yes Yes Yes Yes Yes Yes
10-Bit ADC Yes Yes Yes Yes Yes Yes

S Channels 16 16 8 16 16 8
S Conversion Time (minimum) 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns

SPI Yes Yes — Yes Yes —
SCI Yes Yes Yes Yes Yes Yes
CAN Yes Yes — Yes — —
Digital I/O Pins (Shared) 41 41 21 41 41 21
External Interrupts 5 5 3 5 5 3
Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Packaging 144 TQFP 100 TQFP 64 PQFP 100 TQFP 100 TQFP 64 PQFP

†

’LF2407, the full-featured device of the ’LF240x family of DSP controllers, is useful for emulation and code development.

DARAM 544 544 544 544 544 544
SARAM 2K 2K — 2K 1K —

EVA, EVB EVA, EVB EVA EVA, EVB EVA, EVB EVA

†

’LF2406 ’LF2402 ’LC2406 ’LC2404 ’LC2402

32K 32K 8K — — —

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

3

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

functional block diagram of the ’2407 DSP controller

XINT1/IOPA2

XINT2/ADCSOC/IOPD0

CLKOUT/IOPE0

CAP1/QEP1/IOPA3
CAP2/QEP2/IOPA4

T1PWM/T1CMP/IOPB4
T2PWM/T2CMP/IOPB5

TCLKINA/IOPB7

RS

TMS2

BIO/IOPC1

MP/MC

BOOT_EN/XF

VDD (3.3 V)

V

TP1
TP2

V

(5V)

CCP

A0–A15

D0–D15

PS, DS, IS

R/W

RD

READY

STRB

WE

ENA_144

VIS_OE

W/R / IOPC0

PDPINTA

CAP3/IOPA5
PWM1/IOPA6
PWM2/IOPA7
PWM3/IOPB0
PWM4/IOPB1
PWM5/IOPB2
PWM6/IOPB3

TDIRA/IOPB6

Indicates optional modules
The memory size and peripheral selection of these modules change for different ’240x devices. See
Table 1 for device-specific details.

’C2xx

DSP
Core

SS

SARAM (2K Words)

(32K Words:

4K/12K/12K/4K)

External Memory Interface

Event Manager A

D 3 × Capture Input
D 6 × Compare/PWM

Output
D 2 × GP Timers/PWM

DARAM (B0)

256 Words

DARAM (B1)

256 Words

DARAM (B2)

32 Words

Flash/ROM

PLL Clock

10-Bit ADC

(With Twin

Autosequencer)

SCI

SPI

CAN

WD

Digital I/O

(Shared With Other Pins)

JTAG Port

Event Manager B

D 3 × Capture Input
D 6 × Compare/PWM

Output
D 2 × GP Timers/PWM

PLLF
PLLV

CCA

PLLF2
XTAL1/CLKIN
XTAL2
ADCIN00–ADCIN07
ADCIN08–ADCIN15

V

CCA

V

SSA

V

REFHI

V

REFLO
XINT2/ADCSOC/IOPD0
SCITXD/IOPA0
SCIRXD/IOPA1
SPISIMO/IOPC2
SPISOMI/IOPC3
SPICLK/IOPC4
SPISTE/IOPC5

CANTX/IOPC6
CANRX/IOPC7

V

(5V)

CCP
Port A(0–7) IOPA[0:7]

Port B(0–7) IOPB[0:7]
Port C(0–7) IOPC[0:7]

Port D(0) IOPD[0]
Port E(0–7) IOPE[0:7]
Port F(0–6) IOPF[0:6]

TRST
TDO
TDI

TMS
TCK

EMU0
EMU1

PDPINTB
CAP4/QEP3/IOPE7
CAP5/QEP4/IOPF0
CAP6/IOPF1
PWM7/IOPE1
PWM8/IOPE2
PWM9/IOPE3
PWM10/IOPE4
PWM11/IOPE5
PWM12/IOPE6
T3PWM/T3CMP/IOPF2
T4PWM/T4CMP/IOPF3
TDIRB/IOPF4
TCLKINB/IOPF5

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

TDIRB/

T4PWM/T4CMP/

T3PWM/T3CMP/

TDIRA/

T1PWM/T1CMP/

T2PWM/T2CMP/

W/R

XINT2/ADCSOC/

XINT1/

SCITXD/
SCIRXD/

SPISIMO/

SPISOMI/

SPISTE/

SPICLK/

TRST

IOPF4

V

SSO

V

DDO

IOPF3

PDPINTA

IOPF2

PLLF2

PLLF

PLLV

PLLV

CCA

CCA

IOPB6

D10

IOPB4

D11

IOPB5

/IOPC0

D12

IOPD0

D13

IOPA2

D14

IOPA0
IOPA1

D15
V
V

IOPC2

A15

IOPC3
IOPC5

A14

IOPC4

TMS2

PGE PACKAGE

†

(TOP VIEW)

‡

IOPF5

SS

SSO

DDO

V

PDPINTB

D5

138

A12

D4

137

136

A11

IOPB2

PWM5/

TCK

135

IOPE5

PWM11/

D3

134RS133

A10

IOPB1

PWM4/

TDI

TDO

TMS

D6

V

144

143

142

141

140

139

1
2
3
4
5

D7

6
7
8
9

D8

10
11
12
13

D9

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

SS

29

DD

30
31
32
33
34
35
36

373839404142434445464748495051525354555657585960616263646566676869

A13

SSO

DDO

V

V

IOPE6

IOPB3

IOPB7

PWM6/

PWM12/

TCLKINA/

DD

D1

D2

V

IOPF6

132

131

130

129

TMS320LF2407

A9

SS

DD

V

V

IOPB0

PWM3/

V

128

A8

D0

TCLKINB/

127

126

IOPE4

IOPA7

PWM2/

PWM10/

SSO

V

125

IOPA6

PWM1/

XTAL1/CLKIN

XTAL2

124

123

A7

CCP

V

BOOT_EN/XF

ENA_144

122

121

TP1

IOPE3

PWM9/

IOPC1

READY

BIO/

119

120

A6

IOPE2

PWM8/

SSA

MP/MC

V

118

117

A5

TP2

CCA

V

116

IOPE1

PWM7/

REFHI

V

115

SSO

V

REFLO

V

114

DDO

V

ADCIN00

ADCIN08

113

112

A4

IOPF1

CAP6/

ADCIN01

ADCIN09

111

110

707172

A3

IOPC7

CANRX/

ADCIN10

109

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

IOPC6

CANTX/

ADCIN11
ADCIN02
ADCIN12
ADCIN03
ADCIN13
ADCIN04
ADCIN05
ADCIN14
ADCIN06
ADCIN07
ADCIN15
VIS_OE
STRB
V

DDO

V

SSO

RD
R/W
EMU1/OFF
EMU0
WE
CAP4/QEP3/
DS
V

DD

V

SS

PS
CAP1/QEP1/
IS
CAP5/QEP4/
A0
CAP2/QEP2/
A1
V

DDO

V

SSO

CAP3/

IOPA5

A2

/IOPE0

CLKOUT

IOPE7

IOPA3

IOPF0

IOPA4

†

Bold, italicized pin names

‡

BOOT_EN

is available only on flash devices.

indicate pin function after reset.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

5

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

PZ PACKAGE

(TOP VIEW)

DDO

ADCIN06

ADCIN07

ADCIN15

SSO

V

V

ADCIN10
ADCIN01
ADCIN09
ADCIN00

ADCIN08

BIO

BOOT_EN

XTAL1/CLKIN

TCLKINB/

PDPINTB

V

REFLO

V

REFHI

V

V

/IOPC1

/XF

XTAL2

IOPF5

V

IOPF6

TCK

V

V

TDO
TMS

CCA

SSA

V

RS

TDI

SSO

DDO

ADCIN11

ADCIN02

ADCIN12

ADCIN03

ADCIN13

ADCIN04

ADCIN05

ADCIN14

76
77
78
79
80
81
82
83
84
85

§

86
87
88
89
90

SS

DD

91
92
93
94
95
96
97
98
99

TMS320LC2404
TMS320LC2406
TMS320LF2406

†

IOPE7

OFF

DD

SS

EMU1/

EMU0

CAP4/QEP3/VCAP1/QEP1/

V

IOPA4

IOPF0

IOPA3

CAP5/QEP4/

CAP2/QEP2/VCAP3/

DDO

V

SSO

/IOPE0

IOPA5

CLKOUT

51525354555657585960616263646566676869707172737475

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26100

25242322212019181716151413121110987654321

CANTX/
CANRX/
CAP6/

IOPF1

V

DDO

V

SSO

PWM7/
TP2
PWM8/
TP1
PWM9/
V

CCP

PWM1/
PWM10/
PWM2/
PWM3/
V

DD

V

SS

PWM4/
PWM11/
PWM5/
V

DDO

V

SSO

PWM6/
PWM12/
TCLKINA/

IOPC6

IOPC7

IOPE1

IOPE2

IOPE3

IOPA6

IOPE4
IOPA7
IOPB0

IOPB1

IOPE5
IOPB2

IOPB3

IOPE6

IOPB7

‡

‡

†

Bold, italicized pin names

‡

CANTX and CANRX are not available on ’LC2404 devices.

§

BOOT_EN

indicate pin function after reset.

is available only on flash devices.

TRST

SSOVSSO

V

IOPF4

IOPF4

TDIRB/

TDIRB/

DDO

IOPF2

IOPF3

V

PDPINTA

T3PWM/T3CMP/

T4PWM/T4CMP/

PLLF

PLLF2

CCA

IOPB4

IOPB6

PLLV

TDIRA/

T1PWM/T1CMP/

IOPA0

IOPA2

IOPB5

IOPC0

IOPD0

XINT1/

SCITXD/

T2PWM/T2CMP/

XINT2/ADCSOC/

SS

DD

V

V

IOPA1

SCIRXD/

IOPC3

IOPC2

IOPC5

SPISTE/

SPISIMO/

SPISOMI/

TMS2

IOPC4

SPICLK/

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

V

DDO

PWM5
PWM4

V

SS

V

DD

PWM3
PWM2

PWM1

V

CCP

TP1
TP2

IOPC7
IOPC6

52
53
54

55
56
57

58
59
60
61
62

63
64

SSO

V

IOPB7

IOPB3

TCLKINA/

PWM6/

TMS2

IOPC4

PG PACKAGE

(TOP VIEW)

IOPA1

IOPA0

SCIRXD/

SCITXD/

IOPC2

IOPC3

TMS320LC2402
TMS320LF2402

†

IOPD0

IOPB4

IOPB5

CCA

T1PWM/T1CMP/

T2PWM/T2CMP/

XINT2/ADCSOC/

PLLV

PLLF

PDPINTA

PLLF2

DDO

V

SSO

V

3351 343550 49 48 47 46 45 44 43 42 41 40 3938 37 36

191 2 3 4 5 6 7 8 9101112131415161718

TRST

32
31

30
29
28
27
26
25
24
23
22
21
20

TMS
TDO

TDI
TCK
RS
V

DD

V

SS

XTAL2
XTAL1/CLKIN
BOOT_EN
V

SSA

V

CCA

V

REFHI

/XF

‡

†

Bold, italicized pin names

‡

BOOT_EN

is available only on flash devices.

SS

VDDV

IOPA3

IOPA4

IOPA5

/IOPE0

CAP3/

CLKOUT

CAP1/QEP1/

CAP2/QEP2/

indicate pin function after reset.

OFF

EMU0

EMU1/

SSO

V

DDO

V

ADCIN07

ADCIN04

ADCIN05

ADCIN06

ADCIN01

ADCIN02

ADCIN03

REFLO

V

ADCIN00

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7

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

pin functions

The TMS320LF2407 device is the superset of all the ’240x devices. All signals are available on the ’2407 device.
Table 2 lists the key signals available in the ’240x family of devices.

CAP1/QEP1/

CAP2/QEP2/
CAP3/

PWM1/
PWM2/
PWM3/
PWM4/
PWM5/
PWM6/
T1PWM/T1CMP/
T2PWM/T2CMP/

TDIRA/

TCLKINA/

CAP4/QEP3/

CAP5/QEP4/
CAP6/

PWM7/
PWM8/
PWM9/
PWM10/
PWM11/
PWM12/
T3PWM/T3CMP/
T4PWM/T4CMP/

TDIRB/

TCLKINB/

†

Bold, italicized pin names

‡

GPIO – General-purpose input/output pin. All GPIOs come up as input after reset.

§

Pin changes with respect to SPRS094B data sheet.
LEGEND: ↑ – Internal pullup ↓ – Internal pulldown

Table 2. ’LF240x and ’LC240x Pin List and Package Options

PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION

EVENT MANAGER A (EVA)

Capture input #1/quadrature encoder pulse input #1 (EVA) or
GPIO (↑)

Capture input #2/quadrature encoder pulse input #2 (EVA) or
GPIO (↑)

§

Compare/PWM output pin #1 (EVA) or GPIO (↑)

§

Compare/PWM output pin #2 (EVA) or GPIO (↑)

§

Compare/PWM output pin #3 (EVA) or GPIO (↑)

§

Compare/PWM output pin #4 (EVA) or GPIO (↑)

§

Compare/PWM output pin #5 (EVA) or GPIO (↑)

Counting direction for general-purpose (GP) timer (EVA) or
GPIO. If TDIRA=1, upward counting is selected. If TDIRA=0,
downward counting is selected. (↑)

External clock input for GP timer (EVA) or GPIO. Note that timer
can also use the internal device clock. (↑)

Capture input #4/quadrature encoder pulse input #3 (EVB) or
GPIO (↑)

Capture input #5/quadrature encoder pulse input #4 (EVB) or
GPIO (↑)

Counting direction for general-purpose (GP) timer (EVB) or
GPIO. If TDIRB=1, upward counting is selected. If TDIRB=0,
downward counting is selected. (↑)

External clock input for GP timer (EVB) or GPIO. Note that timer
can also use the internal device clock. (↑)

IOPA5

IOPA6
IOPA7
IOPB0
IOPB1
IOPB2
IOPB3

IOPB6

IOPB7

IOPF1

IOPE1
IOPE2
IOPE3

IOPE4
IOPE5
IOPE6

IOPF4

IOPF5

IOPA3

IOPA4

IOPB4
IOPB5

IOPE7

IOPF0

IOPF2
IOPF3

83 57 57 4

79 55 55 3
75 52 52 2 Capture input #3 (EVA) or GPIO (↑)

56 39 39 59
54 37 37 58
52 36 36 57
47 33 33 54
44 31 31 53
40 28 28 50 Compare/PWM output pin #6 (EVA) or GPIO (↑)
16 12 12 40 Timer 1 compare output (EVA) or GPIO (↑)
18 13 13 41 Timer 2 compare output (EVA) or GPIO (↑)

14 11 11

37 26 26 49

EVENT MANAGER B (EVB)

88 60 60

81 56 56
69 48 48 Capture input #6 (EVB) or GPIO (↑)

65 45 45 Compare/PWM output pin #7 (EVB) or GPIO (↑)
62 43 43 Compare/PWM output pin #8 (EVB) or GPIO (↑)
59 41 41 Compare/PWM output pin #9 (EVB) or GPIO (↑)
55 38 38 Compare/PWM output pin #10 (EVB) or GPIO (↑)
46 32 32 Compare/PWM output pin #11 (EVB) or GPIO (↑)
38 27 27 Compare/PWM output pin #12 (EVB) or GPIO (↑)

8 7 7 Timer 3 compare output (EVB) or GPIO (↑)
6 5 5 Timer 4 compare output (EVB) or GPIO (↑)

2 2 2

126 89 89

indicate pin function after reset.

†‡

8

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ADVANCE

INFORMATION

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

pin functions (continued)

Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued)

PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION

ANALOG-TO-DIGITAL CONVERTER (ADC)

ADCIN00 112 79 79 18 Analog input #0 to the ADC
ADCIN01 110 77 77 17 Analog input #1 to the ADC
ADCIN02 107 74 74 16 Analog input #2 to the ADC
ADCIN03 105 72 72 15 Analog input #3 to the ADC
ADCIN04 103 70 70 14 Analog input #4 to the ADC
ADCIN05 102 69 69 13 Analog input #5 to the ADC
ADCIN06 100 67 67 12 Analog input #6 to the ADC
ADCIN07 99 66 66 11 Analog input #7 to the ADC
ADCIN08 113 80 80 Analog input #8 to the ADC
ADCIN09 111 78 78 Analog input #9 to the ADC
ADCIN10 109 76 76 Analog input #10 to the ADC
ADCIN11 108 75 75 Analog input #11 to the ADC
ADCIN12 106 73 73 Analog input #12 to the ADC
ADCIN13 104 71 71 Analog input #13 to the ADC
ADCIN14 101 68 68 Analog input #14 to the ADC
ADCIN15 98 65 65 Analog input #15 to the ADC
V

REFHI

V

REFLO

V

CCA

V

SSA

CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)

CANRX/

CANTX/

SCITXD/

SCIRXD/

SPICLK/

SPISIMO/

SPISOMI/

SPISTE/

†
‡

IOPC7

IOPC6

IOPA0

IOPA1

IOPC4

IOPC2

IOPC3

IOPC5

Bold, italicized pin names

GPIO – General-purpose input/output pin. All GPIOs come up as input after reset.
LEGEND: ↑ – Internal pullup ↓ – Internal pulldown

CANRX 70 49 – –

IOPC7 70 49 49 63

CANTX 72 50 – –

IOPC6 72 50 50 64

SPICLK 35 24 24 –
IOPC4 35 24 24 47
SPISIMO 30 21 21 –
IOPC2 30 21 21 45
SPISOMI 32 22 22 –
IOPC3 32 22 22 46
SPISTE 33 23 23 –
IOPC5 33 23 23 –

indicate pin function after reset.

115 82 82 20 ADC analog high-voltage reference input
114 81 81 19 ADC analog low-voltage reference input

116 83 83 21
117 84 84 22 Analog ground reference for ADC

25 17 17 43

26 18 18 44

Analog supply voltage for ADC (3.3 V). V
be isolated from digital supply voltage.

CAN receive data or GPIO (↑)

CAN transmit data or GPIO (↑)
SCI asynchronous serial port transmit data or

GPIO (↑)
SCI asynchronous serial port receive data or or

GPIO (↑)

SPI clock or GPIO (↑)

SPI slave in, master out or GPIO (↑)

SPI slave out, master in or GPIO (↑)

SPI slave transmit enable (optional) or GPIO (↑)

CCA

must

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9

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

pin functions (continued)

RS 133 93 93 28

PDPINTA 7 6 6 36

XINT1/

XINT2/ADCSOC/

CLKOUT

PDPINTB 137 95 95

XTAL1/CLKIN 123 87 87 24

XTAL2 124 88 88 25

PLLF 11 9 9 38 Filter input 1
PLLV
PLLF2 10 8 8 37 Filter input 2

BOOT_EN / XF

†

Bold, italicized pin names

‡

GPIO – General-purpose input/output pin. All GPIOs come up as input after reset.
LEGEND: ↑ – Internal pullup ↓ – Internal pulldown

Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued)

PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION

EXTERNAL INTERRUPTS, CLOCK

Device reset. RS causes the ’240x to terminate
execution and sets PC = 0. When RS
high level, execution begins at location zero of
program memory. RS
registers and status bits. When the watchdog timer
overflows, it initiates a system reset pulse that is
reflected on the RS

Power drive protection interrupt input. This interrupt,
when activated, puts the PWM output pins (EVA) in the
high-impedance state should motor drive/power
converter abnormalities, such as overvoltage or
overcurrent, etc., arise. PDPINTA
falling-edge-sensitive interrupt. (↑)

External user interrupt 1 or GPIO. Both XINT1 and

IOPA2

IOPD0

/IOPE0 73 51 51 1

CCA

BOOT_EN 121 86 – 23

XF 121 86 86 23

indicate pin function after reset.

23 16 16

21 15 15 42

OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS

12 10 10 39 PLL supply (3.3 V)

XINT2 are edge-sensitive. The edge polarity is
programmable. (↑)

External user interrupt 2 and ADC start of conversion
or GPIO. External “start-of-conversion” input for
ADC/GPIO. Both XINT1 and XINT2 are
edge-sensitive. The edge polarity is
programmable. (↑)

Clock output or GPIO. This pin outputs either the CPU
clock (CLKOUT) or the watchdog clock (WDCLK). The
selection is made by the CLKSRC bit (bit 14) of the
System Control and Status Register (SCSR). This pin
can be used as a GPIO if not used as a clock output
pin. (↑)

Power drive protection interrupt input. This interrupt,
when activated, puts the PWM output pins (EVB) in
the high-impedance state should motor drive/power
converter abnormalities, such as overvoltage or
overcurrent, etc., arise. PDPINT
falling-edge-sensitive interrupt. (↑)

PLL oscillator input pin. Crystal input to PLL/clock
source input to PLL. XTAL1/CLKIN is tied to one side
of a reference crystal.

Crystal output. PLL oscillator output pin. XTAL2 is tied
to one side of a reference crystal. This pin goes in the
high-impedance state when EMU1/OFF

Boot ROM enable, GPO, XF. This pin will be sampled
as input (BOOT_EN
bit) during reset and then driven as an output signal for
XF. ROM devices do not have boot ROM, hence, no
BOOT_EN modes. (↑)

is brought to a

affects (or sets to zero) various

pin. (↑)

is a

is a

is active low.

) to update SCSR2.3 (BOOT_EN

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADVANCE

INFORMATION

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

pin functions (continued)

Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued)

PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION

OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED)

Flash programming voltage pin. This is the 5-V supply used for
flash programming. Flash cannot be programmed if this pin is

V

(5V) 58 40 40 60

CCP

TP1 (Flash) 60 42 42 61
TP2 (Flash) 63 44 44 62
IOPF6 131 92 92 General-purpose I/O (↑)

BIO

/IOPC1 119 85 85

EMULATION AND TEST

EMU0 90 61 61 7

EMU1/OFF 91 62 62 8

TCK 135 94 94 29 JTAG test clock with internal pullup (↑)

TDI 139 96 96 30

TDO 142 99 99 31

TMS 144 100 100 32

TMS2 36 25 25 48

TRST 1 1 1 33

†

Bold, italicized pin names

‡

GPIO – General-purpose input/output pin. All GPIOs come up as input after reset.

§

Pin changes with respect to SPRS094B data sheet.
LEGEND: ↑ – Internal pullup ↓ – Internal pulldown

indicate pin function after reset.

§
held at 0 V . Connect to 5-V supply for programming or tie it to

GND during functional mode.

§

Flash array test pin.

§

Flash array test pin

Branch control input. BIO is polled by the BCND pma,BIO
instruction. If BIO
used, it should be pulled high. This pin is configured as a branch
control input by all device resets. It can be used as a GPIO, if
not used as a branch control input. (↑)

Emulator I/O #0 with internal pullup. When TRST is driven high,
this pin is used as an interrupt to or from the emulator system
and is defined as input/output through the JTAG scan. (↑)

Emulator pin 1. Emulator pin 1 disables all outputs. When TRST
is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as an input/output through the
JTAG scan. When TRST
OFF

. EMU1/OFF, when active low, puts all output drivers in the
high-impedance state. Note that OFF
testing and emulation purposes (not for multiprocessing
applications). Therefore, for the OFF
apply:

= 0

TRST
EMU0 = 1
EMU1/OFF

JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising edge of
TCK. (↑)

JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK. (↓)

JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising edge
of TCK. (↑)

JTAG test-mode select 2 (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising edge
of TCK. Used for test and emulation only. (↑)

JTAG test reset with internal pulldown. TRST, when driven high,
gives the scan system control of the operations of the device. If
this signal is not connected or driven low, the device operates in
its functional mode, and the test reset signals are ignored. (↓)

= 0

Do not connect.

. Do not connect.

is low, a branch is executed. If BIO is not

is driven low, this pin is configured as

is used exclusively for

condition, the following

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11

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

pin functions (continued)

DS 87

IS 82

PS 84

R/W 92

W/R

RD 93

WE 89

STRB 96

READY 120

†

Bold, italicized pin names

‡

GPIO – General-purpose input/output pin. All GPIOs come up as input after reset.
LEGEND: ↑ – Internal pullup ↓ – Internal pulldown

Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued)

PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS

Data space strobe. IS, DS, and PS are always high
unless low-level asserted for access to the relevant
external memory space or I/O. They are placed in the
high-impedance state during reset, power down, and
when EMU1/OFF

I/O space strobe. IS, DS, and PS are always high
unless low-level asserted for access to the relevant
external memory space or I/O. They are placed in the
high-impedance state during reset, power down, and
when EMU1/OFF

Program space strobe. IS, DS, and PS are always
high unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state during reset,
power down, and when EMU1/OFF

Read/write qualifier signal. R/W indicates transfer
direction during communication to an external device.
It is normally in read mode (high), unless low level is
asserted for performing a write operation. It is placed
in the high-impedance state when EMU1/OFF
active low and during power down.

Write/Read qualifier or GPIO. This is an inverted R/W
signal useful for zero-wait-state memory interface. It
is normally low, unless a memory write operation is
performed. See T able 13, Port C section, for reset
note regarding ’LF2406 and ’LF2402. (↑)

Read enable strobe. Read-select indicates an active,
external read cycle. RD
program, data, and I/O reads. RD
high-impedance state when EMU1/OFF

Write enable strobe. The falling edge of WE indicates
that the device is driving the external data bus
(D15–D0). WE
data, and I/O writes. WE
state when EMU1/OFF

External memory access strobe. STRB is always high
unless asserted low to indicate an external bus cycle.

is active for all off-chip accesses. It is placed in

STRB
the high-impedance state during power down, and
when EMU1/OFF

READY is pulled low to add wait states for external
accesses. READY indicates that an external device is
prepared for a bus transaction to be completed. If the
device is not ready, it pulls the READY pin low. The
processor waits one cycle and checks READY again.
Note that the processor performs READY-detection if
at least one software wait state is programmed. To
meet the external READY timings, the wait-state
generator control register (WSGR) should be
programmed for at least one wait state. (↑)

is active on all external program,

/ IOPC0

W/R

IOPC0 19 14 14

indicate pin function after reset.

19

is active low.

is active low.

is active low.

is

is active on all external

goes into the

is active low.

goes in the high-impedance

is active low.

is active low.

12

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ADVANCE

INFORMATION

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

pin functions (continued)

Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued)

PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)

Microprocessor/Microcomputer mode select. If this pin is low
during reset, the device is put in microcomputer mode and
program execution begins at 0000h of internal program memory

MP/MC 118

ENA_144 122

VIS_OE 97

A0 80 Bit 0 of the 16-bit address bus
A1 78 Bit 1 of the 16-bit address bus
A2 74 Bit 2 of the 16-bit address bus
A3 71 Bit 3 of the 16-bit address bus
A4 68 Bit 4 of the 16-bit address bus
A5 64 Bit 5 of the 16-bit address bus
A6 61 Bit 6 of the 16-bit address bus
A7 57 Bit 7 of the 16-bit address bus
A8 53 Bit 8 of the 16-bit address bus
A9 51 Bit 9 of the 16-bit address bus
A10 48 Bit 10 of the 16-bit address bus
A11 45 Bit 11 of the 16-bit address bus
A12 43 Bit 12 of the 16-bit address bus
A13 39 Bit 13 of the 16-bit address bus
A14 34 Bit 14 of the 16-bit address bus
A15 31 Bit 15 of the 16-bit address bus
D0 127 Bit 0 of 16-bit data bus (↑)
D1 130 Bit 1 of 16-bit data bus (↑)
D2 132 Bit 2 of 16-bit data bus (↑)
D3 134 Bit 3 of 16-bit data bus (↑)
D4 136 Bit 4 of 16-bit data bus (↑)
D5 138 Bit 5 of 16-bit data bus (↑)
D6 143 Bit 6 of 16-bit data bus (↑)
D7 5 Bit 7 of 16-bit data bus (↑)
D8 9 Bit 8 of 16-bit data bus (↑)

†

Bold, italicized pin names

‡

GPIO – General-purpose input/output pin. All GPIOs come up as input after reset.
LEGEND: ↑ – Internal pullup ↓ – Internal pulldown

indicate pin function after reset.

(flash EEPROM). A high value during reset puts the device in
microprocessor mode and program execution begins at 0000h of
external program memory. This line sets the MP/MC
the SCSR2 register). (↓)

Active high to enable external interface signals. If pulled low, the
’2407 behaves like the ’2406/’2404—i.e., it has no external
memory and generates an illegal address if any of the three
external spaces are accessed (IS
has an internal pulldown. (↓)

Visibility output enable (active when data bus is output). This pin
is active (low) whenever the external databus is driving as an
output during visibility mode. Can be used by external decode
logic to prevent data bus contention while running in visibility
mode.

DSP CONTROLLERS

bit (bit 2 in

and DS asserted). This pin

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

13

TMS320LF2407, TMS320LF2406, TMS320LF2402

V

SSO

I/O buffer ground. Digital logic and buffer ground reference.

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

pin functions (continued)

D9 13 Bit 9 of 16-bit data bus (↑)
D10 15 Bit 10 of 16-bit data bus (↑)
D11 17 Bit 11 of 16-bit data bus (↑)
D12 20 Bit 12 of 16-bit data bus (↑)
D13 22 Bit 13 of 16-bit data bus (↑)
D14 24 Bit 14 of 16-bit data bus (↑)
D15 27 Bit 15 of 16-bit data bus (↑)

V

DD

V

DDO

V

SS

V

SSO

†

Bold, italicized pin names

‡

GPIO – General-purpose input/output pin. All GPIOs come up as input after reset.

§

Pin changes with respect to SPRS094B data sheet.
LEGEND: ↑ – Internal pullup ↓ – Internal pulldown

Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued)

PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)

POWER SUPPLY

29 20 20 6
50 35 35 27
86 59 59 56

129 91 91

4 4 4 10
42 30 30 35
67 47 47 52
77 54 54
95 64 64

141 98 98

28 19 19 5
49 34 34 26
85 58 58 55

128 90 90

3 3 3 9
41 29 29 34
66 46 46 51
76 53 53
94 63 63

125 97 97
140

indicate pin function after reset.

Core supply +3.3 V . Digital logic supply voltage.

§

§
I/O buffer supply +3.3 V. Digital logic and buffer supply voltage.

Core ground. Digital logic ground reference.

§

§
I/O buffer ground. Digital logic and buffer ground reference.

14

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memory maps – ’LF2407

ADVANCE

INFORMATION

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

Hex Program

0000

003F

0040

0FFF

1000

3FFF
4000

6FFF

7000

7FFF

8000

87FF
8800

FDFF
FE00

FEFF
FF00

On-Chip DARAM (B0)† (CNF = 1)

FFFF

Interrupt Vectors

FLASH SECTOR 0 (4K)

FLASH SECTOR 1 (12K)

FLASH SECTOR 2 (12K)

FLASH SECTOR 3 (4K)

SARAM (2K) (PON = 1)

Internal

External (PON=0)

External

Reserved† (CNF = 1)

External (CNF = 0)

External (CNF = 0)

Hex Data

0000
005F

0060
007F

0080
01FF

0200

On-Chip DARAM (B0)‡ (CNF = 0)

02FF
0300

03FF
0400

07FF
0800

0FFF
1000

6FFF

7000

7FFF

8000

FFFF

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Reserved

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

SARAM (2K) (DON = 1)

Internal

External (DON=0)

Reserved

Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, CAN, I/O, Interrupts)

External

Hex I/O

0000

§

External

FEFF

FF00

FF0E

FF0F

FF10

FFFE

FFFF

Reserved

Flash Control Mode Register

(Only for Flash Devices)

Reserved

Wait-State Generator Control

Register (On-Chip)

On-Chip Flash Memory (Sectored) – if MP/MC = 0
External Program Memory – if MP/MC

NOTE A: Boot ROM: If the boot ROM is enabled, then address 0000–00FF in the program space will be occupied by boot ROM.
†

When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved when
CNF = 1.

‡

When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.

§

Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity , addresses 0400h–04FFh are referred to as reserved.

= 1

SARAM (See Table 1 for details.)

Figure 1. TMS320LF2407 Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

15

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

memory maps (continued) – ’LF2406

Hex Program

0000

003F
0040

0FFF

1000

3FFF
4000

6FFF

7000

7FFF
8000

87FF

8800

FDFF
FE00

FEFF

FF00

FFFF

Interrupt Vectors

FLASH SECTOR 0 (4K)

FLASH SECTOR 1 (12K)

FLASH SECTOR 2 (12K)

FLASH SECTOR 3 (4K)

SARAM (2K) (PON = 1)

Internal

External (PON=0)

Reserved

Reserved† (CNF = 1)

External (CNF = 0)

On-Chip DARAM (B0)† (CNF = 1)

External (CNF = 0)

Hex Data

0000

005F

0060

007F

0080

01FF

0200

02FF

0300

03FF

0400

07FF

0800

0FFF

1000

6FFF

7000

7FFF

8000

FFFF

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Reserved

On-Chip DARAM (B0)‡ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

SARAM (2K) (DON = 1)

Internal

Reserved (DON = 0)

Reserved

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, SPI, CAN, I/O, Interrupts)

Reserved

Hex I/O

0000

§

Reserved

FEFF

FF00

FF0E

FF0F

FF10

FFFE

FFFF

Flash Control Mode Register

Reserved

(Only for Flash devices)

Reserved

Reserved

NOTE A: Boot ROM: If the boot ROM is enabled, then address 0000–00FF in the program space will be occupied by boot ROM.
†

When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved when
CNF = 1.

‡

When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.

§

Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity , addresses 0400h–04FFh are referred to as reserved.

16

On-Chip Flash Memory (Sectored)

Figure 2. TMS320LF2406 Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SARAM (See Table 1 for details.)

memory maps (continued) – ’LF2402

ADVANCE

INFORMATION

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

Hex Program

Hex Program
0000
003F

0040

0FFF

1000

1FFF

2000

7FFF

8000

87FF

8800

Interrupt Vectors

FLASH SECTOR 0 (4K)

FLASH SECTOR 1 (4K)

Reserved

Reserved

Hex Data

0000
005F

0060
007F

0080

01FF

0200

On-Chip DARAM (B0)‡ (CNF = 0)

02FF

0300

03FF

0400

07FF

0800

0FFF

1000

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Reserved

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Reserved

Reserved

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, I/O, Interrupts)

Hex I/O

0000

§

Reserved

Reserved

FEFF

Reserved

FDFF

FDFF
FE00

FE00

Reserved† (CNF = 1)

Reserved† (CNF = 1)

External (CNF = 0)

FEFF

FEFF
FF00

FF00

FFFF

FFFF

NOTE A: Boot ROM: If the boot ROM is enabled, then address 0000–00FF in the program space will be occupied by boot ROM.
†

When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved when
CNF = 1.

‡

When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.

§

Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity , addresses 0400h–04FFh are referred to as reserved.

External (CNF = 0)

On-Chip DARAM (B0)† (CNF = 1)

External (CNF = 0)

FFFF

On-Chip Flash Memory (Sectored)

FF00

FF0E

FF0F

FF10

FFFE

FFFF

Flash Control Mode Register

Reserved

(Only for Flash devices)

Reserved

Reserved

Figure 3. TMS320LF2402 Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

17

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

memory maps (continued) – ’LC2406

Hex

0000

003F
0040

7FFF
8000

87FF

8800

Program

Interrupt Vectors

On-Chip ROM

32K

SARAM (2K) (PON = 1)

Internal

Reserved (PON = 0)

Hex Data

0000
005F

0060
007F

0080

01FF

0200

02FF

0300

03FF

0400

07FF

0800

0FFF

1000

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Reserved

On-Chip DARAM (B0)‡ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

SARAM (2K) (DON = 1)

Internal

Reserved (DON = 0)

Reserved

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, SPI, CAN, I/O, Interrupts)

Hex I/O

0000

§

Reserved

FDFF
FE00

FEFF
FF00

FFFF

†

When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved when
CNF = 1.

‡

When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.

§

Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity , addresses 0400h–04FFh are referred to as reserved.

Reserved

Reserved† (CNF = 1)

External (CNF = 0)

On-Chip DARAM (B0)† (CNF = 1)

Reserved (CNF = 0)

On-Chip ROM memory

Reserved in the ’LC240x devices

Reserved

FFFF

Figure 4. TMS320LC2406 Memory Map

FEFF

FF00
FF0E

FF0F

FF10

FFFE

FFFF

SARAM (See Table 1 for details.)

Reserved

Reserved

Reserved

Reserved

18

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory maps (continued) – ’LC2404

ADVANCE

INFORMATION

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

Hex

0000

003F
0040

3FFF

4000

7FFF

8000

83FF
8400

Program

Interrupt Vectors

On-Chip ROM

16K

Reserved

SARAM (1K) (PON = 1)

Internal

Reserved (PON = 0)

Reserved

Hex Data

0000

005F

0060

007F

0080

01FF

0200

On-Chip DARAM (B0)‡ (CNF = 0)

02FF

0300

03FF

0400

07FF

0800

0BFF
0C00

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Reserved

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

SARAM (1K) (DON = 1)

Internal

Reserved (DON = 0)

Reserved

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, SPI, I/O, Interrupts)

Hex I/O

0000

§

Reserved

FEFF

Reserved

FDFF
FE00

Reserved† (CNF = 1)

FEFF

FF00

FFFF

†

When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved when
CNF = 1.

‡

When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.

§

Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity , addresses 0400h–04FFh are referred to as reserved.

External (CNF = 0)

On-Chip DARAM (B0)† (CNF = 1)

Reserved (CNF = 0)

FFFF

On-Chip ROM memory

Reserved in the ’LC240x devices

FF00

FF0E

FF0F

FF10

FFFE

FFFF

SARAM (See Table 1 for details.)

Reserved

Reserved

Reserved

Reserved

Figure 5. TMS320LC2404 Memory Map

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19

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

memory maps (continued) – ’LC2402

Hex

0000

003F

0040

0FFF

7FFF

8000

87FF

8800

Program

Interrupt Vectors

On-Chip ROM (4K)

Reserved

Reserved

Reserved

Hex Data

0000
005F

0060
007F

0080

01FF

0200

02FF

0300

03FF

0400

07FF

0800

0FFF

1000

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Reserved

On-Chip DARAM (B0)‡ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Reserved

Reserved

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, I/O, Interrupts)

Hex I/O

0000

§

Reserved

FDFF
FE00

FEFF
FF00

FFFF

†

When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved when
CNF = 1.

‡

When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.

§

Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity , addresses 0400h–04FFh are referred to as reserved.

Reserved† (CNF = 1)

External (CNF = 0)

On-Chip DARAM (B0)† (CNF = 1)

Reserved (CNF = 0)

On-Chip ROM memory

Reserved in the ’LC240x devices

Reserved

FFFF

Figure 6. TMS320LC2402 Memory Map

FEFF

FF00
FF0E

FF0F

FF10

FFFE

FFFF

Reserved

Reserved

Reserved

Reserved

20

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320LC2406, TMS320LC2404, TMS320LC2402

ADVANCE

INFORMATION

peripheral memory map of the ’LF240x/’LC240x

TMS320LF2407, TMS320LF2406, TMS320LF2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

Hex

Reserved

Interrupt-Mask Register

Global-Memory Allocation

Register (Reserved)

Interrupt Flag Register

Emulation Registers

and Reserved

0000
0003
0004

0005

0006
0007

005F

Hex
0000

005F
0060

007F
0080

01FF
0200

02FF
0300

03FF
0400

07FF
0800

6FFF
7000

73FF
7400

743F
7440

74FF
7500

753F
7540

7FFF
8000

FFFF

Illegal

Reserved

Memory-Mapped Registers

and Reserved

On-Chip DARAM B2

Reserved

On-Chip DARAM B0

On-Chip DARAM B1

Reserved

Illegal

Peripheral Frame 1 (PF1)

Peripheral Frame 2 (PF2)

Illegal

Peripheral Frame 3 (PF3)

Illegal

External

“Illegal” indicates that access to
these addresses causes a
nonmaskable interrupt (NMI).

“Reserved” indicates addresses that
are reserved for test and future expansion.

Illegal

System Configuration and

Control Registers

Watchdog Timer Registers

Illegal

SPI

SCI

Illegal

External-Interrupt Registers

Illegal

Digital I/O Control Registers

ADC Control Registers

Illegal

CAN Control Registers

Illegal

Event Manager – EVA

General-Purpose

Timer Registers

Compare, PWM, and
Deadband Registers

Capture and QEP Registers

Interrupt Mask, Vector and

Flag Registers

Reserved

Event Manager – EVB

General-Purpose

Timer Registers

Compare, PWM, and
Deadband Registers

Capture and QEP Registers

Interrupt Mask, Vector, and

Flag Registers

Reserved

7000–700F

7010–701F

7020–702F

7030–703F
7040–704F
7050–705F
7060–706F
7070–707F
7080–708F
7090–709F
70A0–70BF
70C0–70FF
7100–722F
7230–73FF

7400–7408

7411–7419
7420–7429

742C–7431

7432–743F

7500–7508

7511–7519
7520–7529

752C–7531

7532–753F

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

21

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

device reset and interrupts

The TMS320x240x software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The ’LF240x recognizes three types
of interrupt sources.

D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any

other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The ’LF240x devices have two sources of reset: an external reset pin and a watchdog timer timeout (reset).

D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two

types:
–

External interrupts

XINT2, PDPINT A, and PDPINTB. These four can be masked both by dedicated enable bits and by t he
CPU’s interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.

–

Peripheral interrupts

event manager B, SPI, SCI, WD, CAN, and ADC. They can be masked both by enable bits for each
event in each peripheral and by the CPU’s IMR, which can mask each maskable interrupt line at the DSP
core.

are generated by one of four external pins corresponding to the interrupts XINT1,

are initiated internally by these on-chip peripheral modules: event manager A,

D Software-generated interrupts for the ’LF240x devices include:

–

The INTR instruction.

operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).

–

The NMI instruction.

globally disables maskable interrupts. ’240x devices do not have the NMI hardware signal, only
software activation is provided.

–

The TRAP instruction.

TRAP instruction does
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.

–

An emulator trap.

Six core interrupts (INT1–INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the ’F24x devices. The PIE manages all the peripheral interrupts from the ’240x peripherals and are grouped to
share the six-core level interrupts. Figure 7 shows the PIE block diagram for hardware-generated interrupts.

The PIE diagram (Figure 7) and the interrupt table (Table 3) explain the grouping and interrupt vector maps.
’LF240x devices have interrupts identical to the ’F24x devices and should be completely code-compatible.
’240x devices also have peripheral interrupts identical to the ’F24x – plus additional interrupts for new
peripherals such as event manager B. Though the new interrupts share the ’24x interrupt grouping, they all have
a unique vector to differentiate among the interrupts. See Table 3 for details.

This instruction allows initialization of any ’LF240x interrupt with software. Its

This instruction forces a branch to interrupt vector location 24h. This instruction

This instruction forces the CPU to branch to interrupt vector location 22h. The

not

disable maskable interrupts (INTM is not set to 1); therefore, when the CPU

This interrupt can be generated with either an INTR instruction or a TRAP instruction.

22

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

PDPINTB

XINT2

XINT2

PDPINTA

ADCINT

XINT1

SPIINT

RXINT

TXINT

CANMBINT

CANERINT

CMP1INT
CMP2INT
CMP3INT
CMP4INT
CMP5INT
CMP6INT

T1PINT

T1CINT
T1UFINT
T1OFINT

T3PINT

T3CINT
T3UFINT
T3OFINT

T2PINT

T2CINT
T2UFINT
T2OFINT

T4PINT

T4CINT

T4UFINT

T4OFINT

CAP1INT
CAP2INT
CAP3INT

CAP4INT
CAP5INT
CAP6INT

SPIINT

RXINT

TXINT

CANMBINT

CANERINT

ADCINT

XINT1

Level 1

IRQ GEN

Level 2

IRQ GEN

Level 3

IRQ GEN

Level 4

IRQ GEN

Level 5

IRQ GEN

Level 6

IRQ GEN

PIVR & Logic

PIRQR#
PIACK#

PIE

IMR
IFR

INT1

INT2

CPU

INT3

INT4

INT5

INT6

IACK

Addr

Data

Bus

Bus

Indicates change with respect to the TMS320F243/F241/C242 data sheets.

Interrupts from external interrupt pins. The remaining interrupts are internal to the peripherals.

Figure 7. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

23

TMS320LF2407, TMS320LF2406, TMS320LF2402

Power device rotection

0002h
0004h

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

interrupt request structure

Table 3. ’LF240x/’LC240x Interrupt Source Priority and Vectors

INTERRUPT

Reset 1

Reserved 2

NMI 3
PDPINTA 4 0.0 0020h Y EVA

PDPINTB 5 2.0 0019h Y EVB
ADCINT 6

XINT1 7 0.2 0001h Y

XINT2 8
SPIINT 9
RXINT 10

TXINT 11 0.6 0007h Y SCI

CANMBINT 12 0.7 0040 Y CAN

CANERINT 13 0.8 0041 Y CAN
CMP1INT 14 0.9 0021h Y EVA Compare 1 interrupt

CMP2INT 15 0.10 0022h Y EVA Compare 2 interrupt
CMP3INT 16 0.11 0023h Y EVA Compare 3 interrupt
T1PINT 17
T1CINT 18
T1UFINT 19
T1OFINT 20 0.15 002Ah Y EVA Timer 1 overflow interrupt
CMP4INT 21 2.1 0024h Y EVB Compare 4 interrupt
CMP5INT 22 2.2 0025h Y EVB Compare 4 interrupt
CMP6INT 23 2.3 0026h Y EVB Compare 4 interrupt
T3PINT 24 2.4 002Fh Y EVB Timer 3 period interrupt
T3CINT 25 2.5 0030h Y EVB Timer 3 compare interrupt
T3UFINT 26 2.6 0031h Y EVB Timer 3 underflow interrupt
T3OFINT 27 2.7 0032h Y EVB Timer 3 overflow interrupt

†

Refer to the

TMS320F243/’F241/’C242 DSP Controllers System and Peripherals User’s Guide

NAME

CPU

OVERALL
PRIORITY

TMS320C240 DSP Controllers CPU, System, and Instruction Set Reference Guide

INTERRUPT

AND

VECTOR

ADDRESS

RSN

0000h

–

0026h

NMI

0024h

INT1

INT2

BIT
POSITION IN
PIRQRx AND

PIACKRx

0.1 0004h Y ADC

0.3 0011h Y

0.4 0005h Y SPI SPI interrupt pins in high priority

0.5 0006h Y SCI

0.12 0027h Y EVA Timer 1 period interrupt

0.13 0028h Y EVA Timer 1 compare interrupt

0.14 0029h Y EVA Timer 1 underflow interrupt

PERIPHERAL

INTERRUPT

VECTOR

(PIV)

N/A N

N/A N CPU Emulator trap

N/A N

MASK­ABLE?

(literature number SPRU276) for more information.

SOURCE

PERIPHERAL

MODULE

RS pin,

Watchdog

Nonmaskable

Interrupt

External

Interrupt Logic

External

Interrupt Logic

DESCRIPTION

Reset from pin, watchdog
timeout

Nonmaskable interrupt,
software interrupt only

Power device protection
interrupt pins

ADC interrupt in
high-priority mode

External interrupt pins in high
priority

External interrupt pins in high
priority

SCI receiver interrupt in
high-priority mode

SCI transmitter interrupt in
high-priority mode

CAN mailbox in high-priority
mode

CAN error interrupt in
high-priority mode

(literature number SPRU160) and the

24

New peripheral interrupts and vectors with respect to the ’F243/’F241 devices.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

interrupt request structure (continued)

INT3

INT4

000Ah

000Ch

†

ADVANCE

INFORMATION

Table 3.’LF240x/’LC240x Interrupt Source Priority and Vectors (Continued)

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

CPU

INTERRUPT

NAME

T2PINT 28 1.0 002Bh Y EVA Timer 2 period interrupt
T2CINT 29 1.1 002Ch Y EVA Timer 2 compare interrupt
T2UFINT 30 1.2 002Dh Y EVA Timer 2 underflow interrupt
T2OFINT 31
T4PINT 32
T4CINT 33 2.9 003Ah Y EVB Timer 4 compare interrupt
T4UFINT 34 2.10 003Bh Y EVB Timer 4 underflow interrupt
T4OFINT 35 2.11 003Ch Y EVB Timer 4 overflow interrupt
CAP1INT 36 1.4 0033h Y EVA Capture 1 interrupt
CAP2INT 37 1.5 0034h Y EVA Capture 2 interrupt
CAP3INT 38
CAP4INT 39
CAP5INT 40 2.13 0037h Y EVB Capture 5 interrupt
CAP6INT 41 2.14 0038h Y EVB Capture 6 interrupt
SPIINT 42 1.7 0005h Y SPI SPI interrupt (low priority)

RXINT 43 1.8 0006h Y SCI

TXINT 44

CANMBINT 45

CANERINT 46 1.11 0041h Y CAN

ADCINT 47 1.12 0004h Y ADC

XINT1 48

XINT2 49
Reserved 000Eh N/A Y CPU Analysis interrupt

TRAP N/A 0022h N/A N/A CPU TRAP instruction
Phantom

Interrupt
Vector

INT8–INT16 N/A 0010h–0020h N/A N/A CPU
INT20–INT31 N/A 00028h–0603Fh N/A N/A CPU

†

Refer to the

TMS320F243/’F241/’C242 DSP Controllers System and Peripherals User’s Guide

OVERALL
PRIORITY

N/A N/A 0000h N/A CPU Phantom interrupt vector

TMS320C240 DSP Controllers CPU, System, and Instruction Set Reference Guide

INTERRUPT

AND

VECTOR

ADDRESS

INT3

0006h

INT4

0008h

INT5

INT6

000Ch

BIT
POSITION IN
PIRQRx AND

PIACKRx

1.3 002Eh Y EVA Timer 2 overflow interrupt

2.8 0039h Y EVB Timer 4 period interrupt

1.6 0035h Y EVA Capture 3 interrupt

2.12 0036h Y EVB Capture 4 interrupt

1.9 0007h Y SCI

1.10 0040h Y CAN

1.13 0001h Y

1.14 0011h Y

PERIPHERAL

INTERRUPT

VECTOR

(PIV)

MASK-

ABLE?

(literature number SPRU276) for more information.

SOURCE

PERIPHERAL

MODULE

External

Interrupt Logic

External

Interrupt Logic

(literature number SPRU160) and the

DESCRIPTION

SCI receiver interrupt
(low-priority mode)

SCI transmitter interrupt
(low-priority mode)

CAN mailbox interrupt
(low-priority mode)

CAN error interrupt
(low-priority mode)

ADC interrupt
(low priority)

External interrupt pins
(low-priority mode)

External interrupt pins
(low-priority mode)

Software interrupt vectors

New peripheral interrupts and vectors with respect to the ’F243/’F241 devices.

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25

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

DSP CPU Core

The TMS320x240x devices use an advanced Harvard-type architecture that maximizes processing power by
maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple
bus structure allows data and instructions to be read simultaneously. Instructions support data transfers
between program memory and data memory . This architecture permits coefficients that are stored in program
memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a
four-deep pipeline, allows the ’LF240x/’LC240x devices to execute most instructions in a single cycle. See the
architectural block diagram of the ’24x DSP Core for more information.

TMS320x240x instruction set

The ’x240x microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control. Source code for the ’C1x and ’C2x DSPs is upwardly compatible with the ’x243/’x241 and ’240x devices.

For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or
external memory . Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.

addressing modes

scan-based emulation

The TMS320x240x instruction set provides four basic memory-addressing modes: direct, indirect, immediate,
and register.

In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each
page containing 128 words.

Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0–AR7) provide flexible and powerful indirect addressing. T o select a specific auxiliary register , the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.

TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardware­development support. Scan-based emulation allows the emulator to control the processor in the system without
the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the ’x2xx
by way of the IEEE 1149.1-compatible (JTAG) interface. The ’x240x DSPs, like the TMS320F243/241,
TMS320F206, TMS320C203, and TMS320LC203, do not include boundary scan. The scan chain of these
devices is useful for emulation function only.

26

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TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

functional block diagram of the ’240x DSP CPU

IS
DS
PS

Control

MUXMUX

ARP(3)

ARB(3)

XTAL1
CLKOUT
XTAL2

RD
WE

16

16

3

3

3

A15–A0

D15–D0

R/W

STRB

READY

MP/MC

XINT[1–2]

16

XF

RS

Data Bus

Memory Map

GREG (16)

2

16

16

3

Register
IMR (16)

IFR (16)

16

1616

MUX

Data/Prog

DARAM

B0 (256 × 16)

MUX

PC

FLASH EEPROM/

ROM

16

16

AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)

ARAU(16)

16

MUX

NPAR

PAR MST ACK

16

16

DP(9)

MUX

MUX

Data

DARAM

B2 (32 × 16)
B1 (256 × 16)

16

Program Bus

9

9

16

MUX

Stack 8 × 16

16

7
LSB
from
IR

MUX

ISCALE (0–16)

32

16

Program Control

(PCTRL)

16

16

16

16

PSCALE (–6,ā0,ā1,ā4)

CALU(32)

ACCL(16)ACCH(16)C

OSCALE (0–7)

Data Bus

TREG0(16)

Multiplier

PREG(32)

32

MUX

32

32

16

3232

32

MUX

Data Bus

1616

16

Program Bus

Program Bus

NOTES: A. See T able 4 for symbol descriptions.

B. For clarity, the data and program buses are shown as single buses although they include address and data bits.

C. Refer to the TMS320F243, TMS320F241 DSP Controllers data sheet (literature number SPRS064), the TMS320C240,

TMS320F240 DSP Controllers data sheet (literature number SPRS042), and the

Instruction Set Reference Guide

(literature number SPRU160) for CPU instruction set information.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C240 DSP Controllers CPU, System, and

27

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

’240x legend for the internal hardware

SYMBOL NAME DESCRIPTION

ACC Accumulator

ARAU

AUX
REGS

C Carry

CALU

DARAM Dual-Access RAM

DP

GREG

IMR

IFR
INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available.
ISCALE

MPY Multiplier

MSTACK Micro Stack
MUX Multiplexer Multiplexes buses to a common input
NPAR

OSCALE

PAR

PC Program Counter

PCTRL

Auxiliary Register
Arithmetic Unit

Auxiliary Registers
0–7

Central Arithmetic
Logic Unit

Data Memory
Page Pointer

Global Memory
Allocation
Register

Interrupt Mask
Register

Interrupt Flag
Register

Input Data-Scaling
Shifter

Next Program
Address Register

Output
Data-Scaling
Shifter

Program Address
Register

Program
Controller

Table 4. Legend for the ’240x DSP CPU Internal Hardware

32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities

An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs

These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.

Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.

32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
provides status results to PCTRL.

If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM
(DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2
are mapped to data memory space only, at addresses 0300–03FF and 0060–007F, respectively. Blocks 0
and 1 contain 256 words, while block 2 contains 32 words.

The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to
form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.

GREG specifies the size of the global data memory space. Since the global memory space is not used in
the ’240x devices, this register is reserved.

IMR individually masks or enables the seven interrupts.
The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable

interrupts.

16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.

16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.

MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.

NPAR holds the program address to be driven out on the PAB in the next cycle.
16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization

management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data
bus (DWEB).

PAR holds the address currently being driven on P AB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.

PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.

PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.

28

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TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

’240x legend for the internal hardware (continued)

Table 4. Legend for the ’240x DSP CPU Internal Hardware (Continued)

SYMBOL NAME DESCRIPTION

PREG Product Register 32-bit register holds results of 16 × 16 multiply

0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the

PSCALE

STACK Stack

TREG

Product-Scaling
Shifter

Temporary
Register

status and control registers

Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory , thus allowing the status of the machine to be saved
and restored for subroutines.

The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)
instruction is used to read from ST0 and ST1 — except for the INTM bit, which is not affected by the LST
instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC
instructions. Figure 8 shows the organization of status registers ST0 and ST1, indicating all status bits contained
in each. Several bits in the status registers are reserved and are read as logic 1s. Table 5 lists status register
field definitions.

additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle
overhead.

STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The ’C2xx stack is 16-bit wide and eight-level deep.

16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.

15 13 12 11 10 9 8 0

ST0

15 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ST1

ARP OV OVM 1 INTM DP

ARB CNF TC SXM C 1 1 1 1 XF 1 1 PM

Figure 8. Organization of Status Registers ST0 and ST1

Table 5. Status Register Field Definitions

FIELD FUNCTION

ARB

ARP

C

CNF

Auxiliary register pointer buffer . When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.

Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the
LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.

Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these
cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate
instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch
on the status of C. C is set to 1 on a reset.

On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data
space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1
instructions. RS

sets the CNF to 0.

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29

TMS320LF2407, TMS320LF2406, TMS320LF2402

ADVANCE

INFORMATION

TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

status and control registers (continued)

Table 5. Status Register Field Definitions (Continued)

FIELD FUNCTION

DP

INTM

OV

OVM

PM

SXM

TC

XF

Data memory page pointer. The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct
memory address of 16 bits. DP can be modified by the LST and LDP instructions.

Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.
INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS

and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when

RS
a maskable interrupt trap is taken.

Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an
overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV .

Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator
is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset
this bit, respectively. LST can also be used to modify the OVM.

Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG
output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by four
bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of six bits, sign-extended. Note that the PREG
contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the
SPM and LST #1 instructions. PM is cleared by RS

Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter.
SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction
suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction
and can be loaded by the LST #1 instruction. SXM is set to 1 by reset.

T est/control flag bit. TC is affected by the BIT, BITT , CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT
or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the two
most significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return
instructions can execute based on the condition of TC.

XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset
by the CLRC XF instruction. XF is set to 1 by reset.

also sets INTM. INTM has no effect on the unmaskable

.

central processing unit

input scaling shifter

The TMS320x240x central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel
multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the
outputs of both the accumulator and the multiplier. This section describes the CPU components and their
functions. The functional block diagram shows the components of the CPU.

The TMS320x240x provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output
connected to the CALU. This shifter operates as part of the path of data coming from program or data space
to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit
CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.

The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to
the system’s performance.

30

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