Texas Instruments TMS320C674X User Manual
TMS320C674x/OMAP-L1x Processor
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO) Module
User's Guide
Literature Number: SPRUFL5B
April 2011
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Preface ...................................................................................................................................... 10
1 Introduction ...................................................................................................................... 12
1.1 Purpose of the Peripheral ............................................................................................. 12
1.2 Features ................................................................................................................. 12
1.3 Functional Block Diagram ............................................................................................. 13
1.4 Industry Standard(s) Compliance Statement ....................................................................... 14
2 Architecture ...................................................................................................................... 14
2.1 Clock Control ........................................................................................................... 14
2.2 Memory Map ............................................................................................................ 14
2.3 Signal Descriptions .................................................................................................... 14
2.4 Ethernet Protocol Overview .......................................................................................... 17
2.5 Programming Interface ................................................................................................ 18
2.6 EMAC Control Module ................................................................................................ 29
2.7 MDIO Module ........................................................................................................... 30
2.8 EMAC Module .......................................................................................................... 35
2.9 MAC Interface .......................................................................................................... 37
2.10 Packet Receive Operation ............................................................................................ 41
2.11 Packet Transmit Operation ........................................................................................... 46
2.12 Receive and Transmit Latency ....................................................................................... 47
2.13 Transfer Node Priority ................................................................................................. 47
2.14 Reset Considerations .................................................................................................. 48
2.15 Initialization ............................................................................................................. 49
2.16 Interrupt Support ....................................................................................................... 51
2.17 Power Management ................................................................................................... 55
2.18 Emulation Considerations ............................................................................................. 55
3 EMAC Control Module Registers ......................................................................................... 56
3.1 EMAC Control Module Revision ID Register (REVID) ............................................................ 57
3.2 EMAC Control Module Software Reset Register (SOFTRESET) ............................................... 58
3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) ............................................. 59
3.4 EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers
(C0RXTHRESHEN-C2RXTHRESHEN) ............................................................................. 60
3.5 EMAC Control Module Interrupt Core Receive Interrupt Enable Registers (C0RXEN-C2RXEN) ........... 61
3.6 EMAC Control Module Interrupt Core Transmit Interrupt Enable Registers (C0TXEN-C2TXEN) ........... 62
3.7 EMAC Control Module Interrupt Core Miscellaneous Interrupt Enable Registers
(C0MISCEN-C2MISCEN) ............................................................................................. 63
3.8 EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers
(C0RXTHRESHSTAT-C2RXTHRESHSTAT) ...................................................................... 64
3.9 EMAC Control Module Interrupt Core Receive Interrupt Status Registers (C0RXSTAT-C2RXSTAT)
............................................................................................................................ 65
3.10 EMAC Control Module Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-C2TXSTAT)
............................................................................................................................ 66
3.11 EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers
(C0MISCSTAT-C2MISCSTAT) ...................................................................................... 67
3.12 EMAC Control Module Interrupt Core Receive Interrupts Per Millisecond Registers
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(C0RXIMAX-C2RXIMAX) ............................................................................................. 68
3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers
(C0TXIMAX-C2TXIMAX) .............................................................................................. 69
4 MDIO Registers ................................................................................................................. 70
4.1 MDIO Revision ID Register (REVID) ................................................................................ 70
4.2 MDIO Control Register (CONTROL) ................................................................................ 71
4.3 PHY Acknowledge Status Register (ALIVE) ....................................................................... 72
4.4 PHY Link Status Register (LINK) .................................................................................... 72
4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ................................... 73
4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .................................. 74
4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) .......................... 75
4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ......................... 76
4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ....................... 77
4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ................. 78
4.11 MDIO User Access Register 0 (USERACCESS0) ................................................................ 79
4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................ 80
4.13 MDIO User Access Register 1 (USERACCESS1) ................................................................ 81
4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) ............................................................ 82
5 EMAC Module Registers ..................................................................................................... 83
5.1 Transmit Revision ID Register (TXREVID) ......................................................................... 86
5.2 Transmit Control Register (TXCONTROL) ......................................................................... 86
5.3 Transmit Teardown Register (TXTEARDOWN) ................................................................... 87
5.4 Receive Revision ID Register (RXREVID) .......................................................................... 88
5.5 Receive Control Register (RXCONTROL) .......................................................................... 88
5.6 Receive Teardown Register (RXTEARDOWN) .................................................................... 89
5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ............................................ 90
5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .......................................... 91
5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................ 92
5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .................................................. 93
5.11 MAC Input Vector Register (MACINVECTOR) ..................................................................... 94
5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) ..................................................... 95
5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ............................................ 96
5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) .......................................... 97
5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ........................................................ 98
5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) .................................................. 99
5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ............................................ 100
5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) .......................................... 100
5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ........................................................ 101
5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) .................................................. 101
5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .................. 102
5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ...................................................... 105
5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) ......................................................... 106
5.24 Receive Maximum Length Register (RXMAXLEN) .............................................................. 107
5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) ......................................................... 107
5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ......................... 108
5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH) ........ 108
5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) ................. 109
5.29 MAC Control Register (MACCONTROL) .......................................................................... 110
5.30 MAC Status Register (MACSTATUS) ............................................................................. 112
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5.31 Emulation Control Register (EMCONTROL) ...................................................................... 114
5.32 FIFO Control Register (FIFOCONTROL) ......................................................................... 114
5.33 MAC Configuration Register (MACCONFIG) ..................................................................... 115
5.34 Soft Reset Register (SOFTRESET) ................................................................................ 115
5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) .............................................. 116
5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) .............................................. 116
5.37 MAC Hash Address Register 1 (MACHASH1) ................................................................... 117
5.38 MAC Hash Address Register 2 (MACHASH2) ................................................................... 117
5.39 Back Off Test Register (BOFFTEST) .............................................................................. 118
5.40 Transmit Pacing Algorithm Test Register (TPACETEST) ....................................................... 118
5.41 Receive Pause Timer Register (RXPAUSE) ...................................................................... 119
5.42 Transmit Pause Timer Register (TXPAUSE) ..................................................................... 119
5.43 MAC Address Low Bytes Register (MACADDRLO) ............................................................. 120
5.44 MAC Address High Bytes Register (MACADDRHI) ............................................................. 121
5.45 MAC Index Register (MACINDEX) ................................................................................. 121
5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) ........................... 122
5.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP) ........................... 122
5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) ............................................ 123
5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP) ............................................ 123
5.50 Network Statistics Registers ........................................................................................ 124
Appendix A Glossary ............................................................................................................... 133
Appendix B Revision History ..................................................................................................... 135
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List of Figures
1 EMAC and MDIO Block Diagram........................................................................................ 13
2 Ethernet Configuration—MII Connections.............................................................................. 15
3 Ethernet Configuration—RMII Connections............................................................................ 16
4 Ethernet Frame Format................................................................................................... 17
5 Basic Descriptor Format.................................................................................................. 18
6 Typical Descriptor Linked List............................................................................................ 19
7 Transmit Buffer Descriptor Format...................................................................................... 22
8 Receive Buffer Descriptor Format....................................................................................... 25
9 EMAC Control Module Block Diagram.................................................................................. 29
10 MDIO Module Block Diagram............................................................................................ 31
11 EMAC Module Block Diagram........................................................................................... 35
12 EMAC Control Module Revision ID Register (REVID)................................................................ 57
13 EMAC Control Module Software Reset Register (SOFTRESET) ................................................... 58
14 EMAC Control Module Interrupt Control Register (INTCONTROL)................................................. 59
15 EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN)....................................................................................................... 60
16 EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN)....................... 61
17 EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 62
18 EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 63
19 EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT).................................................................................................... 64
20 EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 65
21 EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT).................... 66
22 EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT).......... 67
23 EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX)......... 68
24 EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) ........ 69
25 MDIO Revision ID Register (REVID).................................................................................... 70
26 MDIO Control Register (CONTROL).................................................................................... 71
27 PHY Acknowledge Status Register (ALIVE)........................................................................... 72
28 PHY Link Status Register (LINK)........................................................................................ 72
29 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)....................................... 73
30 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ..................................... 74
31 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW).............................. 75
32 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ............................ 76
33 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)........................... 77
34 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .................... 78
35 MDIO User Access Register 0 (USERACCESS0) .................................................................... 79
36 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................... 80
37 MDIO User Access Register 1 (USERACCESS1) .................................................................... 81
38 MDIO User PHY Select Register 1 (USERPHYSEL1) ............................................................... 82
39 Transmit Revision ID Register (TXREVID)............................................................................. 86
40 Transmit Control Register (TXCONTROL)............................................................................. 86
41 Transmit Teardown Register (TXTEARDOWN)....................................................................... 87
42 Receive Revision ID Register (RXREVID) ............................................................................. 88
43 Receive Control Register (RXCONTROL) ............................................................................. 88
44 Receive Teardown Register (RXTEARDOWN) ....................................................................... 89
45 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ............................................... 90
46 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED).............................................. 91
6
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47 Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................... 92
48 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................... 93
49 MAC Input Vector Register (MACINVECTOR) ........................................................................ 94
50 MAC End Of Interrupt Vector Register (MACEOIVECTOR)......................................................... 95
51 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)................................................ 96
52 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) .............................................. 97
53 Receive Interrupt Mask Set Register (RXINTMASKSET)............................................................ 98
54 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)...................................................... 99
55 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)................................................ 100
56 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) .............................................. 100
57 MAC Interrupt Mask Set Register (MACINTMASKSET)............................................................ 101
58 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)...................................................... 101
59 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ..................... 102
60 Receive Unicast Enable Set Register (RXUNICASTSET).......................................................... 105
61 Receive Unicast Clear Register (RXUNICASTCLEAR)............................................................. 106
62 Receive Maximum Length Register (RXMAXLEN).................................................................. 107
63 Receive Buffer Offset Register (RXBUFFEROFFSET)............................................................. 107
64 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)............................. 108
65 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH).................................... 108
66 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ........................................... 109
67 MAC Control Register (MACCONTROL) ............................................................................. 110
68 MAC Status Register (MACSTATUS)................................................................................. 112
69 Emulation Control Register (EMCONTROL) ......................................................................... 114
70 FIFO Control Register (FIFOCONTROL)............................................................................. 114
71 MAC Configuration Register (MACCONFIG)......................................................................... 115
72 Soft Reset Register (SOFTRESET)................................................................................... 115
73 MAC Source Address Low Bytes Register (MACSRCADDRLO).................................................. 116
74 MAC Source Address High Bytes Register (MACSRCADDRHI) .................................................. 116
75 MAC Hash Address Register 1 (MACHASH1)....................................................................... 117
76 MAC Hash Address Register 2 (MACHASH2)....................................................................... 117
77 Back Off Random Number Generator Test Register (BOFFTEST)............................................... 118
78 Transmit Pacing Algorithm Test Register (TPACETEST) .......................................................... 118
79 Receive Pause Timer Register (RXPAUSE) ......................................................................... 119
80 Transmit Pause Timer Register (TXPAUSE)......................................................................... 119
81 MAC Address Low Bytes Register (MACADDRLO)................................................................. 120
82 MAC Address High Bytes Register (MACADDRHI) ................................................................. 121
83 MAC Index Register (MACINDEX) .................................................................................... 121
84 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) ......................................... 122
85 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP).......................................... 122
86 Transmit Channel n Completion Pointer Register (TXnCP)........................................................ 123
87 Receive Channel n Completion Pointer Register (RXnCP) ........................................................ 123
88 Statistics Register........................................................................................................ 124
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List of Tables
1 EMAC and MDIO Signals for MII Interface............................................................................. 15
2 EMAC and MDIO Signals for RMII Interface........................................................................... 16
3 Ethernet Frame Description.............................................................................................. 17
4 Basic Descriptor Description............................................................................................. 19
5 Receive Frame Treatment Summary ................................................................................... 44
6 Middle of Frame Overrun Treatment.................................................................................... 45
7 Emulation Control ......................................................................................................... 55
8 EMAC Control Module Registers........................................................................................ 56
9 EMAC Control Module Revision ID Register (REVID) Field Descriptions ......................................... 57
10 EMAC Control Module Software Reset Register (SOFTRESET) ................................................... 58
11 EMAC Control Module Interrupt Control Register (INTCONTROL)................................................. 59
12 EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN)....................................................................................................... 60
13 EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN)....................... 61
14 EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 62
15 EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 63
16 EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT).................................................................................................... 64
17 EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 65
18 EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT).................... 66
19 EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT).......... 67
20 EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX)......... 68
21 EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) ........ 69
22 Management Data Input/Output (MDIO) Registers ................................................................... 70
23 MDIO Revision ID Register (REVID) Field Descriptions ............................................................. 70
24 MDIO Control Register (CONTROL) Field Descriptions ............................................................. 71
25 PHY Acknowledge Status Register (ALIVE) Field Descriptions..................................................... 72
26 PHY Link Status Register (LINK) Field Descriptions ................................................................. 72
27 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions................. 73
28 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ............... 74
29 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions........ 75
30 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions...... 76
31 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .... 77
32 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions ................................................................................................................ 78
33 MDIO User Access Register 0 (USERACCESS0) Field Descriptions.............................................. 79
34 MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions......................................... 80
35 MDIO User Access Register 1 (USERACCESS1) Field Descriptions.............................................. 81
36 MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions......................................... 82
37 Ethernet Media Access Controller (EMAC) Registers ................................................................ 83
38 Transmit Revision ID Register (TXREVID) Field Descriptions ...................................................... 86
39 Transmit Control Register (TXCONTROL) Field Descriptions....................................................... 86
40 Transmit Teardown Register (TXTEARDOWN) Field Descriptions................................................. 87
41 Receive Revision ID Register (RXREVID) Field Descriptions....................................................... 88
42 Receive Control Register (RXCONTROL) Field Descriptions ....................................................... 88
43 Receive Teardown Register (RXTEARDOWN) Field Descriptions ................................................. 89
44 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions......................... 90
45 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ....................... 91
8
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46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions..................................... 92
47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions............................... 93
48 MAC Input Vector Register (MACINVECTOR) Field Descriptions.................................................. 94
49 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions................................... 95
50 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ......................... 96
51 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions........................ 97
52 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ..................................... 98
53 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............................... 99
54 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ......................... 100
55 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions........................ 100
56 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ..................................... 101
57 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ............................... 101
58 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
59 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ................................... 105
60 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ...................................... 106
61 Receive Maximum Length Register (RXMAXLEN) Field Descriptions............................................ 107
62 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions....................................... 107
63 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ...... 108
64 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions.............. 108
65 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ..................... 109
66 MAC Control Register (MACCONTROL) Field Descriptions ....................................................... 110
67 MAC Status Register (MACSTATUS) Field Descriptions........................................................... 112
68 Emulation Control Register (EMCONTROL) Field Descriptions................................................... 114
69 FIFO Control Register (FIFOCONTROL) Field Descriptions....................................................... 114
70 MAC Configuration Register (MACCONFIG) Field Descriptions .................................................. 115
71 Soft Reset Register (SOFTRESET) Field Descriptions............................................................. 115
72 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ........................... 116
73 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................ 116
74 MAC Hash Address Register 1 (MACHASH1) Field Descriptions................................................. 117
75 MAC Hash Address Register 2 (MACHASH2) Field Descriptions................................................. 117
76 Back Off Test Register (BOFFTEST) Field Descriptions ........................................................... 118
77 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions.................................... 118
78 Receive Pause Timer Register (RXPAUSE) Field Descriptions ................................................... 119
79 Transmit Pause Timer Register (TXPAUSE) Field Descriptions .................................................. 119
80 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions .......................................... 120
81 MAC Address High Bytes Register (MACADDRHI) Field Descriptions........................................... 121
82 MAC Index Register (MACINDEX) Field Descriptions .............................................................. 121
83 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions................... 122
84 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ................... 122
85 Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions.................................. 123
86 Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions.................................. 123
87 Physical Layer Definitions .............................................................................................. 134
88 Document Revision History............................................................................................. 135
Descriptions............................................................................................................... 102
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About This Manual
This document provides a functional description of the Ethernet Media Access Controller (EMAC) and
physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device.
Included are the features of the EMAC and MDIO modules, a discussion of their architecture and
operation, how these modules connect to the outside world, and the registers description for each module.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Preface
SPRUFL5B–April 2011
Read This First
Related Documentation From Texas Instruments
The following documents describe the TMS320C674x Digital Signal Processors (DSPs) and OMAP-L1x
Applications Processors. Copies of these documents are available on the Internet at www.ti.com. Tip:
Enter the literature number in the search box provided at www.ti.com.
The current documentation that describes the DSP, related peripherals, and other technical collateral, is
available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRUGM5 — TMS320C6742 DSP System Reference Guide. Describes the C6742 DSP subsystem,
system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller
(PSC), power management, and system configuration module.
SPRUGJ0 — TMS320C6743 DSP System Reference Guide. Describes the System-on-Chip (SoC)
including the C6743 DSP subsystem, system memory, device clocking, phase-locked loop
controller (PLLC), power and sleep controller (PSC), power management, and system configuration
module.
SPRUFK4 — TMS320C6745/C6747 DSP System Reference Guide. Describes the System-on-Chip
(SoC) including the C6745/C6747 DSP subsystem, system memory, device clocking, phase-locked
loop controller (PLLC), power and sleep controller (PSC), power management, and system
configuration module.
SPRUGM6 — TMS320C6746 DSP System Reference Guide. Describes the C6746 DSP subsystem,
system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller
(PSC), power management, and system configuration module.
SPRUGJ7 — TMS320C6748 DSP System Reference Guide. Describes the C6748 DSP subsystem,
system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller
(PSC), power management, and system configuration module.
10
SPRUG84 — OMAP-L137 Applications Processor System Reference Guide. Describes the
System-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory, device
clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), power
management, ARM interrupt controller (AINTC), and system configuration module.
Preface SPRUFL5B–April 2011
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SPRUGM7 — OMAP-L138 Applications Processor System Reference Guide. Describes the
SPRUFK9 — TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides
SPRUFK5 — TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
SPRUFE8 — TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
SPRUG82 — TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
Related Documentation From Texas Instruments
System-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory, device
clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), power
management, ARM interrupt controller (AINTC), and system configuration module.
an overview and briefly describes the peripherals available on the TMS320C674x Digital Signal
Processors (DSPs) and OMAP-L1x Applications Processors.
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors
(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added
functionality and an expanded instruction set.
and describes how the two-level cache-based internal memory architecture in the TMS320C674x
digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain
coherence with external memory, how to use DMA to reduce memory latencies, and how to
optimize your code to improve cache efficiency. The internal memory architecture in the C674x
DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a
dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches
can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
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1 Introduction
This document provides a functional description of the Ethernet Media Access Controller (EMAC) and
physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device.
Included are the features of the EMAC and MDIO modules, a discussion of their architecture and
operation, how these modules connect to the outside world, and a description of the registers for each
module.
The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY
configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the system core through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module and is considered integral to the EMAC/MDIO peripheral.
1.1 Purpose of the Peripheral
The EMAC module is used to move data between the device and another host connected to the same
network, in compliance with the Ethernet protocol.
User's Guide
SPRUFL5B–April 2011
EMAC/MDIO Module
1.2 Features
The EMAC/MDIO has the following features:
• Synchronous 10/100 Mbps operation.
• Standard Media Independent Interface (MII) and/or Reduced Media Independent Interface (RMII) to
physical layer device (PHY).
• EMAC acts as DMA master to either internal or external device memory space.
• Eight receive channels with VLAN tag discrimination for receive quality-of-service (QOS) support.
• Eight transmit channels with round-robin or fixed priority for transmit quality-of-service (QOS) support.
• Ether-Stats and 802.3-Stats statistics gathering.
• Transmit CRC generation selectable on a per channel basis.
• Broadcast frames selection for reception on a single channel.
• Multicast frames selection for reception on a single channel.
• Promiscuous receive mode frames selection for reception on a single channel (all frames, all good
frames, short frames, error frames).
• Hardware flow control.
• 8k-byte local EMAC descriptor memory that allows the peripheral to operate on descriptors without
affecting the CPU. The descriptor memory holds enough information to transfer up to 512 Ethernet
packets without CPU intervention. (This memory is also known as CPPI RAM.)
• Programmable interrupt logic permits the software driver to restrict the generation of back-to-back
interrupts, which allows more work to be performed in a single call to the interrupt service routine.
12
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DMA
Master
8KCPPI
RAM
Interrupt
Combiner
C0
C1
C2
ControlModule
EMAC
Module
MDIO
Module
EMAC
Interrupts
MDIO
Interrupts
Interrupts
EMACSubSystem
RegisterBus
DMA Bus
MII/RMIIBus
MDIOBus
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1.3 Functional Block Diagram
Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral:
• EMAC control module
• EMAC module
• MDIO module
The EMAC control module is the main interface between the device core processor to the EMAC and
MDIO modules. The EMAC control module controls device interrupts and incorporates an 8k-byte internal
RAM to hold EMAC buffer descriptors (also known as CPPI RAM).
The MDIO module implements the 802.3 serial management interface to interrogate and control up to 32
Ethernet PHYs connected to the device by using a shared two-wire bus. Host software uses the MDIO
module to configure the autonegotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor.
The EMAC module provides an efficient interface between the processor and the network. The EMAC on
this device supports 10Base-T (10 Mbits/sec) and 100BaseTX (100 Mbits/sec), half-duplex and full-duplex
mode, and hardware flow control and quality-of-service (QOS) support.
Figure 1 shows the main interface between the EMAC control module and the CPU. The following
connections are made to the device core:
• The DMA bus connection from the EMAC control module allows the EMAC module to read and write
both internal and external memory through the DMA memory transfer controller.
• The EMAC control, EMAC, and MDIO modules all have control registers. These registers are
memory-mapped into device memory space via the device configuration bus. Along with these
registers, the control module’s internal CPPI RAM is mapped into this same range.
• The EMAC and MDIO interrupts are combined into four interrupt signals within the control module.
Three configurable interrupt cores within the control module receive all four interrupt signals from the
combiner and submit interrupt requests to the CPU.
Introduction
Figure 1. EMAC and MDIO Block Diagram
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Architecture
1.4 Industry Standard(s) Compliance Statement
The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access
with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3
standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
However, the EMAC deviates from the standard in the way it handles transmit underflow errors. The
EMAC MII interface does not use the Transmit Coding Error signal MTXER. Instead of driving the error pin
when an underflow condition occurs on a transmitted frame, the EMAC intentionally generates an incorrect
checksum by inverting the frame CRC, so that the transmitted frame is detected as an error by the
network.
2 Architecture
This section discusses the architecture and basic function of the EMAC peripheral.
2.1 Clock Control
All internal EMAC logic is clocked synchronously on one clock domain. See your device-specific data
manual for information.
The MDIO clock is based on a divide-down of the peripheral clock and is specified to run up to 2.5 MHz
(although typical operation would be 1.0 MHz). Because the peripheral clock frequency is variable, the
application software or driver must control the divide-down value.
The transmit and receive clock sources are provided by the external PHY to the MII_TXCLK and
MII_RXCLK pins or to the RMII reference clock pin. Data is transmitted and received with respect to the
reference clocks of the interface pins.
The MII interface frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification
as:
• 2.5 MHz at 10 Mbps
• 25 MHz at 100 Mbps
The RMII interface frequency for the transmit and receive clocks are fixed at 50 MHz for both 10 Mbps
and 100 Mbps.
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2.2 Memory Map
The EMAC peripheral includes internal memory that is used to hold buffer descriptions of the Ethernet
packets to be received and transmitted. This internal RAM is 2K × 32 bits in size. Data can be written to
and read from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer
descriptors that are 4-words (16-bytes) deep. This 8K local memory holds enough information to transfer
up to 512 Ethernet packets without CPU intervention. This EMAC RAM is also referred to as the CPPI
buffer descriptor memory because it complies with the Communications Port Programming Interface
(CPPI) v3.0 standard.
The packet buffer descriptors can also be placed in other on- and off-chip memories such as L2 and
EMIF. There are some tradeoffs in terms of cache performance and throughput when descriptors are
placed in the system memory, versus when they are placed in the EMAC’s internal memory. In general,
the EMAC throughput is better when the descriptors are placed in the local EMAC CPPI RAM.
2.3 Signal Descriptions
Support of interfaces (MII and/or RMII) varies between devices. See your device-specific data manual for
information.
2.3.1 Media Independent Interface (MII) Connections
Figure 2 shows a device with integrated EMAC and MDIO interfaced via a MII connection in a typical
system. The EMAC module does not include a transmit error (MTXER) pin. In the case of transmit error,
CRC inversion is used to negate the validity of the transmitted frame.
14
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MII_TXCLK
MII_TXD[3−0]
MII_TXEN
MII_COL
MII_CRS
MII_RXCLK
MII_RXD[3−0]
MII_RXDV
MII_RXER
MDIO_CLK
MDIO_D
Physical
layer
device
(PHY)
System
core
Transformer
2.5 MHz
or
25 MHz
RJ−45
EMACMDIO
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The individual EMAC and MDIO signals for the MII interface are summarized in Table 1. For more
information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E).
Architecture
Figure 2. Ethernet Configuration—MII Connections
Table 1. EMAC and MDIO Signals for MII Interface
Signal Type Description
MII_TXCLK I Transmit clock (MII_TXCLK). The transmit clock is a continuous clock that provides the timing
MII_TXD[3-0] O Transmit data (MII_TXD). The transmit data pins are a collection of 4 data signals comprising 4 bits
MII_TXEN O Transmit enable (MII_TXEN). The transmit enable signal indicates that the MII_TXD pins are
MII_COL I Collision detected (MII_COL). In half-duplex operation, the MII_COL pin is asserted by the PHY
MII_CRS I Carrier sense (MII_CRS). In half-duplex operation, the MII_CRS pin is asserted by the PHY when
MII_RXCLK I Receive clock (MII_RXCLK). The receive clock is a continuous clock that provides the timing
MII_RXD[3-0] I Receive data (MII_RXD). The receive data pins are a collection of 4 data signals comprising 4 bits of
MII_RXDV I Receive data valid (MII_RXDV). The receive data valid signal indicates that the MII_RXD pins are
MII_RXER I Receive error (MII_RXER). The receive error signal is asserted for one or more MII_RXCLK periods
reference for transmit operations. The MII_TXD and MII_TXEN signals are tied to this clock. The
clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps
operation.
of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MII_TXCLK and
valid only when MII_TXEN is asserted.
generating nibble data for use by the PHY. It is driven synchronously to MII_TXCLK.
when it detects a collision on the network. It remains asserted while the collision condition persists.
This signal is not necessarily synchronous to MII_TXCLK nor MII_RXCLK.
In full-duplex operation, the MII_COL pin is used for hardware transmit flow control. Asserting the
MII_COL pin will stop packet transmissions; packets in the process of being transmitted when
MII_COL is asserted will complete transmission. The MII_COL pin should be held low if hardware
transmit flow control is not used.
the network is not idle in either transmit or receive. The pin is deasserted when both transmit and
receive are idle. This signal is not necessarily synchronous to MII_TXCLK nor MII_RXCLK.
In full-duplex operation, the MII_CRS pin should be held low.
reference for receive operations. The MII_RXD, MII_RXDV, and MII_RXER signals are tied to this
clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at
100 Mbps operation.
data. MRDX0 is the least-significant bit (LSB). The signals are synchronized by MII_RXCLK and
valid only when MII_RXDV is asserted.
generating nibble data for use by the EMAC. It is driven synchronously to MII_RXCLK.
to indicate that an error was detected in the received frame. This is meaningful only during data
reception when MII_RXDV is active.
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RMII_TXD[1-0]
RMII_TXEN
RMII_MHZ_50_CLK
RMII_RXD[1-0]
RMII_CRS_DV
RMII_RXER
MDIO_CLK
MDIO_D
MDIO
EMAC
Physical
Layer
Device
(PHY)
Transformer
50MHz
RJ-45
Architecture
Table 1. EMAC and MDIO Signals for MII Interface (continued)
Signal Type Description
MDIO_CLK O Management data clock (MDIO_CLK). The MDIO data clock is sourced by the MDIO module on the
system. It is used to synchronize MDIO data access operations done on the MDIO pin. The
frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).
MDIO_D I/O Management data input output (MDIO_D). The MDIO data pin drives PHY management data into
and out of the PHY by way of an access frame consisting of start of frame, read/write indication,
PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the
data bit cycles at which time it is an input for read operations.
2.3.2 Reduced Media Independent Interface (RMII) Connections
Figure 3 shows a device with integrated EMAC and MDIO interfaced via a RMII connection in a typical
system.
The individual EMAC and MDIO signals for the RMII interface are summarized in Table 2. For more
information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E).
Figure 3. Ethernet Configuration—RMII Connections
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Signal Type Description
RMII_TXD[1-0] O Transmit data (RMII_TXD). The transmit data pins are a collection of 2 bits of data. RMTDX0 is
RMII_TXEN O Transmit enable (RMII_TXEN). The transmit enable signal indicates that the RMII_TXD pins are
RMII_MHZ_50_CLK I RMII reference clock (RMII_MHZ_50_CLK). The reference clock is used to synchronize all RMII
RMII_RXD[1-0] I Receive data (RMII_RXD). The receive data pins are a collection of 2 bits of data. RMRDX0 is the
RMII_CRS_DV I Carrier sense/receive data valid (RMII_CRS_DV). Multiplexed signal between carrier sense and
RMII_RXER I Receive error (RMII_RXER). The receive error signal is asserted to indicate that an error was
MDIO_CLK O Management data clock (MDIO_CLK). The MDIO data clock is sourced by the MDIO module on
16
MDIO_D I/O Management data input output (MDIO_D). The MDIO data pin drives PHY management data into
EMAC/MDIO Module SPRUFL5B–April 2011
Table 2. EMAC and MDIO Signals for RMII Interface
the least-significant bit (LSB). The signals are synchronized by RMII_MHZ_50_CLK and valid only
when RMII_TXEN is asserted.
generating data for use by the PHY. RMII_TXEN is synchronous to RMII_MHZ_50_CLK.
signals. RMII_MHZ_50_CLK must be continuous and fixed at 50 MHz.
least-significant bit (LSB). The signals are synchronized by RMII_MHZ_50_CLK and valid only
when RMII_CRS_DV is asserted and RMII_RXER is deasserted.
receive data valid.
detected in the received frame.
the system. It is used to synchronize MDIO data access operations done on the MDIO pin. The
frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).
and out of the PHY by way of an access frame consisting of start of frame, read/write indication,
PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but
the data bit cycles at which time it is an input for read operations.
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Preamble SFD Destination Source Len Data
7 1 6 6 2 46−1500 4
FCS
Number of bytes
Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC)
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2.4 Ethernet Protocol Overview
A brief overview of the Ethernet protocol is given in the following subsections. See the IEEE 802.3
standard document for in-depth information on the Carrier Sense Multiple Access with Collision Detection
(CSMA/CD) Access Method.
2.4.1 Ethernet Frame Format
All the Ethernet technologies use the same frame structure. The format of an Ethernet frame is shown in
Figure 4 and described in Table 3. The Ethernet packet, which is the collection of bytes representing the
data portion of a single Ethernet frame on the wire, is shown outlined in bold. The Ethernet frames are of
variable lengths, with no frame smaller than 64 bytes or larger than RXMAXLEN bytes (header, data, and
CRC).
Architecture
Figure 4. Ethernet Frame Format
Table 3. Ethernet Frame Description
Field Bytes Description
Preamble 7 Preamble. These 7 bytes have a fixed value of 55h and serve to wake up the receiving
SFD 1 Start of Frame Delimiter. This field with a value of 5Dh immediately follows the preamble
Destination 6 Destination address. This field contains the Ethernet MAC address of the EMAC port for
Source 6 Source address. This field contains the MAC address of the Ethernet port that transmits the
Len 2 Length/Type field. The length field indicates the number of EMAC client data bytes
Data 46 to Data field. This field carries the datagram containing the upper layer protocol frame, that is,
(RXMAXLEN - 18) IP layer datagram. The maximum transfer unit (MTU) of Ethernet is (RXMAXLEN - 18)
FCS 4 Frame Check Sequence. A cyclic redundancy check (CRC) is used by the transmit and
EMAC ports and to synchronize their clocks to that of the sender’s clock.
pattern and indicates the start of important data.
which the frame is intended. It may be an individual or multicast (including broadcast)
address. When the destination EMAC port receives an Ethernet frame with a destination
address that does not match any of its MAC physical addresses, and no promiscuous,
multicast or broadcast channel is enabled, it discards the frame.
frame to the Local Area Network.
contained in the subsequent data field of the frame. This field can also be used to identify
the type of data the frame is carrying.
bytes. This means that if the upper layer protocol datagram exceeds (RXMAXLEN - 18)
bytes, then the host has to fragment the datagram and send it in multiple Ethernet packets.
The minimum size of the data field is 46 bytes. This means that if the upper layer datagram
is less then 46 bytes, the data field has to be extended to 46 bytes by appending extra bits
after the data field, but prior to calculating and appending the FCS.
receive algorithms to generate a CRC value for the FCS field. The frame check sequence
covers the 60 to 1514 bytes of the packet data. Note that this 4-byte field may or may not
be included as part of the packet data, depending on how the EMAC is configured.
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Architecture
2.4.2 Ethernet’s Multiple Access Protocol
Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel -- when an EMAC
port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex
mode. When operating in full-duplex mode, there is no contention for use of a shared medium because
there are exactly two ports on the local network.
Each port runs the CSMA/CD protocol without explicit coordination with the other ports on the Ethernet
network. Within a specific port, the CSMA/CD protocol works as follows:
1. The port obtains data from upper layer protocols at its node, prepares an Ethernet frame, and puts the
frame in a buffer.
2. If the port senses that the medium is idle, it starts to transmit the frame. If the port senses that the
transmission medium is busy, it waits until it no longer senses energy (plus an Inter-Packet Gap time)
and then starts to transmit the frame.
3. While transmitting, the port monitors for the presence of signal energy coming from other ports. If the
port transmits the entire frame without detecting signal energy from other Ethernet devices, the port is
done with the frame.
4. If the port detects signal energy from other ports while transmitting, it stops transmitting its frame and
instead transmits a 48-bit jam signal.
5. After transmitting the jam signal, the port enters an exponential backoff phase. If a data frame
encounters back-to-back collisions, the port chooses a random value that is dependent on the number
of collisions. The port then waits an amount of time that is a multiple of this random value and returns
to step 2.
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2.5 Programming Interface
2.5.1 Packet Buffer Descriptors
The buffer descriptor is a central part of the EMAC module and is how the application software describes
Ethernet packets to be sent and empty buffers to be filled with incoming packet data. The basic descriptor
format is shown in Figure 5 and described in Table 4.
For example, consider three packets to be transmitted: Packet A is a single fragment (60 bytes), Packet B
is fragmented over three buffers (1514 bytes total), and Packet C is a single fragment (1514 bytes). The
linked list of descriptors to describe these three packets is shown in Figure 6.
Word
Offset 31 16 15 0
0 Next Descriptor Pointer
1 Buffer Pointer
2 Buffer Offset Buffer Length
3 Flags Packet Length
Figure 5. Basic Descriptor Format
Bit Fields
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SOP | EOP 60
0 60
pBuffer
pNext
Packet A
60 bytes
0
SOP
Fragment 1
Packet B
512
1514
pBuffer
pNext
512 bytes
EOP
0
0
−−−
Packet B
Fragment 3
500 bytes
502
pBuffer
−−−
500
pNext
−−−
pBuffer
pNext
Packet B
Fragment 2
502 bytes
SOP | EOP
0
1514 bytes
Packet C
1514
pBuffer
pNext (NULL)
1514
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Architecture
Table 4. Basic Descriptor Description
Word Offset Field Field Description
0 Next Descriptor The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor
Pointer describes a packet or a packet fragment. When a descriptor points to a single buffer packet
or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field. When a
descriptor points to a single buffer packet or the last fragment of a packet, the end of packet
(EOP) flag is set. When a packet is fragmented, each fragment must have its own descriptor
and appear sequentially in the descriptor linked list.
1 Buffer Pointer The buffer pointer refers to the actual memory buffer that contains packet data during
transmit operations, or is an empty buffer ready to receive packet data during receive
operations.
2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data.
This field only has meaning when the buffer descriptor points to a buffer that actually contains
data.
Buffer Length The buffer length is the actual number of valid packet data bytes stored in the buffer. If the
buffer is empty and waiting to receive data, this field represents the size of the empty buffer.
3 Flags The flags field contains more information about the buffer, such as, is it the first fragment in a
packet (SOP), the last fragment in a packet (EOP), or contains an entire contiguous Ethernet
packet (both SOP and EOP). The flags are described in Section 2.5.4 and Section 2.5.5.
Packet Length The packet length only has meaning for buffers that both contain data and are the start of a
new packet (SOP). In the case of SOP descriptors, the packet length field contains the length
of the entire Ethernet packet, regardless if it is contained in a single buffer or fragmented over
several buffers.
Figure 6. Typical Descriptor Linked List
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Architecture
2.5.2 Transmit and Receive Descriptor Queues
The EMAC module processes descriptors in linked lists as discussed in Section 2.5.1. The lists used by
the EMAC are maintained by the application software through the use of the head descriptor pointer
registers (HDP). The EMAC supports eight channels for transmit and eight channels for receive. The
corresponding head descriptor pointers are:
• TXnHDP - Transmit Channel n DMA Head Descriptor Pointer Register
• RXnHDP - Receive Channel n DMA Head Descriptor Pointer Register
After an EMAC reset and before enabling the EMAC for send and receive, all 16 head descriptor pointer
registers must be initialized to 0.
The EMAC uses a simple system to determine if a descriptor is currently owned by the EMAC or by the
application software. There is a flag in the buffer descriptor flags called OWNER. When this flag is set, the
packet that is referenced by the descriptor is considered to be owned by the EMAC. Note that ownership
is done on a packet based granularity, not on descriptor granularity, so only SOP descriptors make use of
the OWNER flag. As packets are processed, the EMAC patches the SOP descriptor of the corresponding
packet and clears the OWNER flag. This is an indication that the EMAC has finished processing all
descriptors up to and including the first with the EOP flag set, indicating the end of the packet (note this
may only be one descriptor with both the SOP and EOP flags set).
To add a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time, the
software application simply writes the pointer to the descriptor or first descriptor of a list to the
corresponding HDP register. Note that the last descriptor in the list must have its “next” pointer cleared to
0. This is the only way the EMAC has of detecting the end of the list. Therefore, in the case where only a
single descriptor is added, its “next descriptor” pointer must be initialized to 0.
The HDP must never be written to while a list is active. To add additional descriptors to a descriptor list
already owned by the EMAC, the NULL “next” pointer of the last descriptor of the previous list is patched
with a pointer to the first descriptor of the new list. The list of new descriptors to be appended to the
existing list must itself be NULL terminated before the pointer patch is performed.
There is a potential race condition where the EMAC may read the “next” pointer of a descriptor as NULL in
the instant before an application appends additional descriptors to the list by patching the pointer. This
case is handled by the software application always examining the buffer descriptor flags of all EOP
packets, looking for a special flag called end of queue (EOQ). The EOQ flag is set by the EMAC on the
last descriptor of a packet when the descriptor’s “next” pointer is NULL. This is the way the EMAC
indicates to the software application that it believes it has reached the end of the list. When the software
application sees the EOQ flag set, the application may at that time submit the new list, or the portion of
the appended list that was missed by writing the new list pointer to the same HDP that started the
process.
This process applies when adding packets to a transmit list, and empty buffers to a receive list.
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2.5.3 Transmit and Receive EMAC Interrupts
The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1, using the linked list
queue mechanism discussed in Section 2.5.2.
The EMAC synchronizes descriptor list processing through the use of interrupts to the software
application. The interrupts are controlled by the application using the interrupt masks, global interrupt
enable, and the completion pointer register (CP). The CP is also called the interrupt acknowledge register.
The EMAC supports eight channels for transmit and eight channels for receive. The corresponding
completion pointer registers are:
• TXnCP - Transmit Channel n Completion Pointer (Interrupt Acknowledge) Register
• RXnCP - Receive Channel n Completion Pointer (Interrupt Acknowledge) Register
These registers serve two purposes. When read, they return the pointer to the last descriptor that the
EMAC has processed. When written by the software application, the value represents the last descriptor
processed by the software application. When these two values do not match, the interrupt is active.
Interrupts in the EMAC control module are routed to three independent interrupt cores which are then
mapped to CPU interrupt controllers. The system configuration determines whether or not an active
interrupt actually interrupts the CPU. In general the following settings are required for basic EMAC
transmit and receive interrupts:
1. EMAC transmit and receive interrupts are enabled by setting the mask registers RXINTMASKSET and
TXINTMASKSET
2. Global interrupts for the appropriate interrupt core registers are set in the EMAC control module:
CnRXEN and CnTXEN on core n
3. The CPU interrupt controller is configured to accept Cn_RX_PULSE and Cn_TX_PULSE interrupts
from the EMAC control module
Whether or not the interrupt is enabled, the current state of the receive or transmit channel interrupt can
be examined directly by the software application reading the EMAC receive interrupt status (unmasked)
register (RXINTSTATRAW) and transmit interrupt status (unmasked) register (TXINTSTATRAW).
After servicing transmit or receive interrupts, the application software must acknowledge both the EMAC
and EMAC control module interrupts.
EMAC interrupts are acknowledged when the application software updates the value of TXnCP or RXnCP
with a value that matches the internal value kept by the EMAC. This mechanism ensures that the
application software never misses an EMAC interrupt because the interrupt acknowledgment is tied
directly to the buffer descriptor processing.
EMAC control module interrupts are acknowledged when the application software writes the appropriate
CnTX or CnRX key to the EMAC End-Of-Interrupt Vector register (MACEOIVECTOR). The
MACEOIVECTOR behaves as an interrupt pulse interlock -- once the EMAC control module has issued an
interrupt pulse to the CPU, it will not generate further pulses of the same type until the original pulse has
been acknowledged.
Architecture
2.5.4 Transmit Buffer Descriptor Format
A transmit (TX) buffer descriptor (Figure 7) is a contiguous block of four 32-bit data words aligned on a
32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer
descriptor described by a C structure.
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Architecture
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Figure 7. Transmit Buffer Descriptor Format
Word 0
31 0
Next Descriptor Pointer
Word 1
31 0
Buffer Pointer
Word 2
31 16 15 0
Buffer Offset Buffer Length
Word 3
31 30 29 28 27 26 25 16
SOP EOP OWNER EOQ TDOWNCMPLT PASSCRC Reserved
15 0
Packet Length
Example 1. Transmit Buffer Descriptor in C Structure Format
/*
// EMAC Descriptor
//
// The following is the format of a single buffer descriptor
// on the EMAC.
*/
typedef struct _EMAC_Desc {
struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */
Uint8 *pBuffer; /* Pointer to data buffer */
Uint32 BufOffLen; /* Buffer Offset(MSW) and Length(LSW) */
Uint32 PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */
} EMAC_Desc;
/* Packet Flags */
#define EMAC_DSC_FLAG_SOP 0x80000000u
#define EMAC_DSC_FLAG_EOP 0x40000000u
#define EMAC_DSC_FLAG_OWNER 0x20000000u
#define EMAC_DSC_FLAG_EOQ 0x10000000u
#define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u
#define EMAC_DSC_FLAG_PASSCRC 0x04000000u
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2.5.4.1 Next Descriptor Pointer
The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor
in the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of this
pointer is zero, then the current buffer is the last buffer in the queue. The software application must set
this value prior to adding the descriptor to the active transmit list. This pointer is not altered by the EMAC.
The value of pNext should never be altered once the descriptor is in an active transmit queue, unless its
current value is NULL. If the pNext pointer is initially NULL, and more packets need to be queued for
transmit, the software application may alter this pointer to point to a newly appended descriptor. The
EMAC will use the new pointer value and proceed to the next descriptor unless the pNext value has
already been read. In this latter case, the transmitter will halt on the transmit channel in question, and the
software application may restart it at that time. The software can detect this case by checking for an end
of queue (EOQ) condition flag on the updated packet descriptor when it is returned by the EMAC.
2.5.4.2 Buffer Pointer
The buffer pointer is the byte-aligned memory address of the memory buffer associated with the buffer
descriptor. The software application must set this value prior to adding the descriptor to the active transmit
list. This pointer is not altered by the EMAC.
2.5.4.3 Buffer Offset
This 16-bit field indicates how many unused bytes are at the start of the buffer. For example, a value of
0000h indicates that no unused bytes are at the start of the buffer and that valid data begins on the first
byte of the buffer, while a value of 000Fh indicates that the first 15 bytes of the buffer are to be ignored by
the EMAC and that valid buffer data starts on byte 16 of the buffer. The software application must set this
value prior to adding the descriptor to the active transmit list. This field is not altered by the EMAC.
Note that this value is only checked on the first descriptor of a given packet (where the start of packet
(SOP) flag is set). It can not be used to specify the offset of subsequent packet fragments. Also, since the
buffer pointer may point to any byte–aligned address, this field may be entirely superfluous, depending on
the device driver architecture.
The range of legal values for this field is 0 to (Buffer Length – 1).
Architecture
2.5.4.4 Buffer Length
This 16-bit field indicates how many valid data bytes are in the buffer. On single fragment packets, this
value is also the total length of the packet data to be transmitted. If the buffer offset field is used, the offset
bytes are not counted as part of this length. This length counts only valid data bytes. The software
application must set this value prior to adding the descriptor to the active transmit list. This field is not
altered by the EMAC.
2.5.4.5 Packet Length
This 16-bit field specifies the number of data bytes in the entire packet. Any leading buffer offset bytes are
not included. The sum of the buffer length fields of each of the packet’s fragments (if more than one) must
be equal to the packet length. The software application must set this value prior to adding the descriptor to
the active transmit list. This field is not altered by the EMAC. This value is only checked on the first
descriptor of a given packet (where the start of packet (SOP) flag is set).
2.5.4.6 Start of Packet (SOP) Flag
When set, this flag indicates that the descriptor points to a packet buffer that is the start of a new packet.
In the case of a single fragment packet, both the SOP and end of packet (EOP) flags are set. Otherwise,
the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the
software application and is not altered by the EMAC.
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Architecture
2.5.4.7 End of Packet (EOP) Flag
When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In
the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the
descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software
application and is not altered by the EMAC.
2.5.4.8 Ownership (OWNER) Flag
When set, this flag indicates that all the descriptors for the given packet (from SOP to EOP) are currently
owned by the EMAC. This flag is set by the software application on the SOP packet descriptor before
adding the descriptor to the transmit descriptor queue. For a single fragment packet, the SOP, EOP, and
OWNER flags are all set. The OWNER flag is cleared by the EMAC once it is finished with all the
descriptors for the given packet. Note that this flag is valid on SOP descriptors only.
2.5.4.9 End of Queue (EOQ) Flag
When set, this flag indicates that the descriptor in question was the last descriptor in the transmit queue
for a given transmit channel, and that the transmitter has halted. This flag is initially cleared by the
software application prior to adding the descriptor to the transmit queue. This bit is set by the EMAC when
the EMAC identifies that a descriptor is the last for a given packet (the EOP flag is set), and there are no
more descriptors in the transmit list (next descriptor pointer is NULL).
The software application can use this bit to detect when the EMAC transmitter for the corresponding
channel has halted. This is useful when the application appends additional packet descriptors to a transmit
queue list that is already owned by the EMAC. Note that this flag is valid on EOP descriptors only.
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2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag
This flag is used when a transmit queue is being torn down, or aborted, instead of allowing it to be
transmitted. This would happen under device driver reset or shutdown conditions. The EMAC sets this bit
in the SOP descriptor of each packet as it is aborted from transmission.
Note that this flag is valid on SOP descriptors only. Also note that only the first packet in an unsent list has
the TDOWNCMPLT flag set. Subsequent descriptors are not processed by the EMAC.
2.5.4.11 Pass CRC (PASSCRC) Flag
This flag is set by the software application in the SOP packet descriptor before it adds the descriptor to the
transmit queue. Setting this bit indicates to the EMAC that the 4 byte Ethernet CRC is already present in
the packet data, and that the EMAC should not generate its own version of the CRC.
When the CRC flag is cleared, the EMAC generates and appends the 4-byte CRC. The buffer length and
packet length fields do not include the CRC bytes. When the CRC flag is set, the 4-byte CRC is supplied
by the software application and is already appended to the end of the packet data. The buffer length and
packet length fields include the CRC bytes, as they are part of the valid packet data. Note that this flag is
valid on SOP descriptors only.
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2.5.5 Receive Buffer Descriptor Format
A receive (RX) buffer descriptor (Figure 8) is a contiguous block of four 32-bit data words aligned on a
32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer
descriptor described by a C structure.
2.5.5.1 Next Descriptor Pointer
This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive
queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero,
then the current buffer is the last buffer in the queue. The software application must set this value prior to
adding the descriptor to the active receive list. This pointer is not altered by the EMAC.
The value of pNext should never be altered once the descriptor is in an active receive queue, unless its
current value is NULL. If the pNext pointer is initially NULL, and more empty buffers can be added to the
pool, the software application may alter this pointer to point to a newly appended descriptor. The EMAC
will use the new pointer value and proceed to the next descriptor unless the pNext value has already been
read. In this latter case, the receiver will halt the receive channel in question, and the software application
may restart it at that time. The software can detect this case by checking for an end of queue (EOQ)
condition flag on the updated packet descriptor when it is returned by the EMAC.
2.5.5.2 Buffer Pointer
The buffer pointer is the byte-aligned memory address of the memory buffer associated with the buffer
descriptor. The software application must set this value prior to adding the descriptor to the active receive
list. This pointer is not altered by the EMAC.
Architecture
Figure 8. Receive Buffer Descriptor Format
Word 0
31 0
Next Descriptor Pointer
Word 1
31 0
Buffer Pointer
Word 2
31 16 15 0
Buffer Offset Buffer Length
Word 3
31 30 29 28 27 26 25 24
SOP EOP OWNER EOQ TDOWNCMPLT PASSCRC JABBER OVERSIZE
23 22 21 20 19 18 17 16
FRAGMENT UNDERSIZED CONTROL OVERRUN CODEERROR ALIGNERROR CRCERROR NOMATCH
15 0
Packet Length
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Architecture
Example 2. Receive Buffer Descriptor in C Structure Format
/*
// EMAC Descriptor
//
// The following is the format of a single buffer descriptor
// on the EMAC.
*/
typedef struct _EMAC_Desc {
struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */
Uint8 *pBuffer; /* Pointer to data buffer */
Uint32 BufOffLen; /* Buffer Offset(MSW) and Length(LSW) */
Uint32 PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */
} EMAC_Desc;
/* Packet Flags */
#define EMAC_DSC_FLAG_SOP 0x80000000u
#define EMAC_DSC_FLAG_EOP 0x40000000u
#define EMAC_DSC_FLAG_OWNER 0x20000000u
#define EMAC_DSC_FLAG_EOQ 0x10000000u
#define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u
#define EMAC_DSC_FLAG_PASSCRC 0x04000000u
#define EMAC_DSC_FLAG_JABBER 0x02000000u
#define EMAC_DSC_FLAG_OVERSIZE 0x01000000u
#define EMAC_DSC_FLAG_FRAGMENT 0x00800000u
#define EMAC_DSC_FLAG_UNDERSIZED 0x00400000u
#define EMAC_DSC_FLAG_CONTROL 0x00200000u
#define EMAC_DSC_FLAG_OVERRUN 0x00100000u
#define EMAC_DSC_FLAG_CODEERROR 0x00080000u
#define EMAC_DSC_FLAG_ALIGNERROR 0x00040000u
#define EMAC_DSC_FLAG_CRCERROR 0x00020000u
#define EMAC_DSC_FLAG_NOMATCH 0x00010000u
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2.5.5.3 Buffer Offset
This 16-bit field must be initialized to zero by the software application before adding the descriptor to a
receive queue.
Whether or not this field is updated depends on the setting of the RXBUFFEROFFSET register. When the
offset register is set to a non-zero value, the received packet is written to the packet buffer at an offset
given by the value of the register, and this value is also written to the buffer offset field of the descriptor.
When a packet is fragmented over multiple buffers because it does not fit in the first buffer supplied, the
buffer offset only applies to the first buffer in the list, which is where the start of packet (SOP) flag is set in
the corresponding buffer descriptor. In other words, the buffer offset field is only updated by the EMAC on
SOP descriptors.
The range of legal values for the BUFFEROFFSET register is 0 to (Buffer Length – 1) for the smallest
value of buffer length for all descriptors in the list.
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2.5.5.4 Buffer Length
This 16-bit field is used for two purposes:
• Before the descriptor is first placed on the receive queue by the application software, the buffer length
field is first initialized by the software to have the physical size of the empty data buffer pointed to by
the buffer pointer field.
• After the empty buffer has been processed by the EMAC and filled with received data bytes, the buffer
length field is updated by the EMAC to reflect the actual number of valid data bytes written to the
buffer.
2.5.5.5 Packet Length
This 16-bit field specifies the number of data bytes in the entire packet. This value is initialized to zero by
the software application for empty packet buffers. The value is filled in by the EMAC on the first buffer
used for a given packet. This is signified by the EMAC setting a start of packet (SOP) flag. The packet
length is set by the EMAC on all SOP buffer descriptors.
2.5.5.6 Start of Packet (SOP) Flag
When set, this flag indicates that the descriptor points to a packet buffer that is the start of a new packet.
In the case of a single fragment packet, both the SOP and end of packet (EOP) flags are set. Otherwise,
the descriptor pointing to the last packet buffer for the packet has the EOP flag set. This flag is initially
cleared by the software application before adding the descriptor to the receive queue. This bit is set by the
EMAC on SOP descriptors.
Architecture
2.5.5.7 End of Packet (EOP) Flag
When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In
the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the
descriptor pointing to the last packet buffer for the packet has the EOP flag set. This flag is initially cleared
by the software application before adding the descriptor to the receive queue. This bit is set by the EMAC
on EOP descriptors.
2.5.5.8 Ownership (OWNER) Flag
When set, this flag indicates that the descriptor is currently owned by the EMAC. This flag is set by the
software application before adding the descriptor to the receive descriptor queue. This flag is cleared by
the EMAC once it is finished with a given set of descriptors, associated with a received packet. The flag is
updated by the EMAC on SOP descriptor only. So when the application identifies that the OWNER flag is
cleared on an SOP descriptor, it may assume that all descriptors up to and including the first with the EOP
flag set have been released by the EMAC. (Note that in the case of single buffer packets, the same
descriptor will have both the SOP and EOP flags set.)
2.5.5.9 End of Queue (EOQ) Flag
When set, this flag indicates that the descriptor in question was the last descriptor in the receive queue for
a given receive channel, and that the corresponding receiver channel has halted. This flag is initially
cleared by the software application prior to adding the descriptor to the receive queue. This bit is set by
the EMAC when the EMAC identifies that a descriptor is the last for a given packet received (also sets the
EOP flag), and there are no more descriptors in the receive list (next descriptor pointer is NULL).
The software application can use this bit to detect when the EMAC receiver for the corresponding channel
has halted. This is useful when the application appends additional free buffer descriptors to an active
receive queue. Note that this flag is valid on EOP descriptors only.
2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag
This flag is used when a receive queue is being torn down, or aborted, instead of being filled with received
data. This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the
descriptor of the first free buffer when the tear down occurs. No additional queue processing is performed.
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2.5.5.11 Pass CRC (PASSCRC) Flag
This flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-byte CRC.
This flag should be cleared by the software application before submitting the descriptor to the receive
queue.
2.5.5.12 Jabber Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet is a jabber frame and was
not discarded because the RXCEFEN bit was set in the RXMBPENABLE. Jabber frames are frames that
exceed the RXMAXLEN in length, and have CRC, code, or alignment errors.
2.5.5.13 Oversize Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet is an oversized frame and
was not discarded because the RXCEFEN bit was set in the RXMBPENABLE.
2.5.5.14 Fragment Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet is only a packet fragment
and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE.
2.5.5.15 Undersized Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet is undersized and was
not discarded because the RXCSFEN bit was set in the RXMBPENABLE.
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2.5.5.16 Control Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet is an EMAC control frame
and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE.
2.5.5.17 Overrun Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet was aborted due to a
receive overrun.
2.5.5.18 Code Error (CODEERROR) Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet contained a code error
and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE.
2.5.5.19 Alignment Error (ALIGNERROR) Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet contained an alignment
error and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE.
2.5.5.20 CRC Error (CRCERROR) Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet contained a CRC error
and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE.
2.5.5.21 No Match (NOMATCH) Flag
This flag is set by the EMAC in the SOP buffer descriptor, if the received packet did not pass any of the
EMAC’s address match criteria and was not discarded because the RXCAFEN bit was set in the
RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the
EMAC is in promiscuous mode.
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Arbiter and
bus switches
CPU
DMA Controllers
8K byte
descriptor
memory
Configuration
registers
Interrupt
logic
Interrupts
to CPU
EMAC interrupts
MDIO interrupts
Configuration bus
Transmit and Receive
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2.6 EMAC Control Module
The EMAC control module (Figure 9) interfaces the EMAC and MDIO modules to the rest of the system,
and also provides a local memory space to hold EMAC packet buffer descriptors. Local memory is used to
help avoid contention with device memory spaces. Other functions include the bus arbiter, and interrupt
logic control.
Architecture
Figure 9. EMAC Control Module Block Diagram
2.6.1 Internal Memory
2.6.2 Bus Arbiter
The EMAC control module includes 8K bytes of internal memory (CPPI buffer descriptor memory). The
internal memory block is essential for allowing the EMAC to operate more independently of the CPU. It
also prevents memory underflow conditions when the EMAC issues read or write requests to descriptor
memory. (Memory accesses to read or write the actual Ethernet packet data are protected by the EMAC's
internal FIFOs).
A descriptor is a 16-byte memory structure that holds information about a single Ethernet packet buffer,
which may contain a full or partial Ethernet packet. Thus with the 8K memory block provided for descriptor
storage, the EMAC module can send and received up to a combined 512 packets before it needs to be
serviced by application or driver software.
The EMAC control module bus arbiter operates transparently to the rest of the system. It is used:
• To arbitrate between the CPU and EMAC buses for access to internal descriptor memory.
• To arbitrate between internal EMAC buses for access to system memory.
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Architecture
2.6.3 Interrupt Control
Interrupt conditions generated by the EMAC and MDIO modules are combined into four interrupt signals
that are routed to three independent interrupt cores in the EMAC control module; the interrupt cores then
relay the interrupt signals to the CPU interrupt controller. The EMAC control module uses two sets of
registers to control the interrupt signals to the CPU:
• CnRXTHRESHEN, CnRXEN, CnTXEN, and CnMISCEN registers enable the interrupt core pulse
signals that are mapped to the CPU interrupt controller
• INTCONTROL, CnRXIMAX, and CnTXIMAX registers enable interrupt pacing to limit the number of
interrupt pulses generated per millisecond
Interrupts must be acknowledged by writing the appropriate value to the EMAC End-Of-Interrupt Vector
(MACEOIVECTOR). The MACEOIVECTOR behaves as an interrupt pulse interlock -- once the EMAC
control module has issued an interrupt pulse to the CPU, it will not generate further pulses of the same
type until the original pulse has been acknowledged.
2.7 MDIO Module
The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet
Media Access Controller (EMAC). The device supports a single PHY being connected to the EMAC at any
given time. The MDIO module is designed to allow almost transparent operation of the MDIO interface
with little maintenance from the CPU.
The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the
system. Once a PHY device has been detected, the MDIO module reads the MDIO PHY link status
register (LINK) to monitor the PHY link state. Link change events are stored in the MDIO module, which
can interrupt the CPU. This storing of the events allows the CPU to poll the link status of the PHY device
without continuously performing MDIO module accesses. However, when the CPU must access the MDIO
module for configuration and negotiation, the MDIO module performs the MDIO read or write operation
independent of the CPU. This independent operation allows the processor to poll for completion or
interrupt the CPU once the operation has completed.
The MDIO module does not support the "Clause 45" interface.
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2.7.1 MDIO Module Components
The MDIO module (Figure 10) interfaces to the PHY components through two MDIO pins (MDIO_CLK and
MDIO), and to the CPU through the EMAC control module and the configuration bus. The MDIO module
consists of the following logical components:
• MDIO clock generator
• Global PHY detection and link state monitoring
• Active PHY monitoring
• PHY register user access
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