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TMS320C6748

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SPRS590B–JUNE 2009–REVISED AUGUST 2010

TMS320C6748 Fixed/Floating-Point DSP

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1 TMS320C6748 Fixed/Floating-Point DSP

1.1 Features

• Highlights – 375/456-MHz C674x Fixed/Floating-Point

VLIW DSP – Six ALU (32-/40-Bit) Functional Units

– Enhanced Direct-Memory-Access Controller • Supports 32-Bit Integer, SP (IEEE Single

(EDMA3) Precision/32-Bit) and DP (IEEE Double – Serial ATA (SATA) Controller – DDR2/Mobile DDR Memory Controller – Two Multimedia Card (MMC)/Secure Digital

(SD) Card Interface – LCD Controller – Video Port Interface (VPIF) – 10/100 Mb/s Ethernet MAC (EMAC): – Programmable Real-Time Unit Subsystem – Three Configurable UART Modules – USB 1.1 OHCI (Host) With Integrated PHY – USB 2.0 OTG Port With Integrated PHY – One Multichannel Audio Serial Port – Two Multichannel Buffered Serial Ports

• 375/456-MHz C674x VLIW DSP

• C674x Instruction Set Features – Superset of the C67x+™ and C64x+™ ISAs – Up to 3648/2746 C674x MIPS/MFLOPS – Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions

• C674x Two Level Cache Memory Architecture – 32K-Byte L1P Program RAM/Cache – 32K-Byte L1D Data RAM/Cache – 256K -Byte L2 Unified Mapped RAM/Cache – Flexible RAM/Cache Partition (L1 and L2)

• Enhanced Direct-Memory-Access Controller 3 (EDMA3):

– 2 Channel Controllers – 3 Transfer Controllers – 64 Independent DMA Channels – 16 Quick DMA Channels – Programmable Transfer Burst Size

• TMS320C674x Floating-Point VLIW DSP Core – Load-Store Architecture With Non-Aligned

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TMS320C6000, C6000 are trademarks of Texas Instruments.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phaseof development. Characteristic dataand other specifications are subjectto change without notice.

Support

– 64 General-Purpose Registers (32 Bit)

Precision/64-Bit) Floating Point

• Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks

• Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle

– Two Multiply Functional Units

• Mixed-Precision IEEE Floating Point Multiply Supported up to:

– 2 SP x SP -> SP Per Clock – 2 SP x SP -> DP Every Two Clocks – 2 SP x DP -> DP Every Three Clocks – 2 DP x DP -> DP Every Four Clocks

• Fixed Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples

– Instruction Packing Reduces Code Size – All Instructions Conditional – Hardware Support for Modulo Loop

Operation – Protected Mode Operation – Exceptions Support for Error Detection and

Program Redirection

• Software Support – TI DSP/BIOS™ – Chip Support Library and DSP Library

• 128K-Byte RAM Memory

• 1.8V or 3.3V LVCMOS IOs (except for USB and DDR2 interfaces)

• Two External Memory Interfaces: – EMIFA

• NOR (8-/16-Bit-Wide Data)

• NAND (8-/16-Bit-Wide Data)

• 16-Bit SDRAM With 128 MB Address Space

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– DDR2/Mobile DDR Memory Controller – Telecom Interfaces (ST-Bus, H100)

• 16-Bit DDR2 SDRAM With 512 MB – 128-channel TDM Address Space or

• 16-Bit mDDR SDRAM With 256 MB Address Space

• Three Configurable 16550 type UART Modules: – With Modem Control Signals – 16-byte FIFO – 16x or 13x Oversampling Option

• LCD Controller

• Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects

• Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Interfaces

• Two Master/Slave Inter-Integrated Circuit (I2C Bus™)

• One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth

• Programmable Real-Time Unit Subsystem (PRUSS)

– Two Independent Programmable Realtime

Unit (PRU) Cores

• 32-Bit Load/Store RISC architecture

• 4K Byte instruction RAM per core

• 512 Bytes data RAM per core

• PRU Subsystem (PRUSS) can be disabled via software to save power

• Register 30 of each PRU is exported from the subsystem in addition to the normal R31 output of the PRU cores.

– Standard power management mechanism

• Clock gating

• Entire subsystem under a single PSC clock gating domain

– Dedicated interrupt controller

– FIFO buffers for Transmit and Receive

• 10/100 Mb/s Ethernet MAC (EMAC): – IEEE 802.3 Compliant – MII Media Independent Interface – RMII Reduced Media Independent Interface – Management Data I/O (MDIO) Module

• Video Port Interface (VPIF): – Two 8-bit SD (BT.656), Single 16-bit or Single

Raw (8-/10-/12-bit) Video Capture Channels

– Two 8-bit SD (BT.656), Single 16-bit Video

Display Channels

• Universal Parallel Port (uPP): – High-Speed Parallel Interface to FPGAs and

Data Converters

– Data Width on Each of Two Channels is 8- to

16-bit Inclusive – Single Data Rate or Dual Data Rate Transfers – Supports Multiple Interfaces with START,

ENABLE and WAIT Controls

• Serial ATA (SATA) Controller: – Supports SATA I (1.5 Gbps) and SATA II (3.0

Gbps)

– Supports all SATA Power Management

Features

– Hardware-Assisted Native Command

Queueing (NCQ) for up to 32 Entries

– Supports Port Multiplier and

Command-Based Switching

• Real-Time Clock With 32 KHz Oscillator and Separate Power Rail

• Three 64-Bit General-Purpose Timers (Each configurable as Two 32-Bit Timers)

• One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose

– Dedicated switched central resource Timers)

• USB 1.1 OHCI (Host) With Integrated PHY • Two Enhanced Pulse Width Modulators (USB1) (eHRPWM):

• USB 2.0 OTG Port With Integrated PHY (USB0) – Dedicated 16-Bit Time-Base Counter With – USB 2.0 High-/Full-Speed Client – USB 2.0 High-/Full-/Low-Speed Host – End Point 0 (Control) – End Points 1,2,3,4 (Control, Bulk, Interrupt or

ISOC) Rx and Tx

• One Multichannel Audio Serial Port: – Two Clock Zones and 16 Serial Data Pins – Supports TDM, I2S, and Similar Formats – DIT-Capable – FIFO buffers for Transmit and Receive

• Two Multichannel Buffered Serial Ports: – Supports TDM, I2S, and Similar Formats – AC97 Audio Codec Interface

Period And Frequency Control

– 6 Single Edge, 6 Dual Edge Symmetric or 3

Dual Edge Asymmetric Outputs – Dead-Band Generation – PWM Chopping by High-Frequency Carrier – Trip Zone Input

• Three 32-Bit Enhanced Capture Modules (eCAP):

– Configurable as 3 Capture Inputs or 3

Auxiliary Pulse Width Modulator (APWM) outputs

– Single Shot Capture of up to Four Event

Time-Stamps

• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)

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[ZCE Suffix], 0.65-mm Ball Pitch Temperature

• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) • Community Resources [ZWT Suffix], 0.80-mm Ball Pitch

• Commercial, Extended or Industrial

– TI E2E Community – TI Embedded Processors Wiki

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1.2 Trademarks

DSP/BIOS, TMS320C6000, C6000, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

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1.3 Description

The device is a Low-power applications processor based on a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller.

SPRS590B–JUNE 2009–REVISED AUGUST 2010

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on each of two channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE and WAIT signals to provide control for a variety of data converters.

A Video Port Interface (VPIF) is included providing a flexible video input/output port. The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Switched Central Resource (SCR)

BOOT ROM

256KB L2 RAM

32KB

L1 RAM

32KB

L1 Pgm

AET

C674x™

DSP CPU

DSP Subsystem

JTAG Interface

System Control

Input

Clock(s)

Power/Sleep

Controller

Multiplexing

PLL/Clock Generator

w/OSC

GeneralPurpose

Timer (x3)

Serial Interfaces

Audio Ports

McASP w/FIFO

DMA

Peripherals

Display Internal Memory

LCD

Ctlr

128KB

RAM

External Memory InterfacesConnectivity

EDMA3

(x2)

Control Timers

ePWM

(x2)

eCAP

(x3)

EMIFA(8b/16B)

NAND/Flash 16b SDRAM

DDR2/MDDR

Controller

RTC/

32-kHz

OSC

I C

(x2)

SPI (x2)

UART

(x3)

McBSP

(x2)

Video

VPIF

Parallel Port

uPP

EMAC 10/100

(MII/RMII)

MDIO

USB1.1

OHCI Ctlr

PHY

USB2.0

OTG Ctlr

PHY

HPI

MMC/SD

(8b) (x2)

SATA

Customizable Interface

PRU Subsystem

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SPRS590B–JUNE 2009–REVISED AUGUST 2010

1.4 Functional Block Diagram

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Figure 1-1. Functional Block Diagram

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1 TMS320C6748 Fixed/Floating-Point DSP ........... 1 6.6 Clock PLLs ......................................... 90

1.1 Features .............................................. 1

1.2 Trademarks .......................................... 4

1.3 Description ........................................... 5

1.4 Functional Block Diagram ............................ 6

2 Revision History ......................................... 8

3 Device Overview ........................................ 9

3.1 Documentation Support .............................. 9

3.2 Device Characteristics ............................... 9

3.3 Device Compatibility ................................ 11

3.4 DSP Subsystem .................................... 12

3.5 Memory Map Summary ............................. 23

3.6 Pin Assignments .................................... 27

3.7 Pin Multiplexing Control ............................ 30

3.8 Terminal Functions ................................. 31

3.9 Unused Pin Configurations ......................... 72

4 Device Configuration ................................. 75

4.1 Boot Modes ......................................... 75

4.2 SYSCFG Module ................................... 75

4.3 Pullup/Pulldown Resistors .......................... 78

5 Device Operating Conditions ....................... 79

5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range

(Unless Otherwise Noted) ................................. 79

5.2 Recommended Operating Conditions .............. 80

5.3 Notes on Recommended Power-On Hours (POH)

...................................................... 82

5.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction

Temperature (Unless Otherwise Noted) ............ 83

6 Peripheral Information and Electrical

Specifications .......................................... 84

6.1 Parameter Information .............................. 84

6.2 Recommended Clock and Control Signal Transition

Behavior ............................................ 85

6.3 Power Supplies ..................................... 85

6.4 Reset ............................................... 86

6.5 Crystal Oscillator or External Clock Input .......... 89

6.7 Interrupts ............................................ 95

6.8 Power and Sleep Controller (PSC) ................. 99

6.9 EDMA ............................................. 104

6.10 External Memory Interface A (EMIFA) ............ 110

6.11 DDR2/mDDR Controller ........................... 121

6.12 Memory Protection Units .......................... 134

6.13 MMC / SD / SDIO (MMCSD0, MMCSD1) ......... 137

6.14 Serial ATA Controller (SATA) ..................... 140

6.15 Multichannel Audio Serial Port (McASP) .......... 145

6.16 Multichannel Buffered Serial Port (McBSP) ....... 154

6.17 Serial Peripheral Interface Ports (SPI0, SPI1) .... 164

6.18 Inter-Integrated Circuit Serial Ports (I2C) ......... 185

6.19 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 189

6.20 Universal Serial Bus OTG Controller (USB0)

[USB2.0 OTG] ..................................... 191

6.21 Universal Serial Bus Host Controller (USB1)

[USB1.1 OHCI] .................................... 198

6.22 Ethernet Media Access Controller (EMAC) ....... 199

6.23 Management Data Input/Output (MDIO) .......... 207

6.24 LCD Controller (LCDC) ............................ 209

6.25 Host-Port Interface (UHPI) ........................ 224

6.26 Universal Parallel Port (uPP) ...................... 232

6.27 Video Port Interface (VPIF) ....................... 237

6.28 Enhanced Capture (eCAP) Peripheral ............ 243

6.29 Enhanced High-Resolution Pulse-Width Modulator

(eHRPWM) ........................................ 246

6.30 Timers ............................................. 251

6.31 Real Time Clock (RTC) ........................... 253

6.32 General-Purpose Input/Output (GPIO) ............ 256

6.33 Programmable Real-Time Unit Subsystem (PRUSS)

..................................................... 260

6.34 Emulation Logic ................................... 263

7 Mechanical Packaging and Orderable

Information ............................................ 267

7.1 Device Support .................................... 267

7.2 Thermal Data for ZCE Package ................... 269

7.3 Thermal Data for ZWT Package .................. 270

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2 Revision History

NOTE: This is a placeholder for the Revision History Table for future revisions of the document. This data manual revision history highlights the changes made to the SPRS590A device-specific data

manual to make it an SPRS590B revision.

Table 2-1. Revision History

ADDITIONS/MODIFICATIONS/DELETIONS

Global - Added MPU Content Global - Replaced all "CLKIN" references with "OSCIN" Global - Updated td(SCSL_SPC)S min from P to 2P Global - Made changes in the document to reflect the following detail.

"The DSP L2 ROM is used for boot purposes and cannot be programmed with application code". Global - Updated the pin map graphic to fix typos. Global -

• All instances of EMU[0] updated to EMU0

• All instances of EMU[1] updated toEMU1

• All instances of UART1_RTS updated to have an overbar

• All instances of UART2_RTS updated to have an overbar

• All instances of SPI1_SCS[0] updated to have an overbar

• All instances of EMA_CS[4] updated to have an overbar

• All instances of SPI1_ENA updated to have an overbar

• All instances of SATA_TXN updated to have an overbar

• All instances of LCD_AC_ENB_CS updated to have an overbar

• All instances of DDR_CS updated to have an overbar

• All instances of UHPI_HRDY updated to have an overbar

• All instances of UHPI_HDS1 updated to have an overbar

• All instances of UHPI_HCS updated to have an overbar Added Table 3-3 C674x L1/L2 Memory Protection Registers Added Section 3.9 Unused Pin Configurations Added Section 6.6.3- Dynamic Voltage and Frequency Scaling (DVFS) AddedSection 4.3 Pullup/Pulldown Resistors Added Section 6.14.3 - SATA Unused Signal Configuration Added sections -Section 6.14.2 - SATA Interface, Section 6.14.2.1 - SATA Interface Schematic, Section 6.14.2.2 - Compatible SATA

Components and Modes, Section 6.14.2.3 - PCB Stackup Specifications, Section 6.14.2.4 - Routing Specifications, Section 6.14.2.5 Coupling Capacitors, Section 6.14.2.6 - SATA Interface Clock Source requirements,

Updated the Nomenclature Graphic in Section 7.1.2

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3 Device Overview

3.1 Documentation Support

3.1.1 Related Documentation From Texas Instruments

The following documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.

DSP Reference Guides

SPRUG82 TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches

and describes how the two-level cache-based internal memory architecture in the TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.

SPRUFE8 TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU

architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added functionality and an expanded instruction set.

SPRS590B–JUNE 2009–REVISED AUGUST 2010

SPRUFK5 TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital

signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRUFK9 TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides

an overview and briefly describes the peripherals available on the device.

SPRUGJ7 TMS320C6748 DSP System Reference Guide .

3.2 Device Characteristics

Table 3-1 provides an overview of the device. The table shows significant features of the device, including

the capacity of on-chip RAM, peripherals, and the package type with pin count.

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HARDWARE FEATURES C6748

DDR2/mDDR Controller

EMIFA Flash Card Interface MMC and SD cards supported. EDMA3

Timers UART 3 (each with RTS and CTS flow control)

SPI 2 (Each with one hardware chip select)

Peripherals Not all peripherals pins

are available at the same time (for more detail, see the Device Configurations section).

On-Chip Memory

I2C 2 (both Master/Slave) Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers) Multichannel Buffered Serial Port [McBSP] 2 (each with transmit/receive, FIFO buffer, 16) 10/100 Ethernet MAC with Management Data I/O 1 (MII or RMII Interface)

eHRPWM eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs

UHPI 1 (16-bit multiplexed address/data) USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY General-Purpose Input/Output Port 9 banks of 16-bit LCD Controller 1 SATA Controller 1 (Support both SATA I and SATAII) Universal Parallel Port (uPP) 1 Video Port Interface (VPIF) 1 (video in and video out) PRU Subsystem (PRUSS) 2 Programmable PRU Cores Size (Bytes) 448KB RAM

Organization

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Table 3-1. Characteristics of C6748

DDR2, 16-bit bus width, up to 150 MHz

Mobile DDR, 16-bit bus width, up to 133 MHz

Asynchronous (8/16-bit bus width) RAM, Flash,

16-bit SDRAM, NOR, NAND

64 independent channels, 16 QDMA channels,

2 channel controllers, 3 transfer controllers

4 64-Bit General Purpose (each configurable as 2 separate

32-bit timers, one configurable as Watch Dog)

4 Single Edge, 4 Dual Edge Symmetric, or

2 Dual Edge Asymmetric Outputs

DSP

32KB L1 Program (L1P)/Cache (up to 32KB)

32KB L1 Data (L1D)/Cache (up to 32KB) 256KB Unified Mapped RAM/Cache (L2)

DSP Memories can be made accessible to EDMA3 and

other peripherals.

ADDITIONAL MEMORY

128KB RAM

C674x CPU ID + CPU Rev ID

C674x Megamodule Revision

JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F CPU Frequency MHz 674x DSP 375 MHz (1.2V) or 456 MHz (1.3V)

Voltage

Packages

Control Status Register (CSR.[31:16]) 0x1400

Revision ID Register (MM_REVID[15:0]) 0x0000

Core (V) I/O (V) 1.8V or 3.3 V

13 mm x 13 mm, 361-Ball 0.65 mm pitch, PBGA (ZCE)

16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT)

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1.2 V nominal for 375 MHz version

1.3 V nominal for 456 MHz version

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Table 3-1. Characteristics of C6748 (continued)

HARDWARE FEATURES C6748

Product Status

(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and

other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1)

Product Preview (PP), Advance Information (AI), or Production Data (PD)

375 MHz versions - PD

456 MHz versions - AI

3.3 Device Compatibility

The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both the C64x+ and C67x+ DSP families.

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Instruction Fetch

C674x

Fixed/Floating Point CPU

File A

File B

Cache Control

Memory Protect

Bandwidth Mgmt

L1P

256

Cache Control

Memory Protect

Bandwidth Mgmt

L1D

64 64

8 x 32

32K Bytes L1D RAM/

Cache

32K Bytes

L1P RAM/

Cache

256

Cache Control

Memory Protect

Bandwidth Mgmt

256K Bytes

L2 RAM

256

BOOT

ROM

256

CFG

MDMA SDMA

EMC

Power Down

Interrupt

Controller

IDMA

256

High

Performance

Switch Fabric

64 64

Configuration

Peripherals

Bus

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3.4 DSP Subsystem

The DSP Subsystem includes the following features:

• C674x DSP CPU

• 32KB L1 Program (L1P)/Cache (up to 32KB)

• 32KB L1 Data (L1D)/Cache (up to 32KB)

• 256KB Unified Mapped RAM/Cache (L2)

• Boot ROM (cannot be used for application code)

• Little endian

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Figure 3-1. C674x Megamodule Block Diagram

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3.4.1 C674x DSP CPU Description

The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core.

Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types.

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The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.

• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.

• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.

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• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRUFE8)

• TMS320C64x Technical Overview (literature number SPRU395)

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src2

.D1

.M1

.S1

.L1

long src

odd dst

src2

src1

even dst

odd dst

dst1

dst

src2

long src

DA1

ST1b

LD1b LD1a

ST1a

Data path A

Odd

file A

(A1, A3,

A5...A31)

Odd

file B

(B1, B3,

B5...B31)

.D2

src1

dst

src2

DA2

LD2a LD2b

src2

.M2

src1

dst1

.S2

src1

even dst

long src

odd dst

ST2a ST2b

long src

.L2

even dst

odd dst

src1

Data path B

Control Register

32 MSB 32 LSB

dst2

(A)

32 MSB 32 LSB

32 LSB

32 MSB

32 LSB

32 MSB

dst2

(B)

(B) (A)

(C)

Even

file A

(A0, A2,

A4...A30)

Even

file B

(B0, B2,

B4...B30)

(D)

A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

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Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths

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3.4.2 DSP Memory Mapping

The DSP memory map is shown in . By default the DSP also has access to most on and off chip memory areas. Additionally, the DSP megamodule includes the capability to limit access to its internal memories through

its SDMA port; without needing an external MPU unit.

3.4.2.1 External Memories

The DSP has access to the following External memories:

• Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)

• SDRAM (DDR2)

3.4.2.2 DSP Internal Memories

The DSP has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

3.4.2.3 C674x CPU

The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both.

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Table 3-2 shows a memory map of the C674x CPU cache registers for the device.

Table 3-2. C674x Cache Registers

Byte Address Register Name Register Description

0x0184 0000 L2CFG L2 Cache configuration register 0x0184 0020 L1PCFG L1P Size Cache configuration register 0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register 0x0184 0040 L1DCFG L1D Size Cache configuration register 0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register

0x0184 0048 - 0x0184 0FFC - Reserved

0x0184 1000 EDMAWEIGHT L2 EDMA access control register

0x0184 1004 - 0x0184 1FFC - Reserved

0x0184 2000 L2ALLOC0 L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3

0x0184 2010 - 0x0184 3FFF - Reserved

0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 0x0184 4018 L2IBAR L2 invalidate base address register 0x0184 401C L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register

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Table 3-2. C674x Cache Registers (continued)

Byte Address Register Name Register Description

0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register 0x0184 404C L1DIWC L1D invalidate word count register

0x0184 4050 - 0x0184 4FFF - Reserved

0x0184 5000 L2WB L2 writeback all register 0x0184 5004 L2WBINV L2 writeback invalidate all register 0x0184 5008 L2INV L2 Global Invalidate without writeback

0x0184 500C - 0x0184 5027 - Reserved

0x0184 5028 L1PINV L1P Global Invalidate

0x0184 502C - 0x0184 5039 - Reserved

0x0184 5040 L1DWB L1D Global Writeback 0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate 0x0184 5048 L1DINV L1D Global Invalidate without writeback

0x0184 8000 – 0x0184 80FF MAR0 - MAR63 Reserved 0x0000 0000 – 0x3FFF FFFF 0x0184 8100 – 0x0184 817F MAR64 – MAR95

0x0184 8180 – 0x0184 8187 MAR96 - MAR97

0x0184 8188 – 0x0184 818F MAR98 – MAR99

0x0184 8190 – 0x0184 8197 MAR100 – MAR101

0x0184 8198 – 0x0184 819F MAR102 – MAR103

0x0184 81A0 – 0x0184 81FF MAR104 – MAR127 Reserved 0x6800 0000 – 0x7FFF FFFF

0x0184 8200 MAR128

0x0184 8204 – 0x0184 82FF MAR129 – MAR191 Reserved 0x8200 0000 – 0xBFFF FFFF 0x0184 8300 – 0x0184 837F MAR192 – MAR223 0x0184 8380 – 0x0184 83FF MAR224 – MAR255 Reserved 0xE000 0000 – 0xFFFF FFFF

Memory Attribute Registers for EMIFA SDRAM Data (CS0) External memory addresses 0x4000 0000 – 0x5FFF FFFF

Memory Attribute Registers for EMIFA Async Data (CS2) External memory addresses 0x6000 0000 – 0x61FF FFFF

Memory Attribute Registers for EMIFA Async Data (CS3) External memory addresses 0x6200 0000 – 0x63FF FFFF

Memory Attribute Registers for EMIFA Async Data (CS4) External memory addresses 0x6400 0000 – 0x65FF FFFF

Memory Attribute Registers for EMIFA Async Data (CS5) External memory addresses 0x6600 0000 – 0x67FF FFFF

Memory Attribute Register for RAM External memory addresses 0x8000 0000 – 0x8001 FFFF

Reserved 0x8002 0000 – 0x81FF FFFF

Memory Attribute Registers for DDR2 Data (CS2) External memory addresses 0xC000 0000 – 0xDFFF FFFF

Table 3-3. C674x L1/L2 Memory Protection Registers

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 A000 L2MPFAR L2 memory protection fault address register 0x0184 A004 L2MPFSR L2 memory protection fault status register 0x0184 A008 L2MPFCR L2 memory protection fault command register

0x0184 A00C - 0x0184 A0FF - Reserved

0x0184 A100 L2MPLK0 L2 memory protection lock key bits [31:0] 0x0184 A104 L2MPLK1 L2 memory protection lock key bits [63:32] 0x0184 A108 L2MPLK2 L2 memory protection lock key bits [95:64]

0x0184 A10C L2MPLK3 L2 memory protection lock key bits [127:96]

0x0184 A110 L2MPLKCMD L2 memory protection lock key command register 0x0184 A114 L2MPLKSTAT L2 memory protection lock key status register

0x0184 A118 - 0x0184 A1FF - Reserved

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 A200 L2MPPA0

0x0184 A204 L2MPPA1

0x0184 A208 L2MPPA2

0x0184 A20C L2MPPA3

0x0184 A210 L2MPPA4

0x0184 A214 L2MPPA5

0x0184 A218 L2MPPA6

0x0184 A21C L2MPPA7

0x0184 A220 L2MPPA8

0x0184 A224 L2MPPA9

0x0184 A228 L2MPPA10

0x0184 A22C L2MPPA11

0x0184 A230 L2MPPA12

0x0184 A234 L2MPPA13

0x0184 A238 L2MPPA14

0x0184 A23C L2MPPA15

0x0184 A240 L2MPPA16

0x0184 A244 L2MPPA17

0x0184 A248 L2MPPA18

0x0184 A24C L2MPPA19

0x0184 A250 L2MPPA20

0x0184 A254 L2MPPA21

0x0184 A258 L2MPPA22

0x0184 A25C L2MPPA23

0x0184 A260 L2MPPA24

0x0184 A264 L2MPPA25

0x0184 A268 L2MPPA26

0x0184 A26C L2MPPA27

L2 memory protection page attribute register 0 (controls memory address 0x0080 0000 - 0x0080 1FFF)

L2 memory protection page attribute register 1 (controls memory address 0x0080 2000 - 0x0080 3FFF)

L2 memory protection page attribute register 2 (controls memory address 0x0080 4000 - 0x0080 5FFF)

L2 memory protection page attribute register 3 (controls memory address 0x0080 6000 - 0x0080 7FFF)

L2 memory protection page attribute register 4 (controls memory address 0x0080 8000 - 0x0080 9FFF)

L2 memory protection page attribute register 5 (controls memory address 0x0080 A000 - 0x0080 BFFF)

L2 memory protection page attribute register 6 (controls memory address 0x0080 C000 - 0x0080 DFFF)

L2 memory protection page attribute register 7 (controls memory address 0x0080 E000 - 0x0080 FFFF)

L2 memory protection page attribute register 8 (controls memory address 0x0081 0000 - 0x0081 1FFF)

L2 memory protection page attribute register 9 (controls memory address 0x0081 2000 - 0x0081 3FFF)

L2 memory protection page attribute register 10 (controls memory address 0x0081 4000 - 0x0081 5FFF)

L2 memory protection page attribute register 11 (controls memory address 0x0081 6000 - 0x0081 7FFF)

L2 memory protection page attribute register 12 (controls memory address 0x0081 8000 - 0x0081 9FFF)

L2 memory protection page attribute register 13 (controls memory address 0x0081 A000 - 0x0081 BFFF)

L2 memory protection page attribute register 14 (controls memory address 0x0081 C000 - 0x0081 DFFF)

L2 memory protection page attribute register 15 (controls memory address 0x0081 E000 - 0x0081 FFFF)

L2 memory protection page attribute register 16 (controls memory address 0x0082 0000 - 0x0082 1FFF)

L2 memory protection page attribute register 17 (controls memory address 0x0082 2000 - 0x0082 3FFF)

L2 memory protection page attribute register 18 (controls memory address 0x0082 4000 - 0x0082 5FFF)

L2 memory protection page attribute register 19 (controls memory address 0x0082 6000 - 0x0082 7FFF)

L2 memory protection page attribute register 20 (controls memory address 0x0082 8000 - 0x0082 9FFF)

L2 memory protection page attribute register 21 (controls memory address 0x0082 A000 - 0x0082 BFFF)

L2 memory protection page attribute register 22 (controls memory address 0x0082 C000 - 0x0082 DFFF)

L2 memory protection page attribute register 23 (controls memory address 0x0082 E000 - 0x0082 FFFF)

L2 memory protection page attribute register 24 (controls memory address 0x0083 0000 - 0x0083 1FFF)

L2 memory protection page attribute register 25 (controls memory address 0x0083 2000 - 0x0083 3FFF)

L2 memory protection page attribute register 26 (controls memory address 0x0083 4000 - 0x0083 5FFF)

L2 memory protection page attribute register 27 (controls memory address 0x0083 6000 - 0x0083 7FFF)

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 A270 L2MPPA28

0x0184 A274 L2MPPA29

0x0184 A278 L2MPPA30

0x0184 A27C L2MPPA31

0x0184 A280 L2MPPA32

0x0184 A284 L2MPPA33

0x0184 A288 L2MPPA34

0x0184 A28C L2MPPA35

0x0184 A290 L2MPPA36

0x0184 A294 L2MPPA37

0x0184 A298 L2MPPA38

0x0184 A29C L2MPPA39

0x0184 A2A0 L2MPPA40

0x0184 A2A4 L2MPPA41

0x0184 A2A8 L2MPPA42

0x0184 A2AC L2MPPA43

0x0184 A2B0 L2MPPA44

0x0184 A2B4 L2MPPA45

0x0184 A2B8 L2MPPA46

0x0184 A2BC L2MPPA47

0x0184 A2C0 L2MPPA48

0x0184 A2C4 L2MPPA49

0x0184 A2C8 L2MPPA50

0x0184 A2CC L2MPPA51

0x0184 A2D0 L2MPPA52

0x0184 A2D4 L2MPPA53

0x0184 A2D8 L2MPPA54

0x0184 A2DC L2MPPA55

L2 memory protection page attribute register 28 (controls memory address 0x0083 8000 - 0x0083 9FFF)

L2 memory protection page attribute register 29 (controls memory address 0x0083 A000 - 0x0083 BFFF)

L2 memory protection page attribute register 30 (controls memory address 0x0083 C000 - 0x0083 DFFF)

L2 memory protection page attribute register 31 (controls memory address 0x0083 E000 - 0x0083 FFFF)

L2 memory protection page attribute register 32 (controls memory address 0x0070 0000 - 0x0070 7FFF)

L2 memory protection page attribute register 33 (controls memory address 0x0070 8000 - 0x0070 FFFF)

L2 memory protection page attribute register 34 (controls memory address 0x0071 0000 - 0x0071 7FFF)

L2 memory protection page attribute register 35 (controls memory address 0x0071 8000 - 0x0071 FFFF)

L2 memory protection page attribute register 36 (controls memory address 0x0072 0000 - 0x0072 7FFF)

L2 memory protection page attribute register 37 (controls memory address 0x0072 8000 - 0x0072 FFFF)

L2 memory protection page attribute register 38 (controls memory address 0x0073 0000 - 0x0073 7FFF)

L2 memory protection page attribute register 39 (controls memory address 0x0073 8000 - 0x0073 FFFF)

L2 memory protection page attribute register 40 (controls memory address 0x0074 0000 - 0x0074 7FFF)

L2 memory protection page attribute register 41 (controls memory address 0x0074 8000 - 0x0074 FFFF)

L2 memory protection page attribute register 42 (controls memory address 0x0075 0000 - 0x0075 7FFF)

L2 memory protection page attribute register 43 (controls memory address 0x0075 8000 - 0x0075 FFFF)

L2 memory protection page attribute register 44 (controls memory address 0x0076 0000 - 0x0076 7FFF)

L2 memory protection page attribute register 45 (controls memory address 0x0076 8000 - 0x0076 FFFF)

L2 memory protection page attribute register 46 (controls memory address 0x0077 0000 - 0x0077 7FFF)

L2 memory protection page attribute register 47 (controls memory address 0x0077 8000 - 0x0077 FFFF)

L2 memory protection page attribute register 48 (controls memory address 0x0078 0000 - 0x0078 7FFF)

L2 memory protection page attribute register 49 (controls memory address 0x0078 8000 - 0x0078 FFFF)

L2 memory protection page attribute register 50 (controls memory address 0x0079 0000 - 0x0079 7FFF)

L2 memory protection page attribute register 51 (controls memory address 0x0079 8000 - 0x0079 FFFF)

L2 memory protection page attribute register 52 (controls memory address 0x007A 0000 - 0x007A 7FFF)

L2 memory protection page attribute register 53 (controls memory address 0x007A 8000 - 0x007A FFFF)

L2 memory protection page attribute register 54 (controls memory address 0x007B 0000 - 0x007B 7FFF)

L2 memory protection page attribute register 55 (controls memory address 0x007B 8000 - 0x007B FFFF)

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 A2E0 L2MPPA56

0x0184 A2E4 L2MPPA57

0x0184 A2E8 L2MPPA58

0x0184 A2EC L2MPPA59

0x0184 A2F0 L2MPPA60

0x0184 A2F4 L2MPPA61

0x0184 A2F8 L2MPPA62

0x0184 A2FC L2MPPA63

0x0184 A300 - 0x0184 A3FF - Reserved

0x0184 A400 L1PMPFAR L1P memory protection fault address register 0x0184 A404 L1PMPFSR L1P memory protection fault status register 0x0184 A408 L1PMPFCR L1P memory protection fault command register

0x0184 A40C - 0x0184 A4FF - Reserved

0x0184 A500 L1PMPLK0 L1P memory protection lock key bits [31:0] 0x0184 A504 L1PMPLK1 L1P memory protection lock key bits [63:32] 0x0184 A508 L1PMPLK2 L1P memory protection lock key bits [95:64]

0x0184 A50C L1PMPLK3 L1P memory protection lock key bits [127:96]

0x0184 A510 L1PMPLKCMD L1P memory protection lock key command register 0x0184 A514 L1PMPLKSTAT L1P memory protection lock key status register

0x0184 A518 - 0x0184 A5FF - Reserved

0x0184 A600 - 0x0184 A63F - Reserved

0x0184 A640 L1PMPPA16

0x0184 A644 L1PMPPA17

0x0184 A648 L1PMPPA18

0x0184 A64C L1PMPPA19

0x0184 A650 L1PMPPA20

0x0184 A654 L1PMPPA21

0x0184 A658 L1PMPPA22

0x0184 A65C L1PMPPA23

0x0184 A660 L1PMPPA24

0x0184 A664 L1PMPPA25

0x0184 A668 L1PMPPA26

L2 memory protection page attribute register 56 (controls memory address 0x007C 0000 - 0x007C 7FFF)

L2 memory protection page attribute register 57 (controls memory address 0x007C 8000 - 0x007C FFFF)

L2 memory protection page attribute register 58 (controls memory address 0x007D 0000 - 0x007D 7FFF)

L2 memory protection page attribute register 59 (controls memory address 0x007D 8000 - 0x007D FFFF)

L2 memory protection page attribute register 60 (controls memory address 0x007E 0000 - 0x007E 7FFF)

L2 memory protection page attribute register 61 (controls memory address 0x007E 8000 - 0x007E FFFF)

L2 memory protection page attribute register 62 (controls memory address 0x007F 0000 - 0x007F 7FFF)

L2 memory protection page attribute register 63 (controls memory address 0x007F 8000 - 0x007F FFFF)

(1)

L1P memory protection page attribute register 16 (controls memory address 0x00E0 0000 - 0x00E0 07FF)

L1P memory protection page attribute register 17 (controls memory address 0x00E0 0800 - 0x00E0 0FFF)

L1P memory protection page attribute register 18 (controls memory address 0x00E0 1000 - 0x00E0 17FF)

L1P memory protection page attribute register 19 (controls memory address 0x00E0 1800 - 0x00E0 1FFF)

L1P memory protection page attribute register 20 (controls memory address 0x00E0 2000 - 0x00E0 27FF)

L1P memory protection page attribute register 21 (controls memory address 0x00E0 2800 - 0x00E0 2FFF)

L1P memory protection page attribute register 22 (controls memory address 0x00E0 3000 - 0x00E0 37FF)

L1P memory protection page attribute register 23 (controls memory address 0x00E0 3800 - 0x00E0 3FFF)

L1P memory protection page attribute register 24 (controls memory address 0x00E0 4000 - 0x00E0 47FF)

L1P memory protection page attribute register 25 (controls memory address 0x00E0 4800 - 0x00E0 4FFF)

L1P memory protection page attribute register 26 (controls memory address 0x00E0 5000 - 0x00E0 57FF)

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(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C674x

megamaodule. These registers are not supported for this device.

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 A66C L1PMPPA27

0x0184 A670 L1PMPPA28

0x0184 A674 L1PMPPA29

0x0184 A678 L1PMPPA30

0x0184 A67C L1PMPPA31

0x0184 A67F – 0x0184 ABFF - Reserved

0x0184 AC00 L1DMPFAR L1D memory protection fault address register 0x0184 AC04 L1DMPFSR L1D memory protection fault status register 0x0184 AC08 L1DMPFCR L1D memory protection fault command register

0x0184 AC0C - 0x0184 ACFF - Reserved

0x0184 AD00 L1DMPLK0 L1D memory protection lock key bits [31:0] 0x0184 AD04 L1DMPLK1 L1D memory protection lock key bits [63:32] 0x0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64] 0x0184 AD0C L1DMPLK3 L1D memory protection lock key bits [127:96] 0x0184 AD10 L1DMPLKCMD L1D memory protection lock key command register 0x0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register

0x0184 AD18 - 0x0184 ADFF - Reserved

0x0184 AE00 - 0x0184 AE3F - Reserved

0x0184 AE40 L1DMPPA16

0x0184 AE44 L1DMPPA17

0x0184 AE48 L1DMPPA18

0x0184 AE4C L1DMPPA19

0x0184 AE50 L1DMPPA20

0x0184 AE54 L1DMPPA21

0x0184 AE58 L1DMPPA22

0x0184 AE5C L1DMPPA23

0x0184 AE60 L1DMPPA24

0x0184 AE64 L1DMPPA25

0x0184 AE68 L1DMPPA26

0x0184 AE6C L1DMPPA27

0x0184 AE70 L1DMPPA28

0x0184 AE74 L1DMPPA29

L1P memory protection page attribute register 27 (controls memory address 0x00E0 5800 - 0x00E0 5FFF)

L1P memory protection page attribute register 28 (controls memory address 0x00E0 6000 - 0x00E0 67FF)

L1P memory protection page attribute register 29 (controls memory address 0x00E0 6800 - 0x00E0 6FFF)

L1P memory protection page attribute register 30 (controls memory address 0x00E0 7000 - 0x00E0 77FF)

L1P memory protection page attribute register 31 (controls memory address 0x00E0 7800 - 0x00E0 7FFF)

(2)

L1D memory protection page attribute register 16 (controls memory address 0x00F0 0000 - 0x00F0 07FF)

L1D memory protection page attribute register 17 (controls memory address 0x00F0 0800 - 0x00F0 0FFF)

L1D memory protection page attribute register 18 (controls memory address 0x00F0 1000 - 0x00F0 17FF)

L1D memory protection page attribute register 19 (controls memory address 0x00F0 1800 - 0x00F0 1FFF)

L1D memory protection page attribute register 20 (controls memory address 0x00F0 2000 - 0x00F0 27FF)

L1D memory protection page attribute register 21 (controls memory address 0x00F0 2800 - 0x00F0 2FFF)

L1D memory protection page attribute register 22 (controls memory address 0x00F0 3000 - 0x00F0 37FF)

L1D memory protection page attribute register 23 (controls memory address 0x00F0 3800 - 0x00F0 3FFF)

L1D memory protection page attribute register 24 (controls memory address 0x00F0 4000 - 0x00F0 47FF)

L1D memory protection page attribute register 25 (controls memory address 0x00F0 4800 - 0x00F0 4FFF)

L1D memory protection page attribute register 26 (controls memory address 0x00F0 5000 - 0x00F0 57FF)

L1D memory protection page attribute register 27 (controls memory address 0x00F0 5800 - 0x00F0 5FFF)

L1D memory protection page attribute register 28 (controls memory address 0x00F0 6000 - 0x00F0 67FF)

L1D memory protection page attribute register 29 (controls memory address 0x00F0 6800 - 0x00F0 6FFF)

(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C674x

megamaodule. These registers are not supported for this device.

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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 AE78 L1DMPPA30

0x0184 AE7C L1DMPPA31

0x0184 AE80 – 0x0185 FFFF - Reserved

L1D memory protection page attribute register 30 (controls memory address 0x00F0 7000 - 0x00F0 77FF)

L1D memory protection page attribute register 31 (controls memory address 0x00F0 7800 - 0x00F0 7FFF)

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3.5 Memory Map Summary

Table 3-4. C6748 Top Level Memory Map

Start End Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC

Address Address Map Peripheral Mem

0x0000 0000 0x0000 0FFF 4K PRUSS Local -

0x0000 1000 0x006F FFFF 0x0070 0000 0x007F FFFF 1024K DSP L2 ROM 0x0080 0000 0x0083 FFFF 256K DSP L2 RAM 0x0084 0000 0x00DF

FFFF 0x00E0 0000 0x00E0 7FFF 32K DSP L1P RAM 0x00E0 8000 0x00EF

FFFF 0x00F0 0000 0x00F0 7FFF 32K DSP L1D RAM 0x00F0 8000 0x017F FFFF 0x0180 0000 0x0180 FFFF 64K DSP Interrupt Controller 0x0181 0000 0x0181 0FFF 4K DSP Powerdown Controller 0x0181 1000 0x0181 1FFF 4K DSP Security ID 0x0181 2000 0x0181 2FFF 4K DSP Revision ID 0x0181 3000 0x0181 FFFF 52K 0x0182 0000 0x0182 FFFF 64K DSP EMC 0x0183 0000 0x0183 FFFF 64K DSP Internal Reserved 0x0184 0000 0x0184 FFFF 64K DSP Memory System 0x0185 0000 0x01BB

FFFF

0x01BC 0000 0x01BC 4K

0FFF

0x01BC 1000 0x01BC 2K

17FF

0x01BC 1800 0x01BC 256

18FF

0x01BC 1900 0x01BF

FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC 0x01C0 8000 0x01C0 83FF 1K EDMA3 TC0 0x01C0 8400 0x01C0 87FF 1K EDMA3 TC1 0x01C0 8800 0x01C0

FFFF 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0 0x01C1 2000 0x01C1 3FFF 0x01C1 4000 0x01C1 4FFF 4K SYSCFG0 0x01C1 5000 0x01C1

FFFF 0x01C2 0000 0x01C2 0FFF 4K Timer0 0x01C2 1000 0x01C2 1FFF 4K Timer1 0x01C2 2000 0x01C2 2FFF 4K I2C 0 0x01C2 3000 0x01C2 3FFF 4K RTC

(1)

Address

Space

Mem Map Map

(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code

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Table 3-4. C6748 Top Level Memory Map (continued)

Start End Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC

Address Address Map Peripheral Mem

0x01C2 4000 0x01C3

FFFF 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 0x01C4 1000 0x01C4 1FFF 4K SPI 0 0x01C4 2000 0x01C4 2FFF 4K UART 0 0x01C4 3000 0x01CF

FFFF 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data 0x01D0 3000 0x01D0

BFFF

0x01D0 C000 0x01D0 4K UART 1

CFFF

0x01D0 D000 0x01D0 4K UART 2

DFFF

0x01D0 E000 0x01D0

FFFF 0x01D1 0000 0x01D1 07FF 2K McBSP0 0x01D1 0800 0x01D1 0FFF 2K McBSP0 FIFO Ctrl 0x01D1 1000 0x01D1 17FF 2K McBSP1 0x01D1 1800 0x01D1 1FFF 2K McBSP1 FIFO Ctrl 0x01D1 2000 0x01DF

FFFF 0x01E0 0000 0x01E0 FFFF 64K USB0 0x01E1 0000 0x01E1 0FFF 4K UHPI 0x01E1 1000 0x01E1 2FFF 0x01E1 3000 0x01E1 3FFF 4K LCD Controller 0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1) 0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2) 0x01E1 6000 0x01E1 6FFF 4K UPP 0x01E1 7000 0x01E1 7FFF 4K VPIF 0x01E1 8000 0x01E1 9FFF 8K SATA

0x01E1 A000 0x01E1 4K PLL Controller 1

AFFF

0x01E1 B000 0x01E1 4K MMCSD1

BFFF

0x01E1 C000 0x01E1 FFFF

0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM 0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers 0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers 0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port 0x01E2 5000 0x01E2 5FFF 4K USB1 0x01E2 6000 0x01E2 6FFF 4K GPIO 0x01E2 7000 0x01E2 7FFF 4K PSC 1 0x01E2 8000 0x01E2 8FFF 4K I2C 1 0x01E2 9000 0x01E2

BFFF

Mem Map Map

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Table 3-4. C6748 Top Level Memory Map (continued)

Start End Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC

Address Address Map Peripheral Mem

0x01E2 C000 0x01E2 4K SYSCFG1

0x01E2 D000 0x01E2 FFFF

0x01E3 0000 0x01E3 7FFF 32K EDMA3 CC1 0x01E3 8000 0x01E3 83FF 1K EDMA3 TC2 0x01E3 8400 0x01EF

0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 0x01F0 4000 0x01F0 5FFF 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 0x01F0 7000 0x01F0 7FFF 4K ECAP 1 0x01F0 8000 0x01F0 8FFF 4K ECAP 2 0x01F0 9000 0x01F0 BFFF

0x01F0 C000 0x01F0 4K Timer2

0x01F0 D000 0x01F0 4K Timer3

0x01F0 E000 0x01F0 EFFF 4K SPI1 0x01F0 F000 0x01F0 FFFF 0x01F1 0000 0x01F1 0FFF 4K McBSP0 FIFO Data 0x01F1 1000 0x01F1 1FFF 4K McBSP1 FIFO Data 0x01F1 2000 0x116F FFFF 0x1170 0000 0x117F FFFF 1024K DSP L2 ROM 0x1180 0000 0x1183 FFFF 256K DSP L2 RAM 0x1184 0000 0x11DF

0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM 0x11E0 8000 0x11EF

0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM 0x11F0 8000 0x3FFF

0x4000 0000 0x5FFF 512M EMIFA SDRAM data (CS0)

0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) 0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) 0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) 0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) 0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs 0x6800 8000 0x7FFF

0x8000 0000 0x8001 FFFF 128K On-chip RAM 0x8002 0000 0xAFFF

0xB000 0000 0xB000 7FFF 32K DDR2 Control Regs

CFFF

FFFF

CFFF

DFFF

(2)

FFFF

Mem Map Map

(2) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code

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Table 3-4. C6748 Top Level Memory Map (continued)

Start End Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC

Address Address Map Peripheral Mem

0xB000 8000 0xBFFF

FFFF 0xC000 0000 0xDFFF 512M DDR2 Data

FFFF 0xE000 0000 0xFFFC

FFFF

0xFFFD 0000 0xFFFD 64K

FFFF

0xFFFE 0000 0xFFFE

DFFF

0xFFFE 0xFFFE 8K

E000 FFFF

0xFFFF 0000 0xFFFF 8K

1FFF

0xFFFF 2000 0xFFFF

FFFF

Mem Map Map

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DVDD3318_C

VP_CLKOUT3/

PRU1_R30[0]/

GP6[1]/

PRU1_R31[1]

SATA_VSS

SATA_RXP

VP_CLKOUT2/

MMCSD1_DAT[2]/

PRU1_R30[2]/

GP6[3]/

PRU1_R31[3]

SATA_RXN

SATA_VDD

SATA_REFCLKN

SATA_REGSATA_REFCLKP SATA_VDD

SATA_VDD SATA_VDDRSATA_VDD

DVDD3318_C

DDR_A[11]

VP_DOUT[15]/

LCD_D[15]/ UPP_XD[7]/

GP7[7]/

BOOT[7]

DD3318_C

DD18

DDR_DVDD18 DDR_DVDD18

DDR_D[15]

DDR_RAS

DDR_CLKPDDR_CLKN

DDR_A[2]DDR_A[10]

LCD_AC_ENB_CS/

GP6[0]/

PRU1_R31[28]

DDR_A[13]

DDR_CAS

DDR_A[5]

DDR_CKE

DDR_BA[0]

DDR_A[9] DDR_A[1]

DDR_WE

DDR_D[10]

DDR_A[7]

DDR_A[0] DDR_D[12]

DDR_A[12]

DDR_A[3]

DDR_CS

DDR_A[6]

DDR_DQM[1]

SATA_VSS

DDR_DVDD18

VP_DOUT[12]/

LCD_D[12]/ UPP_XD[4]/

GP7[4]/

BOOT[4]

DDR_VREF

DDR_BA[1]

DDR_A[8]

DDR_A[4]

DDR_BA[2]

SATA_VSS

DDR_D[13]

DD18

DDR_DVDD18DDR_DVDD18DDR_DVDD18DDR_DVDD18

DVDD3318_C

VP_DOUT[13]/

LCD_D[13]/

UPP_XD[5]/

GP7[5]/

BOOT[5]

VP_DOUT[14]/

LCD_D[14]/ UPP_XD[6]/

GP7[6]/

BOOT[6]

DDR_DVDD18 DDR_DVDD18 DDR_DVDD18

VP_DOUT[9]/

LCD_D[9]/

UPP_XD[1]/

GP7[1]/

BOOT[1]

VP_DOUT[10]/

LCD_D[10]/ UPP_XD[2]/

GP7[2]/

BOOT[2]

VP_DOUT[11]/

LCD_D[11]/ UPP_XD[3]/

GP7[3]/

BOOT[3]

VP_DOUT[6]/

LCD_D[6]/

UPP_XD[14]/

GP7[14]/

PRU1_R31[14]

VP_DOUT[7]/

LCD_D[7]/

UPP_XD[15]/

GP7[15]/

PRU1_R31[15]

VP_DOUT[8]/

LCD_D[8]/

UPP_XD[0]/

GP7[0]/

BOOT[0]

VP_DOUT[3]/

LCD_D[3]/

UPP_XD[11]/

GP7[11]/

PRU1_R31[11]

VP_DOUT[4]/

LCD_D[4]/

UPP_XD[12]/

GP7[12]/

PRU1_R31[12]

VP_DOUT[5]/

LCD_D[5]/

UPP_XD[13]/

GP7[13]/

PRU1_R31[13]

VP_DOUT[0]/

LCD_D[0]/

UPP_XD[8]/

GP7[8]/

PRU1_R31[8]

VP_DOUT[1]/

LCD_D[1]/

UPP_XD[9]/

GP7[9]/

PRU1_R31[9]

VP_DOUT[2]/

LCD_D[2]/

UPP_XD[10]/

GP7[10]/

PRU1_R31[10]

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3.6 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

3.6.1 Pin Map (Bottom View)

The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four quadrants (A, B, C, and D). The pin assignments for both packages are identical.

Figure 3-3. Pin Map (Quad A)

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USB1_VDD33

DVDD3318_C

USB_CVDD

DVDD3318_C

DDR_DQGATE0

DVDD18

DDR_DQGATE1

DDR_D[9] DDR_D[8]DDR_D[11]

DVDD18

RTC_CVDD

RESET

USB0_DM USB0_DP

VP_DIN[11]/

UHPI_HD[3]/

UPP_D[3]/

PRU0_R30[11]/

PRU0_R31[11]

USB0_VDDA33 USB0_VBUS

USB1_DM

VP_DIN[0]/

UHPI_HD[8]/

UPP_D[8]/ RMII_CRS_DV/ PRU1_R31[29]

VP_DIN[1]/

UHPI_HD[9]/

UPP_D[9]/

RMII_MHZ_50_CLK/

PRU0_R31[23]

VP_DIN[2]/

UHPI_HD[10]/

UPP_D[10]/

RMII_RXER/

PRU0_R31[24]

VP_DIN[4]/

UHPI_HD[12]/

UPP_D[12]/

RMII_RXD[1]/

PRU0_R31[26]

PRU0_R30[28]/ UHPI_HCNTL1/

UPP_CHA_START/

GP6[10]

USB1_DP

PLL0_VDDA

PRU0_R30[30]/

PRU1_R30[11]/

GP6[12]

UHPI_HINT

USB0_VDDA18

VP_DIN[5]/

UHPI_HD[13]/

UPP_D[13]/

RMII_TXEN/

PRU0_R31[27]

DDR_D[1]

VP_DIN[7]/

UHPI_HD[15]/

UPP_D[15]/

RMII_TXD[1]/

PRU0_R31[29]

OSCVSS

DDR_D[2]

VP_DIN[6]/

UHPI_HD[14]/

UPP_D[14]/

RMII_TXD[0]/

PRU0_R31[28]

VP_DIN[3]/

UHPI_HD[11]/

UPP_D[11]/

RMII_RXD[0]/

PRU0_R31[25]

VP_DIN[14]_

HSYNC/

UHPI_HD[6]/

UPP_D[6]/ PRU0_R30[14]/ PRU0_R31[14]

EMU1

VP_DIN[8]/

UHPI_HD[0]/

UPP_D[0]/

GP6[5]/

PRU1_R31[0]

USB0_VDDA12

TDI

PRU0_R30[26]/

UHPI_HR /

UPP_CHA_WAIT/

GP6[8]/

PRU1_R31[17]

VP_DIN[12]/ UHPI_HD[4]/

UPP_D[4]/

PRU0_R30[12]/

PRU0_R31[12]

RESETOUT

UHPI_HAS//

PRU1_R30[14]/

GP6[15]

RSV2

GP8[0]

OSCOUT

DDR_D[0]

PRU0_R30[27]/

UHPI_HHWIL/

UPP_CHA_ENABLE/

GP6[9]

VP_DIN[13]_

FIELD/

UHPI_HD[5]/

UPP_D[5]/ PRU0_R30[13]/ PRU0_R31[13]

TRST

OSCIN

VP_CLKIN1/

PRU1_R30[9]/

GP6[6]/

PRU1_R31[16]

UHPI_HDS1

VP_DIN[15]_

VSYNC/

UHPI_HD[7]/

UPP_D[7]/ PRU0_R30[15]/ PRU0_R31[15]

VP_CLKIN0/

PRU1_R30[10]/

GP6[7]/

UPP_2xTXCLK

UHPI_HCS

VP_DIN[10]/

UHPI_HD[2]/

UPP_D[2]/ PRU0_R30[10]/ PRU0_R31[10]

DVDD3318_B

PLL0_VSSA

TMS

PRU0_R30[31]/

PRU1_R30[12]/

GP6[13]

UHPI_HRDY

NC PLL1_VSSA

PLL1_VDDA

USB1_VDD18 USB0_ID

VP_DIN[9]/

UHPI_HD[1]/

UPP_D[1]/

PRU0_R30[9]/

PRU0_R31[9]

CLKOUT/

PRU1_R30[13]/

GP6[14]

UHPI_HDS2

USB0_DRVVBUS

DDR_DQS[0]

PRU0_R30[29]/

UHPI_HCNTL0/

UPP_CHA_CLOCK/

GP6[11]

DDR_DQM[0]

DDR_D[3]

DDR_D[4]

DDR_D[6]

DDR_ZP

DDR_D[5]

DDR_D[7]

DDR_D[14]

DDR_DQS[1]

DVDD3318_C

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Figure 3-4. Pin Map (Quad B)

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EMA_A[8]/

PRU1_R30[16]/

GP5[8]

EMA_A[14]/

MMCSD0_DAT[7]/

PRU1_R30[22]/

GP5[14]/

PRU1_R31[22]

EMA_A[15]/

MMCSD0_DAT[6]/

PRU1_R30[23]/

GP5[15]/

PRU1_R31[23]

EMA_A[10]/

PRU1_R30[18]/

GP5[10]/

PRU1_R31[18]

EMA_A[9]/

PRU1_R30[17]/

GP5[9]

EMA_A[13]/ PRU0_R30[21]/ PRU1_R30[21] /

GP5[13]/

PRU1_R31[21]

EMA_A[12]/

PRU1_R30[20]/

GP5[12]/

PRU1_R31[20]

EMA_A[16]/

MMCSD0_DAT[5]/

PRU1_R30[24]/

GP4[0]

EMA_A[18]/

MMCSD0_DAT[3]/

PRU1_R30[26]/

GP4[2]

DD3318_B

DD18

EMA_A[6]/

GP5[6]

EMA_A[5]/

GP5[5]

EMA_A[2]/

GP5[2]

EMA_A7/

PRU1_R30[15]/

GP5[7]

EMA_A[4]/

GP5[4]

SPI0_SIMO/

EPWMSYNCO/

GP8[5]/

MII_CRS

SPI0_SCS[5]/ UART0_RXD/

GP8[4]/

MII_RXD[3]

SPI1_SCS[1]/

EPWM1A/

PRU0_R30[7]/

GP2[15]/

TM64P2_IN12

SPI0_SCS[4]/

UART0_TXD/

GP8[3]/

MII_RXD[2]

SPI0_CLK/

EPWM0A/

GP1[8]/

MII_RXCLK

SPI1_SCS[3]/ UART1_RXD/

SATA_LED/

GP1[1]

SPI1_SCS[0]/

EPWM1B/

PRU0_R30[8]/

GP2[14]/

TM64P3_IN12

EMA_OE/

GP3[10]

SPI1_SCS[4]/ UART2_TXD/

I2C1_SDA/

GP1[2]

EMA_A[3]/

GP5[3]

DD18

RTC_VSS

EMA_WAIT[0]/ PRU0_R30[0]/

GP3[8]/

PRU0_R31[0]

EMA_RAS/

PRU0_R30[3]/

GP2[5]/

PRU0_R31[3]

SPI0_SCS[3] UART0_CTS//

GP8[2]/

MII_RXD[1]/

SATA_MP_SWITCH

SPI0_SCS[0]/

TM64P1_OUT12/

GP1[6]/

MDIO_D/

TM64P1_IN12

SPI0_SOMI/

EPWMSYNCI/

GP8[6]/

MII_RXER

SPI0_SCS[2] UART0_RTS//

GP8[1]/

MII_RXD[0]/

SATA_CP_DET

SPI1_SCS[7]/

I2C0_SCL/

TM64P2_OUT12/

GP1[5]

SPI1_SIMO/

GP2[10]

SPI1_CLK/

GP2[13]

EMA_CS[3]/

GP3[14]

SPI1_ENA/

GP2[12]

RTC_XO

EMA_CS[2]/

GP3[15]

EMA_WAIT[1]/ PRU0_R30[1]/

GP2[1]/

PRU0_R31[1]

EMA_A[20]/

MMCSD0_DAT[1]/

PRU1_R30[28]/

GP4[4]

EMA_BA[1]/

GP2[9]

SPI0_ENA/

EPWM0B/

PRU0_R30[6]/

MII_RXDV

EMA_CS[5]/

GP3[12]

SPI1_SCS[5]/ UART2_RXD/

I2C1_SCL/

GP1[3]

EMA_A[0]/

GP5[0]

EMA_BA[0]/

GP2[8]

EMA_A[1]/

GP5[1]

DD3318_B

SPI0_SCS[1]/

TM64P0_OUT12/

GP1[7]/

MDIO_CLK/

TM64P0_IN12

DD3318_A

SPI1_SCS[6]/

I2C0_SDA/

TM64P3_OUT12/

GP1[4]

EMA_CS[0]/

GP2[0]

SPI1_SOMI/

GP2[11]

TDO

TCK

EMU0

RTC_XI

NMI

SPI1_SCS[2]/ UART1_TXD/

SATA_CP_POD/

GP1[0]

EMA_A[11]/

PRU1_R30[19]/

GP5[11]/

PRU1_R31[19]

EMA_A[17]/

MMCSD0_DAT[4]/

PRU1_R30[25]

GP4[1]

DD3318_B

DD18

DD3318_A

DD18

DD3318_B

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Figure 3-5. Pin Map (Quad C)

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EMA_D[15]/

GP3[7]

AXR15/

EPWM0TZ[0]/

ECAP2_APWM2/

GP0[7]

ACLKR/

PRU0_R30[20]/

GP0[15]/

PRU0_R31[22]

ACLKX/

PRU0_R30[19]/

GP0[14]/

PRU0_R31[21]

AHCLKX/

USB_REFCLKIN/

GP0[10]/

PRU0_R31[17]

UART1_CTS

AFSX/

GP0[12]/

PRU0_R31[19]

AFSR/

GP0[13]/

PRU0_R31[20]

AXR9/

DX1/

GP0[1]

AXR4/

FSR0/ GP1[12]/ MII_COL

AXR5/

CLKX0/

GP1[13]/

MII_TXCLK

AXR7/

EPWM1TZ[0]/

PRU0_R30[17]

GP1[15]/

PRU0_R31[7]

AXR10/

DR1/

GP0[2]

AXR1/

DX0/

GP1[9]/

MII_TXD[1]

AXR3/ FSX0/

GP1[11]/

MII_TXD[3]

AXR2/

DR0/

GP1[10]/

MII_TXD[2]

MMCSD1_DAT[6]/

LCD_MCLK/

PRU1_R30[6]/

GP8[10]/

PRU1_R31[7]

RTC_ALARM/

GP0[8]/

UART2_CTS

DEEPSLEEP

AXR0/

ECAP0_APWM0/

GP8[7]/

MII_TXD[0]/

CLKS0

PRU0_R30[24]/ MMCSD1_CLK/

UPP_CHB_START/

GP8[14]/

PRU1_R31[26]

MMCSD1_DAT[4]/

LCD_VSYNC/ PRU1_R30[4]/

GP8[8]/

PRU1_R31[5]

SATA_VSS

PRU0_R30[22]/

PRU1_R30[8]/

UPP_CHB_WAIT/

GP8[12]/

PRU1_R31[24]

AXR8/

CLKS1/

ECAP1_APWM1/

GP0[0]/

PRU0_R31[8]

AXR12/

FSR1/ GP0[4]

EMA_D[4]/

GP4[12]

AXR14/ CLKR1/

GP0[6]

EMA_WEN_DQM[1]/

GP2[2]

EMA_D[0]/

GP4[8]

EMA_A[19]/

MMCSD0_DAT[2]/

PRU1_R30[27]/

GP4[3]

EMA_D[9]/

GP3[1]

EMA_A_R /

GP3[9]

MMCSD0_CLK/ PRU1_R30[31]/

GP4[7]

EMA_D[8]/

GP3[0]

EMA_D[13]/

GP3[5]

VP_CLKIN2/

MMCSD1_DAT[3]/

PRU1_R30[3]/

GP6[4]/

PRU1_R31[4]

VP_CLKIN3/

MMCSD1_DAT[1]/

PRU1_R30[1]/

GP6[2]/

PRU1_R31[2]

AMUTE/

GP0[9]/

PRU0_R31[16]

PRU0_R30[16]/

UART2_RTS/

DD3318_A

EMA_WE/

GP3[11]

EMA_D[10]/

GP3[2]

EMA_D[3]/

GP4[11]

EMA_SDCKE/ PRU0_R30[4]/

GP2[6]/

PRU0_R31[4]

EMA_D[14]/

GP3[6]

EMA_D[7]/

GP4[15]

EMA_D[1]/

GP4[9]

EMA_A[22]/

MMCSD0_CMD/

PRU1_R30[30]/

GP4[6]

EMA_D[2]/

GP4[10]

EMA_A[21]/

MMCSD0_DAT[0]/

PRU1_R30[29]/

GP4[5]

PRU0_R30[23]/ MMCSD1_CMD/

UPP_CHB_ENABLE/

GP8[13]/

PRU1_R31[25]

AHCLKR/

GP0[11]/

PRU0_R31[18]

PRU0_R30[18]/

UART1_RTS

EMA_D[12]/

GP3[4]

EMA_WEN_DQM[0]/

GP2[3]

EMA_CLK/

PRU0_R30[5]/

GP2[7]/

PRU0_R31[5]

AXR6/

CLKR0/

GP1[14]/

MII_TXEN/

PRU0_R31[6]

AXR11/

FSX1/ GP0[3]

EMA_D[6]/

GP4[14]

EMA_D[11]/

GP3[3]

EMA_D[5]/

GP4[13]

MMCSD1_DAT[7]/

LCD_PCLK/

PRU1_R30[7]/

GP8[11]

MMCSD1_DAT[5]/

LCD_HSYNC/ PRU1_R30[5]/

GP8[9]/

PRU1_R31[6]

PRU0_R30[25]/

MMCSD1_DAT[0]/

UPP_CHB_CLOCK/

GP8[15]/

PRU1_R31[27]

AXR13/ CLKX1/

GP0[5]

EMA_CS[4]/

GP3[13]

EMA_CAS/

PRU0_R30[2]/

GP2[4]/

PRU0_R31[2]

DD3318_B

DD18

DD3318_B

DD18

SATA_VSS

DD3318_A

SATA_TXP

SATA_TXN

DD3318_C

TMS320C6748

SPRS590B–JUNE 2009–REVISED AUGUST 2010

www.ti.com

3.7 Pin Multiplexing Control

Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module. For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed

with several different functions has a corresponding 4-bit field in one of the PINMUX registers. Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data

and output enable values only. The default pin multiplexing control for almost every pin is to select 'none' of the peripheral functions in which case the pin's IO buffer is held tri-stated.

Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers have no effect on input from a pin.

Figure 3-6. Pin Map (Quad D)

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Specifications and Main Features

Frequently Asked Questions

User Manual

1 TMS320C6748 Fixed/Floating-Point DSP

1.1 Features

1.2 Trademarks

1.3 Description

1.4 Functional Block Diagram

2 Revision History

3 Device Overview

3.1 Documentation Support

3.1.1 Related Documentation From Texas Instruments

3.2 Device Characteristics

3.3 Device Compatibility

3.4 DSP Subsystem

3.4.1 C674x DSP CPU Description

3.4.2 DSP Memory Mapping

3.4.2.1 External Memories

3.4.2.2 DSP Internal Memories

3.4.2.3 C674x CPU

3.5 Memory Map Summary

3.6 Pin Assignments

3.6.1 Pin Map (Bottom View)

3.7 Pin Multiplexing Control