Texas Instruments TMS320C645x DSP User Manual
TMS320C645x DSP
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO)
User's Guide
Literature Number: SPRU975B
August 2006
2 SPRU975B – August 2006
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Contents
Preface .............................................................................................................................. 10
1 Introduction .............................................................................................................. 11
1.1 Purpose of the Peripheral ..................................................................................... 11
1.2 Features ......................................................................................................... 11
1.3 Functional Block Diagram ..................................................................................... 12
1.4 Industry Standard(s) Compliance Statement ............................................................... 13
2 EMAC Functional Architecture .................................................................................... 14
2.1 Clock Control .................................................................................................... 14
2.2 Memory Map .................................................................................................... 15
2.3 System Level Connections .................................................................................... 16
2.4 Ethernet Protocol Overview ................................................................................... 24
2.5 Programming Interface ......................................................................................... 26
2.6 EMAC Control Module ......................................................................................... 37
2.7 Management Data Input/Output (MDIO) Module ........................................................... 38
2.8 EMAC Module ................................................................................................... 43
2.9 Media Independent Interfaces ................................................................................ 46
2.10 Packet Receive Operation ..................................................................................... 50
2.11 Packet Transmit Operation .................................................................................... 55
2.12 Receive and Transmit Latency ............................................................................... 55
2.13 Transfer Node Priority .......................................................................................... 56
2.14 Reset Considerations .......................................................................................... 56
2.15 Initialization ...................................................................................................... 57
2.16 Interrupt Support ................................................................................................ 60
2.17 Power Management ............................................................................................ 63
2.18 Emulation Considerations ..................................................................................... 63
3 EMAC Control Module Registers ................................................................................. 64
3.1 Introduction ...................................................................................................... 64
3.2 EMAC Control Module Interrupt Control Register (EWCTL) .............................................. 64
3.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) ................................. 65
4 MDIO Registers ......................................................................................................... 66
4.1 Introduction ...................................................................................................... 66
4.2 MDIO Version Register (VERSION) ......................................................................... 67
4.3 MDIO Control Register (CONTROL) ......................................................................... 68
4.4 PHY Acknowledge Status Register (ALIVE) ................................................................ 69
4.5 PHY Link Status Register (LINK) ............................................................................. 70
4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................ 71
4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .......................... 72
4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ................... 73
4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ................. 74
4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ................ 75
4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .......... 76
4.12 MDIO User Access Register 0 (USERACCESS0) ......................................................... 77
4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) .................................................... 78
4.14 MDIO User Access Register 1 (USERACCESS1) ......................................................... 79
SPRU975B – August 2006 Table of Contents 3
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4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 80
5 EMAC Port Registers ................................................................................................. 81
5.1 Introduction ...................................................................................................... 81
5.2 Transmit Identification and Version Register (TXIDVER) ................................................. 85
5.3 Transmit Control Register (TXCONTROL) .................................................................. 86
5.4 Transmit Teardown Register (TXTEARDOWN) ............................................................ 87
5.5 Receive Identification and Version Register (RXIDVER) .................................................. 88
5.6 Receive Control Register (RXCONTROL) .................................................................. 89
5.7 Receive Teardown Register (RXTEARDOWN) ............................................................. 90
5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .................................... 91
5.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................... 92
5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET) ................................................ 93
5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .......................................... 94
5.12 MAC Input Vector Register (MACINVECTOR) ............................................................. 95
5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ..................................... 96
5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................... 97
5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ................................................. 98
5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ........................................... 99
5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ..................................... 100
5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ................................... 101
5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ................................................. 102
5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ........................................... 103
5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .......... 104
5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................... 106
5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) .................................................. 107
5.24 Receive Maximum Length Register (RXMAXLEN) ....................................................... 108
5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) .................................................. 109
5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .................. 110
5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) ....................... 111
5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) .............................. 112
5.29 MAC Control Register (MACCONTROL) .................................................................. 113
5.30 MAC Status Register (MACSTATUS) ...................................................................... 115
5.31 Emulation Control Register (EMCONTROL) .............................................................. 117
5.32 FIFO Control Register (FIFOCONTROL) .................................................................. 118
5.33 MAC Configuration Register (MACCONFIG) .............................................................. 119
5.34 Soft Reset Register (SOFTRESET) ........................................................................ 120
5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ....................................... 121
5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 122
5.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 123
5.38 MAC Hash Address Register 2 (MACHASH2) ............................................................ 124
5.39 Back Off Test Register (BOFFTEST) ....................................................................... 125
5.40 Transmit Pacing Algorithm Test Register (TPACETEST) ............................................... 126
5.41 Receive Pause Timer Register (RXPAUSE) .............................................................. 127
5.42 Transmit Pause Timer Register (TXPAUSE) .............................................................. 128
5.43 MAC Address Low Bytes Register (MACADDRLO) ...................................................... 129
5.44 MAC Address High Bytes Register (MACADDRHI) ...................................................... 130
5.45 MAC Index Register (MACINDEX) ......................................................................... 131
5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) ............................ 132
5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) ............................ 133
4 Contents SPRU975B – August 2006
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5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) ........................................... 134
5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) ........................................... 135
5.50 Network Statistics Registers ................................................................................. 136
Appendix A Glossary ...................................................................................................... 145
Appendix B Revision History ............................................................................................ 147
SPRU975B – August 2006 Contents 5
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List of Figures
1 EMAC and MDIO Block Diagram ........................................................................................ 12
2 Ethernet Configuration with MII Interface ............................................................................... 16
3 Ethernet Configuration with RMII Interface ............................................................................. 18
4 Ethernet Configuration with GMII Interface ............................................................................. 20
5 Ethernet Configuration with RGMII Interface ........................................................................... 22
6 Ethernet Frame ............................................................................................................. 24
7 Basic Descriptor Format ................................................................................................... 26
8 Typical Descriptor Linked List ............................................................................................ 27
9 Transmit Descriptor Format ............................................................................................... 30
10 Receive Descriptor Format ................................................................................................ 33
11 EMAC Control Module Block Diagram .................................................................................. 37
12 MDIO Module Block Diagram ............................................................................................. 39
13 EMAC Module Block Diagram ............................................................................................ 43
14 EMAC Control Module Interrupt Control Register (EWCTL) .......................................................... 64
15 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) ............................................. 65
16 MDIO Version Register (VERSION) ..................................................................................... 67
17 MDIO Control Register (CONTROL) ..................................................................................... 68
18 PHY Acknowledge Status Register (ALIVE) ............................................................................ 69
19 PHY Link Status Register (LINK) ......................................................................................... 70
20 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ........................................ 71
21 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ...................................... 72
22 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ............................... 73
23 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ............................. 74
24 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ........................... 75
25 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ..................... 76
26 MDIO User Access Register 0 (USERACCESS0) ..................................................................... 77
27 MDIO User PHY Select Register 0 (USERPHYSEL0) ................................................................ 78
28 MDIO User Access Register 1 (USERACCESS1) ..................................................................... 79
29 MDIO User PHY Select Register 1 (USERPHYSEL1) ................................................................ 80
30 Transmit Identification and Version Register (TXIDVER) ............................................................. 85
31 Transmit Control Register (TXCONTROL) .............................................................................. 86
32 Transmit Teardown Register (TXTEARDOWN) ........................................................................ 87
33 Receive Identification and Version Register (RXIDVER) ............................................................. 88
34 Receive Control Register (RXCONTROL) .............................................................................. 89
35 Receive Teardown Register (RXTEARDOWN) ........................................................................ 90
36 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ................................................ 91
37 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .............................................. 92
38 Transmit Interrupt Mask Set Register (TXINTMASKSET) ............................................................ 93
39 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ...................................................... 94
40 MAC Input Vector Register (MACINVECTOR) ......................................................................... 95
41 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................ 96
42 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ............................................... 97
43 Receive Interrupt Mask Set Register (RXINTMASKSET) ............................................................. 98
44 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ...................................................... 99
45 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................ 100
46 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ............................................... 101
47 MAC Interrupt Mask Set Register (MACINTMASKSET) ............................................................. 102
48 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ...................................................... 103
49 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ...................... 104
50 Receive Unicast Enable Set Register (RXUNICASTSET) .......................................................... 106
51 Receive Unicast Clear Register (RXUNICASTCLEAR) ............................................................. 107
52 Receive Maximum Length Register (RXMAXLEN) ................................................................... 108
6 List of Figures SPRU975B – August 2006
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53 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. 109
54 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. 110
55 Receive Channel n Flow Control Threshold Register (RX nFLOWTHRESH) ..................................... 111
56 Receive Channel n Free Buffer Count Register (RX nFREEBUFFER) ............................................ 112
57 MAC Control Register (MACCONTROL) .............................................................................. 113
58 MAC Status Register (MACSTATUS) .................................................................................. 115
59 Emulation Control Register (EMCONTROL) .......................................................................... 117
60 FIFO Control Register (FIFOCONTROL) .............................................................................. 118
61 MAC Configuration Register (MACCONFIG) ......................................................................... 119
62 Soft Reset Register (SOFTRESET) .................................................................................... 120
63 MAC Source Address Low Bytes Register (MACSRCADDRLO)................................................... 121
64 MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................... 122
65 MAC Hash Address Register 1 (MACHASH1) ........................................................................ 123
66 MAC Hash Address Register 2 (MACHASH2) ........................................................................ 124
67 Back Off Random Number Generator Test Register (BOFFTEST) ................................................ 125
68 Transmit Pacing Algorithm Test Register (TPACETEST) ........................................................... 126
69 Receive Pause Timer Register (RXPAUSE) .......................................................................... 127
70 Transmit Pause Timer Register (TXPAUSE) .......................................................................... 128
71 MAC Address Low Bytes Register (MACADDRLO) .................................................................. 129
72 MAC Address High Bytes Register (MACADDRHI) .................................................................. 130
73 MAC Index Register (MACINDEX) ..................................................................................... 131
74 Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP) .......................................... 132
75 Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP) .......................................... 133
76 Transmit Channel n Completion Pointer Register (TX nCP) ......................................................... 134
77 Receive Channel n Completion Pointer Register (RX nCP) ......................................................... 135
78 Statistics Register ......................................................................................................... 136
SPRU975B – August 2006 List of Figures 7
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List of Tables
1 Interface Selection Pins ................................................................................................... 16
2 EMAC and MDIO Signals for MII Interface ............................................................................. 17
3 EMAC and MDIO Signals for RMII Interface ........................................................................... 19
4 EMAC and MDIO Signals for GMII Interface ........................................................................... 21
5 EMAC and MDIO Signals for RGMII Interface ......................................................................... 23
6 Ethernet Frame Description ............................................................................................... 24
7 Basic Descriptors ........................................................................................................... 26
8 Receive Frame Treatment Summary .................................................................................... 53
9 Middle of Frame Overrun Treatment .................................................................................... 54
10 Emulation Control .......................................................................................................... 63
11 EMAC Control Module Registers ......................................................................................... 64
12 EMAC Control Module Interrupt Control Register (EWCTL) Field Descriptions ................................... 64
13 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Descriptions ....................... 65
14 Management Data Input/Output (MDIO) Registers .................................................................... 66
15 MDIO Version Register (VERSION) Field Descriptions ............................................................... 67
16 MDIO Control Register (CONTROL) Field Descriptions .............................................................. 68
17 PHY Acknowledge Status Register (ALIVE) Field Descriptions ..................................................... 69
18 PHY Link Status Register (LINK) Field Descriptions .................................................................. 70
19 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ................. 71
20 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ................ 72
21 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ........ 73
22 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions ....... 74
23 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ..... 75
24 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions ................................................................................................................. 76
25 MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................... 77
26 MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions .......................................... 78
27 MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................... 79
28 MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions .......................................... 80
29 Ethernet Media Access Controller (EMAC) Registers ................................................................. 81
30 Transmit Identification and Version Register (TXIDVER) Field Descriptions ....................................... 85
31 Transmit Control Register (TXCONTROL) Field Descriptions ....................................................... 86
32 Transmit Teardown Register (TXTEARDOWN) Field Descriptions.................................................. 87
33 Receive Identification and Version Register (RXIDVER) Field Descriptions ....................................... 88
34 Receive Control Register (RXCONTROL) Field Descriptions ........................................................ 89
35 Receive Teardown Register (RXTEARDOWN) Field Descriptions .................................................. 90
36 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions .......................... 91
37 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ........................ 92
38 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ...................................... 93
39 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ................................ 94
40 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................... 95
41 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions .......................... 96
42 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions......................... 97
43 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ...................................... 98
44 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ................................ 99
45 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions .......................... 100
46 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions......................... 101
47 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ...................................... 102
48 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................ 103
49 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions 104
8 List of Tables SPRU975B – August 2006
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50 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 106
51 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 107
52 Receive Maximum Length Register (RXMAXLEN) Field Descriptions ............................................ 108
53 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ........................................ 109
54 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ....... 110
55 Receive Channel n Flow Control Threshold Register (RX nFLOWTHRESH) Field Descriptions ............... 111
56 Receive Channel n Free Buffer Count Register (RX nFREEBUFFER) Field Descriptions ...................... 112
57 MAC Control Register (MACCONTROL) Field Descriptions ........................................................ 113
58 MAC Status Register (MACSTATUS) Field Descriptions ........................................................... 115
59 Emulation Control Register (EMCONTROL) Field Descriptions .................................................... 117
60 FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................ 118
61 MAC Configuration Register (MACCONFIG) Field Descriptions ................................................... 119
62 Soft Reset Register (SOFTRESET) Field Descriptions .............................................................. 120
63 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................ 121
64 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................. 122
65 MAC Hash Address Register 1 (MACHASH1) Field Descriptions ................................................. 123
66 MAC Hash Address Register 2 (MACHASH2) Field Descriptions ................................................. 124
67 Back Off Test Register (BOFFTEST) Field Descriptions ............................................................ 125
68 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ..................................... 126
69 Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................... 127
70 Transmit Pause Timer Register (TXPAUSE) Field Descriptions ................................................... 128
71 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ........................................... 129
72 MAC Address High Bytes Register (MACADDRHI) Field Descriptions ............................................ 130
73 MAC Index Register (MACINDEX) Field Descriptions ............................................................... 131
74 Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP) Field Descriptions .................... 132
75 Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP) Field Descriptions .................... 133
76 Transmit Channel n Completion Pointer Register (TX nCP) Field Descriptions .................................. 134
77 Receive Channel n Completion Pointer Register (RX nCP) Field Descriptions ................................... 135
78 Statistics Register Field Descriptions .................................................................................. 136
A-1 Physical Layer Definitions ............................................................................................... 146
B-1 Document Revision History .............................................................................................. 147
SPRU975B – August 2006 List of Tables 9
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About This Manual
This document provides a functional description of the Ethernet Media Access Controller (EMAC) and
Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with
TMS320C645x devices.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com .
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU732B ) describes the
CPU architecture, pipeline, instruction set, and interrupts of the C64x and C64x+ DSPs.
TMS320C6455 Technical Reference (literature number SPRU965 ) gives an introduction to the
TMS320C6455™ DSP and discusses the application areas that are enhanced.
TMS320C6000 Programmer's Guide (literature number SPRU198 ) describes ways to optimize C and
assembly code for the TMS320C6000™ DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301 ) introduces the Code
Composer Studio™ integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference Guide (literature number
SPRU321 ) describes the Code Composer Studio™ application programming interface (API), which allows
you to program custom plug-ins for Code Composer.
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 ) describes the
TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct
memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,
bandwidth management, and the memory and cache.
TMS320C645x DSP Peripherals Overview Reference Guide (literature number SPRUE52 ) provides a
brief description of the peripherals available on the TMS320C645x digital signal processors (DSPs).
TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234 ) is a download with the latest
chip support libraries.
Trademarks
C6000, TMS320C6455, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.
Preface
SPRU975B – August 2006
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10 Preface SPRU975B – August 2006
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Ethernet Media Access Controller (EMAC)/Management
1 Introduction
This document provides a functional description of the Ethernet Media Access Controller (EMAC) and
Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with
TMS320C645x (C645x) devices. Included are the features of the EMAC and MDIO modules, a discussion
of their architecture and operation, how these modules connect to the outside world, and the registers
description for each module.
The EMAC controls the flow of packet data from the processor to the PHY. The MDIO module controls
PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows
efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral.
1.1 Purpose of the Peripheral
The EMAC module is used on TMS320C645x devices to move data between the device and another host
connected to the same network, in compliance with the Ethernet protocol.
User's Guide
SPRU975B – August 2006
Data Input/Output (MDIO)
1.2 Features
The basic feature set of the EMAC module integrated with C645x is:
• Synchronous 10/100/1000 Mbps operation
• Full duplex Gigabit operation (half duplex gigabit is not supported)
• Little endian and big endian support
• Supports four types of interfaces to the physical layer device (PHY): standard media independent
interface (MII), reduced pin count media independent interface (RMII), standard gigabit media
independent interface (GMII) and reduced pin count gigabit media independent interface (RGMII)
• EMAC acts as DMA master to either internal or external device memory space
• Eight receive channels with VLAN tag discrimination for receive quality of service (QOS) support
• Eight transmit channels with round–robin or fixed priority for transmit quality of service (QOS) support
• Ether-stats and 802.3-stats statistics gathering
• Transmit CRC generation selectable on a per-channel basis
• Broadcast frames selection for reception on a single channel
• Multicast frames selection for reception on a single channel
• Promiscuous receive mode frames selection for reception on a single channel (all frames, all good
frames, short frames, error frames)
• Hardware flow control
• 8K byte local EMAC descriptor memory that allows the peripheral to operate on descriptors without
affecting the CPU. The descriptor memory holds enough information to transfer up to 512 ethernet
packets without CPU intervention.
• Programmable interrupt logic permits the software driver to restrict the generation of back-to-back
interrupts, thus allowing more work to be performed in a single call to the interrupt service routine
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 11
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Configuration bus
DMA memory
transfer controller
Peripheral bus
EMAC control module
EMAC module MDIO module
MII MDIO bus
EMAC/MDIO
interrupt
Interrupt
controller
RMII GMII RGMII
Introduction
1.3 Functional Block Diagram
Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral:
• EMAC control module
• EMAC module
• MDIO module
The EMAC control module is the main interface between the device core processor and the EMAC
module and MDIO module. The EMAC control module contains the necessary components to allow the
EMAC to make efficient use of device memory, plus it controls device interrupts. The EMAC control
module incorporates 8K byte internal RAM to hold EMAC buffer descriptors.
The management data input / output (MDIO) module implements the 802.3 serial management interface to
interrogate and control up to 32 ethernet PHY(s) connected to the device, using a shared two–wire bus.
Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY
attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC
module for correct operation. The module is designed to allow almost transparent operation of the MDIO
interface, with very little maintenance from the core processor.
The ethernet media access controller (EMAC) module provides an efficient interface between the C645x
core processor and the networked community. The EMAC supports 10Base-T (10 Mbits / sec), and
100BaseTX (100 Mbits / sec), in either half or full duplex mode, and 1000BaseT (1000 Mbits / sec) in full
duplex mode, with hardware flow control and quality-of-service (QOS) support.
Figure 1. EMAC and MDIO Block Diagram
Figure 1 also shows the main interface between the EMAC control module and the CPU.
The following connections are made to the device core:
• The peripheral bus connection from the EMAC control module allows the EMAC module to read and
write both internal and external memory through the switch fabric interface.
• The EMAC control, EMAC, and MDIO modules all have control registers. These registers are
memory-mapped into device memory space via the device configuration bus. The control module’s
internal RAM maps to this same range along with these registers.
• The EMAC and MDIO interrupts are combined into a single interrupt within the control module. The
interrupt from the control module then goes to the device’s interrupt controller.
The EMAC and MDIO interrupts are combined within the control module, so only the control module
interrupt needs to be monitored by the application software or device driver. The interrupt is mapped to a
specific CPU interrupt via the enhanced interrupt selector within the C64x+ core. The combined EMAC /
MDIO interrupt maps to the interrupt controller input as system event 17.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)12 SPRU975B – August 2006
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1.4 Industry Standard(s) Compliance Statement
The EMAC peripheral conforms to the IEEE 802.3 standard, describing the “Carrier Sense Multiple Access
with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. ISO / IEC has
also adopted the IEEE 802.3 standard and re-designated it as ISO/IEC 8802-3:2000(E).
In difference from this standard, the EMAC peripheral integrated with the C645x devices does not use the
transmit coding error signal MTXER. Instead of driving the error pin when an underflow condition occurs
on a transmitted frame, the EMAC intentionally generates an incorrect check sum by inverting the frame
CRC so that the network will detect the transmitted frame as an error.
Introduction
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 13
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EMAC Functional Architecture
2 EMAC Functional Architecture
This chapter discusses the architecture and basic function of the EMAC peripheral.
2.1 Clock Control
The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as shown
below:
• 2.5 Mhz at 10 Mbps
• 25 Mhz at 100 Mbps
• 125 MHz at 1000 Mbps
The C645x device uses two PLL controllers to generate all of the clocks that the DSP needs. The primary
PLL controller generates a peripheral clock (SYSCLK2) that several peripherals use, including the EMAC.
SYSCLK2 runs at a rate equal to 1/6th of the CPU clock frequency (CPUclk/6), and is not programmable.
The secondary PLL controller conveniently generates a reference clock (SYSCLK1). The EMAC uses the
SYSCLK1 to generate the transmit and receive clocks for the GMII and RGMII interfaces. The frequency
of SYSCLK1 is equal to the secondary PLL controller’s input clock (25 MHz) multiplied by 10 and divided
by either 5 or 2. You must program SYSCLK1 to the correct frequency based on the interface that you are
using (as determined by the configuration pins MACSEL[1:0]). See Section 2.1.1 , Section 2.1.3 , and
Section 2.1.4 for the configuration of SYSCLK1 that is required on each interface.
Note: The RGMII interface does not require an interface clock. However, a reference clock that
is derived from SYSCLK1 is provided for your convenience. The reference clock is not a
free running clock. The reference clock stops while the DSP is in reset; therefore, you
must be careful if you use this clock elsewhere in the system.
2.1.1 MII Clocking
2.1.2 RMII Clocking
2.1.3 GMII Clocking
The MDIO clock is based on a divide-down of the peripheral clock (SYSCLK2) and is specified to run up
to 2.5 MHz, although typical operation is 1.0 MHz. Since the peripheral clock frequency is variable, the
application software or driver controls the divide-down amount.
When you select the MII clocking interface by setting MACSEL to the default value (00b), the transmit and
receive clock sources are provided from an external PHY via the MTCLK and MRCLK pins. These clocks
are inputs to the EMAC module and operate at 2.5 MHz in 10 Mbps mode, and at 25 MHz in 100 MHz
mode. The MII clocking interface is not used in 1000 Mbps mode. For timing purposes, data is transmitted
and received with reference to MTCLK and MRCLK, respectively.
When you select the RMII interface by setting MACSEL to 01b, you must provide a 50MHz reference
clock through the MREFCLK pin. The EMAC clocks the transmit and receive operations from the
reference clock. The MTCLK and MRCLK device pins are not used for this interface. The RMII protocol
turns one data phase of an MII transfer into two data phases at double the clock frequency. This is the
driving factor for the 50 MHz reference clock. Data at the IO pins are running at 5 MHZ in 10 Mbps mode,
and at 50 MHz in 100 Mbps mode.
When you set MACSEL to 02b to select GMII, the transmit and receive clock sources for 10/100 Mbps
modes are provided from an external PHY via the MTCLK and MRCLK pins. For 1000 Mbps mode, the
receive clock is provided by an external PHY via the MRCLK pin. For transmit in 1000 Mbps mode, the
clock is sourced synchronous with the data, and is provided by the EMAC to be output on the GMTCLK
pin.
The SYSCLK1 of the secondary PLL controller sources the GMTCLK. The divider generating SYSCLK1
needs to be programmed to /2 (the default value) for this interface to provide a 125 MHz clock to the
EMAC.
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2.1.4 RGMII Clocking
EMAC Functional Architecture
For timing purposes, data in 10/100 mode is transmitted and received with reference to MTCLK and
MRCLK, respectively. For 1000 Mbps mode, receive timing is the same, but transmit is relative to
GMTCLK.
When the RGMII interface is selected by setting MACSEL to 11b, you must configure the internal clock
(SYSCLK1) to a 125 MHz frequency by setting the divider for the secondary PLL controller to /5. This
provides a reference clock that you can use to source the clock on the RGMII PHY as necessary.
Note: This reference clock is not a free running clock. An external device should only use this
clock if it does not expect a valid clock during device reset.
The EMAC drives the transmit clock, while an external PHY generates the receive clock. The reference
clock drives the device pin that gives the 125 MHz clock to the PHY; this enables the PHY to generate the
receive clock that is sent to EMAC.
The RGMII protocol takes a GMII data stream and turns it into an interface with half of the data bus width
and sends the same amount of data with a reduced pinout. The RGMII protocol also allows for dynamic
switching of the mode between 10/100/1000 Mbps modes. This negotiation data is embedded in the
incoming data stream from the external PHY. For timing purposes, data is transmitted and received with
respect to MTCLK and MRCLK respectively.
The RGMII interface has separate I/O pins from the other EMAC pins because the interface voltage is
different from the other interfaces.
2.2 Memory Map
The EMAC includes an internal memory that holds information about the ethernet packets that are
received or transmitted. This internal RAM is 2K x 32 bits in size. You can write data to and read data
from the EMAC internal memory via either the EMAC or the CPU. It is used to store buffer descriptors that
are 4 words (16 bytes) deep. This 8K local memory can hold enough information to transfer up to 512
ethernet packets without CPU intervention.
You can put the packet buffer descriptors in internal processor memory (L2) on the C645x devices. There
are some trade-offs in terms of cache performance and throughput when you put descriptors in L2 versus
when you put them in EMAC’s internal memory. Cache performance improves when you put the buffer
descriptors in internal memory. However, the EMAC throughput is better when you put the descriptors in
the local EMAC RAM.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 15
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MTCLK
MTXD[3−0]
MTXEN
MCOL
MCRS
MRCLK
MRXD[3−0]
MRXDV
MRXER
MDCLK
MDIO
Physical
layer
device
(PHY)
System
core
Transformer
2.5 MHz
or
25 MHz
RJ−45
EMACMDIO
EMAC Functional Architecture
2.3 System Level Connections
The C645x device supports four different interfaces to a physical layer device. You can only transfer data
on one interface at a given time. Each of these interfaces is selected in hardware via the configuration
pins (MACSEL[1:0]).
Table 1 shows the possible settings for these configuration pins.
2.3.1 Media Independent Interface (MII) Connections
Figure 2 shows a device with integrated EMAC and MDIO interfaced via a MII connection. This interface is
only available in 10 Mbps and 100 Mbps modes.
Figure 2. Ethernet Configuration with MII Interface
Table 1. Interface Selection Pins
MACSEL [1:0] Interface
00 MII
01 RMII
10 GMII
11 RGMII
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EMAC Functional Architecture
Table 2 summarizes the individual EMAC and MDIO signals for the MII interface. For more information,
refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E).
The EMAC module does not include a transmit error (MTXER) pin. If a transmit error occurs, CRC
inversion is used to negate the validity of the transmitted frame.
Table 2. EMAC and MDIO Signals for MII Interface
Signal Name I/O Description
MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing
MTXD[3:0] O Transmit data (MTXD). The transmit data pins are a collection of 4 data signals comprising 4
MTXEN O Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are
MCOL I Collision detected (MCOL). The MCOL pin is asserted by the PHY when it detects a collision
MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in
MRCLK I Receive clock (MRCLK). The receive clock is a continuous clock that provides the timing
MRXD[3:0] I Receive data (MRXD). The receive data pins are a collection of 4 data signals comprising 4
MRXDV I Receive data valid (MRXDV). The receive data valid signal indicates that the MRXD pins are
MRXER I Receive error (MRXER). The receive error signal is asserted for one or more MRCLK periods
MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on
MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and
reference for transmit operations. The MTXD and MTXEN signals are tied to this clock. The
clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at 100
Mbps operation.
bits of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MTCLK
and valid only when MTXEN is asserted.
generating nibble data for use by the PHY. It is driven synchronously to MTCLK.
on the network. It remains asserted while the collision condition persists. This signal is not
necessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation
only.
either transmit or receive. The pin is de-asserted when both transmit and receive are idle.
This signal is not necessarily synchronous to MTCLK or MRCLK. This pin is used in
half-duplex operation only.
reference for receive operations. The MRXD, MRXDV, and MRXER signals are tied to this
clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz
at 100 Mbps operation.
bits of data. MRDX0 is the least-significant bit (LSB). The signals are synchronized by
MRCLK and valid only when MRXDV is asserted.
generating nibble data for use by the EMAC. It is driven synchronously to MRCLK.
to indicate that an error was detected in the received frame. This is meaningful only during
data reception when MRXDV is active.
the system. It is used to synchronize MDIO data access operations done on the MDIO pin.
The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register
(CONTROL).
out of the PHY by way of an access frame consisting of start of frame, read/write indication,
PHY address, register address, and data bit cycles. The MDIO pin acts as an output for
everything except the data bit cycles, when the pin acts as an input for read operations.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 17
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MTXD[1−0]
MTXEN
MCRSDV
MREFCLK
MRXD[1−0]
MRXER
MDCLK
MDIO
Physical
layer
device
(PHY)
System
core
Transformer
RJ−45
EMACMDIO
EMAC Functional Architecture
2.3.2 Reduced Media Independent Interface (RMII) Connections
Figure 3 shows a device with integrated EMAC and MDIO interfaced via a RMII connection. This interface
is only available in 10 Mbps and 100 Mbps modes. The RMII interface is only supported in full-duplex
mode for the C645x family of devices.
Figure 3. Ethernet Configuration with RMII Interface
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EMAC Functional Architecture
The RMII interface has the same functionality as the MII, but it does so with a reduced number of pins,
thus lowering the total cost for an application. In devices incorporating many PHY interfaces such as
switches, the number of pins can add significant cost as the port counts increase. Table 3 summarizes the
individual EMAC and MDIO signals for the RMII interface.
The RMII interface does not include an MCOL signal. A collision is detected from the receive and transmit
data delimiters. The data signals are 2 bits wide, and a single reference clock must be provided to the
MAC, operating at 50MHz to sustain the same data rate as MII.
Table 3. EMAC and MDIO Signals for RMII Interface
Signal Name I/O Description
MTXD[1-0] O Transmit data (MTXD). The transmit data pins are a collection of 2 data signals comprising 2
MTXEN O Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are
MCRSDV I Carrier sense/receive data valid (MCRSDV). The MCRSDV pin is asserted by the PHY when
MREFCLK I Reference clock (MREFCLK). A 50MHz clock must be provided through this pin for RMII
MRXD[1-0] I Receive data (MRXD). The receive data pins are a collection of 2 data signals comprising 2
MRXER I Receive error (MRXER). The receive error signal is asserted for one or more reference clock
MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on
MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and
bits of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized to the
RMII reference clock and valid only when MTXEN is asserted.
generating nibble data for use by the PHY. It is driven synchronously to the RMII reference
clock.
the network is not idle in either transmit or receive. The data on MRXD is considered valid
once the MCRSDV signal is asserted. The pin is de-asserted when both transmit and receive
are idle. The assertion of this signal is asynchronous to the RMII reference clock. This pin is
used in half-duplex operation only.
operation.
bits of data. MRDX0 is the least-significant bit (LSB). The signals are synchronized to the
RMII reference clock and valid only when MCRSDV is asserted. In 10 Mbps operation, MRXD
is sampled every 10th cycle of the RMII reference clock.
periods to indicate that an error was detected in the received frame. This is meaningful only
during data reception when MCRSDV is active. It is driven synchronously to the RMII
reference clock.
the system. It is used to synchronize MDIO data access operations done on the MDIO pin.
The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register
(CONTROL).
out of the PHY by way of an access frame consisting of start of frame, read/write indication,
PHY address, register address, and data bit cycles. The MDIO pin acts as an output for
everything except the data bit cycles, when the pin acts as an input for read operations.
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MTCLK
MTXD[7−0]
MTXEN
MCOL
MCRS
MRCLK
MRXD[7−0]
MRXDV
MRXER
MDCLK
MDIO
Physical
layer
device
(PHY)
System
core
Transformer
2.5 MHz,
25 MHz,
RJ−45
EMACMDIO
GMTCLK
or 125 MHz
EMAC Functional Architecture
2.3.3 Gigabit Media Independent Interface (GMII) Connections
Figure 4 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interface
is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes.
Figure 4. Ethernet Configuration with GMII Interface
The GMII interface supports 10/100/1000 Mbps modes. Only full-duplex mode is available in 1000 Mbps
mode. In 10/100 Mbps modes, the GMII interface acts like an MII interface, and only the lower 4 bits of
data are transferred for each of the data buses.
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EMAC Functional Architecture
Table 4 summarizes the individual EMAC and MDIO signals for the GMII interface.
Table 4. EMAC and MDIO Signals for GMII Interface
Signal Name I/O Description
MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing
GMTCLK O GMII source synchronous transmit clock (GMTCLK). This clock is used in 1000 Mbps mode
MTXD[7-0] O Transmit data (MTXD). The transmit data pins are a collection of 8 data signals comprising 8
MTXEN O Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are
MCOL I Collision detected (MCOL). The MCOL pin is asserted by the PHY when it detects a collision
MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in
MRCLK I Receive clock (MRCLK). The receive clock is a continuous clock that provides the timing
MRXD[7-0] I Receive data (MRXD). The receive data pins are a collection of 8 data signals comprising 8
MRXDV I Receive data valid (MRXDV). The receive data valid signal indicates that the MRXD pins are
MRXER I Receive error (MRXER). The receive error signal is asserted for one or more MRCLK periods
MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on
MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and
reference for transmit operations in 10/100 Mbps mode. The MTXD and MTXEN signals are
tied to this clock when in 10/100 Mbps mode. The clock is generated by the PHY and is 2.5
MHz at 10 Mbps operation, and 25 MHz at 100 Mbps operation.
only, providing a continuous 125 MHz frequency for transmit operations. The MTXD and
MTXEN signals are tied to this clock when in Gigabit mode. The clock is generated by the
EMAC and is 125 MHz.
bits of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MTCLK
in 10/100 Mbps mode, and by GMTCLK in Gigabit mode, and valid only when MTXEN is
asserted.
generating nibble data for use by the PHY. It is driven synchronously to MTCLK in 10/100
Mbps mode, and to GMTCLK in Gigabit mode.
on the network. It remains asserted while the collision condition persists. This signal is not
necessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation
only.
either transmit or receive. The pin is de-asserted when both transmit and receive are idle.
This signal is not necessarily synchronous to MTCLK nor MRCLK. This pin is used in
half-duplex operation only.
reference for receive operations. The MRXD, MRXDV, and MRXER signals are tied to this
clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation, 25 MHz at
100 Mbps operation and 125 MHz at 1000 Mbps operation.
bits of data. MRDX0 is the least-significant bit (LSB). The signals are synchronized by
MRCLK and valid only when MRXDV is asserted.
generating nibble data for use by the EMAC. It is driven synchronously to MRCLK.
to indicate that an error was detected in the received frame. This is meaningful only during
data reception when MRXDV is active.
the system. It is used to synchronize MDIO data access operations done on the MDIO pin.
The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register
(CONTROL).
out of the PHY by way of an access frame consisting of start of frame, read/write indication,
PHY address, register address, and data bit cycles. The MDIO pin acts as an output for
everything except the data bit cycles, when the pin acts as an input for read operations.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 21
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TXC
TXD[3−0]
TXCTL
REFCLK
RXC
RXD[3−0]
RXCTL
MDCLK
MDIO
Physical
layer
device
(PHY)
System
core
Transformer
2.5 MHz
25 MHz,
or 125 MHz
RJ−45
EMACMDIO
EMAC Functional Architecture
2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections
Figure 5 shows a device with integrated EMAC and MDIO interfaced via a RGMII connection. This
interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes.
Figure 5. Ethernet Configuration with RGMII Interface
The RGMII interface is a reduced pin alternative to the GMII interface. The data paths are reduced, control
signals are multiplexed together, and both edges of the clock are used.
The RGMII interface does not include a MCOL and a MCRS signal for half-duplex mode (only available in
10/100 Mbps mode).
Carrier sense (MCRS) is indicated by one of the following cases instead:
• MRXDV signal (multiplexed in the RXCTL signal) is true
• MRXDV is false, MRXERR (multiplexed in the RXCTL signal) is true, and a value of FFh exists on the
RXD[7:0] simultaneously
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EMAC Functional Architecture
Table 5 summarizes the individual EMAC and MDIO signals for the RGMII interface.
Table 5. EMAC and MDIO Signals for RGMII Interface
Signal Name I/O Description
TXC O Transmit clock (TXC). The transmit clock is a continuous clock that provides the timing
TXD[3-0] O Transmit data (TXD). The transmit data pins are a collection of 4 data signals comprising 4
TXCTL O Transmit enable (TXCTL). The transmit enable signal indicates that the TXD pins are
REFCLK O Reference clock (REFCLK). This 125 MHz reference clock is provided as a convenience. It
RXC I Receive clock (RXC). The receive clock is a continuous clock that provides the timing
RXD[3-0] I Receive data (RXD). The receive data pins are a collection of 4 data signals comprising 4 bits
RXCTL I Receive control (RXCTL). The receive control data has the receive data valid (MRXDV)
MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module. It
MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and
reference for transmit operations. The TXD and TXCTL signals are tied to this clock. The
clock is driven by the EMAC and is 2.5 MHz at 10 Mbps operation, 25 MHz at 100 Mbps
operation, and 125 MHz at 1000 Mbps operation.
bits of data. TDX0 is the least-significant bit (LSB). The signals are synchronized by TXC and
valid only when TXCTL is asserted. The lower 4 bits of data are transmitted on the rising
edge of the clock, and the higher 4 bits of data are transmitted on the falling edge of the TXC.
generating nibble data for use by the PHY. It is driven synchronously to TXC.
can be used as a clock source to the PHY, so that the PHY may generate the RXC clock to
be sent to EMAC. This clock is stopped while the device is in reset.
reference for receive operations. The RXD, and RXCTL signals are tied to this clock. The
clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation, 25 MHz at 100 Mbps
operation, and 125 MHz at 1000 Mbps operation.
of data. RDX0 is the least-significant bit (LSB). The signals are synchronized by RXC and
valid only when RXCTL is asserted. The lower 4 bits of data are received on the rising edge
of the clock, and the higher 4 bits of data are received on the falling edge of the RXC.
signal on the rising edge of the receive clock, and a derivative of receive data valid and
receive error (MRXER) on the falling edge of RXC.
When receiving a valid frame with no errors, MRXDV = TRUE is generated as a logic high on
the rising edge on RXC and MRXER = FALSE is generated as a logic high on the falling
edge of RXC.
When no frame is being received, MRXDV = FALSE is generated as a logic low on the rising
edge of RXC and MRXER = FALSE is generated as a logic low on the falling edge of RXC.
When receiving a valid frame with errors, MRXDV = TRUE is generated as a logic high on
the rising edge of RXC and MRXER = TRUE is generated as a logic low on the falling edge
of RXC.
synchronizes MDIO data access operations done on the MDIO pin. The frequency of this
clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).
out of the PHY by way of an access frame consisting of start of frame, read/write indication,
PHY address, register address, and data bit cycles. The MDIO pin acts as an output for
everything except the data bit cycles, when the pin acts as an input for read operations.
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Preamble SFD Destination Source Len Data
7 1 6 6 2 46 − (RXMAXLEN - 18) 4
FCS
Number of bytes
Legend: SFD=Start Frame Delimiter; FCS=Frame Check Sequence (CRC)
EMAC Functional Architecture
2.4 Ethernet Protocol Overview
Ethernet provides an unreliable, connectionless service to a networking application. A brief overview of the
ethernet protocol follows. For more information on the carrier sense multiple access with collision
detection (CSMA/CD) access method (ethernet’s multiple access protocol), see the IEEE 802.3 standard
document.
2.4.1 Ethernet Frame Format
All the ethernet technologies use the same frame structure. The format of an ethernet frame is shown in
Figure 6 and described in Table 6 . The ethernet packet is the collection of bytes representing the data
portion of a single ethernet frame on the wire (shown outlined in bold in Figure 6 ).
The ethernet frames are of variable lengths, with no frame smaller than 64 bytes or larger than
RXMAXLEN bytes (header, data, and CRC).
Field Bytes Description
Preamble 7 These 7 bytes have a fixed value of 55h. They wake up the receiving EMAC ports and
Start of Frame 1 This field with a value of 5Dh immediately follows the preamble pattern and indicates
Delimiter the start of important data.
Destination 6 This field contains the Ethernet MAC address of the intended EMAC port for the frame.
address It may be an individual or multicast (including broadcast) address. If the destination
Source 6 This field contains the MAC address of the Ethernet port that transmits the frame to the
address Local Area Network.
Length/Type 2 The length field indicates the number of EMAC client data bytes contained in the
Data 46 to (RXMAXLEN - 18) This field carries the datagram containing the upper layer protocol frame (the IP layer
Frame Check 4 A cyclic redundancy check (CRC) is used by the transmit and receive algorithms to
Sequence generate a CRC value for the FCS field. The frame check sequence covers the 60 to
Figure 6. Ethernet Frame
Table 6. Ethernet Frame Description
synchronize their clocks to that of the sender’s clock.
EMAC port receives an Ethernet frame with a destination address that does not match
any of its MAC physical addresses, and no promiscuous, multicast or broadcast
channel is enabled, it discards the frame.
subsequent data field of the frame. This field can also be used to identify the data type
carried by the frame.
datagram). The maximum transfer unit (MTU) of Ethernet is (RXMAXLEN - 18) bytes.
Therefore, if the upper layer protocol datagram exceeds (RXMAXLEN - 18) bytes, the
host must fragment the datagram and send it in multiple Ethernet packets. The
minimum size of the data field is 46 bytes. Thus, if the upper layer datagram is less
then 46 bytes, the data field must be extended to 46 bytes by appending extra bits after
the data field, but prior to calculating and appending the FCS.
(RXMAXLEN - 4) bytes of the packet data. Note that the 4-byte FCS field may not be
included as part of the packet data, depending on the EMAC configuration.
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2.4.2 Multiple Access Protocol
Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an
EMAC port transmits a frame, all of the adapters on the local network receive the frame. Carrier sense
multiple access with collision detection (CSMA/CD) algorithms are used when the EMAC operates in
half-duplex mode. When operating in full-duplex mode, there is no contention for use of a shared medium,
because there are exactly two ports on the local network.
Each port runs the CSMA/CD protocol without explicit coordination with the other ports on the ethernet
network.
Within a specific port, the CSMA/CD protocol is as follows:
1. The port obtains data from upper layer protocols at its node, prepares an ethernet frame, and puts the
frame in a buffer.
2. If the port senses that the medium is idle, it starts to transmit the frame. If the port senses that the
transmission medium is busy, it waits until it senses no signal energy (plus an inter-packet gap time)
and then starts to transmit the frame.
3. While transmitting, the port monitors for the presence of signal energy coming from other ports. If the
port transmits the entire frame without detecting signal energy from other ethernet devices, the port is
finished with the frame.
4. If the port detects signal energy from other ports while transmitting, it stops transmitting its frame and
instead transmits a 48-bit jam signal.
5. After transmitting the jam signal, the port enters an exponential back off phase. Specifically, when
transmitting a given frame, after experiencing a number of collisions in a row for the frame, the port
chooses a random value that is dependent on the number of collisions. The port then waits an amount
of time which is multiple of this random value, and returns to Step 1.
EMAC Functional Architecture
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EMAC Functional Architecture
2.5 Programming Interface
2.5.1 Packet Buffer Descriptors
The buffer descriptor is a central part of the EMAC module. It determines how the application software
describes ethernet packets to be sent and empty buffers to be filled with incoming packet data.
The basic descriptor format is shown in Figure 7 and described in Table 7 .
Figure 7. Basic Descriptor Format
Word Offset Bit Fields
31 16 15 0
0 Next Descriptor Pointer
1 Buffer Pointer
2 Buffer Offset Buffer Length
3 Flags Packet Length
Table 7. Basic Descriptors
Word Field Description
Offset Field
0 Next Descriptor The next descriptor pointer creates a single linked list of descriptors. Each descriptor describes a
1 Buffer Pointer The buffer pointer refers to the memory buffer that either contains packet data during transmit
2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data. This
2 Buffer Length The buffer length is the number of valid packet data bytes stored in the buffer. If the buffer is empty
3 Flags The flags field contains more information about the buffer, such as whether it is the first fragment in
3 Packet Length The packet length only has meaning for buffers that both contain data and are the start of a new
Pointer packet or a packet fragment. When a descriptor points to a single buffer packet or the first fragment
of a packet, the start of packet (SOP) flag is set in the flags field. When a descriptor points to a
single buffer packet or the last fragment of a packet, the end of packet (EOP) flag is set. When a
packet is fragmented, each fragment must have its own descriptor and appear sequentially in the
descriptor linked list.
operations, or is an empty buffer ready to receive packet data during receive operations.
field only has meaning when the buffer descriptor points to a buffer that contains data.
and waiting to receive data, this field represents the size of the empty buffer.
a packet (SOP), the last fragment in a packet (EOP), or contains an entire contiguous Ethernet
packet (both SOP and EOP). Section 2.5.4 and Section 2.5.5 describe the flags.
packet (SOP). For SOP descriptors, the packet length field contains the length of the entire Ethernet
packet, even if it is contained in a single buffer or fragmented over several buffers.
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SOP | EOP 60
0 60
pBuffer
pNext
Packet A
60 bytes
0
SOP
Fragment 1
Packet B
512
1514
pBuffer
pNext
512 bytes
EOP
0
0
−−−
Packet B
Fragment 3
500 bytes
502
pBuffer
−−−
500
pNext
−−−
pBuffer
pNext
Packet B
Fragment 2
502 bytes
SOP | EOP
0
1514 bytes
Packet C
1514
pBuffer
pNext (NULL)
1514
EMAC Functional Architecture
For example, consider three packets to be transmitted, Packet A is a single fragment (60 bytes), Packet B
is fragmented over three buffers (1514 bytes total), and Packet C is a single fragment (1514 bytes).
Figure 8 shows the linked list of descriptors to describe these three packets.
Figure 8. Typical Descriptor Linked List
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EMAC Functional Architecture
2.5.2 Transmit and Receive Descriptor Queues
The EMAC module processes descriptors in linked list chains (Section 2.5.1 ). The lists controlled by the
EMAC are maintained by the application software via the head descriptor pointer (HDP) registers. Since
the EMAC supports eight channels for both transmit and receive, there are eight head descriptor pointer
registers for both.
They are designated as follows:
• TX nHDP: Transmit Channel n DMA Head Descriptor Pointer Register
• RX nHDP: Receive Channel n DMA Head Descriptor Pointer Register
After an EMAC reset, and before enabling the EMAC for send or receive, you must initialize all 16 head
descriptor pointer registers to zero.
The EMAC uses a simple system to determine ownership of a descriptor (either the EMAC or the
application software). There is a flag in the descriptor flags field called OWNER. When this flag is set, the
EMAC owns the referenced packet.
Note: Ownership is assigned on a packet-based granularity, not on descriptor granularity. Thus,
only SOP descriptors make use of the OWNER flag. The EMAC patches the SOP
descriptor of the corresponding packet and clears the OWNER flag as packets are
processed. This means that the EMAC is finished processing all descriptors up to and
including the first with the EOP flag set. This indicates that you have reached the end of
the packet. This may only be one descriptor with both the SOP and EOP flags set.
To add a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time, the
software application writes the pointer to the descriptor or first descriptor of a list to the corresponding
HDP register. Note that the last descriptor in the list must have its next pointer cleared so that the EMAC
can detect the end of the list. If only a single descriptor is added, its next descriptor pointer must be
initialized to zero.
The HDP register must never be written to a second time while a previous list is active. To add additional
descriptors to a descriptor list already owned by the EMAC, the NULL next pointer of the last descriptor of
the previous list is patched with a pointer to the first descriptor in the new list. The list of new descriptors
to be appended to the existing list must itself be NULL terminated before the pointer patch is performed.
If the EMAC reads the next pointer of a descriptor as NULL in the instant before an application appends
additional descriptors to the list by patching the pointer, this may result in a race condition. Thus, the
software application must always examine the Flags field of all EOP packets, looking for a special flag
called end of queue (EOQ). The EOQ flag is set by the EMAC on the last descriptor of a packet when the
descriptor’s next pointer is NULL, allowing the EMAC to indicate to the software application that it has
reached the end of the list. When the software application sees the EOQ flag set, and there are more
descriptors to process, the application may then submit the new list or missed list portion by writing the
new list pointer to the same HDP register that started the process.
This process applies when adding packets to a transmit list, and empty buffers to a receive list.
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2.5.3 Transmit and Receive EMAC Interrupts
The EMAC processes descriptors in linked list chains (Section 2.5.1 ), using the linked list queue
mechanism (Section 2.5.2 ).
The EMAC synchronizes the descriptor list processing by using interrupts to the software application. The
interrupts are controlled by the application by using the interrupt masks, global interrupt enable, and the
completion pointer register (CP). This register is also called interrupt acknowledge register.
As the EMAC supports eight channels for both transmit and receive, there are eight CP registers for both.
They are designated as:
• TX nCP: Transmit Channel n Completion Pointer (Interrupt Acknowledge) Register
• RX nCP: Receive Channel n Completion Pointer (Interrupt Acknowledge) Register
These registers serve two purposes. When read, they return the pointer to the last descriptor that the
EMAC has processed. When written by the software application, the value represents the last descriptor
processed by the software application. If these two values do not match, the interrupt is active.
The system configuration determines whether an active interrupt can interrupt the CPU. In general, the
global interrupt for EMAC and MDIO must be enabled in the EMAC control module, and it also must be
mapped in the DSP interrupt controller and enabled as a CPU interrupt. If the system is configured
properly, the interrupt for a specific receive or transmit channel executes under these conditions when the
corresponding interrupt is enabled in the EMAC using the RXINTMASKSET or TXINTMASKSET registers.
The current state of the receive or transmit channel interrupt can be examined directly by the software
application by reading the RXINTSTATRAW and TXINTSTATRAW registers, whether or not the interrupt
is enabled.
Interrupts are acknowledged when the application software updates the value of TX nCP or RX nCP with a
value that matches the internal value kept by the EMAC.
This mechanism ensures that the application software never misses an EMAC interrupt, as the interrupt
and its acknowledgment are tied directly to the actual buffer descriptors processing.
EMAC Functional Architecture
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EMAC Functional Architecture
2.5.4 Transmit Buffer Descriptor Format
A transmit (TX) buffer descriptor (Figure 9 ) is a contiguous block of four 32-bit data words aligned on a
32-bit boundary that describes a packet or a packet fragment.
Example 1 shows the transmit buffer descriptor described by a C structure.
Figure 9. Transmit Descriptor Format
(a) Word 0
31 0
Next Descriptor Pointer
(b) Word 1
31 0
Buffer Pointer
(c) Word 2
31 16 15 0
Buffer Offset Buffer Length
(d) Word 3
31 30 29 28 27 26 25 16
SOP EOP OWNER EOQ TDOWN PASS Reserved
15 0
CMPLT CRC
Packet Length
Example 1. Transmit Descriptor in C Structure Format
/*
// EMAC Descriptor
//
// The following is the format of a single buffer descriptor
// on the EMAC.
*/
typedef struct _EMAC_Desc {
struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */
Uint8 *pBuffer; /* Pointer to data buffer */
Uint32 BufOffLen; /* Buffer Offset(MSW) and Length(LSW) */
Uint32 PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */
} EMAC_Desc;
/* Packet Flags */
#define EMAC_DSC_FLAG_SOP 0x80000000u
#define EMAC_DSC_FLAG_EOP 0x40000000u
#define EMAC_DSC_FLAG_OWNER 0x20000000u
#define EMAC_DSC_FLAG_EOQ 0x10000000u
#define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u
#define EMAC_DSC_FLAG_PASSCRC 0x04000000u
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