Texas Instruments TMS320C645X User Manual
TMS320C645x Serial Rapid IO (SRIO)
User's Guide
Literature Number: SPRU976
March 2006
2 SPRU976 – March 2006
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Contents
Preface .............................................................................................................................. 13
1 Overview .................................................................................................................. 14
1.1 General RapidIO System ......................................................................................... 14
1.2 RapidIO Feature Support in SRIO .............................................................................. 17
1.3 Standards .......................................................................................................... 18
1.4 External Devices Requirements ................................................................................. 18
2 SRIO Functional Description ....................................................................................... 19
2.1 Overview ............................................................................................................ 19
2.2 SRIO Pins .......................................................................................................... 24
2.3 Functional Operation .............................................................................................. 24
3 Logical/Transport Error Handling and Logging ............................................................. 73
4 Interrupt Conditions ................................................................................................... 74
4.1 CPU Interrupts ..................................................................................................... 74
4.2 General Description ............................................................................................... 74
4.3 Interrupt Condition Control Registers ........................................................................... 75
4.4 Interrupt Status Decode Registers .............................................................................. 83
4.5 Interrupt Generation ............................................................................................... 85
4.6 Interrupt Pacing .................................................................................................... 85
4.7 Interrupt Handling ................................................................................................. 86
5 SRIO Registers .......................................................................................................... 88
5.1 Introduction ......................................................................................................... 88
5.2 Peripheral Identification Register (PID) ......................................................................... 99
5.3 Peripheral Control Register (PCR) ............................................................................ 100
5.4 Peripheral Settings Control Register (PER_SET_CNTL) ................................................... 101
5.5 Peripheral Global Enable Register (GBL_EN) ............................................................... 104
5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) .............................................. 105
5.7 Block n Enable Register (BLK n_EN) .......................................................................... 106
5.8 Block n Enable Status Register (BLK n_EN_STAT) ......................................................... 107
5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) ......................................................... 108
5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) ......................................................... 109
5.11 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTL n) ..................................... 110
5.12 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTL n) ........................................ 111
5.13 SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n_CNTL) ................... 112
5.14 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTX n_CNTL) .................. 114
5.15 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL) ..................................... 116
5.16 DOORBELL n Interrupt Status Register (DOORBELL n_ICSR) ............................................ 117
5.17 DOORBELL n Interrupt Clear Register (DOORBELL n_ICCR) ............................................. 118
5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ...................................................... 119
5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) ....................................................... 120
5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) ....................................................... 121
5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ........................................................ 122
5.22 LSU Status Interrupt Register (LSU_ICSR) .................................................................. 123
5.23 LSU Clear Interrupt Register (LSU _ICCR) .................................................................. 124
5.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) ................. 125
SPRU976 – March 2006 Table of Contents 3
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5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) .................. 126
5.26 DOORBELL n Interrupt Condition Routing Register (DOORBELL n_ICRR) .............................. 127
5.27 DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n_ICRR2) .......................... 128
5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) ....................................... 129
5.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) ...................................... 130
5.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) ........................................ 131
5.31 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) ...................................... 132
5.32 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) ....................................... 133
5.33 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) ....................................... 134
5.34 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) ....................................... 135
5.35 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) ....................................... 136
5.36 Error, Reset, and Special Event Interrupt Condition Routing Register
(ERR_RST_EVNT_ICRR) ...................................................................................... 137
5.37 Error, Reset, and Special Event Interrupt Condition Routing Register 2
(ERR_RST_EVNT_ICRR2) ..................................................................................... 138
5.38 Error, Reset, and Special Event Interrupt Condition Routing Register 3
(ERR_RST_EVNT_ICRR3) ..................................................................................... 139
5.39 INTDST n Interrupt Status Decode Registers (INTDST n_DECODE)...................................... 140
5.40 INTDST n Interrupt Rate Control Registers (INTDST n_RATE_CNTL) .................................... 141
5.41 LSU n Control Register 0 (LSU n_REG0) ...................................................................... 142
5.42 LSU n Control Register 1 (LSU n_REG1) ...................................................................... 143
5.43 LSU n Control Register 2 (LSU n_REG2) ...................................................................... 144
5.44 LSU n Control Register 3 (LSU n_REG3) ...................................................................... 145
5.45 LSU n Control Register 4 (LSU n_REG4) ...................................................................... 146
5.46 LSU n Control Register 5 (LSU n_REG5) ...................................................................... 147
5.47 LSU n Control Register 6 (LSU n_REG6) ...................................................................... 148
5.48 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) .......................................... 149
5.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP) ................. 150
5.50 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) ......................... 151
5.51 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP) .................. 152
5.52 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP) .......................... 153
5.53 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) ...................................... 154
5.54 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKS n) ....................... 155
5.55 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) ....................................... 157
5.56 Receive CPPI Control Register (RX_CPPI_CNTL) ......................................................... 158
5.57 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) ..................... 159
5.58 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) ..................... 160
5.59 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) ..................... 161
5.60 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) ..................... 162
5.61 Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n) .................................................. 163
5.62 Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n) ................................................. 164
5.63 Flow Control Table Entry Registers (FLOW_CNTL n) ....................................................... 165
5.64 Device Identity CAR (DEV_ID) ................................................................................. 166
5.65 Device Information CAR (DEV_INFO) ........................................................................ 167
5.66 Assembly Identity CAR (ASBLY_ID) .......................................................................... 168
5.67 Assembly Information CAR (ASBLY_INFO).................................................................. 169
5.68 Processing Element Features CAR (PE_FEAT) ............................................................. 170
5.69 Source Operations CAR (SRC_OP)........................................................................... 171
5.70 Destination Operations CAR (DEST_OP) .................................................................... 172
5.71 Processing Element Logical Layer Control CSR (PE_LL_CTL) ........................................... 173
4 Contents SPRU976 – March 2006
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5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ................................... 174
5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) ..................................... 175
5.74 Base Device ID CSR (BASE_ID) .............................................................................. 176
5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) ............................................... 177
5.76 Component Tag CSR (COMP_TAG) .......................................................................... 178
5.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) ............................ 179
5.78 Port Link Time-Out Control CSR (SP_LT_CTL) ............................................................. 180
5.79 Port Response Time-Out Control CSR (SP_RT_CTL) ..................................................... 181
5.80 Port General Control CSR (SP_GEN_CTL) .................................................................. 182
5.81 Port Link Maintenance Request CSR n (SP n_LM_REQ) .................................................. 183
5.82 Port Link Maintenance Response CSR n (SP n_LM_RESP) ............................................... 184
5.83 Port Local AckID Status CSR n (SP n_ACKID_STAT) ...................................................... 185
5.84 Port Error and Status CSR n (SP n_ERR_STAT) ............................................................ 186
5.85 Port Control CSR n (SP n_CTL) ................................................................................ 188
5.86 Error Reporting Block Header (ERR_RPT_BH) ............................................................. 190
5.87 Logical/Transport Layer Error Detect CSR (ERR_DET) .................................................... 191
5.88 Logical/Transport Layer Error Enable CSR (ERR_EN) ..................................................... 192
5.89 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)................................. 193
5.90 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) .......................................... 194
5.91 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) ............................................. 195
5.92 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) ............................................ 196
5.93 Port-Write Target Device ID CSR (PW_TGT_ID) ........................................................... 197
5.94 Port Error Detect CSR n (SP n_ERR_DET) .................................................................. 198
5.95 Port Error Rate Enable CSR n (SP n_RATE_EN) ........................................................... 199
5.96 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) ............................... 200
5.97 Port n Packet/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) ....................... 201
5.98 Port n Packet/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) ....................... 202
5.99 Port n Packet/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) ....................... 203
5.100 Port n Packet/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) ...................... 204
5.101 Port Error Rate CSR n (SP n_ERR_RATE) .................................................................. 205
5.102 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) ................................................. 206
5.103 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) .................................... 207
5.104 Port IP Mode CSR (SP_IP_MODE) .......................................................................... 208
5.105 Serial Port IP Prescalar (IP_PRESCAL) ..................................................................... 210
5.106 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPT n) ................................................... 211
5.107 Port Reset Option CSR n (SP n_RST_OPT) ................................................................ 212
5.108 Port Control Independent Register n (SP n_CTL_INDEP) ................................................. 213
5.109 Port Silence Timer n (SP n_SILENCE_TIMER) ............................................................. 215
5.110 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) .................. 216
5.111 Port Control Symbol Transmit n (SP n_CS_TX) ............................................................. 217
SPRU976 – March 2006 Contents 5
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List of Figures
1 RapidIO Architectural Hierarchy .......................................................................................... 15
2 RapidIO Interconnect Architecture ....................................................................................... 16
3 Serial RapidIO Device to Device Interface Diagrams ................................................................. 17
4 SRIO Peripheral Block Diagram .......................................................................................... 20
5 Operation Sequence ....................................................................................................... 21
6 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) ........................................................ 22
7 Serial RapidIO Control Symbol Format.................................................................................. 22
8 SRIO Conceptual Block Diagram ........................................................................................ 25
9 Load/Store Data Transfer Diagram ...................................................................................... 32
10 Load/Store Registers for RapidIO (Address Offset: LSU1 0x400-0x418, LSU2 0x420-0x438, LSU3
0x440-0x458, LSU4 0x460-0x478) ....................................................................................... 33
11 LSU Registers Timing ..................................................................................................... 35
12 Example Burst NWRITE_R ............................................................................................... 36
13 Load/Store Module Data Flow ............................................................................................ 37
14 CPPI RX Scheme for RapidIO ............................................................................................ 41
15 Message Request Packet ................................................................................................. 41
16 Queue Mapping Table (Address Offset: 0x0800 - 0x08FC) .......................................................... 42
17 Queue Mapping Register RXU_MAP_L n ............................................................................... 43
18 Queue Mapping Register RXU_MAP_H n ............................................................................... 43
19 RX Buffer Descriptor Fields ............................................................................................... 44
20 RX CPPI Mode Explanation .............................................................................................. 47
21 CPPI Boundary Diagram .................................................................................................. 48
22 TX Buffer Descriptor Fields ............................................................................................... 49
23 Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) .............................. 52
24 RX Buffer Descriptor ....................................................................................................... 57
25 TX Buffer Descriptor ....................................................................................................... 58
26 Doorbell Operation ......................................................................................................... 59
27 Flow Control Table Entry Registers (Address Offset 0x0900 - 0x093C) ............................................ 61
28 Transmit Source Flow Control Masks ................................................................................... 62
29 Configuration Bus Example ............................................................................................... 63
30 DMA Example .............................................................................................................. 64
31 GBL_EN (Address 0x0030) ............................................................................................... 65
32 GBL_EN_STAT (Address 0x0034) ....................................................................................... 65
33 BLK0_EN (Address 0x0038) .............................................................................................. 65
34 BLK0_EN_STAT (Address 0x003C) ..................................................................................... 66
35 BLK1_EN (Address 0x0040) .............................................................................................. 66
36 BLK1_EN_STAT (Address 0x0044) ..................................................................................... 66
37 BLK8_EN (Address 0x0078) .............................................................................................. 66
38 BLK8_EN_STAT (Address 0x007C) ..................................................................................... 66
39 Emulation Control (Peripheral Control Register PCR 0x0004) ....................................................... 68
40 Bootload Operation ........................................................................................................ 72
41 Detectable Errors ........................................................................................................... 73
42 RapidIO DOORBELL Packet for Interrupt Use ......................................................................... 74
43 DOORBELL0 Interrupt Registers for Direct I/O Transfers ............................................................ 76
44 DOORBELL1 Interrupt Registers for Direct I/O Transfers ............................................................ 76
45 DOORBELL2 Interrupt Registers for Direct I/O Transfers ............................................................ 77
46 DOORBELL3 Interrupt Registers for Direct I/O Transfers ............................................................ 77
47 RX_CPPI Interrupts Using Messaging Mode Data Transfers ........................................................ 78
48 TX _CPPI Interrupts Using Messaging Mode Data Transfers ........................................................ 78
49 LSU Load/Store Module Interrupts ....................................................................................... 79
50 ERR_RST_EVNT Error, Reset, and Special Event Interrupt ......................................................... 80
51 Doorbell 0 Interrupt Condition Routing Registers ...................................................................... 81
6 List of Figures SPRU976 – March 2006
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52 Load/Store Module Interrupt Condition Routing Registers ............................................................ 82
53 Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 83
54 Sharing of ISDR Bits ....................................................................................................... 84
55 Example Diagram of Interrupt Status Decode Register Mapping .................................................... 84
56 INTDST n_Decode Interrupt Status Decode Register ................................................................. 85
57 INTDST n_RATE_CNTL Interrupt Rate Control Register .............................................................. 86
58 Peripheral ID Register (PID) .............................................................................................. 99
59 Peripheral Control Register (PCR) ..................................................................................... 100
60 Peripheral Settings Control Register (PER_SET_CNTL) ............................................................ 101
61 Peripheral Global Enable Register (GBL_EN) ........................................................................ 104
62 Peripheral Global Enable Status Register (GBL_EN_STAT) ....................................................... 105
63 Block n Enable Register (BLK n_EN) ................................................................................... 106
64 Block n Enable Status Register (BLK n_EN_STAT) .................................................................. 107
65 RapidIO DEVICEID1 Register (DEVICEID_REG1) .................................................................. 108
66 RapidIO DEVICEID2 Register (DEVICEID_REG2) .................................................................. 109
67 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTL n) .............................................. 110
68 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTL n) ................................................. 111
69 SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n_CNTL) ............................ 112
70 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTX n_CNTL) ........................... 114
71 SERDES Macros CFG (0-3) Registers (SERDES_CFG n_CNTL) ................................................. 116
72 DOORBELL n Interrupt Status Register (DOORBELL n_ICSR) ..................................................... 117
73 DOORBELL n Interrupt Clear Register (DOORBELL n_ICCR) ...................................................... 118
74 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ............................................................... 119
75 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) ................................................................ 120
76 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) ................................................................ 121
77 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ................................................................. 122
78 LSU Status Interrupt Register (LSU_ICSR) ........................................................................... 123
79 LSU Clear Interrupt Register (LSU _ICCR) ........................................................................... 124
80 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) .......................... 125
81 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) ........................... 126
82 DOORBELL n Interrupt Condition Routing Register (DOORBELL n_ICRR) ....................................... 127
83 DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n_ICRR2) ................................... 128
84 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) ................................................ 129
85 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) ............................................... 130
86 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) ................................................. 131
87 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) ............................................... 132
88 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) ................................................ 133
89 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) ................................................ 134
90 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) ................................................ 135
91 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) ................................................ 136
92 Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) ............ 137
93 Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) ........ 138
94 Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3) ........ 139
95 INTDST n Interrupt Status Decode Registers (INTDST n_DECODE)............................................... 140
96 INTDST n Interrupt Rate Control Registers (INTDST n_RATE_CNTL) ............................................. 141
97 LSU n Control Register 0 (LSU n_REG0) ............................................................................... 142
98 LSU n Control Register 1 (LSU n_REG1) ............................................................................... 143
99 LSU n Control Register 2 (LSU n_REG2) ............................................................................... 144
100 LSU n Control Register 3 (LSU n_REG3) ............................................................................... 145
101 LSU n Control Register 4 (LSU n_REG4) ............................................................................... 146
102 LSU n Control Register 5 (LSU n_REG5) ............................................................................... 147
103 LSU n Control Register 6 (LSU n_REG6) ............................................................................... 148
104 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) ................................................... 149
SPRU976 – March 2006 List of Figures 7
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105 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP) .......................... 150
106 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) .................................. 151
107 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP) ........................... 152
108 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP) ................................... 153
109 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) ............................................... 154
110 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKS n) ................................ 155
111 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) ................................................ 157
112 Receive CPPI Control Register (RX_CPPI_CNTL) .................................................................. 158
113 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) .............................. 159
114 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) .............................. 160
115 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) .............................. 161
116 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) .............................. 162
117 Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n) ........................................................... 163
118 Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n) .......................................................... 164
119 Flow Control Table Entry Registers (FLOW_CNTL n) ................................................................ 165
120 Device Identity CAR (DEV_ID) .......................................................................................... 166
121 Device Information CAR (DEV_INFO) ................................................................................. 167
122 Assembly Identity CAR (ASBLY_ID) ................................................................................... 168
123 Assembly Information CAR (ASBLY_INFO)........................................................................... 169
124 Processing Element Features CAR (PE_FEAT) ...................................................................... 170
125 Source Operations CAR (SRC_OP).................................................................................... 171
126 Destination Operations CAR (DEST_OP) ............................................................................. 172
127 Processing Element Logical Layer Control CSR (PE_LL_CTL) .................................................... 173
128 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ............................................ 174
129 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) .............................................. 175
130 Base Device ID CSR (BASE_ID) ....................................................................................... 176
131 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) ........................................................ 177
132 Component Tag CSR (COMP_TAG) ................................................................................... 178
133 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) ..................................... 179
134 Port Link Time-Out Control CSR (SP_LT_CTL) ...................................................................... 180
135 Port Response Time-Out Control CSR (SP_RT_CTL) .............................................................. 181
136 Port General Control CSR (SP_GEN_CTL) ........................................................................... 182
137 Port Link Maintenance Request CSR n (SP n_LM_REQ) ........................................................... 183
138 Port Link Maintenance Response CSR n (SP n_LM_RESP) ........................................................ 184
139 Port Local AckID Status CSR n (SP n_ACKID_STAT) ............................................................... 185
140 Port Error and Status CSR n (SP n_ERR_STAT) ..................................................................... 186
141 Port Control CSR n (SP n_CTL) ......................................................................................... 188
142 Error Reporting Block Header (ERR_RPT_BH) ...................................................................... 190
143 Logical/Transport Layer Error Detect CSR (ERR_DET) ............................................................. 191
144 Logical/Transport Layer Error Enable CSR (ERR_EN) .............................................................. 192
145 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT).......................................... 193
146 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) ................................................... 194
147 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) ...................................................... 195
148 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) ..................................................... 196
149 Port-Write Target Device ID CSR (PW_TGT_ID) .................................................................... 197
150 Port Error Detect CSR n (SP n_ERR_DET) ........................................................................... 198
151 Port Error Rate Enable CSR n (SP n_RATE_EN) .................................................................... 199
152 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) ........................................ 200
153 Port n Packet/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) ................................ 201
154 Port n Packet/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) ................................ 202
155 Port n Packet/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) ................................ 203
156 Port n Packet/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) ................................ 204
157 Port Error Rate CSR n (SP n_ERR_RATE) ............................................................................ 205
8 List of Figures SPRU976 – March 2006
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158 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) ........................................................... 206
159 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) .............................................. 207
160 Port IP Mode CSR (SP_IP_MODE) .................................................................................... 208
161 Serial Port IP Prescalar (IP_PRESCAL) ............................................................................... 210
162 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPT n) ............................................................. 211
163 Port Reset Option CSR n (SP n_RST_OPT) .......................................................................... 212
164 Port Control Independent Register n (SP n_CTL_INDEP) ........................................................... 213
165 Port Silence Timer n (SP n_SILENCE_TIMER) ....................................................................... 215
166 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) ............................ 216
167 Port Control Symbol Transmit n (SP n_CS_TX) ...................................................................... 217
SPRU976 – March 2006 List of Figures 9
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List of Tables
1 RapidIO Documents and Links ........................................................................................... 18
2 Packet Type ................................................................................................................. 23
3 Pin Description .............................................................................................................. 24
4 Bits of SERDES_CFG n_CNTL Register (0x120 - 0x12c) ............................................................. 26
5 Line Rate versus PLL Output Clock Frequency ........................................................................ 27
6 RATE Bit Effects ............................................................................................................ 27
7 Frequency Range versus MPY ........................................................................................... 28
8 Bits of SERDES_CFGRX n_CNTL Registers ........................................................................... 28
9 EQ Bits ....................................................................................................................... 30
10 Bits of SERDES_CFGTX n_CNTL Registers ........................................................................... 30
11 SWING Bits ................................................................................................................. 31
12 DE Bits ....................................................................................................................... 31
13 Control/Command Register Field Mapping ............................................................................. 33
14 Status Fields ................................................................................................................ 34
15 RX DMA State Head Descriptor Pointer (HDP) (Address Offset 0x600-0x63C) ................................... 43
16 RX DMA State Completion Pointer (CP) (Address Offset 0x600-0x63C) ........................................... 43
17 RX Buffer Descriptor Field Descriptions ................................................................................. 45
18 TX DMA State Head Descriptor Pointer (HDP) (Address Offset 0x500 – 0x53C) ................................. 49
19 TX DMA State Completion Pointer (CP) (Address Offset 0x580 – 0x5BC) ........................................ 49
20 TX Buffer Descriptor Field Definitions ................................................................................... 49
21 Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) .............................. 52
22 Flow Control Table Entry Registers (Address Offset 0x0900 - 0x093C) ............................................ 61
23 Transmit Source Flow Control Masks ................................................................................... 62
24 Enable and Enable Status Bit Field Descriptions ...................................................................... 66
25 Emulation Control Signals ................................................................................................. 69
26 Interrupt Source Configuration Options ................................................................................. 76
27 Interrupt Condition Routing Options ..................................................................................... 81
28 Serial Rapid IO (SRIO) Registers ........................................................................................ 88
29 Peripheral ID Register (PID) Field Descriptions ........................................................................ 99
30 Peripheral Control Register (PCR) Field Descriptions ............................................................... 100
31 Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions ..................................... 101
32 Peripheral Global Enable Register (GBL_EN) Field Descriptions .................................................. 104
33 Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions ................................. 105
34 Block n Enable Register (BLK n_EN) Field Descriptions ............................................................. 106
35 Block n Enable Status Register (BLK n_EN_STAT) Field Descriptions ............................................ 107
36 RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions ............................................ 108
37 RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions ............................................ 109
38 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTL n) Field Descriptions ....................... 110
39 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTL n) Field Descriptions .......................... 111
40 SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n_CNTL) Field Descriptions ..... 112
41 EQ Bits ..................................................................................................................... 113
42 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTX n_CNTL) Field Descriptions ..... 114
43 SWING Bits ................................................................................................................ 115
44 DE Bits ..................................................................................................................... 115
45 SERDES Macros CFG (0-3) Registers (SERDES_CFG n_CNTL) Field Descriptions ........................... 116
46 DOORBELL n Interrupt Status Register (DOORBELL n_ICSR) Field Descriptions ............................... 117
47 DOORBELL n Interrupt Clear Register (DOORBELL n_ICCR) Field Descriptions ................................ 118
48 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Field Descriptions ......................................... 119
49 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Field Descriptions .......................................... 120
10 List of Tables SPRU976 – March 2006
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50 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions ......................................... 121
51 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions .......................................... 122
52 LSU Status Interrupt Register (LSU_ICSR) Field Descriptions ..................................................... 123
53 LSU Clear Interrupt Register (LSU _ICCR) Field Descriptions ..................................................... 124
54 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) Field Descriptions .... 125
55 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) Field Descriptions ..... 126
56 DOORBELL n Interrupt Condition Routing Register (DOORBELL n_ICRR) Field Descriptions ................. 127
57 DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n_ICRR2) Field Descriptions ............. 128
58 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) Field Descriptions .......................... 129
59 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) Field Descriptions ......................... 130
60 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) Field Descriptions ........................... 131
61 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) Field Descriptions ......................... 132
62 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) Field Descriptions ......................... 133
63 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) Field Descriptions ......................... 134
64 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) Field Descriptions ......................... 135
65 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) Field Descriptions ......................... 136
66 Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) Field
Descriptions ............................................................................................................... 137
67 Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) Field
Descriptions ............................................................................................................... 138
68 Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3) Field
Descriptions ............................................................................................................... 139
69 INTDST n Interrupt Status Decode Registers (INTDST n_DECODE) Field Descriptions ........................ 140
70 INTDST n Interrupt Rate Control Registers (INTDST n_RATE_CNTL) Field Descriptions ....................... 141
71 LSU n Control Register 0 (LSU n_REG0) Field Descriptions ........................................................ 142
72 LSU n Control Register 1 (LSU n_REG1) Field Descriptions ........................................................ 143
73 LSU n Control Register 2 (LSU n_REG2) Field Descriptions ........................................................ 144
74 LSU n Control Register 3 (LSU n_REG3) Field Descriptions ........................................................ 145
75 LSU n Control Register 4 (LSU n_REG4) Field Descriptions ........................................................ 146
76 LSU n Control Register 5 (LSU n_REG5) Field Descriptions ........................................................ 147
77 LSU n Control Register 6 (LSU n_REG6) Field Descriptions ........................................................ 148
78 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) Field Descriptions ............................ 149
79 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP) Field Descriptions .... 150
80 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) Field Descriptions ............ 151
81 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP) Field Descriptions .... 152
82 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP) Field Descriptions ............ 153
83 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 154
84 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKS n) Field Descriptions ......... 156
85 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 157
86 Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions ............................................ 158
87 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) Field Descriptions ........ 159
88 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) Field Descriptions ........ 160
89 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) Field Descriptions ........ 161
90 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) Field Descriptions ........ 162
91 Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n) Field Descriptions ..................................... 163
92 Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n) Field Descriptions .................................... 164
93 Flow Control Table Entry Registers (FLOW_CNTL n) Field Descriptions ......................................... 165
94 Device Identity CAR (DEV_ID) Field Descriptions ................................................................... 166
95 Device Information CAR (DEV_INFO) Field Descriptions ........................................................... 167
96 Assembly Identity CAR (ASBLY_ID) Field Descriptions ............................................................. 168
97 Assembly Information CAR (ASBLY_INFO) Field Descriptions .................................................... 169
98 Processing Element Features CAR (PE_FEAT) Field Descriptions ............................................... 170
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99 Source Operations CAR (SRC_OP) Field Descriptions ............................................................. 171
100 Destination Operations CAR (DEST_OP) Field Descriptions ....................................................... 172
101 Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions .............................. 173
102 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions ...................... 174
103 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions ........................ 175
104 Base Device ID CSR (BASE_ID) Field Descriptions ................................................................. 176
105 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions .................................. 177
106 Component Tag CSR (COMP_TAG) Field Descriptions ............................................................ 178
107 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Field Descriptions .............. 179
108 Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions ................................................. 180
109 Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions ........................................ 181
110 Port General Control CSR (SP_GEN_CTL) Field Descriptions .................................................... 182
111 Port Link Maintenance Request CSR n (SP n_LM_REQ) Field Descriptions ..................................... 183
112 Port Link Maintenance Response CSR n (SP n_LM_RESP) Field Descriptions ................................. 184
113 Port Local AckID Status CSR n (SP n_ACKID_STAT) Field Descriptions ......................................... 185
114 Port Error and Status CSR n (SP n_ERR_STAT) Field Descriptions .............................................. 186
115 Port Control CSR n (SP n_CTL) Field Descriptions .................................................................. 188
116 Error Reporting Block Header (ERR_RPT_BH) Field Descriptions ................................................ 190
117 Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ...................................... 191
118 Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions ....................................... 192
119 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions ................... 193
120 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions ............................. 194
121 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions ................................ 195
122 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions ............................... 196
123 Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions .............................................. 197
124 Port Error Detect CSR n (SP n_ERR_DET) Field Descriptions ..................................................... 198
125 Port Error Rate Enable CSR n (SP n_RATE_EN) Field Descriptions .............................................. 199
126 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) Field Descriptions ................. 200
127 Port n Packet/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) Field Descriptions .......... 201
128 Port n Packet/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) Field Descriptions .......... 202
129 Port n Packet/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) Field Descriptions .......... 203
130 Port n Packet/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) Field Descriptions .......... 204
131 Port Error Rate CSR n (SP n_ERR_RATE) Field Descriptions ..................................................... 205
132 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) Field Descriptions ..................................... 206
133 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) Field Descriptions ........................ 207
134 Port IP Mode CSR (SP_IP_MODE) Field Descriptions .............................................................. 208
135 Serial Port IP Prescalar (IP_PRESCAL) Field Descriptions ........................................................ 210
136 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPT n) Field Descriptions ....................................... 211
137 Port Reset Option CSR n (SP n_RST_OPT) Field Descriptions .................................................... 212
138 Port Control Independent Register n (SP n_CTL_INDEP) Field Descriptions .................................... 213
139 Port Silence Timer n (SP n_SILENCE_TIMER) Field Descriptions ................................................. 215
140 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) Field Descriptions ...... 216
141 Port Control Symbol Transmit n (SP n_CS_TX) Field Descriptions ................................................ 217
12 List of Tables SPRU976 – March 2006
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About This Manual
This document describes the Serial Rapid IO (SRIO) on the TMS320C645x devices.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
• The term "word" describes a 32-bit value. The term "halfword" describes a 16-bit value.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com .
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189 ) gives an
introduction to the TMS320C62x™ and TMS320C67x™ DSPs, development tools, and third-party support.
TMS320C6455 Technical Reference (literature number SPRU965 ) gives an introduction to the
TMS320C6455™ DSP and discusses the application areas that are enhanced.
TMS320C6000 Programmer's Guide (literature number SPRU198 ) describes ways to optimize C and
assembly code for the TMS320C6000™ DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301 ) introduces the Code
Composer Studio™ integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference Guide (literature number
SPRU321 ) describes the Code Composer Studio™ application programming interface (API), which allows
you to program custom plug-ins for Code Composer.
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 ) describes the
TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct
memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,
bandwidth management, and the memory and cache.
TMS320C645x DSP Peripherals Overview Reference Guide (literature number SPRUE52 ) provides a
brief description of the peripherals available on the TMS320C645x digital signal processors (DSPs).
TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234 ) is a download with the latest
chip support libraries.
Trademarks
C6000, TMS320C62x, TMS320C67x, TMS320C6455, TMS320C6000, Code Composer Studio, RapidIO
are trademarks of Texas Instruments.
Preface
SPRU976 – March 2006
Read This First
InfiniBand is a trademark of the InfiniBand Trade Association.
SPRU976 – March 2006 Preface 13
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1 Overview
The RapidIO peripheral used in the TMS320C645x is called a serial RapidIO (SRIO). This chapter
describes the general operation of a RapidIO system, how this module is connected to the outside world,
the definitions of terms used within this document, and the features supported and not supported for
SRIO.
1.1 General RapidIO System
RapidIO™ is a non-proprietary high-bandwidth system level interconnect. It is a packet-switched
interconnect intended primarily as an intra-system interface for chip-to-chip and board-to-board
communications at Gigabyte-per-second performance levels. Uses for the architecture can be found in
connected microprocessors, memory, and memory mapped I/O devices that operate in networking
equipment, memory subsystems, and general purpose computing. Principle features of RapidIO include:
• Flexible system architecture allowing peer-to-peer communication
• Robust communication with error detection features
• Frequency and port width scalability
• Operation that is not software intensive
• High bandwidth interconnect with low overhead
• Low pin count
• Low power
• Low latency
User's Guide
SPRU976 – March 2006
Serial RapidIO (SRIO)
1.1.1 RapidIO Architectural Hierarchy
RapidIO is defined as a 3-layer architectural hierarchy.
• Logical layer: Specifies the protocols, including packet formats, which are needed by endpoints to
process transactions
• Transport layer: Defines addressing schemes to correctly route information packets within a system
• Physical layer: Contains the device level interface information such as the electrical characteristics,
error management data, and basic flow control data
In the RapidIO architecture, a single specification for the transport layer is compatible with differing
specifications for the logical and physical layers (see Figure 1 ).
14 Serial RapidIO (SRIO) SPRU976 – March 2006
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Globally
shared
memory spec
logical
Future
Message
passingsystem
I/O
Logical specification
Information necessary for the end point
to process the transaction (i.e., transaction
type, size, physical address)
to end in the system (i.e., routing address)
Information to transport packet from end
Transport specification
spec
transport
Common
between two physical devices (i.e., electrical
Information necessary to move packet
interface, flow control)
Physical specification
1x/4x
LP serialLP-LVDS
8/16
Future
spec
physical
checklist
Compliance
Inter-
operability
specification
Figure 1. RapidIO Architectural Hierarchy
Overview
SPRU976 – March 2006 Serial RapidIO (SRIO) 15
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Host Subsystem
I/O Control Subsystem
DSP Farm
TDM,GMII, Utopia
Communications Subsystem PCI Subsystem
InfiniBand HCA™
To SystemArea
Network
Memory
Memory
Memory
Memory
RapidIO
RapidIO RapidIO
RapidIO
RapidIO
Backplane
PCI
RapidIO
RapidIO
RapidIO
RapidIO
Switch
Control
Processor
IO
Processor
RapidIO to
InfiniBand
RapidIO
Switch
RapidIO
Switch
Legacy
Comm
Processor
RapidIO
Switch
RapidIO to
PCI Bridge
ASIC/FPGA
Memory
Memory
Host
Processor
Host
Processor
DSP DSP DSP DSP
Comm
Processor
Overview
1.1.2 RapidIO Interconnect Architecture
The interconnect architecture is defined as a packet switched protocol independent of a physical layer
implementation. Figure 2 illustrates the interconnection system.
Figure 2. RapidIO Interconnect Architecture
1.1.3 1x/4x LP-Serial
(1) InfiniBand™ is a trademark of the InfiniBand Trade Association.
Currently, there are two physical layer specifications recognized by the RapidIO Trade Association: 8/16
LP-LVDS and 1X/4X LP-Serial. The 8/16 LP-LVDS specification is a point-to-point synchronous clock
sourcing DDR interface. The 1X/4X LP-Serial specification is a point-to-point, AC coupled, clock recovery
interface. The two physical layer specifications are not compatible.
SRIO complies with the 1X/4X LP-Serial specification. The serializer/deserializer (SERDES) technology in
SRIO also aligns with that specification.
The 1X/4X LP-Serial specification currently covers three frequency points: 1.25, 2.5, and 3.125 Gbps. This
defines the total bandwidth of each differential pair of I/O signals. An 8b/10b encoding scheme ensures
ample data transitions for the clock recovery circuits. Due to the 8b/10b encoding overhead, the effective
data bandwidth per differential pair is 1.0, 2.0, and 2.5 Gbps respectively. Serial RapidIO only specifies
these rates for both the 1X and 4X ports. A 1X port is defined as 1 TX and 1 RX differential pair. A 4X port
is a combination of four of these pairs. This document describes a 4X RapidIO port that can also be
configured as four 1X ports, thus providing a scalable interface capable of supporting a data bandwidth of
1 to 10 Gbps.
16 Serial RapidIO (SRIO) SPRU976 – March 2006
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Serial RapidIO 1x Device to 1x Device Interface Diagram
Serial RapidIO 4x Device to 4x Device Interface Diagram
1x Device
TD[0]
TD[0]
RD[0]
RD[0]
TD[0]
TD[0]
1x Device
RD[0]
RD[0]
RD[0-3]
RD[0-3]
4x Device
TD[0-3]
RD[0-3]
RD[0-3]
TD[0-3]
4x Device
TD[0-3]
TD[0-3]
Figure 3. Serial RapidIO Device to Device Interface Diagrams
1.2 RapidIO Feature Support in SRIO
Features Supported in SRIO:
• RapidIO Interconnect Specification V1.2 compliance, Errata 1.2
• LP-Serial Specification V1.2 compliance
• 4X Serial RapidIO with auto-negotiation to 1X port, optional operation for four 1X ports
• Integrated clock recovery with TI SERDES
• Hardware error handling including Cyclic Redundancy Code (CRC)
• Differential CML signaling supporting AC and DC coupling
• Support for 1.25, 2.5, and 3.125 Gbps rates
• Power-down option for unused ports
• Read, write, write with response, streaming write, outgoing Atomic, and maintenance operations
• Generates interrupts to the CPU (Doorbell packets and internal scheduling)
• Support for 8b and 16b device ID
• Support for receiving 34b addresses
• Support for generating 34b, 50b, and 66b addresses
• Support for the following data sizes: byte, half-word, word, double-word
• Big endian data transfers
• Direct IO transfers
• Message passing transfers
• Data payloads of up to 256B
• Single messages consisting of up to 16 packets
• Elastic storage FIFOs for clock domain handoff
• Short run and long run compliance
• Support for Error Management Extensions
• Support for Congestion Control Extensions
• Support for one multi-cast ID
Overview
SPRU976 – March 2006 Serial RapidIO (SRIO) 17
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Overview
Features Not Supported:
• Compliance with the Global Shared Memory specification (GSM)
• 8/16 LP-LVDS compatible
• Destination support of RapidIO Atomic Operations
• Simultaneous mixing of frequencies between 1X ports (all ports must be the same frequency)
• Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal
1.3 Standards
The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specification and V1.2 of the
LP-Serial specification.
Document Link Description
Official RapidIO Web Site http://www.RapidIO.org Various associated docs
1.4 External Devices Requirements
SRIO provides a seamless interface to all devices which are compliant to V1.2 of the LP-Serial RapidIO
specification. This includes ASIC, microprocessor, DSP, and switch fabric devices from multiple vendors.
Compliance to the specification can be verified with bus-functional models available through the RapidIO
Trade Association, as well as test suites currently available for licensing.
L2 memory and registers
Table 1. RapidIO Documents and Links
Serial RapidIO (SRIO)18 SPRU976 – March 2006
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2 SRIO Functional Description
2.1 Overview
2.1.1 Peripheral Data Flow
This peripheral is designed to be an external slave module that is capable of mastering the internal DMA.
This means that an external device can push (burst write) data to the DSP as needed, without having to
generate an interrupt to the CPU. This has two benefits. It cuts down on the total number of interrupts, and
it reduces handshaking (latency) associated with read-only peripherals.
SRIO specifies data packets with payloads up to 256 bytes. Many times, transactions will span across
multiple packets. RapidIO specifies a maximum of 16 transactions per message. Although a request is
generated for each packet transaction so that the DMA can transfer the data to L2 memory, an interrupt is
only generated after the final packet of the message. This interrupt notifies the CPU that data is available
in L2 Memory for processing.
As an endpoint device, the peripheral accepts packets based on the destination ID. Two options exist for
packet acceptance and are mode selectable. The first option is to only accept packets whose DestIDs
match the local deviceID in 0x0080. This provides a level of security. The second option is to accept
incoming packets matching the deviceID in either 0x0080 or 0x0084. This allows for system multicast
operations.
Data flow through the peripheral can be explained using the high-level block diagram shown in Figure 4 .
High-speed data enters from the device pins into the RX block of the SERDES macro. The RX block is a
differential receiver expecting a minimum of 175mV peak-to-peak differential input voltage (Vid). Level
shifting is performed in the RX block, such that the output is single ended CMOS. The serial data is then
fed to the SERDES clock recovery block. The sole purpose of this block is to extract a clock signal from
the data stream. To do this, a low-frequency reference clock is required, 1/10
example, for 3.125 Gbps data, a reference clock of 312.5Mhz or 156.25Mhz is needed. Typically, this
clock comes from an off-chip stable crystal oscillator and is a LVDS device input separate to the SERDES.
This clock is distributed to the SERDES PLL block which multiplies that frequency up to that of the data
rate. Eight phases of this high-speed clock are created and routed to the clock recovery blocks. The clock
recovery block further interpolates eight times between these clock phases. This provides clock edge
resolution of 1/96
monitors the relative positions of the data edges. With this information, it can provide the data and a
center-aligned clock to the S2P block. The S2P block uses the newly recovered clock to demux the data
into 10-bit words. At this point, the data leaves the SERDES macro at 1/10th the pin data rate,
accompanied by an aligned byte clock.
SRIO Functional Description
th
or ½0ththe data rate. For
th
the Unit Interval (UI). The clock recovery block samples the incoming data and
SPRU976 – March 2006 Serial RapidIO (SRIO) 19
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1.25-3.125 Gbps
differential data
Rx
Clock
recovery
S2P
10b
Clk
8b/10b
decode
8b
Clock
recovery
Rx
8b8b/10b
decode
10b
ClkS2P
Clock
recovery
Rx
8b8b/10b
decode
10b
ClkS2P
Clock
recovery
Rx
8b8b/10b
decode
10b
ClkS2P
PLL
Tx
Tx
Tx
Tx
P2S
P2S
P2S
P2S
8b
8b
8b
8b
10b
8b/10b
coding
Clk
8b/10b
coding
8b/10b
coding
8b/10b
coding
10b
Clk
10b
Clk
10b
Clk
FIFO
FIFO
FIFO
FIFO
System
clock
Capability
registers
Control
Command
and status
registers
SERDES
Clock domain 2
Clock domain 3
Clock domain 1
DMA
bus
Packet Generation
Lane striping
Lane de-skew
CRC error detection
CRC generation
Buffering address and data handoff
FIFO
FIFO
FIFO
FIFO
SRIO Functional Description
Figure 4. SRIO Peripheral Block Diagram
Within the physical layer, the data next goes to the 8b/10b decode block. 8b/10b encoding is used by
RapidIO to ensure adequate data transitions for the clock recovery circuits. Here the 20% encoding
overhead is removed as the 10-bit data is decoded to the raw 8-bit data. At this point, the recovered byte
clock is still being used.
The next step is clock synchronization and data alignment. These functions are handled by the FIFO and
lane de-skewing blocks. The FIFO provides an elastic store mechanism used to hand off between the
recovered clock domains and a common system clock. After the FIFO, the four lanes are synchronized in
frequency and phase, whether 1X or 4X mode is being used. The FIFO is 8 words deep. The lane
de-skew is only meaningful in the 4X mode, where it aligns each channel’s word boundaries, such that the
resulting 32-bit word is correctly aligned.
The CRC error detection block keeps a running tally of the incoming data and computes the expected
CRC value for the 1X or 4X mode. The expected value is compared against the CRC value at the end of
the received packet.
After the packet reaches the logical layer, the packet fields are decoded and the payload is buffered.
Depending on the type of received packet, the packet routing is handled by functional blocks which control
the DMA access.
2.1.2 SRIO Packets
2.1.2.1 Operation Sequence
20 Serial RapidIO (SRIO) SPRU976 – March 2006
The SRIO data stream consists of data fields pertaining to the logical layer, the transport layer, and the
physical layer.
• The logical layer consists of the header (defining the type of access) and the payload (if present).
• The transport layer is partially dependent on the physical topology in the system, and consists of
• The physical layer is dependent on the physical interface (i.e., serial versus parallel RapidIO) and
SRIO transactions are based on request and response packets. Packets are the communication element
between endpoint devices in the system. A master or initiator generates a request packet which is
transmitted to a target. The target then generates a response packet back to the initiator to complete the
transaction.
source and destination IDs for the sending and receiving devices.
includes priority, acknowledgment, and error checking fields.
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Initiator
Request
Packet Issued
Operation
Completed for
Master
Acknowledge
Symbol
Acknowledge
Symbol
Response
Packet
Forwarded
Request Packet
Forwarded
Acknowledge
Symbol
Acknowledge
Symbol
Response Packet
Issued
Fabric
Target
Target
Completes
Operation
Operation
Issued By
Master
SRIO Functional Description
SRIO endpoints are typically not connected directly to each other but instead have intervening connection
fabric devices. Control symbols are used to manage the flow of transactions in the SRIO physical
interconnect. Control symbols are used for packet acknowledgment, flow control information, and
maintenance functions. Figure 5 shows how a packet progresses through the system.
Figure 5. Operation Sequence
2.1.2.2 Example Packet – Streaming Write
An example packet is shown as two data streams in Figure 6 . The first is for payload sizes of 80 bytes or
less, while the second applies to payload sizes of 80 to 256 bytes. SRIO packets must have a length that
is an even integer of 32 bits. If the combination of physical, logical and transport layers has a length that is
an integer of 16 bits, a 16-bit pad of value 0x0000 is added to the end of the packet, after the CRC (not
shown). Bit fields that are defined as reserved are assigned to logic 0s when generated and ignored when
received. All request and response packet formats are described in the I/O and Message Passing Logical
Specifications.
SPRU976 – March 2006 Serial RapidIO (SRIO) 21
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double-word n-1
acklD rsv
prio
tt ftype
destID
sourcelD
address
rsrv
xamsbs double-word 0
double-word 1
...
double-word n-2
CRC
PHY
LOG
TRA
LOG
TRA
PHY
5
3
2
2
4
8
8
29
1
2
64 64
(n-4)*64
64
64
16
16
n*64+32
16
4
2
10
LOG
PHY10TRA
2 4
9 * 6 4 + 32
LOG
TRA
16
PHY
16
double-word 0
5
acklD sourcelDrsv
3
prio
2
ftype
tt
2 4
destiD
8
1
rsrv
address
8 29
xamsbs
2
64
double-word 8
double-word 1
64
5*64
...
64
double-word 9
64
CRC
16
LOG
(n-9)*64
16
PHY
double-word 10
64
double-word n-2double-word 11
64
(n-13)*64
...
double-word n-1
6464
16
CRC
n*64+96
n*64+80
PHY = Physical layer
TRA = Transport layer
LOG = Logical layer
SC or PD parameter1stype0 stype1Parameter0 cmd CRC
533553
Delimiter 1st Byte 2nd Byte 3rd Byte
8
SRIO Functional Description
Figure 6. 1x/4x RapidIO Packet Data Stream (Streaming-Write Class)
Note: Figure 6 assumes that addresses are 32-bit and device IDs are 8-bit.
The device ID, being an 8-bit field, will address up to 256 nodes in the system. If 16-bit addresses were
used, the system could accommodate up to 64k nodes.
The data stream includes a Cyclic Redundancy Code (CRC) field to ensure the data was correctly
received. The CRC value protects the entire packet except the ackID and one bit of the reserved PHY
field. The peripheral checks the CRC automatically in hardware. If the CRC is correct, a Packet-Accepted
control symbol is sent by the receiving device. If the CRC is incorrect, a Packet-Not-Accepted control
symbol is sent so that transmission may be retried.
2.1.2.3 Control Symbols
Control symbols are physical layer message elements used to manage link maintenance, packet
delimiting, packet acknowledgment, error reporting, and error recovery. All transmitted data packets are
delimited by start-of-packet and end-of-packet delimiters. SRIO control symbols are 24 bits long and are
protected by their own CRC. Control symbols provide two functions: stype0 symbols convey the status of
the port transmitting the symbol, and stype1 symbols are requests to the receiving port or transmission
delimiters. They have the following format, which is detailed in section 3 of the RapidIO LP-Serial
specification.
Figure 7. Serial RapidIO Control Symbol Format
Control symbols are delimited by special characters at the beginning of the symbol. If the control symbol
If the control symbol does not contain a packet delimiter, the special character SC (K28.0) is used. This
use of special characters provides an early warning of the contents of the control symbol. The CRC does
contains a packet delimiter(start-of-packet, end-of-packet, etc.), the special character PD (K28.3) is used.
not protect the special characters, but an illegal or invalid character is recognized and flagged as
Packet-Not-Accepted. Since control symbols are known length, they do not need end delimiters.
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The type of received packet determines how the packet routing is handled. Reserved or undefined packet
types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous
allocation of resources to them. Unsupported packet types are responded to with an error response
packet. Section 2.1.2.4 details the handling of such packets.
2.1.2.4 SRIO Packet Ftype/Ttype
The type of SRIO packet is determined by the combination of Ftype and Ttype fields in the packet. Table 2
lists all supported combinations of Ftype/Ttype and the corresponding decoded actions on the packets.
Ftype Ttype Packet Type
Ftype=0, Ttype=don't care
Ftype=2, Ttype=0100b, NREAD
Ftype=5, Ttype=0100b, NWRITE
Ftype=6, Ttype=don't care, SWRITE
Ftype=7, Ttype=don't care, Congestion
Ftype=8, Ttype=0000b, Mtn Rd
Ftype=10, Ttype=don't care, Doorbell
Ftype=11, Ttype=don't care, Message
Ftype=13, Ttype=0000b, Resp(+Dbll Resp)
Undefined Ftype (1,3,4,9,12,14,15):
SRIO Functional Description
Table 2. Packet Type
Ttype=1100b, Atomic inc
Ttype=1101b, Atomic dec
Ttype=1110b, Atomic set
Ttype=1111b, Atomic clr
Ttype=others,
Ttype=0101b, NWRITE_R
Ttype=1110b, Atomic t&s
Ttype=others,
Ttype=0001b, Mtn Wr
Ttype=0010b, Mtn Rd Resp
Ttype=0011b, Mtn Wr Resp
Ttype=0100b, Mtn Pt-Wr
Ttype=others,
Ttype=0001b, Message Resp
Ttype=1000b, Resp w/payload
Ttype=other,
Packet type definition:
#define REQ_MAINT_RD 0x80 //0b10000000 // ftype=8
#define REQ_MAINT_WR 0x81 //0b10000001 // ftype=8
#define REQ_MAINT_PW 0x84 //0b10000100 // ftype=8
#define REQ_ATOMIC_INC 0x2C //0b00101100 // ftype=2
#define REQ_ATOMIC_DEC 0x2D //0b00101101 // ftype=2
#define REQ_ATOMIC_SET 0x2E //0b00101110 // ftype=2
#define REQ_ATOMIC_CLR 0x2F //0b00101111 // ftype=2
#define REQ_ATOMIC_TNS 0x5E //0b01011110 // ftype=5
#define REQ_NREAD 0x24 //0b00100100 // ftype=2
#define REQ_NWRITE 0x54 //0b01010100 // ftype=5
#define REQ_NWRITE_R 0x55 //0b01010101 // ftype=5
#define REQ_SWRITE 0x60 //0b01100000 // ftype=6
#define REQ_DOORBELL 0xA0 //0b10100000 // ftype=10
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SRIO Functional Description
2.2 SRIO Pins
The SRIO device pins are high-speed differential signals based on Current-Mode Logic (CML) switching
levels. The transmit and receive buffers are self-contained within the clock recovery blocks. The reference
clock input is not incorporated into the SERDES macro. It uses a common LVDS input buffer that aligns
interfaces with crystal oscillator manufacturers. None of the peripheral pins may be used as GPIO pins.
Table 3 provides more detail.
Table 3. Pin Description
Pin Name Pin Signal Description
Count Direction
RIOTX3/ RIOTX3 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Most significant bit of a 4X
device.
RIOTX2/ RIOTX2 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins.
RIOTX1/ RIOTX1 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins.
RIOTX0/ RIOTX0 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Bit used for 1X mode.
RIORX3/ RIORX3 2 Input Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Most significant bits in
4X mode.
RIORX2/ RIORX2 2 Input Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins.
RIORX1/ RIORX1 2 Input Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins.
RIORX0/ RIORX0 2 Input Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Bit used for 1X mode
RIOCLK/ RIOCLK 2 Input Reference Clock Input Buffer for peripheral clock recovery circuitry.
2.3 Functional Operation
2.3.1 Block Diagram
Figure 8 shows a conceptual block diagram of the SRIO peripheral. The load/store unit (LSU) controls the
transmission of Direct I/O packets, and the memory access unit (MAU) controls the reception of Direct I/O
packets. The LSU also controls the transmission of maintenance packets. Message packets are
transmitted by the TXU and received by the RXU. These four units use the internal DMA to communicate
with internal memory, and they use buffers and receive/transmit ports to communicate with external
devices. Serializer/deserializer (SERDES) macros support the ports by performing the parallel-to-serial
coding for transmission and serial-to-parallel decoding for reception.
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Port 0
8 x 276 TX
8 x 276 RX
8 x 276 RX
8 x 276 TX
Port 1
8 x 276 TX
8 x 276 RX
Port 2
8 x 276 RX
8 x 276 TX
Port 3
Physical
layer
buffers
SERDES 0 SERDES 1 SERDES 2 SERDES 3
SERDES
differential
signals
4x mode
data path
TX buffering
32 x 276B
8 buffers per 1X port - all priorities
32 buffers per 4X port - 8 per priority
Transaction
mapping
layer
buffers
Logical
Load/store
unit (LSU)
Tx direct I/O
Maintenance
Messaging
TXU
Rx direct I/O
(MAU)
Memory
access unit
RXU
Messaging
buffer
4.5 KB Tx
shared
buffer
shared
4.5 KB Tx
handle
Queue
128-bit
DMA bus 128-bit
SRIO Functional Description
Figure 8. SRIO Conceptual Block Diagram
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SRIO Functional Description
2.3.2 SERDES and its Configurations
SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of
TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can
be used for all three frequency nodes specified in V1.2 of the RapidIO specification (1.25, 2.5, and 3.125
Gbps). This allows you to design to only one protocol throughout the system and selectively choose the
bandwidth, thus eliminating the need for user’s proprietary protocols in many instances, and providing a
faster design turn and production ramp. Since this interface is serial, the application space is not limited to
a single board. It will propagate into backplane applications as well. Integration of these macros on an
ASIC or DSP allows you to reduce the number of discrete components on the board and eliminates the
need for bus driver chips.
Additionally, there are some valuable features built into TI SERDES. System optimization can be uniquely
managed to meet individual customer applications. For example, control registers within the SERDES
allow you to adjust the TX differential output voltage (Vod) on a per driver basis. This allows power
savings on short trace links (on the same board) by reducing the TX swing. Similarly, data edge rates can
be adjusted through the control registers to help reduce any EMI affects. Unused links can be individually
powered down without affecting the working links.
Because the high-speed analog nature of the SERDES is often the most critical portion of the RapidIO
peripheral, good test access is important.
The SERDES is a self-contained macro which includes transmitter (TX), receiver (RX), phase-locked-loop
(PLL), clock recovery, serial-to-parallel (S2P), and parallel-to-serial (P2S) blocks. The internal PLL
multiplies a user-supplied reference clock. All loop filter components of the PLL are onchip. Likewise, the
differential TX and RX buffers contain on-chip termination resistors. The only off-chip component
requirement is for DC blocking capacitors. These capacitors are needed only to ensure interoperability
between vendors and can be removed in cases where TI devices talk to other TI devices at the same
voltage node. The SERDES are designed for 1.2V ± 5% operation. This provides for excellent power
efficiency.
2.3.2.1 Enabling the PLL
The Physical layer SERDES has a built-in PLL, which is used for the clock recovery circuitry. The PLL is
responsible for clock multiplication of a slow speed reference clock. This reference clock has no timing
relationship to the serial data and is asynchronous to any CPU system clock. The multiplied high-speed
clock is only routed within the SERDES block, it is not distributed to the remaining blocks of the peripheral,
nor is it a boundary signal to the core of the device. It is extremely important to have a good quality
reference clock, and to isolate it and the PLL from all noise sources. A unique Reference Clock
Distribution (RCD) macro is used for this purpose. Since RapidIO requires 8b/10b encoded data, the 8-bit
mode of the SERDES PLL will not be used.
SERDES_CFG n_CNTL, SERDES_CFGRX n_CNTL, and SERDES_CFGTX n_CNTL registers are used to
configure SERDES. To enable the internal PLL, the ENPLL bit of SERDES_CFG n_CNTL must be set
high. After setting this bit, it is necessary to allow 1µs for the regulator to stabilize. Thereafter, the PLL will
take no longer than 200 reference clock cycles to lock to the required frequency, provided RIOCLK and
RIOCLK are stable.
Table 4. Bits of SERDES_CFG n_CNTL Register (0x120 - 0x12c)
Bit Name Value Description
31:10 Reserved Reserved.
9:8 LB Loop bandwidth. Specify loop bandwidth settings.
00 Frequency dependent bandwidth. The PLL bandwidth is set to a twelfth of the frequency of RIOCLK
and RIOCLK.
01 Reserved
10 Low bandwidth. The PLL bandwidth is set to a twentieth of the frequency of RIOCLK and RIOCLK,
or 3MHz (whichever is larger).
11 High bandwidth. The PLL bandwidth is set to an eighth of the frequency of RIOCLK and RIOCLK.
7:6 Reserved Reserved.
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SRIO Functional Description
Table 4. Bits of SERDES_CFG n_CNTL Register (0x120 - 0x12c) (continued)
Bit Name Value Description
5:1 MPY PLL multiply. Select PLL multiply factors between 4 and 60. Multiply modes shown below.
0000 4x
0001 5x
0010 6x
0011 Reserved
0100 8x
0101 10x
0110 12x
0111 12.5x
1000 15x
1001 20x
1010 25x
1011 Reserved
1100 Reserved
1101 50x
1110 60x
1111 Reserved
0 ENPLL Enable PLL. Enables the PLL.
Based on the MPY value, the following line rate versus PLL output clock frequency can be estimated:
Table 5. Line Rate versus PLL Output Clock Frequency
Rate Line Rate PLL Output Frequency RATESCALE
Full x Gbps 0.5x GHz 0.5
Half x Gbps x GHz 1
Quarter x Gbps 2x GHz 2
RIOCLK and RIOCLK
FREQ
= LINERATE × RATESCALE
MPY
The rate is defined by the RATE bits of the SERDES_CFGRX n_CNTL register and the
SERDES_CFGTX n_CNTL register, respectively.
The primary operating frequency of the SERDES macro is determined by the reference clock frequency
and PLL multiplication factor. However, to support lower frequency applications, each receiver and
transmitter can also be configured to operate at a half or quarter of this rate via the RATE bits of the
SERDES_CFGRX n_CNTL and SERDES_CFGTX n_CNTL registers as described in Table 6 .
Table 6. RATE Bit Effects
Value Description
0 0 Full rate. Two data samples taken per PLL output clock cycle.
0 1 Half rate. One data sample taken per PLL output clock cycle.
1 0 Quarter rate. One data sample taken every two PLL output clock cycles.
1 1 Reserved.
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SRIO Functional Description
Here is the frequency range versus MPY:
MPY RIOCLK and RIOCLK Line Rate Range (Gbps)
4x 250 - 425 2 - 3.4 1 - 1.7 0.5 - 0.85
5x 200 - 425 2 - 4.25 1 - 2.125 0.5 - 1.0625
6x 167 - 354.167 2 - 4.25 1 - 2.125 0.5 - 1.0625
8x 125 - 265.625 2 - 4.25 1 - 2.125 0.5 - 1.0625
10x 100 - 212.5 2 - 4.25 1 - 2.125 0.5 - 1.0625
12x 83.33 - 177.08 2 - 4.25 1 - 2.125 0.5 - 1.0625
12.5x 80 - 170 2 - 4.25 1 - 2.125 0.5 - 1.0625
15x 66.67 - 141.67 2 - 4.25 1 - 2.125 0.5 - 1.0625
20x 50 - 106.25 2 - 4.25 1 - 2.125 0.5 - 1.0625
25x 40 - 85 2 - 4.25 1 - 2.125 0.5 - 1.0625
50x 25 - 42.5 2.5 - 4.25 1.25 - 2.125 0.625 - 1.0625
60x 25 - 35.42 3 - 4.25 1.5 - 2.125 0.75 - 1.0625
2.3.2.2 Enabling the Receiver
To enable a receiver for deserialization, the ENRX bit of the associated SERDES_CFGRX n_CNTL
registers (0x100-0x10c) must be set high.
When ENRX is low, all digital circuitry within the receiver will be disabled, and clocks will be gated off. All
current sources within the receiver will be fully powered down, with the exception of those associated with
the loss of signal detector and IEEE1149.6 boundary scan comparators. Loss of signal power down is
independently controlled via the LOS bits of SERDES_CFGRX n_CNTL.
Table 7. Frequency Range versus MPY
Range (MHz) Full Half Quarter
Table 8. Bits of SERDES_CFGRX n_CNTL Registers
Bit Field Value Description
31:26 Reserved Reserved.
25 Reserved Reserved, keep as zero during writes to this register.
24 Reserved Reserved, keep as zero during writes to this register.
23 Reserved Reserved.
22:19 EQ Equalizer. Enables and configures the adaptive equalizer to compensate for loss in the
18:16 CDR Clock/data recovery. Configures the clock/data recovery algorithm.
000 First order. Phase offset tracking up to ± 488 ppm.
001 Second order. Highest precision frequency offset matching but poorest response to changes in
010 Second order. Medium precision frequency offset matching, frequency offset change response
011 Second order. Best response to changes in frequency offset and fastest lock time, but lowest
100 First order with fast lock. Phase offset tracking up to ± 1953 ppm in the presence of ..10101010..
101 Second order with fast lock. As per setting 001, but with improved response to changes in
110 Second order with fast lock. As per setting 010, but with improved response to changes in
111 Second order with fast lock. As per setting 011, but with improved response to changes in
transmission media. For values, see Table 9 .
frequency offset, and longest lock time. Suitable for use in systems with fixed frequency offset.
and lock time.
precision frequency offset matching. Suitable for use in systems with spread spectrum clocking.
training pattern, and ± 448 ppm otherwise.
frequency offset when not close to lock.
frequency offset when not close to lock.
frequency offset when not close to lock.
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SRIO Functional Description
Table 8. Bits of SERDES_CFGRX n_CNTL Registers (continued)
Bit Field Value Description
15:14 LOS Loss of signal. Enables loss of signal detection with 2 selectable thresholds.
00 Disabled. Loss of signal detection disabled.
01 High threshold. Loss of signal detection threshold in the range 85 to 195mV
suitable for Infiniband.
10 Low threshold. Loss of signal detection threshold in the range 65-175mV
suitable for PCI-E and S-ATA.
11 Reserved
13:12 ALIGN Symbol alignment. Enables internal or external symbol alignment.
00 Alignment disabled. No symbol alignment will be performed while this setting is selected, or
when switching to this selection from another.
01 Comma alignment enabled. Symbol alignment will be performed whenever a misaligned comma
symbol is received.
10 Alignment jog. The symbol alignment will be adjusted by one bit position when this mode is
selected (i.e., CFGRX[13:12] changes from 0x to 1x).
11 Reserved
11 Reserved Reserved.
10:8 TERM Termination. Selects input termination options suitable for a variety of AC or DC coupled
scenarios.
000 Common point connected to VDDT. This configuration is for DC coupled systems using CML
transmitters. The common mode voltage is determined jointly by both the receiver and the
transmitter. Common mode termination is via a 50 pF capacitor to VSSA.
001 Common point set to 0.8 VDDT. This configuration is for AC coupled systems using CML
transmitters. The transmitter has no effect on the receiver common mode, which is set to
optimize the input sensitivity of the receiver. Common mode termination is via a 50 pF capacitor
to VSSA.
010 Reserved
011 Common point floating. This configuration is for DC coupled systems that require the common
mode voltage to be determined by the transmitter only. These are typically not CML. Common
mode termination is via a 50 pF capacitor to VSSA.
1xx Reserved
7 INVPAIR Invert polarity. Inverts polarity of RXP n and RXN n.
0 Normal polarity. RXP n considered to be positive data and RXN n negative.
1 Inverted polarity. RXP n considered to be negative data and RXN n positive.
6:5 RATE Operating rate. Selects full, half or quarter rate operation.
00 Full rate. Two data samples taken per PLL output clock cycle.
01 Half rate. One data sample taken per PLL output clock cycle.
10 Quarter rate. One data sample taken every two PLL output clock cycles.
11 Reserved
4:2 BUS- Bus width. Selects the width of the parallel interface (10 or 8 bit).
WIDTH
000 10-bit operation. Data is output on RD n[9:0]. RXBCLK[ n] period is 10 bit periods (4 high, 6 low).
001 8-bit operation. Data is output on RD n[7:0]. RXBCLK[ n] period is 8 bit periods (4 high, 4 low).
RD n[9:8] will replicate bits [1:0] from the previous byte.
01x Reserved
1xx Reserved
1 Reserved Reserved, keep as zero during writes to this register.
0 ENRX Enable receiver. Enables this receiver when high.
0 Disable
1 Enable
. This setting is
dfpp
. This setting is
dfpp
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SRIO Functional Description
2.3.2.3 Enabling the Transmitter
To enable a transmitter for serialization, the ENTX bit of the associated SERDES_CFGTX n_CNTL
registers (0x110 – 0x10c) must be set high. When ENTX is low, all digital circuitry within the transmitter
will be disabled, and clocks will be gated off, with the exception of the transmit clock (TXBCLK[ n]) output,
which will continue to operate normally. All current sources within the transmitter will be fully powered
down, with the exception of the CML driver, which will remain powered up if boundary scan is selected.
Table 9. EQ Bits
CFGRX[22:19] Low Freq Gain Zero Freq (at e28(min))
0000 Maximum 0001 Adaptive Adaptive
001x Reserved
01xx Reserved
1000 Adaptive 1084MHz
1001 805MHz
1010 573MHz
1011 402MHz
1100 304MHz
1101 216MHz
1110 156MHz
1111 135MHz
Table 10. Bits of SERDES_CFGTX n_CNTL Registers
Bit Field Value Description
31:17 Reserved Reserved.
16 ENFTP Enable fixed TXBCLKIN n phase. Enables fixed phase relationship of TXBCLKIN n with respect to
0 Arbitrary phase. No required phase relationship between TXBCLKIN n and TXBCLK n.
1 Fixed phase. Requires direct connection of TXBCLK n to TXBCLKIN n using a minimum length
15:12 DE De-emphasis. Selects one of 15 output de-emphasis settings from 4.76 to 71.42%. See
11:9 SWING Output swing. Selects one of 8 output amplitude settings between 125 and 1250mV
8 CM Common mode. Adjusts the common mode to suit the termination at the attached receiver.
0 Normal common mode. Common mode not adjusted.
1 Raised common mode. Common mode raised by 5% of e54.
7 INVPAIR Invert polarity. Inverts polarity of TXP n and TXNn.
0 Normal polarity. TXP n considered to be positive data and TXN n negative.
1 Inverted polarity. TXP n considered to be negative data and TXN n positive.
6:5 RATE Operating rate. Selects full, half or quarter rate operation.
00 Full rate. Two data samples taken per PLL output clock cycle.
01 Half rate. One data sample taken per PLL output clock cycle.
10 Quarter rate. One data sample taken every two PLL output clock cycles.
11 Reserved
TXBCLK n.
net without buffers.
Table 12 .
Table 11 .
. See
dfpp
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