Texas Instruments TMS320C642x DSP User Manual
TMS320C642x DSP
Phase-Locked Loop Controller (PLLC)
User's Guide
Literature Number: SPRUES0B
December 2007
2 SPRUES0B – December 2007
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Contents
Preface ............................................................................................................................... 5
1 Device Clocking .......................................................................................................... 6
1.1 Overview .......................................................................................................... 6
1.2 Clock Domains ................................................................................................... 6
2 PLL Controller ........................................................................................................... 11
2.1 PLL Module ...................................................................................................... 11
2.2 PLL1 Control .................................................................................................... 12
2.3 PLL2 Control .................................................................................................... 16
2.4 PLL Controller Registers ....................................................................................... 21
Appendix A Revision History ............................................................................................. 34
SPRUES0B – December 2007 Table of Contents 3
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List of Figures
1 Overall Clocking Diagram ................................................................................................... 7
2 PLL1 Structure in the TMS320C642x DSP ............................................................................. 12
3 PLL2 Structure in the TMS320C642x DSP ............................................................................. 16
4 Peripheral ID Register (PID) .............................................................................................. 22
5 Reset Type Status Register (RSTYPE) ................................................................................. 22
6 PLL Control Register (PLLCTL) .......................................................................................... 23
7 PLL Multiplier Control Register (PLLM) ................................................................................. 24
8 PLL Controller Divider 1 Register (PLLDIV1) ........................................................................... 24
9 PLL Controller Divider 2 Register (PLLDIV2) .......................................................................... 25
10 PLL Controller Divider 3 Register (PLLDIV3) .......................................................................... 25
11 Oscillator Divider 1 Register (OSCDIV1) ................................................................................ 26
12 Bypass Divider Register (BPDIV) ........................................................................................ 27
13 PLL Controller Command Register (PLLCMD) ......................................................................... 28
14 PLL Controller Status Register (PLLSTAT) ............................................................................. 28
15 PLL Controller Clock Align Control Register (ALNCTL) ............................................................... 29
16 PLLDIV Ratio Change Status Register (DCHANGE) .................................................................. 30
17 Clock Enable Control Register (CKEN) ................................................................................. 31
18 Clock Status Register (CKSTAT) ........................................................................................ 32
19 SYSCLK Status Register (SYSTAT) ..................................................................................... 33
List of Tables
1 System Clock Modes and Fixed Ratios for Core Clock Domains ..................................................... 6
2 Example PLL1 Frequencies and Dividers (25 MHZ Clock Input)...................................................... 8
3 Example PLL2 Frequencies (Core Voltage = 1.2V) ..................................................................... 9
4 Example PLL2 Frequencies (Core Voltage = 1.05V) ................................................................... 9
5 Peripheral I/O Domain Clock ............................................................................................. 10
6 System PLLC1 Output Clocks ............................................................................................ 13
7 DDR PLLC2 Output Clocks ............................................................................................... 17
8 PLL and Reset Controller List ............................................................................................ 21
9 PLL and Reset Controller Registers ..................................................................................... 21
10 Peripheral ID Register (PID) Field Descriptions ........................................................................ 22
11 Reset Type Status Register (RSTYPE) Field Descriptions ........................................................... 22
12 PLL Control Register (PLLCTL) Field Descriptions .................................................................... 23
13 PLL Multiplier Control Register (PLLM) Field Descriptions ........................................................... 24
14 PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions .................................................... 24
15 PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions .................................................... 25
16 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions .................................................... 25
17 Oscillator Divider 1 Register (OSCDIV1) Field Descriptions ......................................................... 26
18 Bypass Divider Register (BPDIV) Field Descriptions .................................................................. 27
19 PLL Controller Command Register (PLLCMD) Field Descriptions................................................... 28
20 PLL Controller Status Register (PLLSTAT) Field Descriptions ....................................................... 28
21 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions ........................................ 29
22 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ........................................... 30
23 Clock Enable Control Register (CKEN) Field Descriptions ........................................................... 31
24 Clock Status Register (CKSTAT) Field Descriptions .................................................................. 32
25 SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................. 33
A-1 Document Revision History ............................................................................................... 34
4 List of Figures SPRUES0B – December 2007
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About This Manual
Describes the operation of the phase-locked loop controller (PLLC) in the TMS320C642x Digital Signal
Processor (DSP).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320C642x Digital Signal Processor (DSP). Copies of these
documents are available on the Internet at www.ti.com . Tip: Enter the literature number in the search box
provided at www.ti.com.
The current documentation that describes the C642x DSP, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRUEM3 — TMS320C642x DSP Peripherals Overview Reference Guide. Provides an overview and
briefly describes the peripherals available on the TMS320C642x Digital Signal Processor (DSP).
Preface
SPRUES0B – December 2007
Read This First
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in the
devices that is identical is not included.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
SPRUES0B – December 2007 Preface 5
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1 Device Clocking
1.1 Overview
User's Guide
SPRUES0B – December 2007
Phase-Locked Loop Controller (PLLC)
The C642x DSP requires one primary reference clock. The primary reference clock can be either crystal
input or driven by external oscillators. A 15 to 30 MHZ crystal at the MXI/CLKIN pin is recommended for
the system PLLs, which generate the clocks for the DSP, peripherals, and DMA.
For detailed specifications on clock frequency and voltage requirements, see the device-specific data
manual.
There are two clocking modes:
• PLL Bypass Mode - power saving (device defaults to this mode)
• PLL Mode - PLL multiplies input clock up to the desired operating frequency
The clock of the major chip components must be programmed to operate at fixed ratios of the primary
system/DSP clock frequency within each mode, as shown in Table 1 . The C642x DSP clocking
architecture is shown in Figure 1 .
1.2 Clock Domains
1.2.1 Core Domains
Table 1. System Clock Modes and Fixed Ratios for Core Clock Domains
Components Core Clock Domain Fixed Ratio vs. DSP frequency
DSP CLKDIV1 1:1
EDMA CLKDIV3 1:3
Peripherals (CLKDIV3 domain) CLKDIV3 1:3
Peripherals (CLKDIV6 domain) CLKDIV6 1:6
The core domains refer to the clock domains for all of the internal processing elements of the C642x DSP,
such as the DSP/EDMA/peripherals, etc. All internal communications between DSP and modules operate
at core domain clock frequencies. All of the core clock domains are synchronous to each other, come from
a single PLL (PLL1), have aligned clock edges, and have fixed divide by ratio requirements, as shown in
Table 1 and Figure 1 . It is user's responsibility to ensure the fixed divide ratios between these core clock
domains are achieved.
The DSP is in the CLKDIV1 domain and receives the PLL1 frequency directly (PLLDIV1 of PLL controller
1 (PLLC1) set to divide by 1), or receives the divided-down PLL1 frequency (PLLDIV1 of PLLC1 set to
divide by 2, 3, etc.). The DSP has internal clock dividers that it uses to create the DSP ÷ 3 clock frequency
to communicate with other components on-chip.
Modules in the CLKDIV3 domain (for example, EDMA, CLKDIV3 domain peripherals) must run at 1/3 the
DSP frequency.
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DSP Subsystem
SYSCLK1
SYSCLK3
SCR
EDMA
DDR2 PHY
DDR2 VTP
DDR2 Mem Ctlr
PLLDIV1 (/2)
BPDIV
PLL Controller 2
PLL Controller 1
PLLDIV2 (/3)
PLLDIV3 (/6)
PLLDIV1 (/1)
SYSCLK2
UARTs (x2)
I2C
Timers (x3)
PWMs (x3)
EMAC
EMIFA
VLYNQ
HPI
McASP0
McBSP0
GPIO
McBSP1
PCI
MXI/CLKIN
(15−30 MHz)
OSCDIV1 (/1)
OBSCLK
(CLKOUT0 Pin)
AUXCLK
Device Clocking
Modules in the CLKDIV6 domain (for example, CLKDIV6 domain peripherals) must run at 1/6 the DSP
frequency.
Modules in the CLKIN domain (for example, UART, Timer, I2C, PWM) run at the MXI/CLKIN frequency,
asynchronous to the DSP. There is no fixed ratio requirement between these peripherals frequencies and
the DSP frequency.
Refer to device-specific data manual for the core clock domain for each peripheral.
Figure 1. Overall Clocking Diagram
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Device Clocking
1.2.2 Core Frequency Flexibility
The core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain clocks are
flexible, to a degree, within the limitations specified in the device-specific data manual. All of the following
frequency ranges and multiplier/divider ratios in the data manual must be adhered to:
• Input clock frequency range (MXI/CLKIN)
• PLL1 multiplier (PLLM) range
• PLL1 output (PLLOUT) frequency range based on the core voltage (1.05V or 1.2V) of the device
• Maximum device speed
• PLLC1's SYSCLK3:SYSCLK2:SYSCLK1 frequency ratio must be fixed to 1:3:6. For example, if
SYSCLK1 is at 600 MHZ, SYSCLK2 must be at 200 MHZ, and SYSCLK3 must be at 100 MHZ.
As specified in the data manual, the PLLs can be driven by any input ranging from 15 to 30 MHZ.
Table 2 shows some example PLL1 multiplier and divider settings assuming MXI/CLKIN frequency of 25
MHZ. The Applicable to Device Core Voltage column indicates whether the setting is allowed for a given
device core voltage. For example, the last row in Table 2 (PLL1 multiplier 24 for a 25 MHZ clock input)
only applies to devices with a core voltage 1.2V to meet the PLL1 output (PLLOUT) frequency range
required in the data manual. In addition, you must ensure the SYSCLK1 frequency does not exceed the
speed grade of the device. For example, for a device rated at 400 MHZ speed grade, SYSCLK1 must not
exceed 400 MHZ.
PLL1 PLLOUT Freq Freq Freq
Multiplier Freq (MHZ) Divider
16 400.0 1 400.0 3 133.3 6 66.7 Y Y
17 425.0 1 425.0 3 141.7 6 70.8 Y Y
18 450.0 1 450.0 3 150.0 6 75.0 Y Y
19 475.0 1 475.0 3 158.3 6 79.2 Y Y
20 500.0 1 500.0 3 166.7 6 83.3 Y Y
21 525.0 1 525.0 3 175.0 6 87.5 Y 22 550.0 1 550.0 3 183.3 6 91.7 Y 23 575.0 1 575.0 3 191.7 6 95.8 Y 24 600.0 1 600.0 3 200.0 6 100.0 Y
24 600.0 2 300.0 6 100.0 12 50.0 Y -
Table 2. Example PLL1 Frequencies and Dividers (25 MHZ Clock Input)
CLKDIV1 Domain CLKDIV3 Domain CLKDIV6 Domain Applicable to Device
(SYSCLK1) (SYSCLK2) (SYSCLK3) Core Voltage
PLL1
(1)
(MHZ) Divider
(1)
(MHZ) Divider
(1)
(MHZ) 1.2V 1.05V
(1)
The RATIO bit in PLLDIV n is programmed as Divider - 1. For example, for a SYSCLK1 divider of 1, you should program
PLLDIV1.RATIO = 0, PLLDIV2.RATIO = 2, PLLDIV3.RATIO = 5.
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1.2.3 DDR2/EMIF Clock
The DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from the
PLL1 clocks provided to other components of the system. This dedicated clock allows the reduction of the
core clock rates to save power while maintaining the required minimum clock rate (125 MHZ) for DDR2.
PLL2 must be configured to output a 2 × clock to the DDR2 PHY interface.
All of the following frequency ranges and multiplier/divider ratios in the device-specific data manual must
be adhered to when configuring PLL2:
• Input clock frequency range (MXI/CLKIN)
• PLL2 multiplier (PLLM) range
• PLL2 output (PLLOUT) frequency range based on core voltage (1.05V or 1.2V) of the device
Table 3 and Table 4 show some PLL2/DDR2 clock rates assuming a MXI/CLKIN frequency of 25 MHZ.
PLL2 Multiplier (MHZ) Divider
Table 3. Example PLL2 Frequencies (Core Voltage = 1.2V)
PLL2 PLLOUT Freq SYSCLK1
20 500.0 2 250.0 125.0
21 525.0 2 262.5 131.3
22 550.0 2 275.0 137.5
23 575.0 2 287.5 143.8
24 600.0 2 300.0 150.0
25 625.0 2 312.5 156.3
26 650.0 2 325.0 162.5
30 750.0 3 250.0 125.0
31 775.0 3 258.3 129.2
32 800.0 3 266.7 133.3
(1)
PHY [2 × clock] (MHZ) DDR2 Clock (MHZ)
Device Clocking
(1)
The RATIO bit in PLLDIV n is programmed as Divider - 1. For example, for SYSCLK1 divider of 3, you should program
PLLDIV1.RATIO = 2.
Table 4. Example PLL2 Frequencies (Core Voltage = 1.05V)
PLL2 Multiplier (MHZ) Divider
20 500.0 2 250.0 125.0
21 525.0 2 262.5 131.3
22 550.0 2 275.0 137.5
23 575.0 2 287.5 143.8
24 600.0 2 300.0 150.0
25 625.0 2 312.5 156.3
26 650.0 2 325.0 162.5
(1)
The RATIO bit in PLLDIV n is programmed as Divider - 1. For example, for SYSCLK1 divider of 3, you should program
PLLDIV1.RATIO = 2.
PLL2 PLLOUT Freq SYSCLK1
(1)
PHY [2 × clock] (MHZ) DDR2 Clock (MHZ)
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Device Clocking
1.2.4 I/O Domains
The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the core frequency domain by definition.
Table 5 lists peripherals with external I/O interface, and their I/O domain clock/frequency. It also shows the
core clock domain as a reference to show the core clock used for internal communications. See section
Section 1.2.1 for more details on core clock domains. See device-specific data manual for the exact I/O
clock frequency supported on the device.
Table 5. Peripheral I/O Domain Clock
Peripheral Frequency Internal Clock Source External Clock Source Core Clock Domain
I/O Domain Clock
DDR2 125-166 MHZ PLLC2 SYSCLK1 — CLKDIV3
PCI 33 MHZ — PCICLK CLKDIV3
EMAC (MII) 25 MHZ — MTXCLK, MRXCLK CLKDIV6
EMAC (RMII) 50 MHZ — RMREFCLK CLKDIV6
VLYNQ up to 80 MHZ PLLC1 SYSCLK3 VLYNQ_CLOCK CLKDIV6
McBSP up to 40 MHZ PLLC1 SYSCLK3 CLKS, CLKX, CLKR CLKDIV6
McASP up to 40 MHZ PLLC1 SYSCLK3 AHCLKX, AHCLKR, CLKDIV6
GPIO NA (asynchronous — — CLKDIV6
interface)
EMIFA NA (asynchronous — — CLKDIV6
interface)
HPI NA (asynchronous — — CLKDIV6
interface)
I2C up to 400 kHz MXI/CLKIN SCL CLKIN
Timer output up to 1/2 CLKIN MXI/CLKIN TINP0L (Timer 0), CLKIN
frequency TINP1L (Timer 1)
input up to 1/4 CLKIN
frequency
Watchdog Timer NA MXI/CLKIN — CLKIN
PWM NA — — CLKIN
UART NA — — CLKIN
I/O (External) Domain Clock Source Options
ACLKX, ACLKR
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2 PLL Controller
2.1 PLL Module
PLL Controller
The C642x DSP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system. PLL1
provides clocks (though various dividers) to most of the components of the C642x DSP. PLL2 is dedicated
to the DDR2 port. The reference clock is the 15 to 30 MHZ crystal or 1.8V LVCMOS-compatible clock
input, as mentioned in the data manual.
The PLL controller provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power down
The various clock outputs given by the controller are as follows:
• Domain Clocks: SYSCLK[1: n]
• Auxiliary Clock from reference clock source: AUXCLK
• Bypass Domain clock: SYSCLKBP
• Observe Clock: OBSCLK
Various dividers that can be used on the C642x DSP are as follows:
• PLL Controller Dividers (for SYSCLK[1: n]): PLLDIV1, ..., PLLDIV n
• Bypass Divider (for SYSCLKBP): BPDIV
• Oscillator Divider (for OBSCLK): OSCDIV1
Various other controls supported are as follows:
• PLL Multiplier Control: PLLM
• Software-programmable PLL Bypass: PLLEN
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