Texas Instruments TMS320C6201 User Manual
TMS320C6201
Digital Signal Processor
Silicon Errata
SPRZ153
November 2000
Copyright 2000, Texas Instruments Incorporated
TMS320C6201 Silicon Errata
SPRZ153
Contents
1 Introduction 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Quality and Reliability Conditions 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMX Definition 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMP Definition 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS Definition 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Revision Identification 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications 8. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.1.1 Issues When Pausing at a Block Boundary 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.1.2 DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame 8. . . . . . . . . . . . . .
Advisory 3.1.3 DMA Multiframe Split-mode Transfers Source Address Indexing Not Functional 9. . . . . . . . . . . . . . .
Advisory 3.1.4 DMA: Stopped Transfer Reprogrammed Does Not Wait for Sync 9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.1.5 DMA Freezes if Postincrement/Decrement Across Port Boundary 9. . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.1.6 DMA Paused During Emulation Halt 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.1.7 DMA: RSYNC = 10000b (DSPINT) Does Not Wait for Sync 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.1.8 EMIF: Invalid SDRAM Access to Last 1K Byte of CE3 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.1.9 Cache During Emulation With Extremely Slow External Memory 11. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications 12. . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.0.8 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz 12. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 3.0.9 CPU: L2-unit Long Instructions Corrupted During Interrupt 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications 15. . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.1 EMIF: CE Space Crossing on Continuous Request Not Allowed 15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.2 EMIF: SDRAM Invalid Access 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.4 DMA: RSYNC Cleared Late for Frame-synchronized Transfer 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.5 McBSP: DXR to XSR Copy Not Generated 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.6 DMA Split-mode End-of-frame Indexing 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.7 DMA Channel 0 Multiframe Split-Mode Incompletion 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.8 Timer Clock Output Not Driven for External Clock 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.9 Power-Down Pin PD Not Set High for Power-Down 2 Mode 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.10 EMIF: RBTR8 Bit Not Functional 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.11 McBSP: Incorrect mLaw Companding Value 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.12 False Cache Hit – Extremely Rare 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.13 EMIF: HOLD Feature Improvement on Revision 3 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.14 EMIF: HOLD Request Causes Problems With SDRAM Refresh 21. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.15 DMA Priority Ignored by PBUS 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.16 DMA Split-mode Receive Transfer Incomplete After Pause 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.17 DMA Multiframe Transfer Data Lost During Stop 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.18 Bootload: HPI Feature Improvement on Revision 3 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
TMS320C6201 Silicon Errata
Advisory 2.1.19 PMEMC: Branch from External to Internal 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.1.21 DMA: DMA Data Block Corrupted After Start Zero Transfer Count 23. . . . . . . . . . . . . . . . . . . . . . . . . .
6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications 24. . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.1 Program Fetch: Cache Modes Not Functional 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.2 Bootload: Boot from 16-Bit and 32-Bit Asynchronous ROMs Not Functional 24. . . . . . . . . . . . . . . . . .
Advisory 2.0.3 DMA Channel 0 Split Mode Combined With autoinitialization Performs Improper
Reinitialization 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.4 DMA/Program Fetch: Cannot DMA into Program Memory From External 24. . . . . . . . . . . . . . . . . . . .
Advisory 2.0.5 Data Access: Parallel Accesses to EMIF or Internal Peripheral Bus Location
Sequenced Wrong 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.7 EMIF: Reserved Fields Have Incorrect Values 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.8 EMIF: SDRAM Refresh/DCAB Not Performed Prior to HOLD Request Being Granted 25. . . . . . . . .
Advisory 2.0.9 McBSP New Block Interrupt Does Not Occur for Start of Block 0 26. . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.11 DMA/Internal Data Memory: First Load Data Corrupted When DMA in High Priority 26. . . . . . . . . . .
Advisory 2.0.12 McBSP: FRST Improved in 2.1 over 2.0 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.13 McBSP: XEMPTY Stays Low When DXR Written Late 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.14 EMIF: Multiple SDRAM CE Spaces: Invalid Access After Refresh 27. . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.18 DMA/Internal Data Memory: Conflict Data Corruption 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.19 EMIF: Data Setup Times 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advisory 2.0.24 EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur 28. . . . . . . . . . . . . . . . . . . .
7 Documentation Support 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRZ153
3
TMS320C6201 Silicon Errata
1 Introduction
This document describes the silicon updates to the functional specifications for the TMS320C6201 silicon
releases 3.1, 3.0, 2.1, and 2.0.
1.1 Quality and Reliability Conditions
TMX Definition
Texas Instruments (TI) does not warranty either (1) electrical performance to specification, or (2) product reliability
for products classified as “TMX.” By definition, the product has not completed data sheet verification or reliability
performance qualification according to TI Quality Systems Specifications.
The mere fact that a “TMX” device was tested over a particular temperature and voltage ranges should not, in any
way, be construed as a warranty of performance.
TMP Definition
TI does not warranty product reliability for products classified as “TMP.” By definition, the product has not
completed reliability performance qualification according to TI Quality Systems Specifications; however, products
are tested to a published electrical and mechanical specification.
SPRZ153
TMS Definition
Fully-qualified production device.
4
TMS320C6201 Silicon Errata
1.2 Revision Identification
The device revision can be determined by the lot trace code marked on the top of the package. The
location for the lot trace codes for the GJL package is shown in Figure 1 and the revision numbers are
listed in Table 1.
Figure 1. Example, Lot Trace Code for TMS320C6201
SPRZ153
DSP
TMS320C6201GJL
Cxx–YMLLLLS
Lot trace code
NOTE: Qualified devices are marked with the letters “TMS” at the beginning of the device name, while nonqualified devices are marked with
the letters “TMX” at the beginning of the device name.
TMS320C6201GJL
C31–YMLLLLS
Lot trace code with revision 3.1
DSP
Table 1. Lot Trace Number Names
Lot Trace Code Silicon Revision Comments
20 2.0
21 2.1
30 3.0
31 3.1
5
TMS320C6201 Silicon Errata
NO.
UNIT
2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051)
Table 2. Timing Requirements for Interrupt Response Cycles
SPRZ153
NO.
4 t
5 t
6 t
NO.
1 T
4 T
d(CKO2L-IACKV)
d(CKO2L-INUMV)
d(CKO2L-INUMIV)
c(TCK)
h(TCKH-TDIV)
Figure 2. SBSRAM Read Timing (1/2 Rate SSCLK) (See Note)
SSCLK
CE
BE_ [3:0]
EA [21:2]
C6201B
MIN MAX
Delay time, CLKOUT2 low to IACK valid –4 6 ns
Delay time, CLKOUT2 low to INUMx valid 6 ns
Delay time, CLKOUT2 low to INUMx invalid –4 ns
UNIT
Table 3. JTAG Test-Port Timing
C6201,
C6201B
MIN MAX
Cycle time, TCK 50 ns
Hold time, TDI/TMS/TRST valid after TCK high 9 ns
43
BE1 BE2 BE3 BE4
65
A1 A2 A3 A4
UNIT
21
8
7
ED [31:0]
SSADS
SSOE
SSWE
Q1 Q2 Q3 Q4
109
1211
NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since
these timings are specified as minimums. However, the CE
in the data sheet in multiples of P ns. In other words, for output setup time, the CE
2P, …, or nP ns before the time specified by the data sheet. Similarly, for output hold time, the CE
output setup and hold time may be greater than that shown
x transition from high to low may happen P,
x low-to-high transition may
happen P, 2P, …, or nP ns after the time specified by the data sheet. This is indicated by the period of uncertainty for specs 1
and 2 in Figure 2, and Figure 3.
6
TMS320C6201 Silicon Errata
SPRZ153
Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note)
SSCLK
21
CE
BE_ [3:0]
EA [21:2]
ED [31:0]
SSADS
SSOE
SSWE
BE1
A1 A2 A3 A4
Q1
BE2
Q2
BE3
Q3 Q4
NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since
these timings are specified as minimums. However, the CE
in the data sheet in multiples of P ns. In other words, for output setup time, the CEx
output setup and hold time may be greater than that shown
transition from high to low may happen P,
2P, …, or nP ns before the time specified by the data sheet. Similarly, for output hold time, the CEx
happen P, 2P, …, or nP ns after the time specified by the data sheet. This is indicated by the period of uncertainty for specs 1
and 2 in Figure 2, and Figure 3.
43
BE4
65
1413
109
1615
low-to-high transition may
7
TMS320C6201 Silicon Errata
3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications
SPRZ153
Advisory 3.1.1
Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0
Details: The following problems exist when a DMA channel is paused at a block boundary:
Issues When Pausing at a Block Boundary
• DMA does not flush internal FIFO when a channel is paused across block boundary.
As a result, data from old and new blocks of that channel are in FIFO simultaneously.
This prevents other channels from using the FIFO for high performance until that
channel is restarted. Data is not lost when that channel is started again. (Internal
reference number C601299)
• For DMA transfers with autoinitialization, if a channel is paused just as the last transfer in a
block completes (just as the transfer counter reaches zero), none of the register reloads
take place (count, source address, and destination address). When the same channel is
restarted, the channel will not transfer anything due to the zero transfer count. This
problem only occurs at block boundaries. (Internal reference number C601258)
Workaround: Do not pause across block boundary if the internal FIFO is to be used by other channels for
high performance. For DMA transfers with autoinitialization, if a channel is paused with a zero
transfer count, manually reload all registers before restarting the channel.
Advisory 3.1.2
Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0
DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame
Details: If a frame-synchronized transfer is paused in mid-frame and then restarted again, a DMA
channel does not continue the transfer. Instead, the channel waits for synchronization. If the
channel is manually synchronized, it will properly complete the frame, but will immediately begin
the transfer of the next frame. This behavior occurs for both a software pause (setting START =
10b) and for an emulation halt (with EMOD = 1). (Internal reference number C601257)
Workaround: If pausing the DMA channel in software, do the following to restart:
1. Set the RSYNC bit in the Secondary Control Register.
2. Read the Transfer Count Register and then write back to Transfer Count Register. This
enables the present frame to transfer but will wait for the next sync event to trigger the
next frame transfer.
3. Set START to 01b or 11b.
If pausing the DMA channel with an emulation halt, do the following to restart:
1. Double-click on the Transfer Count Register and hit enter (rewrite current transfer count).
2. Set the RSYNC STAT bit in the Secondary Control Register (change 0xXXXX4XXX to
0xXXXX1XXX).
3. Run.
NOTE: The sequence of 1 and 2 is critical for an emulator halt (EMOD = 1), but not for the software
pause.
8
TMS320C6201 Silicon Errata
SPRZ153
Advisory 3.1.3
Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0
Details: If a DMA channel is configured to do a multiframe split-mode transfer with SRC_DIR = Index
Workaround: For multiframe transfers, use two DMA channels instead of using the split mode. Source Index
Advisory 3.1.4
Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0
Details: If any non-synchronized transfer (e.g., auto-init transfer) is stopped, and then the same
Workaround: Perform a nonsynchronized dummy transfer of one element to/from the same location before
DMA Multiframe Split-mode Transfers Source Address Indexing Not Functional
(11b), the source address is always modified using the Element Index, even during the last
element transfer of a frame. The transfer of the last element in a frame should index the
source address using the Frame Index instead of the Element Index. DST_DIR = 11b
functions properly. (Internal reference number C601256)
works properly for non-split-mode transfers.
DMA: Stopped Transfer Reprogrammed Does Not Wait for Sync
channel is programmed to do a write-synchronized transfer (e.g., split-mode transfer), the
write transfer does not wait for the sync event. (Internal reference number C601261)
starting the synchronized transfer.
Advisory 3.1.5
Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0
Details: For any DMA transfers with source/destination address postincrement/decrement, if the last
element to be transferred is aligned on a port boundary, then the DMA may freeze before
transferring this element. A port boundary is the address boundary between external memory
and program memory, between external memory and the peripheral address space, or
between program memory and the peripheral address space.
The following conditions cause DMA to freeze:
DMA Freezes if Postincrement/Decrement Across Port Boundary
• For non-sync and frame-sync transfers: if a channel is paused after the second-to-last
element is read, the DMA will freeze when the channel is then restarted with a request
to the address at a port boundary.
• For split-mode transfers or read/write-sync transfers: the DMA will freeze while
transferring the element aligned on the port boundary. A continuous burst transfer with
post-increment/decrement source/destination address does not exhibit this problem.
(Internal reference number C601300)
Workaround: Do not transfer to boundary addresses if the DMA source/destination address is
post-incremented/
decremented.
9
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