TEXAS INSTRUMENTS TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811 Technical data

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

Digital Signal Processors

Data Manual

Literature Number: SPRS174O
April 2001 − Revised July 2007

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!   

Revision History

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS174N device-specific data
sheet to make it an SPRS174O revision.

Global change:

PAGE

NO.

115 Added note to Figure 6−23
117 Modified note on Table 6−24
119 Added note to Table 6−25

121 Added note to Table 6−26

ADDITIONS/CHANGES/DELETIONS

22 Modified description of ADCRESEXT in Table 2−2
37 Added to note in Section 3.2.11 on security
37 Added Table 3−5
40 Modified Section 3.2.20 32−Bit CPU-Timers (0, 1, 2)
46 Modified Figure 3−6
57 Modified Section 4.1 32-Bit CPU-Timers 0/1/2
72 Added note under Figure 4−8 concerning RAM
78 Modified Max bit rate equation in Section 4.6
94 Changed IDD Max value for IDLE in Section 6.5
97 Added Section 6.8 Emulator Connection Without Signal Buffering for the DSP

123 Added note to Table 6−27
155 Added note on Table 6−57 and deleted notes on Table 6−58
156 Added Flash to title, added OTP column, changed notes and added equation for OTP wait state to Table 6−59

2

April 2001 − Revised July 2007SPRS174O

Contents

Contents

Section Page

1 Features 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Introduction 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Description 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Device Summary 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Pin Assignments 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Terminal Assignments for the GHH Package 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Pin Assignments for the PGF Package 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Pin Assignments for the PBK Package 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Signal Descriptions 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Functional Overview 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Memory Map 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Brief Descriptions 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 C28x CPU 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Memory Bus (Harvard Bus Architecture) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3 Peripheral Bus 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.4 Real-Time JTAG and Analysis 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 External Interface (XINTF) (2812 Only) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.6 Flash (F281x Only) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.7 ROM (C281x Only) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.8 M0, M1 SARAMs 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.9 L0, L1, H0 SARAMs 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.10 Boot ROM 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.11 Security 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.12 Peripheral Interrupt Expansion (PIE) Block 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI) 38. . . . . . . . . . . . . . . . . . . . . . .

3.2.14 Oscillator and PLL 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.15 Watchdog 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.16 Peripheral Clocking 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.17 Low-Power Modes 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.18 Peripheral Frames 0, 1, 2 (PFn) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.19 General-Purpose Input/Output (GPIO) Multiplexer 39. . . . . . . . . . . . . . . . . . . . . . . .

3.2.20 32-Bit CPU-Timers (0, 1, 2) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.21 Control Peripherals 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.22 Serial Port Peripherals 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Register Map 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Device Emulation Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 External Interface, XINTF (2812 Only) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 Timing Registers 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 XREVISION Register 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Interrupts 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 External Interrupts 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 System Control 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 OSC and PLL Block 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1 Loss of Input Clock 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9 PLL-Based Clock Module 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 External Reference Oscillator Clock Option 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11 Watchdog Block 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

April 2001 − Revised July 2007 SPRS174O

3

Contents

3.12 Low-Power Modes Block 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Peripherals 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 32-Bit CPU-Timers 0/1/2 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Event Manager Modules (EVA, EVB) 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 General-Purpose (GP) Timers 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 Full-Compare Units 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.3 Programmable Deadband Generator 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.4 PWM Waveform Generation 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.5 Double Update PWM Mode 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.6 PWM Characteristics 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.7 Capture Unit 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.9 External ADC Start-of-Conversion 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Enhanced Analog-to-Digital Converter (ADC) Module 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Enhanced Controller Area Network (eCAN) Module 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Multichannel Buffered Serial Port (McBSP) Module 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Serial Communications Interface (SCI) Module 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Serial Peripheral Interface (SPI) Module 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 GPIO MUX 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Development Support 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Device and Development Support Tool Nomenclature 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Documentation Support 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Electrical Specifications 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Absolute Maximum Ratings 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Recommended Operating Conditions† 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Electrical Characteristics Over Recommended Operating Conditions

(Unless Otherwise Noted) 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions

During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320F281x) 94. . . . . . . . . . . . . . . . . .

6.5 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions

During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320C281x) 94. . . . . . . . . . . . . . . . . .

6.6 Current Consumption Graphs 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 Reducing Current Consumption 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8 Emulator Connection Without Signal Buffering for the DSP 97. . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9 Power Sequencing Requirements 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10 Signal Transition Levels 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11 Timing Parameter Symbology 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.12 General Notes on Timing Parameters 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13 Test Load Circuit 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.14 Device Clock Table 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.15 Clock Requirements and Characteristics 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.15.1 Input Clock Requirements 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.15.2 Output Clock Characteristics 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16 Reset Timing 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.17 Low-Power Mode Wakeup Timing 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.18 Event Manager Interface 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.18.1 PWM Timing 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.18.2 Interrupt Timing 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.19 General-Purpose Input/Output (GPIO) − Output Timing 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.20 General-Purpose Input/Output (GPIO) − Input Timing 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.21 SPI Master Mode Timing 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

April 2001 − Revised July 2007SPRS174O

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6.22 SPI Slave Mode Timing 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.23 External Interface (XINTF) Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.24 XINTF Signal Alignment to XCLKOUT 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.25 External Interface Read Timing 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.26 External Interface Write Timing 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.27 External Interface Ready-on-Read Timing With One External Wait State 131. . . . . . . . . . . . . . . .

6.28 External Interface Ready-on-Write Timing With One External Wait State 134. . . . . . . . . . . . . . . .

6.29 XHOLD and XHOLDA 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.30 XHOLD/XHOLDA Timing 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.31 On-Chip Analog-to-Digital Converter 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.31.1 ADC Absolute Maximum Ratings† 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.31.2 ADC Electrical Characteristics Over Recommended Operating

Conditions 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.31.3 Current Consumption for Different ADC Configurations

(at 25-MHz ADCCLK) 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.31.4 ADC Power-Up Control Bit Timing 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.31.5 Detailed Description 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.31.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0) 144. . . . . . . . . . . . . . .

6.31.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) 146. . . . . . . . . . . . . .

6.31.8 Definitions of Specifications and Terminology 147. . . . . . . . . . . . . . . . . . . . . . . . . . .

6.32 Multichannel Buffered Serial Port (McBSP) Timing 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.32.1 McBSP Transmit and Receive Timing 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.32.2 McBSP as SPI Master or Slave Timing 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.33 Flash Timing (F281x Only) 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.33.1 Recommended Operating Conditions 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.34 ROM Timing (C281x only) 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.35 Migrating From F281x Devices to C281x Devices 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Mechanical Data 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

April 2001 − Revised July 2007 SPRS174O

5

Figures

List of Figures

Figure Page

Figure 2−1. TMS320F2812 and TMS320C2812 179-Ball GHH MicroStar BGA (Bottom View) 14. . . . . . . . . . . . .

Figure 2−2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View) 15. . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2−3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP

(Top View) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−1. Functional Block Diagram 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−2. F2812/C2812 Memory Map 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−3. F2811/C2811 Memory Map 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−4. F2810/C2810 Memory Map 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−5. External Interface Block Diagram 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−6. Interrupt Sources 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−7. Multiplexing of Interrupts Using the PIE Block 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−8. Clock and Reset Domains 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−9. OSC and PLL Block 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−10. Recommended Crystal/Clock Connection 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−11. Watchdog Module 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−1. CPU-Timers 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−2. CPU-Timer Interrupts Signals and Output Signal 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−3. Event Manager A Functional Block Diagram ( 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−4. Block Diagram of the F281x and C281x ADC Module 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−5. ADC Pin Connections With Internal Reference 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−6. ADC Pin Connections With External Reference 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−7. eCAN Block Diagram and Interface Circuit 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−8. eCAN Memory Map 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−9. McBSP Module With FIFO 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram 80. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) 83. . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−12. GPIO/Peripheral Pin Multiplexing 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 5−1. TMS320x28x Device Nomenclature 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−1. F2812/F2811/F2810 Typical Current Consumption Over Frequency 95. . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−2. F2812/F2811/F2810 Typical Power Consumption Over Frequency 95. . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−3. C2812/C2811/C2810 Typical Current Consumption Over Frequency

96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−4. C2812/C2811/C2810 Typical Power Consumption Over Frequency 96. . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−5. Emulator Connection Without Signal Buffering for the DSP 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−6. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence − Option 2 99. . . . . . . . . . . . . . .

Figure 6−7. Output Levels 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−8. Input Levels 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−9. 3.3-V Test Load Circuit 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−10. Clock Timing 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−11. Power-on Reset in Microcomputer Mode (XMP/MC = 0) 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−12. Power-on Reset in Microprocessor Mode (XMP/MC = 1) 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

April 2001 − Revised July 2007SPRS174O

Figure 6−13. Warm Reset in Microcomputer Mode 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−14. Effect of Writing Into PLLCR Register 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−15. IDLE Entry and Exit Timing 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−16. STANDBY Entry and Exit Timing 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−17. HALT Wakeup Using XNMI 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−18. PWM Output Timing 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−19. TDIRx Timing 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−20. EVASOC Timing 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−21. EVBSOC Timing 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−22. External Interrupt Timing 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−23. General-Purpose Output Timing 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−24. GPIO Input Qualifier − Example Diagram for QUALPRD = 1 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−25. General-Purpose Input Timing 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−26. SPI Master Mode External Timing (Clock Phase = 0) 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−27. SPI Master External Timing (Clock Phase = 1) 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−28. SPI Slave Mode External Timing (Clock Phase = 0) 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−29. SPI Slave Mode External Timing (Clock Phase = 1) 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−30. Relationship Between XTIMCLK and SYSCLKOUT 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−31. Example Read Access 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−32. Example Write Access 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−33. Example Read With Synchronous XREADY Access 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−34. Example Read With Asynchronous XREADY Access 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−35. Write With Synchronous XREADY Access 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−36. Write With Asynchronous XREADY Access 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−37. External Interface Hold Waveform 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−38. XHOLD

/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 139. . . . . . . . . . . . . . . . . . . . .

Figure 6−39. ADC Analog Input Impedance Model 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−40. ADC Power-Up Control Bit Timing 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−41. Sequential Sampling Mode (Single-Channel) Timing 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−42. Simultaneous Sampling Mode Timing 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−43. McBSP Receive Timing 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−44. McBSP Transmit Timing 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 151. . . . . . . . . . . . . . . . . . . . . .

Figure 6−46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 152. . . . . . . . . . . . . . . . . . . . . .

Figure 6−47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 153. . . . . . . . . . . . . . . . . . . . . .

Figure 6−48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 154. . . . . . . . . . . . . . . . . . . . . .

Figures

April 2001 − Revised July 2007 SPRS174O

7

Tables

List of Tables

Table Page

Table 2−1. Hardware Features† 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2−2. Signal Descriptions† 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−1. Addresses of Flash Sectors in F2812 and F2811 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−2. Addresses of Flash Sectors in F2810 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−3. Wait States 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−4. Boot Mode Selection 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−5. Impact of Using the Code Security Module 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−6. Peripheral Frame 0 Registers 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−7. Peripheral Frame 1 Registers 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−8. Peripheral Frame 2 Registers 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−9. Device Emulation Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−10. XINTF Configuration and Control Register Mappings 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−11. XREVISION Register Bit Definitions 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−12. PIE Peripheral Interrupts 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−13. PIE Configuration and Control Registers 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−14. External Interrupts Registers 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−15. PLL, Clocking, Watchdog, and Low-Power Mode Registers 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−16. PLLCR Register Bit Definitions 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−17. Possible PLL Configuration Modes 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−18. F281x and C281x Low-Power Modes 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−2. Module and Signal Names for EVA and EVB 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−3. EVA Registers 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−4. ADC Registers 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−5. 3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs 71. . . . . . . . . . . . . . . . . . .

Table 4−6. CAN Registers Map 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−7. McBSP Register Summary 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−8. SCI-A Registers 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−9. SCI-B Registers 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−10. SPI Registers 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−11. GPIO Mux Registers 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−12. GPIO Data Registers 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz) 97. . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−2. Recommended “Low-Dropout Regulators” 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−3. TMS320F281x and TMS320C281x Clock Table and Nomenclature 102. . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−4. Input Clock Frequency 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−5. XCLKIN Timing Requirements − PLL Bypassed or Enabled 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−6. XCLKIN Timing Requirements − PLL Disabled 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−7. Possible PLL Configuration Modes 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) 104. . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−9. Reset (XRS) Timing Requirements 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−10. IDLE Mode Timing Requirements 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−11. IDLE Mode Switching Characteristics 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−12. STANDBY Mode Timing Requirements 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−13. STANDBY Mode Switching Characteristics 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−14. HALT Mode Timing Requirements 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

April 2001 − Revised July 2007SPRS174O

Table 6−15. HALT Mode Switching Characteristics 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−16. PWM Switching Characteristics 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−17. Timer and Capture Unit Timing Requirements 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−18. External ADC Start-of-Conversion − EVA − Switching Characteristics 113. . . . . . . . . . . . . . . . . . . . . .

Table 6−19. External ADC Start-of-Conversion − EVB − Switching Characteristics 113. . . . . . . . . . . . . . . . . . . . . .

Table 6−20. Interrupt Switching Characteristics 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−21. Interrupt Timing Requirements 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−22. General-Purpose Output Switching Characteristics 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−23. General-Purpose Input Timing Requirements 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−24. SPI Master Mode External Timing (Clock Phase = 0) 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−25. SPI Master Mode External Timing (Clock Phase = 1) 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−26. SPI Slave Mode External Timing (Clock Phase = 0) 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−27. SPI Slave Mode External Timing (Clock Phase = 1) 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−28. Relationship Between Parameters Configured in XTIMING and Duration of Pulse 125. . . . . . . . . . . .

Table 6−29. XINTF Clock Configurations 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−30. External Memory Interface Read Switching Characteristics 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−31. External Memory Interface Read Timing Requirements 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−32. External Memory Interface Write Switching Characteristics 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−33. External Memory Interface Read Switching Characteristics

(Ready-on-Read, 1 Wait State) 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−34. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) 131. . . . . .

Table 6−35. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) 131. . . . . . . . . . . . . . .

Table 6−36. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) 131. . . . . . . . . . . . . .

Table 6−37. External Memory Interface Write Switching Characteristics

(Ready-on-Write, 1 Wait State) 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−38. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) 134. . . . . . . . . . . . . . .

Table 6−39. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) 134. . . . . . . . . . . . . .

Table 6−40. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) 138. . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−41. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 139. . . . . . . . . . . . . . . . . . . . . .

Table 6−42. DC Specifications 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−43. AC Specifications 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−44. ADC Power-Up Delays 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−45. Sequential Sampling Mode Timing 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−46. Simultaneous Sampling Mode Timing 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−47. McBSP Timing Requirements 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−48. McBSP Switching Characteristics 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 151. . . . . . . . .

Table 6−50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 151. . . . . .

Table 6−51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 152. . . . . . . . . .

Table 6−52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 152. . . . . .

Table 6−53. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 153. . . . . . . . .

Table 6−54. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 153. . . . . .

Table 6−55. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 154. . . . . . . . . .

Table 6−56. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 154. . . . . .

Table 6−57. Flash Parameters at 150-MHz SYSCLKOUT 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−58. Flash/OTP Access Timing 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−59. Minimum Required Flash Wait-States at Different Frequencies (F281x devices) 156. . . . . . . . . . . . .

Table 6−60. ROM Access Timing 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−61. Minimum Required ROM Wait-States at Different Frequencies (C281x devices) 157. . . . . . . . . . . . .

Table 7−1. Thermal Resistance Characteristics for 179-Ball GHH 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

April 2001 − Revised July 2007 SPRS174O

9

Tables

Table 7−2. Thermal Resistance Characteristics for 179-Ball ZHH 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7−3. Thermal Resistance Characteristics for 176-Pin PGF 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7−4. Thermal Resistance Characteristics for 128-Pin PBK 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

April 2001 − Revised July 2007SPRS174O

1 Features

D

High-Performance Static CMOS Technology

− 150 MHz (6.67-ns Cycle Time)

− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design

D JTAG Boundary Scan Support

†

D High-Performance 32-Bit CPU

(TMS320C28x)

− 16 x 16 and 32 x 32 MAC Operations

− 16 x 16 Dual MAC

− Harvard Bus Architecture

− Atomic Operations

− Fast Interrupt Response and Processing

− Unified Memory Programming Model

− 4M Linear Program/Data Address Reach

− Code-Efficient (in C/C++ and Assembly)

− TMS320F24x/LF240x Processor Source
Code Compatible

D On-Chip Memory

− Flash Devices: Up to 128K x 16 Flash
(Four 8K x 16 and Six 16K x 16 Sectors)

− ROM Devices: Up to 128K x 16 ROM

− 1K x 16 OTP ROM

− L0 and L1: 2 Blocks of 4K x 16 Each
Single-Access RAM (SARAM)

− H0: 1 Block of 8K x 16 SARAM

− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM

D Boot ROM (4K x 16)

− With Software Boot Modes

− Standard Math Tables

D External Interface (2812)

− Up to 1M Total Memory

− Programmable Wait States

− Programmable Read/Write Strobe Timing

− Three Individual Chip Selects

D Clock and System Control

− Dynamic PLL Ratio Changes Supported

− On-Chip Oscillator

− Watchdog Timer Module

D Three External Interrupts
D Peripheral Interrupt Expansion (PIE) Block

That Supports 45 Peripheral Interrupts

D Three 32-Bit CPU-Timers

Features

D 128-Bit Security Key/Lock

− Protects Flash/ROM/OTP and L0/L1
SARAM

− Prevents Firmware Reverse Engineering

D Motor Control Peripherals

− Two Event Managers (EVA, EVB)

− Compatible to 240xA Devices

D Serial Port Peripherals

− Serial Peripheral Interface (SPI)

− Two Serial Communications Interfaces
(SCIs), Standard UART

− Enhanced Controller Area Network
(eCAN)

− Multichannel Buffered Serial Port
(McBSP)

D 12-Bit ADC, 16 Channels

− 2 x 8 Channel Input Multiplexer

− Two Sample-and-Hold

− Single/Simultaneous Conversions

− Fast Conversion Rate: 80 ns/12.5 MSPS

D Up to 56 General Purpose I/O (GPIO) Pins
D Advanced Emulation Features

− Analysis and Breakpoint Functions

− Real-Time Debug via Hardware

D Development Tools Include

− ANSI C/C++ Compiler/Assembler/Linker

− Code Composer Studio IDE

− DSP/BIOS

− JTAG Scan Controllers

†

D Low-Power Modes and Power Savings

− IDLE, STANDBY, HALT Modes Supported

− Disable Individual Peripheral Clocks

D Package Options

− 179-Ball MicroStar BGA With External
Memory Interface (GHH), (ZHH) (2812)

− 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Memory Interface
(PGF) (2812)

− 128-Pin LQFP Without External Memory
Interface (PBK) (2810, 2811)

D Temperature Options:

− A: −40°C to 85°C (GHH, ZHH, PGF, PBK)

− S: −40°C to 125°C (GHH, ZHH, PGF, PBK)

− Q: −40°C to 125°C (PGF, PBK)

TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
†

IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port

April 2001 − Revised July 2007 SPRS174O

11

Introduction

2 Introduction

This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.

2.1 Description

The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, and TMS320C2812
devices, members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions
for demanding control applications. The functional blocks and the memory maps are described in Section 3,
Functional Overview.

Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812 are abbreviated as F2810,
F2811, and F2812, respectively. F281x denotes all three Flash devices. TMS320C2810, TMS320C2811, and
TMS320C2812 are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM
devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811 devices; and
2812 denotes both F2812 and C2812 devices.

TMS320C28x is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

12

April 2001 − Revised July 2007SPRS174O

2.2 Device Summary

Table 2−1 provides a summary of each device’s features.

Introduction

Table 2−1. Hardware Features

FEATURE F2810 F2811 F2812 C2810 C2811 C2812

Instruction Cycle (at 150 MHz) 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns
Single-Access RAM (SARAM)

(16-bit word)

3.3-V On-Chip Flash (16-bit word) 64K 128K 128K — — —
On-Chip ROM (16-bit word) — — — 64K 128K 128K
Code Security for

On-Chip Flash/SARAM/OTP/ROM
Boot ROM Yes Yes Yes Yes Yes Yes
OTP ROM (1K X 16) Yes Yes Yes Yes
External Memory Interface — — Yes — — Yes
Event Managers A and B

(EVA and EVB)

S General-Purpose (GP) Timers 4 4 4 4 4 4
S Compare (CMP)/PWM 16 16 16 16 16 16
S Capture (CAP)/QEP Channels 6/2 6/2 6/2 6/2 6/2 6/2

Watchdog Timer Yes Yes Yes Yes Yes Yes
12-Bit ADC Yes Yes Yes Yes Yes Yes

S Channels 16 16 16 16 16 16
32-Bit CPU Timers 3 3 3 3 3 3
SPI Yes Yes Yes Yes Yes Yes
SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB
CAN Yes Yes Yes Yes Yes Yes
McBSP Yes Yes Yes Yes Yes Yes
Digital I/O Pins (Shared) 56 56 56 56 56 56
External Interrupts 3 3 3 3 3 3
Supply Voltage 1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O

Packaging 128-pin PBK 128-pin PBK

A: −40°C to
85°C

Temperature Options

Product Status

§

S: −40°C to
125°C

Q: −40°C to
125°C

18K 18K 18K 18K 18K 18K

Yes Yes Yes Yes Yes Yes

EVA, EVB EVA, EVB EVA, EVB EVA, EVB EVA, EVB EVA, EVB

179-ball GHH

and ZHH

176-pin PGF

Yes Yes Yes Yes Yes Yes

Yes Yes Yes Yes Yes Yes

Yes Yes PGF only Yes Yes PGF only

TMS TMS TMS TMS TMS TMS

†

‡

128-pin PBK 128-pin PBK

Yes

‡

‡

Yes

179-ball GHH

and ZHH

176-pin PGF

†

The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Silicon Errata
(literature number SPRZ193) has been posted on the Texas Instruments (TI) website. It will be updated as needed.

‡

On C281x devices, OTP is replaced by a 1K X 16 block of ROM.

§

See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.

April 2001 − Revised July 2007 SPRS174O

13

Introduction

2.3 Pin Assignments

Figure 2−1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) package.
Figure 2−2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3
shows the pin assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin.

2.3.1 Terminal Assignments for the GHH Package

See Table 2−2 for a description of each terminal’s function(s).

P

N

M

XZCS0AND1

SPISOMIA PWM9 XR/W

SPISIMOA XA[1] XRD

L

K

J

MCLKXA MFSRA XD[3]

H

G

F

E

MDXA MDRA XD[0]

XMP/MC

AVDD-

REFBG

PWM8

PWM10

PWM7 TEST2

V

DD

V

SPICLKA

SS

V

MCLKRA XD[1] MFSXA XD[2]

DD

RESEXT

ADCREFP

XD[6] PWM11 XD[7] C5TRIP

V

SS

XD[4]

ADC-

V

AVSS-

REFBG

V

PWM12

SPISTEA

V

DDIO

V

V

SSA1

DDA1

ADCREFM ADCINA5

SS

T4PWM

_T4CMP

_QEP3

T3PWM

_T3CMP

SS

ADCINB7 C3TRIP

CAP6

V

DD

_QEPI2

C4TRIP

CAP4

CAP5

_QEP4

XD[5] XD[13]

XA[0]

ADC-

BGREFIN

XD[8]

TEST1 XD[9] X2

V

V

C6TRIP

SS

XHOLD

DDIO

V

SS

V

DD3VFL

TDIRB XD[10]

TCLKINB

XNMI

_XINT13

T3CTRIP

V

DD

_PDPINTB

XD[11] XA[2] XWE

X1/

XCLKIN

V

DDIO

T4CTRIP/

EVBSOC

V

XA[3] PWM1

SS

V

DDIOVSS

XHOLDA

T2CTRIP

EVASOC

PWM5

T1PWM

_T1CMP

CAP1

_QEP1

XA[13] C2TRIP XA[8] C1TRIP

CAP2

_QEP2

/

V

XCLKOUT XA[7] TCLKINA TDIRA

V

DD

CANTXA CANRXA

PWM3 PWM4 XD[12]

V

DD

XA[4]

CAP3

_QEPI1

V

DDIO

DD

XZCS2

SCIRXDB

V

SS

T2PWM

_T2CMP

XA[5]

V

SS

SCITXDB

V

DDIO

PWM2

PWM6

V

SS

T1CTRIP

_PDPINTA

XA[6]

V

SS

14

XINT1

D

C

B

A

ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6 XRS

ADCINB3 ADCINB0 ADCINB1 ADCINA2

ADCINB2

V

DDAIO

V

ADCINA0 ADCINA4 V

SSAIO

ADCLO ADCINA3 ADCINA7 XREADY XA[17]

V

SSA2VSS1

DDA2VDD1

XA[18]

SCITXDA

SCIRXDA XA[16] XD[15] TESTSEL XA[11]

XINT2

_ADCSOC

V

DD

V

SS

_XBIO

EMU1

XA[15]

V

EMU0 TDO TMS XA[9]

SS

V

XA[12] XA[10] TDI

SS

XD[14] TRST

V

DD

XA[14]

XF

_XPLLDIS

XZCS6AND7

TCK

Figure 2−1. TMS320F2812 and TMS320C2812 179-Ball GHH MicroStar BGA (Bottom View)

April 2001 − Revised July 2007SPRS174O

V

DD

V

SS

1412 1310 1189563412 7

2.3.2 Pin Assignments for the PGF Package

The TMS320F2812 and TMS320C2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are
shown in Figure 2−2. See Table 2−2 for a description of each pin’s function(s).

Introduction

XZCS6AND7

TESTSEL

TRST

TCK

EMU0
XA[12]
XD[14]

XF_XPLLDIS

XA[13]

V

SS

V

DD
XA[14]
V

DDIO

EMU1
XD[15]
XA[15]

XINT1_XBIO

XNMI_XINT13

XINT2_ADCSOC

XA[16]

V

SS

V

DD

SCITXDA

XA[17]

SCIRXDA

XA[18]

XHOLD

XRS

XREADY

V

DD1

V

SS1

ADCBGREFIN

V

SSA2

V

DDA2
ADCINA7
ADCINA6
ADCINA5

ADCINA4

ADCINA3
ADCINA2

ADCINA1
ADCINA0

ADCLO

V

SSAIO

SS

VDDV

XA[11]

TDI

XA[10]

TDO

TMS

XA[9]

132 89

133

176

131

130

129

128

127

126

134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175

23456789101112131415161718192021222324252627282930313233343536373839404142

125

C2TRIP

C3TRIP

124

123

C1TRIP

XA[8]

121

122

SS

V

XCLKOUT

120

119

XA[7]

TCLKINA

118

117

T2CTRIP / EVASOC

TDIRA

116

115

DDIO

114

T1CTRIP_PDPINTA

VDDVSSV

XA[6]

111

113

112

110

SS

CAP3_QEPI1

XA[5]

CAP2_QEP2

CAP1_QEP1

V

109

108

107

106

105

DD

T2PWM_T2CMP

XA[4]

T1PWM_T1CMP

PWM6

VSSV

99989796959493

101

104

103

102

100

PWM5

XD[13]

XD[12]

PWM4

PWM3

PWM2

PWM1

SCIRXDB

929190

SCITXDB

CANRXA

87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46

43

88

XZCS2
CANTXA

V

SS

XA[3]
XWE
T4CTRIP/EVBSOC
XHOLDA
V

DDIO

XA[2]
T3CTRIP_PDPINTB
V

SS

X1/XCLKIN
X2

V

DD
XD[11]
XD[10]

TCLKINB
TDIRB
V

SS
V

DD3VFL
XD[9]
TEST1

TEST2
XD[8]
V

DDIO
C6TRIP

C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
V

SS
CAP4_QEP3
V

DD
T4PWM_T4CMP

XD[7]
T3PWM_T3CMP
V

SS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7

45

1

DDAIO

V

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFP

ADCREFM

SSA1

DDA1

V

V

AVSSREFBG

AVDDREFBG

SS

MCXMP/

V

XA[0]

MDRA

ADCRESEXT

XD[0]

MDXA

DD

V

XD[1]

MCLKRA

XD[2]

MFSXA

XD[3]VDDIO

MFSRA

MCLKXA

SS

V

XD[4]

SPICLKA

DD

V

XD[5]

SPISTEA

SS

V

XD[6]

SPISIMOA

XRD

XA[1]

SPISOMIA

44

XZCS0AND1

Figure 2−2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)

April 2001 − Revised July 2007 SPRS174O

15

Introduction

2.3.3 Pin Assignments for the PBK Package

The TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-pin PBK low-profile quad
flatpack (LQFP) pin assignments are shown in Figure 2−3. See Table 2−2 for a description of each pin’s
function(s).

TESTSEL

TRST

TCK

EMU0

XF_XPLLDIS

V

DD

V

SS

V

DDIO

EMU1

XINT1_XBIO

XNMI_XINT13

XINT2_ADCSOC

ADCBGREFIN

V

SS

V

DD

SCITXDA

SCIRXDA

XRS

V

DD1

V

SS1

V

SSA2

V

DDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0

ADCLO

V

SSAIO

97

128

SS

TDO

TDI

96 65

98

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

TMS

VDDV

93

9291908988

95

94

2345678

C1TRIP

C2TRIP

C3TRIP

SS

XCLKOUT

V

878685

9

101112

TCLKINA

TDIRA

T2CTRIP/ EVASOC

84

131415

DDIO

VDDV

83

82

CAP1_QEP1

CAP2_QEP2

CAP3_QEPI1

T1CTRIP_PDPINTA

81

79

78

80

16

18

19

17

DD

T2PWM_T2CMP

T1PWM_T1CMP

76

77

21

20

PWM6

757473

222324

VSSV

PWM5

72

25

PWM4

PWM3

71

70

27

26

PWM1

PWM2

69

68

28

29

SCIRXDB

SCITXDB

CANRXA

66

67

63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

31

30

64

CANTXA
V

DD

V

SS
T4CTRIP
T3CTRIP_PDPINTB

V

SS
X1/XCLKIN
X2
V

DD
TCLKINB
TDIRB

V

SS
V

DD3VFL
TEST1
TEST2
V

DDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3

V

DD
T4PWM_T4CMP

T3PWM_T3CMP
V

SS
PWM12

PWM11
PWM10
PWM9
PWM8
PWM7

33

/EVBSOC

1

DDAIO

V

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFP

ADCREFM

AVSSREFBG

AVDDREFBG

SSA1

DDA1

V

V

ADCRESEXT

V

SS

MDRA

MDXA

DD

V

MCLKRA

MFSXA

MFSRA

MCLKXA

DDIO

V

SS
V

SPICLKA

SPISTEA

DD
V

V

SS

32

SPISIMOA

SPISOMIA

Figure 2−3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP

(Top View)

16

April 2001 − Revised July 2007SPRS174O

Introduction

§

19-bit XINTF Address Bus

2.4 Signal Descriptions

Table 2−2 specifies the signals on the F281x and C281x devices. All digital inputs are TTL-compatible. All
outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.

†

Table 2−2. Signal Descriptions

PIN NO.

NAME

XA[18] D7 158 − O/Z −
XA[17] B7 156 − O/Z −
XA[16] A8 152 − O/Z −
XA[15] B9 148 − O/Z −
XA[14] A10 144 − O/Z −
XA[13] E10 141 − O/Z −
XA[12] C11 138 − O/Z −
XA[11] A14 132 − O/Z
XA[10] C12 130 − O/Z −
XA[9] D14 125 − O/Z −
XA[8] E12 121 − O/Z −
XA[7] F12 118 − O/Z −
XA[6] G14 111 − O/Z −
XA[5] H13 108 − O/Z −
XA[4] J12 103 − O/Z −
XA[3] M11 85 − O/Z −
XA[2] N10 80 − O/Z −
XA[1] M2 43 − O/Z −
XA[0] G5 18 − O/Z
XD[15] A9 147 − I/O/Z PU
XD[14] B11 139 − I/O/Z PU
XD[13] J10 97 − I/O/Z PU
XD[12] L14 96 − I/O/Z PU
XD[11] N9 74 − I/O/Z PU
XD[10] L9 73 − I/O/Z PU
XD[9] M8 68 − I/O/Z PU
XD[8] P7 65 − I/O/Z PU
XD[7] L5 54 − I/O/Z PU
XD[6] L3 39 − I/O/Z PU
XD[5] J5 36 − I/O/Z PU
XD[4] K3 33 − I/O/Z PU
XD[3] J3 30 − I/O/Z PU
XD[2] H5 27 − I/O/Z PU
XD[1] H3 24 − I/O/Z PU
XD[0] G3 21 − I/O/Z PU

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PINGHH176-PINPGF128-PINP

BK

XINTF SIGNALS (2812 ONLY)

I/O/Z‡PU/PD

DESCRIPTION

19-bit XINTF Address Bus

16-bit XINTF Data Bus

April 2001 − Revised July 2007 SPRS174O

17

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

XMP/MC F1 17 − I PD

XHOLD E7 159 − I PU

XHOLDA K10 82 − O/Z −

XZCS0AND1 P1 44 − O/Z −

XZCS2 P13 88 − O/Z −

XZCS6AND7 B13 133 − O/Z −

XWE N11 84 − O/Z −

XRD M3 42 − O/Z −

XR/W N4 51 − O/Z −

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

176-PINP

GF
XINTF SIGNALS (2812 ONLY) (CONTINUED)

128-PINP

BK

I/O/Z

I/O/Z

†

(Continued)

‡

‡

§

§

Microprocessor/Microcomputer Mode Select.
Switches between microprocessor and
microcomputer mode. When high, Zone 7 is enabled
on the external interface. When low, Zone 7 is
disabled from the external interface, and on-chip
boot ROM may be accessed instead. This signal is
latched into the XINTCNF2 register on a reset and
the user can modify this bit in software. The state of
the XMP/MC

External Hold Request. XHOLD, when active (low),
requests the XINTF to release the external bus and
place all buses and strobes into a high-impedance
state. The XINTF will release the bus when any
current access is complete and there are no pending
accesses on the XINTF.

External Hold Acknowledge. XHOLDA is driven
active (low) when the XINTF has granted a XHOLD
request. All XINTF buses and strobe signals will be
in a high-impedance state. XHOLDA
when the XHOLD
devices should only drive the external bus when
XHOLDA

XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1
is active (low) when an access to the XINTF Zone 0
or Zone 1 is performed.

XINTF Zone 2 Chip Select. XZCS2 is active (low)
when an access to the XINTF Zone 2 is performed.

XINTF Zone 6 and Zone 7 Chip Select.
XZCS6AND7
XINTF Zone 6 or Zone 7 is performed.

Write Enable. Active-low write strobe. The write
strobe waveform is specified, per zone basis, by the
Lead, Active, and Trail periods in the XTIMINGx
registers.

Read Enable. Active-low read strobe. The read
strobe waveform is specified, per zone basis, by the
Lead, Active, and Trail periods in the XTIMINGx
registers. NOTE: The XRD
mutually exclusive.

Read Not Write Strobe. Normally held high. When
low, XR/W
XR/W

pin is ignored after reset.

is released

signal is released. External

is active (low).

is active (low) when an access to the

and XWE signals are

indicates write cycle is active; when high,

indicates read cycle is active.

18

April 2001 − Revised July 2007SPRS174O

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

XREADY B6 161 − I PU

X1/XCLKIN K9 77 58 I

X2 M9 76 57 O Oscillator Output

XCLKOUT F11 119 87 O −

TESTSEL A13 134 97 I PD

179-PING

HH

176-PINP

GF
XINTF SIGNALS (2812 ONLY) (CONTINUED)

128-PINP

BK

JTAG AND MISCELLANEOUS SIGNALS

I/O/Z

I/O/Z

†

(Continued)

‡

‡

§

§

Ready Signal. Indicates peripheral is ready to
complete the access when asserted to 1. XREADY
can be configured to be a synchronous or an
asynchronous input. See the timing diagrams for
more details.

Oscillator Input − input to the internal oscillator. This
pin is also used to feed an external clock. The 28x
can be operated with an external clock source,
provided that the proper voltage levels be driven on
the X1/XCLKIN pin. It should be noted that the
X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V)
core digital power supply (VDD), rather than the

3.3-V I/O supply (V
used to clamp a buffered clock signal to ensure that
the logic-high level does not exceed VDD (1.8 V or

1.9 V) or a 1.8-V oscillator may be used.

Output clock derived from SYSCLKOUT to be used
for external wait-state generation and as a
general-purpose clock source. XCLKOUT is either
the same frequency, 1/2 the frequency, or 1/4 the
frequency of SYSCLKOUT. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be
turned off by setting bit 3 (CLKOFF) of the
XINTCNF2 register to 1. Unlike other GPIO pins, the
XCLKOUT pin is not placed in a high impedance
state during reset.

Test Pin. Reserved for TI. Must be connected to
ground.

Device Reset (in) and Watchdog Reset (out).

). A clamping diode may be

DDIO

Device reset. XRS
execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS
brought to a high level, execution begins at the

XRS D6 160 113 I/O PU

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

April 2001 − Revised July 2007 SPRS174O

location pointed to by the PC. This pin is driven low
by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS
watchdog reset duration of 512 XCLKIN cycles.

The output buffer of this pin is an open-drain with an
internal pullup (100 µA, typical). It is recommended
that this pin be driven by an open-drain device.

causes the device to terminate

pin will be driven low for the

is

19

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

TEST1 M7 67 51 I/O −

TEST2 N7 66 50 I/O −

TRST B12 135 98 I PD

TCK A12 136 99 I PU JTAG test clock with internal pullup

TMS D13 126 92 I PU

TDI C13 131 96 I PU

TDO D12 127 93 O/Z −

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

176-PINP

GF

JTAG AND MISCELLANEOUS SIGNALS (CONTINUED)

128-PINP

BK

I/O/Z

I/O/Z

JTAG

†

(Continued)

‡

‡

§

§

T est Pin. Reserved for TI. On F281x devices, TEST1
must be left unconnected. On C281x devices, this
pin is a “no connect (NC)” (i.e., this pin is not
connected to any circuitry internal to the device).

T est Pin. Reserved for TI. On F281x devices, TEST2
must be left unconnected. On C281x devices, this
pin is a “no connect (NC)” (i.e., this pin is not
connected to any circuitry internal to the device).

JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is not
connected or driven low, the device operates in its
functional mode, and the test reset signals are
ignored.

NOTE: Do not use pullup resistors on TRST
an internal pulldown device. TRST
test pin and must be maintained low at all times
during normal device operation. In a low-noise
environment, TRST
instances, an external pulldown resistor is highly
recommended. The value of this resistor should be
based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally
offers adequate protection. Since this is
application-specific, it is recommended that each
target board be validated for proper operation of the
debugger and the application.

JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK.

JTAG test data input (TDI) with internal pullup. TDI
is clocked into the selected register (instruction or
data) on a rising edge of TCK.

JTAG scan out, test data output (TDO). The contents
of the selected register (instruction or data) is shifted
out of TDO on the falling edge of TCK.

may be left floating. In other

is an active high

; it has

20

April 2001 − Revised July 2007SPRS174O

Introduction

.

The ADC pins should not be driven before V

,

V

DDA2

, and V

DDAIO

pins have been fully powered up.

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

EMU0 D11 137 100 I/O/Z PU

EMU1 C9 146 105 I/O/Z PU

ADCINA7 B5 167 119 I
ADCINA6 D5 168 120 I
ADCINA5 E5 169 121 I
ADCINA4 A4 170 122 I
ADCINA3 B4 171 123 I
ADCINA2 C4 172 124 I
ADCINA1 D4 173 125 I
ADCINA0 A3 174 126 I

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

176-PINP

GF

128-PINP

BK
JTAG (CONTINUED)

ADC ANALOG INPUT SIGNALS

I/O/Z

I/O/Z

†

(Continued)

‡

‡

§

§

Emulator pin 0. When TRST is driven high, this pin
is used as an interrupt to or from the emulator
system and is defined as input/output through the
JTAG scan. This pin is also used to put the device
into boundary-scan mode. With the EMU0 pin at a
logic-high state and the EMU1 pin at a logic-low
state, a rising edge on the TRST
the device into boundary-scan mode.

NOTE: An external pullup resistor is
recommended on this pin. The value of this
resistor should be based on the drive strength of
the debugger pods applicable to the design. A

2.2-kΩ to 4.7-kΩ resistor is generally adequate.
Since this is application-specific, it is
recommended that each target board be validated
for proper operation of the debugger and the
application.

Emulator pin 1. When TRST is driven high, this pin
is used as an interrupt to or from the emulator
system and is defined as input/output through the
JTAG scan. This pin is also used to put the device
into boundary-scan mode. With the EMU0 pin at a
logic-high state and the EMU1 pin at a logic-low
state, a rising edge on the TRST
the device into boundary-scan mode.

NOTE: An external pullup resistor is
recommended on this pin. The value of this
resistor should be based on the drive strength of
the debugger pods applicable to the design. A

2.2-kΩ to 4.7-kΩ resistor is generally adequate.
Since this is application-specific, it is
recommended that each target board be validated
for proper operation of the debugger and the
application.

8-Channel analog inputs for Sample-and-Hold A

pin would latch

pin would latch

DDA1

April 2001 − Revised July 2007 SPRS174O

21

Introduction

8-Channel Analog Inputs for Sample-and-Hold B.
The ADC pins should not be driven before the

The ADC pins should not be driven before the

y

V

DDA1

, V

DDA2

, and V

DDAIO

pins have been fully

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

ADCINB7 F5 9 9 I
ADCINB6 D1 8 8 I
ADCINB5 D2 7 7 I
ADCINB4 D3 6 6 I
ADCINB3 C1 5 5 I
ADCINB2 B1 4 4 I
ADCINB1 C3 3 3 I
ADCINB0 C2 2 2 I

ADCREFP E2 11 11 I/O

ADCREFM E4 10 10 I/O

ADCRESEXT F2 16 16 O

ADCBGREFIN E6 164 116 T est Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG E3 12 12 ADC Analog GND
AVDDREFBG E1 13 13 ADC Analog Power (3.3-V)

ADCLO B3 175 127
V

SSA1

V

SSA2

V

DDA1

V

DDA2

V

SS1

V

DD1

V

DDAIO

V

SSAIO

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

F3 15 15 ADC Analog GND

C5 165 117 ADC Analog GND

F4 14 14 ADC Analog 3.3-V Supply
A5 166 118 ADC Analog 3.3-V Supply

C6 163 115 ADC Digital GND

A6 162 114 ADC Digital 1.8-V (or 1.9-V) Supply
B2 1 1 3.3-V Analog I/O Power Pin
A2 176 128 Analog I/O Ground Pin

176-PINP

GF

ADC ANALOG INPUT SIGNALS (CONTINUED)

128-PINP

BK

I/O/Z

I/O/Z

†

(Continued)

‡

‡

§

§

V

, V

DDA1

powered up.

ADC Voltage Reference Output (2 V). Requires a
low ESR (50 mΩ − 1.5 Ω) ceramic bypass capacitor
of 10 µF to analog ground. (Can accept external
reference input (2 V) if the software bit is enabled for
this mode. 1−10 µF low ESR capacitor can be used
in the external reference mode.)

ADC Voltage Reference Output (1 V). Requires a
low ESR (50 mΩ − 1.5 Ω) ceramic bypass capacitor
of 10 µF to analog ground. (Can accept external
reference input (1 V) if the software bit is enabled for
this mode. 1−10 µF low ESR capacitor can be used
in the external reference mode.)

ADC External Current Bias Resistor
Use 24.9 kΩ ±5% for ADC clock range 1 − 18.75 MHz

20 kΩ ±5% for ADC clock range 18.75 MHz − 25 MHz

Common Low Side Analog Input. Connect to analog
ground.

DDA2

, and V

pins have been full

DDAIO

22

April 2001 − Revised July 2007SPRS174O

Introduction

Section 6.2, Recommended Operating Conditions,

for voltage requirements.

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DD3VFL

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

H1 23 20

L1 37 29
P5 56 42
P9 75 56

P12 − 63

K12 100 74
G12 112 82
C14 128 94
B10 143 102

C8 154 110

G4 19 17

K1 32 26

L2 38 30
P4 52 39
K6 58 −
P8 70 53

M10 78 59

L11 86 62

K13 99 73

J14 105 −
G13 113 −
E14 120 88
B14 129 95
D10 142 −
C10 − 103

B8 153 109

J4 31 25
L7 64 49

L10 81 −
N14 − −
G11 114 83

E9 145 104

N8 69 52

176-PINP

GF

128-PINP

BK

I/O/Z

I/O/Z

POWER SIGNALS

†

(Continued)

‡

‡

§

§

1.8-V or 1.9-V Core Digital Power Pins. See

Core and Digital I/O Ground Pins

3.3-V I/O Digital Power Pins

3.3-V Flash Core Power Pin. This pin should be
connected to 3.3 V at all times after power-up
sequence requirements have been met. This pin is
used as VDDIO in ROM parts and must be
connected to 3.3 V in ROM parts as well.

April 2001 − Revised July 2007 SPRS174O

23

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

GPIOA0 − PWM1 (O) M12 92 68 I/O PU GPIO or PWM Output Pin #1
GPIOA1 − PWM2 (O) M14 93 69 I/O PU GPIO or PWM Output Pin #2
GPIOA2 − PWM3 (O) L12 94 70 I/O PU GPIO or PWM Output Pin #3
GPIOA3 − PWM4 (O) L13 95 71 I/O PU GPIO or PWM Output Pin #4
GPIOA4 − PWM5 (O) K11 98 72 I/O PU GPIO or PWM Output Pin #5
GPIOA5 − PWM6 (O) K14 101 75 I/O PU GPIO or PWM Output Pin #6
GPIOA6 − T1PWM_T1CMP

(I)
GPIOA7 − T2PWM_T2CMP

(I)
GPIOA8 − CAP1_QEP1 (I) H10 106 78 I/O PU GPIO or Capture Input #1
GPIOA9 − CAP2_QEP2 (I) H11 107 79 I/O PU GPIO or Capture Input #2
GPIOA10 − CAP3_QEPI1

(I)
GPIOA11 − TDIRA (I) F14 116 85 I/O PU GPIO or Timer Direction
GPIOA12 − TCLKINA (I) F13 117 86 I/O PU GPIO or Timer Clock Input
GPIOA13 − C1TRIP (I) E13 122 89 I/O PU GPIO or Compare 1 Output Trip
GPIOA14 − C2TRIP (I) E11 123 90 I/O PU GPIO or Compare 2 Output Trip
GPIOA15 − C3TRIP (I) F10 124 91 I/O PU GPIO or Compare 3 Output Trip

GPIOB0 − PWM7 (O) N2 45 33 I/O PU GPIO or PWM Output Pin #7
GPIOB1 − PWM8 (O) P2 46 34 I/O PU GPIO or PWM Output Pin #8
GPIOB2 − PWM9 (O) N3 47 35 I/O PU GPIO or PWM Output Pin #9
GPIOB3 − PWM10 (O) P3 48 36 I/O PU GPIO or PWM Output Pin #10
GPIOB4 − PWM11 (O) L4 49 37 I/O PU GPIO or PWM Output Pin #11
GPIOB5 − PWM12 (O) M4 50 38 I/O PU GPIO or PWM Output Pin #12
GPIOB6 − T3PWM_T3CMP

(I)
GPIOB7 − T4PWM_T4CMP

(I)
GPIOB8 − CAP4_QEP3 (I) M5 57 43 I/O PU GPIO or Capture Input #4
GPIOB9 − CAP5_QEP4 (I) M6 59 44 I/O PU GPIO or Capture Input #5
GPIOB10 − CAP6_QEPI2

(I)
GPIOB11 − TDIRB (I) L8 71 54 I/O PU GPIO or Timer Direction
GPIOB12 − TCLKINB (I) K8 72 55 I/O PU GPIO or Timer Clock Input
GPIOB13 − C4TRIP (I) N6 61 46 I/O PU GPIO or Compare 4 Output Trip
GPIOB14 − C5TRIP (I) L6 62 47 I/O PU GPIO or Compare 5 Output Trip

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

J11 102 76 I/O PU GPIO or Timer 1 Output

J13 104 77 I/O PU GPIO or Timer 2 Output

H12 109 80 I/O PU GPIO or Capture Input #3

K5 53 40 I/O PU GPIO or Timer 3 Output

N5 55 41 I/O PU GPIO or Timer 4 Output

P6 60 45 I/O PU GPIO or Capture Input #6

176-PINP

GF

128-PINP

BK

GPIO OR PERIPHERAL SIGNALS

GPIOA OR EVA SIGNALS

GPIOB OR EVB SIGNALS

I/O/Z

I/O/Z

†

(Continued)

‡

‡

§

§

24

April 2001 − Revised July 2007SPRS174O

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

GPIOB15 − C6TRIP (I) K7 63 48 I/O PU GPIO or Compare 6 Output Trip
†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

176-PINP

GF

128-PINP

BK

I/O/Z

I/O/Z

†

(Continued)

‡

‡

§

§

April 2001 − Revised July 2007 SPRS174O

25

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

GPIOD0 − T1CTRIP_PDPI
NTA (I)

GPIOD1 −
T2CTRIP

GPIOD5 −
T3CTRIP_PDPINTB

GPIOD6 −
T4CTRIP

GPIOE0 − XINT1_XBIO (I) D9 149 106 I/O/Z − GPIO or XINT1 or XBIO input
GPIOE1 −

XINT2_ADCSOC (I)
GPIOE2 − XNMI_XINT13

(I)

GPIOF0 − SPISIMOA (O) M1 40 31 I/O/Z − GPIO or SPI slave in, master out
GPIOF1 − SPISOMIA (I) N1 41 32 I/O/Z − GPIO or SPI slave out, master in
GPIOF2 −SPICLKA (I/O) K2 34 27 I/O/Z − GPIO or SPI clock
GPIOF3 − SPISTEA (I/O) K4 35 28 I/O/Z − GPIO or SPI slave transmit enable

GPIOF4 − SCITXDA (O) C7 155 111 I/O PU GPIO or SCI asynchronous serial port TX data

GPIOF5 − SCIRXDA (I) A7 157 112 I/O PU GPIO or SCI asynchronous serial port RX data

GPIOF6 − CANTXA (O) N12 87 64 I/O PU GPIO or eCAN transmit data
GPIOF7 − CANRXA (I) N13 89 65 I/O PU GPIO or eCAN receive data

GPIOF8 − MCLKXA (I/O) J1 28 23 I/O PU GPIO or transmit clock
GPIOF9 − MCLKRA (I/O) H2 25 21 I/O PU GPIO or receive clock
GPIOF10 − MFSXA (I/O) H4 26 22 I/O PU GPIO or transmit frame synch
GPIOF11 − MFSRA (I/O) J2 29 24 I/O PU GPIO or receive frame synch
GPIOF12 − MDXA (O) G1 22 19 I/O − GPIO or transmitted serial data
GPIOF13 − MDRA (I) G2 20 18 I/O PU GPIO or received serial data

†
‡

§

/EVASOC (I)

(I)

/EVBSOC (I)

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

H14 110 81 I/O PU GPIO or Timer 1 Compare Output Trip

G10 115 84 I/O PU

P10 79 60 I/O PU GPIO or Timer 3 Compare Output Trip

P11 83 61 I/O PU

D8 151 108 I/O/Z − GPIO or XINT2 or ADC start of conversion

E8 150 107 I/O PU GPIO or XNMI or XINT13

176-PINP

GF

128-PINP

BK

GPIOD OR EVA SIGNALS

GPIOD OR EVB SIGNALS

GPIOE OR INTERRUPT SIGNALS

GPIOF OR SPI SIGNALS

GPIOF OR SCI-A SIGNALS

GPIOD OR EVA SIGNALS

GPIOF OR CAN SIGNALS

GPIOF OR McBSP SIGNALS

I/O/Z

I/O/Z

†

(Continued)

‡

‡

§

§

GPIO or Timer 2 Compare Output Trip or External
ADC Start-of-Conversion EV-A

GPIO or Timer 4 Compare Output Trip or External
ADC Start-of-Conversion EV-B

26

April 2001 − Revised July 2007SPRS174O

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

GPIOF14 − XF_XPLLDIS
(O)

GPIOG4 − SCITXDB (O) P14 90 66 I/O/Z − GPIO or SCI asynchronous serial port transmit data
GPIOG5 − SCIRXDB (I) M13 91 67 I/O/Z − GPIO or SCI asynchronous serial port receive data

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary scan mode.

179-PING

HH

A11 140 101 I/O PU

176-PINP

GF

128-PINP

BK

GPIOF OR XF CPU OUTPUT SIGNAL

GPIOG OR SCI-B SIGNALS

I/O/Z

I/O/Z

†

(Continued)

‡

‡

§

§

This pin has three functions:

1. XF − General-purpose output pin.

2. XPLLDIS − This pin is sampled during reset
to check whether the PLL must be disabled.
The PLL will be disabled if this pin is sensed
low. HALT and STANDBY modes cannot
be used when the PLL is disabled.

3. GPIO − GPIO function

NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However , i t i s acceptable for an I/O pin to ramp along with
the 3.3-V supply.

April 2001 − Revised July 2007 SPRS174O

27

Functional Overview

3 Functional Overview

Memory Bus

GPIO Pins

TINT0

TINT1

G
P

I

O

M

U
X

XINT13

XNMI

CPU-Timer 0
CPU-Timer 1

CPU-Timer 2

TINT2

PIE

(96 interrupts)

External Interrupt

Control

(XINT1/2/13, XNMI)

SCIA/SCIB

SPI FIFO

McBSP

eCAN

EVA/EVB

(A)

FIFO

FIFO

INT14

INT[12:1]

INT13
NMI

C28x CPU

Real-Time JTAG

External

Interface

(B)

(XINTF)

M0 SARAM

1K x 16

M1 SARAM

1K x 16

L0 SARAM

4K x 16

L1 SARAM

4K x 16

Flash
128K x 16 (F2812)
128K x 16 (F2811)

64K x 16 (F2810)

Control

Address(19)

Data(16)

XRS

X1/XCLKIN

X2

XF_XPLLDIS

NOTES: A. 45 of the possible 96 interrupts are used on the devices.

16 Channels

(Oscillator and PLL

Peripheral Clocking

Protected by the code-security module.

B. XINTF is available on the F2812 and C2812 devices only.

C. On C281x devices, the OTP is replaced with a 1K X 16 block of ROM

12-Bit ADC

System Control

+

+

Low-Power

Modes

+

WatchDog)

RS
CLKIN

Memory Bus

Peripheral Bus

Figure 3−1. Functional Block Diagram

ROM
128K x 16 (C2812)
128K x 16 (C2811)

64K x 16 (C2810)

(C)

OTP

1K x 16

H0 SARAM

8K × 16

Boot ROM

4K × 16

28

April 2001 − Revised July 2007SPRS174O

3.1 Memory Map

Block

Start Address

Functional Overview

On-Chip Memory External Memory XINTF

0x00 0000

0x00 0040
0x00 0400

0x00 0800

0x00 0D00

Low 64K

(24x/240x Equivalent Data Space)

0x00 0E00

0x00 2000

0x00 6000

0x00 7000

0x00 8000
0x00 9000

0x00 A000

Data Space Prog Space

M0 Vector − RAM (32 × 32)

(Enabled if VMAP = 0)

M0 SARAM (1K × 16)
M1 SARAM (1K × 16)

Peripheral Frame 0
PIE Vector - RAM

(256 × 16)

(Enabled if VMAP

= 1, ENPIE = 1)

Reserved

Reserved

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)

Reserved

Reserved

Reserved

Data Space Prog Space

Reserved

XINTF Zone 0 (8K × 16, XZCS0AND1

XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)

Reserved

XINTF Zone 2 (0.5M × 16, XZCS2

XINTF Zone 6 (0.5M × 16, XZCS6AND7)

)

)

0x00 2000
0x00 4000

0x08 0000
0x10 0000
0x18 0000

High 64K

Program Space)

(24x/240x Equivalent

LEGEND:

0x3D 7800

0x3D 7C00

0x3D 8000
0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

OTP (or ROM) (1K × 16, Secure Block)

Flash (or ROM) (128K × 16, Secure Block)

H0 SARAM (8K × 16)

(Enabled if MP/MC

BROM Vector - ROM (32 × 32)

(Enabled if VMAP = 1, MP/MC

Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.

NOTES: A. Memory blocks are not to scale.

B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program

cannot access these memory maps in program space.

E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.

F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.

Reserved (1K)

128-Bit Password

Reserved

Boot ROM (4K × 16)

= 0)

= 0, ENPIE = 0)

XINTF Zone 7 (16K × 16, XZCS6AND7

(Enabled if MP/MC

XINTF Vector - RAM (32 × 32)

(Enabled if VMAP = 1, MP/MC

Figure 3−2. F2812/C2812 Memory Map

Reserved

0x3F C000

)

= 1)

= 1, ENPIE = 0)

, not in both.

April 2001 − Revised July 2007 SPRS174O

29

Functional Overview

Block

Start Address

0x00 0000

0x00 0040
0x00 0400

0x00 0800

0x00 0D00

Low 64K

(24x/240x Equivalent Data Space)

0x00 0E00
0x00 2000

0x00 6000

0x00 7000

0x00 8000
0x00 9000

0x00 A000

On-Chip Memory

Data Space Prog Space

M0 Vector − RAM (32 × 32)

(Enabled if VMAP = 0)

M0 SARAM (1K × 16)
M1 SARAM (1K × 16)

Peripheral Frame 0

PIE Vector - RAM

(256 × 16)

(Enabled if VMAP

= 1, ENPIE = 1)

Reserved

Reserved

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)

Reserved

Reserved

High 64K

Program Space)

(24x/240x Equivalent

LEGEND:

Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.

NOTES: A. Memory blocks are not to scale.

B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program

cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.

0x3D 7800

0x3D 7C00

0x3D 8000
0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

Reserved

OTP (or ROM) (1K × 16, Secure Block)

Reserved (1K)

Flash (or ROM) (128K × 16, Secure Block)

128-Bit Password

H0 SARAM (8K × 16)

Reserved

Boot ROM (4K × 16)

(Enabled if MP/MC

BROM Vector - ROM (32 × 32)

(Enabled if VMAP = 1, MP/MC

= 0)

= 0, ENPIE = 0)

30

Figure 3−3. F2811/C2811 Memory Map

April 2001 − Revised July 2007SPRS174O