Texas Instruments TMS320C242FN Datasheet
TMS320C242
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
D High-Performance Static CMOS Technology
D Includes the T320C2xx Core CPU
– Object-Compatible With the TMS320C2xx
– Source-Code-Compatible With
TMS320C25
– Upwardly Compatible With TMS320C5x
– 50-ns Instruction Cycle Time
D Pin Compatible to Emulation Device
TMS320F241 (64-Pin/68-Pin)
D Code Compatible to Emulation Devices
TMS320F243 and TMS320F241
D Commercial and Industrial Temperature
Available
D Memory
– 544 Words x 16 Bits of On-Chip
Data/Program Dual-Access RAM
(DARAM)
– 4K Words x 16 Bits of On-chip
Program ROM
D Event-Manager Module
– Eight Compare/Pulse-Width Modulation
(PWM) Channels
– Two 16-Bit General-Purpose Timers With
Six Modes, Including Continuous Upand
Up/Down Counting
– Three 16-Bit Full Compare Units With
Deadband
– Three Capture Units (Two With
Quadrature Encoder-Pulse Interface
Capability)
D Single 10-Bit Analog-to-Digital Converter
(ADC) Module With 8 Multiplexed Input
Channels
D 26 Individually Programmable, Multiplexed
General-Purpose I/O (GPIO) Pins
D Phase-Locked-Loop (PLL)-Based Clock
D Watchdog (WD) Timer Module
D Serial Communications Interface (SCI)
D Five External Interrupts (Power Drive
Protection, Reset, NMI, and Two Maskable
Interrupts)
D Three Power-Down Modes for Low-Power
Operation
D Scan-Based Emulation
D Development Tools Available:
– Texas Instruments (TI) ANSI C
Compiler, Assembler/Linker, and
C-Source Debugger
– Full Range of Emulation Products
– Self-Emulation (XDS510)
– Third-Party Digital Motor Control and
Fuzzy-Logic Development Support
D 68-Pin PLCC FN Package
D 64-Pin QFP PG Package
description
The TMS320C242 device is a member of the ’24x family of digital signal processor (DSP) controllers based on
the TMS320C2xx generation of 16-bit fixed-point DSPs. The TMS320F241 device is fully compatible with the
’C242 to allow emulation during prototype development. (These two devices share similar core and
peripherals.) This new family is optimized for digital motor /motion control applications. The DSP controllers
combine the enhanced TMS320 architectural design of the ’C2xx core CPU for low-cost, high-performance
processing capabilities and several advanced peripherals optimized for motor/motion control applications.
These peripherals include the event manager module, which provides general-purpose timers and PWM
registers to generate PWM outputs, and a single,10-bit analog-to-digital converter (ADC), which can perform
conversion within 1 µs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI and XDS510 are trademarks of Texas Instruments Incorporated.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Copyright 1999, Texas Instruments Incorporated
1
TMS320C242
ADV ANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
Table of Contents
Description 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Features 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FN Package, 68-Pin PLCC, ’C242 4. . . . . . . . . . . . . . . . .
PG Package, 64-Pin QFP, ’242 5. . . . . . . . . . . . . . . . . . . .
Terminal Functions - ’C242 PG and FN Packages 6. . . .
Functional Block Diagram 9. . . . . . . . . . . . . . . . . . . . . . . .
Architectural Overview 10. . . . . . . . . . . . . . . . . . . . . . . . . .
System-Level Functions 10. . . . . . . . . . . . . . . . . . . . . . . . .
Device Memory Map 10. . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map 1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory Map 12. . . . . . . . . . . . . . . . . . . . . . . .
Digital I/O and Shared Pin Functions 13. . . . . . . . . . . . .
Digital I/O Control Registers 15. . . . . . . . . . . . . . . . . . . .
Device Reset and Interrupts 15. . . . . . . . . . . . . . . . . . . .
Clock Generation 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes 23. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram
’24x Legend for the Internal Hardware 27. . . . . . . . . . .
’C242 DSP Core CPU 28. . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Memory 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripherals 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event-Manager (EV2) Module 30. . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC) Module 34. . . . . . . .
A/D Overview 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications Interface (SCI) Module 36. . . .
Watchdog (WD) Timer Module 38. . . . . . . . . . . . . . . . . .
of the ’24x DSP CPU 26. . . .
Scan-Based Emulation 40. . . . . . . . . . . . . . . . . . . . . . . . . .
Development Support 40. . . . . . . . . . . . . . . . . . . . . . . . . . .
Nomenclature 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Documentation Support 43. . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 44. . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 44. . . . . . . . . . . . .
Electrical Characteristics 44. . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information 45. . . . . . . . . . . . . .
Signal Transition Levels 45. . . . . . . . . . . . . . . . . . . . . . . .
Timing Parameter Symbology 46. . . . . . . . . . . . . . . . . . .
General Notes on Timing Parameters 46. . . . . . . . . . . .
Clock Characteristics and Timings 47. . . . . . . . . . . . . . . .
Clock Options 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ext Reference Crystal/Clock w/PLL Circuit Enabled 48
Low-Power Mode Timings 49. . . . . . . . . . . . . . . . . . . . . .
RS
Timings 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XF, BIO
Timing Event Manager Interface 52. . . . . . . . . . . . . . . . . .
PWM Timings 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture and QEP Timings 53. . . . . . . . . . . . . . . . . . . . . .
Interrupt Timings 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output Timings 55. . . . . . . . . . .
10-Bit Dual Analog-to-Digital Converter (ADC) 56. . . . . .
ADC Operating Frequency 56. . . . . . . . . . . . . . . . . . . . .
ADC Input Pin Circuit 57. . . . . . . . . . . . . . . . . . . . . . . . . .
Internal ADC Module Timings 58. . . . . . . . . . . . . . . . . . .
Register File Compilation 59. . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
, and MP/MC Timings 51. . . . . . . . . . . . . . . . . . .
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C242
C
POWER
CYCLE
INTERFACE
()
()
DEVICES
CHANNELS
PIN COUNT
FN 68 PLCC
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
device features
Table 1 and Table 2 provide a comparison of the features of the ’C242 to the ’F241. See the functional block
diagram for the ’C242 peripherals and memory.
Table 1. Hardware Features of the TMS320x24x DSP Controllers
ON-CHIP MEMORY (WORDS)
TMS320x24x
DEVICES
TMS320C242
TMS320F241
DATA SPACE
(B1 RAM - 256 WORDS)
(B2 RAM - 32 WORDS)
288 256 – 5 50
RAM
CONFIGURABLE
DATA/PROG SPACE
(B0 RAM)
EXTERNAL
MEMORY
INTERFA
E
Table 2. Device Specifications of the TMS320x24x DSP Controllers
POWER CYCLE
SUPPLY
(V)
TIME
(ns)
ON-CHIP MEMORY (WORDS)
TMS320x24x
DEVICES
TMS320C242 4K –
TMS320F241 – 8K
ROM
PROG PROG
FLASH
EEPROM
ADC
CHANNELS
8
PERIPHERALS
CAN SPI
– –
√ √
GPIO
26
PACKAGE
TYPE
FN 68-PLCC
PG 64-PQFP
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
3
TMS320C242
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
pinouts
IOPC7
IOPC6
CLKOUT/IOPD0
CAP3/IOPA5
CAP2/QEP1/IOPA4
CAP1/QEP0/IOPA3
V
DD
V
SS
T2CMP/T2PWM/IOPB5
T1CMP/T1PWM/IOPB4
V
SSA
V
CCA
ADCIN07
V
REFHI
V
REFLO
ADCIN06
ADCIN05
PDPINT
35 36 37 38 3927
†
TCLKIN/IOPB7
TDIR/IOPB6
XINT1/IOPA2
SSO
XINT2/ADCSOC/IOPD1
NMI
40 41 42 43
DDO
V
WDDIS
V
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PMT
IOPC5
IOPC4
IOPC3
IOPC2
SCIRXD/IOPA1
SCITXD/IOPA0
/IOPC1
BIO
V
DD
V
SS
XF/IOPC0
EMU1
EMU0
XTAL2
XTAL1/CLKIN
V
DDO
V
SSO
FN PACKAGE
(TOP VIEW)
DDO
SSO
PWM1/IOPA6
V
V
87654321686766659 64636261
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28 29 30 31 32 33 34
PWM2/IOPA7
PWM3/IOPB0
PWM4/IOPB1
PWM5/IOPB2
PWM6/IOPB3
TMS320C242
(68-Pin PLCC)
4
NC
ADCIN04
†
NC = No connection, DNC = Do not connect
RS
TDI
SSO
DNC
V
ADCIN01
ADCIN02
ADCIN03
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ADCIN00
TCK
TDO
TMS
V
TRST
SS
DDO
V
SSO
V
pinouts (continued)
ADVANCE
INFORMATION
XINT2/ADCSOC/IOPD1
XINT1/IOPA2
TDIR/IOPB6
TCLKIN/IOPB7
PWM6/IOPB3
PWM5/IOPB2
PWM4/IOPB1
PWM3/IOPB0
PWM2/IOPA7
PWM1/IOPA6
WDDIS
NMI
PDPINT
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
PG PACKAGE
(TOP VIEW)
SSO
DDO
PMT
IOPC5
IOPC4
IOPC3
IOPC2
V
V
51 50 494847 46 45 44 43 42 41 4039 38 37 36 35 34 33
52
53
54
55
56
57
58
59
60
61
62
63
64
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19
SCIRXD/IOPA1
TMS320C242
(64-Pin QFP)
†
DD
SCITXD/IOPA0
BIO/IOPC1
XF/IOPC0
VSSV
EMU1
EMU0
XTAL2
SSO
DDO
XTAL1/CLKIN
V
V
32
31
30
29
28
27
26
25
24
23
22
21
20
TMS320C242
DSP CONTROLLER
TRST
TMS
TDO
TDI
TCK
RS
V
SSO
DNC
ADCIN00
ADCIN01
ADCIN02
ADCIN03
ADCIN04
SSO
DDO
V
V
IOPC7
†
NC = No connection, DNC = Do not connect
IOPC6
CAP3/IOPA5
CLKOUT/IOPD0
CAP2/QEP1/IOPA4
CAP1/QEP0/IOPA3
VDDV
SS
SSA
CCA
V
V
T2CMP/T2PWM/IOPB5
T1CMP/T1PWM/IOPB4
REFHI
REFLO
V
V
ADCIN07
ADCIN06
ADCIN05
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5
TMS320C242
NAME
TYPE
†
‡
DESCRIPTION
I
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
Terminal Functions - ’C242 PG and FN Packages
WDDIS 52 63 I I
ADCIN00 24 32
ADCIN01 23 31
ADCIN02 22 30
ADCIN03 21 29
ADCIN04 20 28
ADCIN05 19 26
ADCIN06 18 25
ADCIN07 15 22
V
CCA
V
SSA
V
REFHI
V
REFLO
T1CMP/T1PWM/
T2CMP/T2PWM/
TDIR/
TCLKIN/
CAP1/QEP0/
CAP2/QEP1/
CAP3/
PWM1/
PWM2/
PWM3/
PWM4/
PWM5/
PWM6/IOPB3 59 2 I/O/Z Compare/PWM output pin #6 or GPIO
PDPINT 58 1 I I
†
I = input, O = output, Z = high impedance
‡
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§
These pins are internally pulled high. However, these pins are not pulled high in the emulation devices (’F243/’F241).
NOTE:
64-PIN
NAME
IOPB4
IOPB5
IOPB6
IOPB7
IOPA3
IOPA4
IOPA5
IOPA6
IOPA7
IOPB0
IOPB1
IOPB2
Bold, italicized pin names
QFP
NO. NO.
14 21 – –
13 20 – – Analog ground reference for ADC
16 23 – – ADC analog high-voltage reference input
17 24 – – ADC analog low-voltage reference input
12 19 I/O/Z Timer 1 compare output/general-purpose bidirectional digital I/O (GPIO).
11 18 I/O/Z Timer 2 compare output/GPIO
56 67 I/O
57 68 I/O
8 15 I/O Capture input #1/quadrature encoder pulse input #0/GPIO
7 14 I/O
6 13 I/O
64 7 I/O/Z Compare/PWM output pin #1 or GPIO
63 6 I/O/Z Compare/PWM output pin #2 or GPIO
62 5 I/O/Z Compare/PWM output pin #3 or GPIO
61 4 I/O/Z Compare/PWM output pin #4 or GPIO
60 3 I/O/Z Compare/PWM output pin #5 or GPIO
68-PIN
PLCC
indicate pin function after reset.
TYPE
ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS
RESET
†
STATE
INTERFACE CONTROL SIGNALS
Watchdog disable. Note that on ROM devices, only the WDDIS function
is valid. If the input is low, the watchdog timer cannot be disabled in the
software. If the input is high, the watchdog timer can be disabled in the
software through the WDDIS bit in the WDCR register.
I I Analog inputs to the ADC
Analog supply voltage for ADC (5 V). V
digital supply voltage.
EVENT MANAGER
Counting direction for GP timer/GPIO. If TDIR=1, upward counting is
selected. If TDIR=0, downward counting is selected.
External clock input for GP timer/GPIO. Note that timer can also use
the internal device clock.
Capture input #2/quadrature encoder pulse input #1/GPIO
Capture input #3/GPIO
Power drive protection interrupt input. This interrupt, when activated, puts
the PWM output pins in the high-impedance state, should motor
drive/power converter abnormalities, such as overvoltage or overcurrent,
etc., arise. PDPINT
edge, this pin must be held low for two clock cycles for the core to
recognize the interrupt.
DESCRIPTION
must be isolated from
CCA
is a falling-edge-sensitive interrupt. After the falling
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
NAME
TYPE
†
‡
DESCRIPTION
ADVANCE
INFORMATION
Terminal Functions - ’C242 PG and FN Packages (Continued)
TMS320C242
DSP CONTROLLER
64-PIN
NAME
IOPC2
IOPC3
IOPC4
IOPC5
IOPC6
IOPC7
SCITXD/
SCIRXD/
RS 27 35 I/O I
NMI
XINT1/
XINT2/ADCSOC/
XF
BIO/
PMT 49 60 I I Do not connect. Reserved for test.
XTAL1/CLKIN 35 46 I I
XTAL2 36 47 O O
†
‡
§
NOTE:
IOPA0
IOPA1
§
IOPA2
IOPD1
§
/IOPC0
§
IOPC1
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
These pins are internally pulled high. However, these pins are not pulled high in the emulation devices (’F243/’F241).
Bold, italicized pin names
QFP
NO. NO.
68-PIN
PLCC
45 56 I/O GPIO
46 57 I/O GPIO
47 58 I/O
48 59 I/O
4 11 I/O GPIO
3 10 I/O GPIO
SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS
43 54 I/O
44 55 I/O
INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS
53 64 I I
55 66 I/O I
54 65 I/O I
39 50 I/O O – 1
42 53 I/O I
indicate pin function after reset.
TYPE
RESET
†
STATE
BIT I/O PINS
I
I
CLOCK SIGNALS
DESCRIPTION
GPIO
GPIO
SCI asynchronous serial port transmit data or GPIO
SCI asynchronous serial port receive data or GPIO
Device reset. RS causes the ’C242 to terminate execution and sets
PC=0. After RS
zero of program memory. RS
status bits. When the watchdog timer overflows, it initiates a system reset
pulse that is reflected on the RS
Nonmaskable interrupt. When NMI is activated, the device is interrupted
regardless of the state of the INTM bit of the status register. NMI
(falling) edge- and low-level-sensitive. T o be recognized by the core, this
pin must be kept low for at least one clock cycle after the falling edge.
External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edgesensitive. T o be recognized by the core, these pins must be kept low/high
for at least one clock cycle after the edge. The edge polarity is
programmable.
External user interrupt 2. External “start-of-conversion” input for
ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be
recognized by the core, these pins must be kept low/high for at least one
clock cycle after the edge. The edge polarity is programmable.
External flag output (latched software-programmable signal). XF is a
general-purpose output pin. It is set/reset by the SETC XF/CLRC XF
instruction. This pin is configured as an external flag output by all device
resets. It can be used as a GPIO, if not used as XF.
Branch control input. BIO is polled by the BCND pma,BIO instruction. If
is low, a branch is executed. If BIO is not used, it should be pulled
BIO
high. This pin is configured as a branch control input by all device resets.
It can be used as a GPIO, if not used as a branch control input.
PLL oscillator input pin. Crystal input to PLL/clock source input to
PLL. XTAL1/CLKIN is tied to one side of a reference crystal.
Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a
reference crystal. This pin goes in the high-impedance state when
EMU1/OFF
is brought to a high level, execution begins at location
is active low.
affects (sets to zero) various registers and
pin. This pulse is eight clock cycles wide.
is
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7
TMS320C242
NAME
TYPE
†
‡
DESCRIPTION
V
SS
Digital logic ground reference
V
SSO
Digital logic and buffer ground reference
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
Terminal Functions - ’C242 PG and FN Packages (Continued)
CLKOUT
TCK 28 36 I I JTAG test clock with internal pullup
TDI 29 37 I I
TDO 30 38 O O
TMS 31 39 I I
TRST 32 40 I I
EMU0 37 48 I/O I
EMU1 38 49 I/O I
V
DD
V
DDO
V
SS
V
SSO
NC – 27 No internal connection made to this pin
DNC 25 33 – – Do not connect. Reserved for test.
†
I = input, O = output, Z = high impedance
‡
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§
These pins are internally pulled high. However, these pins are not pulled high in the emulation devices (’F243/’F241).
NOTE:
64-PIN
NAME
/IOPD0 5 12 I/O O
Bold, italicized pin names
QFP
NO. NO.
68-PIN
PLCC
9 16 – –
41 52 – –
– 42 – –
1 8 – –
34 45 – –
51 62 – –
– 41 – –
10 17 – –
40 51 – –
– 43 – –
2 9 – –
26 34 – –
33 44 – –
50 61 – –
indicate pin function after reset.
†
TYPE
CLOCK SIGNALS (CONTINUED)
RESET
STATE
Clock output. This pin outputs the CPU clock (CLKOUT) only. This pin can
be used as a GPIO, if it is not used as a clock output pin.
TEST SIGNALS
JTAG test data input (TDI) with internal pullup. TDI is clocked into the
selected register (instruction or data) on a rising edge of TCK.
JTAG scan out, test data output (TDO). The contents of the selected
register (instruction or data) is shifted out of TDO on the falling edge of
TCK.
JTAG test-mode select (TMS) with internal pullup. This serial control
input is clocked into the TAP controller on the rising edge of TCK.
JTAG test reset with internal pulldown. TRST, when driven high, gives
the scan system control of the operations of the device. If this signal is
not connected or driven low, the device operates in its functional mode,
and the test reset signals are ignored.
Emulator I/O pin 0 with internal pullup. When TRST is driven high, this pin
is used as an interrupt to or from the emulator system and is defined as
input/output through the JTAG scan.
Emulator I/O pin 1 with internal pullup. When TRST is driven high, this pin
is used as an interrupt to or from the emulator system and is defined as
input/output through JTAG scan.
SUPPLY SIGNALS
Digital logic supply voltage (5 V)
Digital logic and buffer supply voltage (5 V)
Digital logic ground reference
Digital logic and buffer ground reference
NO CONNECT
DESCRIPTION
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram of the ’24x DSP controller
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
ADVANCE
INFORMATION
Data Bus
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
Interrupts
Initialization
Program Bus
Program
Controller
ROM
Instruction
Register
ARAU
Status/
Control
Registers
Auxiliary
Registers
Memory
Mapped
Registers
DARAM
B0
Input
Shifter
ALU
Accumulator
Output
Shifter
DARAM
B1/B2
Multiplier
TREG
PREG
Product
Shifter
’C2xx
CPU
Test/
Emulation
Event
Manager
General-
Purpose
Timers
Compare
Units
Capture/
Quadrature
Encoder
Pulse (QEP)
7
2
8
3
Interrupts
4
2
General-
Purpose
I/O Pins
Clock
16
Module
Single 10-Bit
Analog-
to-Digital
Converter
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Serial-
Communications
Interface
28
PDPINT
16
Peripheral Bus
Watchdog
Timer
9
TMS320C242
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
architectural overview
The functional block diagram provides a high-level description of each component in the ’C242 DSP controllers.
The TMS320x24x devices are composed of three main functional units: a ’C2xx DSP core, internal memory,
and peripherals. In addition to these three functional units, there are several system-level features of the ’C242
that are distributed. These system features include the memory map, device reset, interrupts, digital
input/output (I/O), clock generation, and low-power operation.
system-level functions
device memory map
The ’C242 device implements three separate address spaces for program memory, data memory, and
I/O space. On the ’C242, the first 96 (0–5Fh) data memory locations are either allocated for memory-mapped
registers or reserved. This memory-mapped register space contains various control and status registers,
including those for the CPU.
All the on-chip peripherals of the ’C242 devices are mapped into data memory space. Access to these registers
is made by the CPU instructions addressing their data memory locations. Figure 1 shows the ’C242 memory
map.
10
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INFORMATION
memory map
Hex
0000
003F
0040
0FBF
0FC0
0FFF
1000
FDFF
FE00
FEFF
FF00
FFFF
Program
Interrupt Vectors
User Code in ROM
Reserved
Reserved
Reserved
On-Chip DARAM
B0† (CNF = 1)
Reserved (CNF = 0)
†
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
Hex
0000
005F
0060
007F
0080
01FF
0200
02FF
0300
03FF
0400
6FFF
7000
73FF
7400
743F
7440
77FF
7800
7FFF
8000
FFFF
Data
Memory-Mapped
Registers/Reserved
Addresses
On-Chip
DARAM B2
Reserved
On-Chip DARAM
(B0)‡ (CNF = 0)
Reserved (CNF = 1)
On-Chip
DARAM (B1)
Illegal
Peripheral Memory-
Mapped Registers
(System,WD, ADC,
SCI, I/O,
Interrupts)
Peripheral
Memory-Mapped
Registers
(Event Manager)
Illegal
Illegal
Illegal
§
On-Chip ROM, (4K)
†
When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h will have the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved
when CNF = 1.
‡
When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h will have the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.
§
Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h–04FFh are referred to as illegal.
NOTE A: There is no external memory space for program, data, global data, or I/O in the ’C242. The GREG register is reserved in the ’C242.
Figure 1. TMS320C242 Memory Map
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11
TMS320C242
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
peripheral memory map
The system and peripheral control register frame contains all the data, status, and control bits to operate the
system and peripheral modules on the device (excluding the event manager). The register frame is mapped
in the data memory space.
Hex
Reserved
Interrupt-Mask Register
0000
0003
0004
Hex
0000
005F
0060
007F
0080
01FF
0200
02FF
0300
03FF
0400
07FF
0800
6FFF
7000
73FF
7400
743F
7440
77FF
7800
7FFF
8000
Memory-Mapped Registers
and Reserved
On-Chip DARAM B2
Reserved
On-Chip DARAM B0
On-Chip DARAM B1
Reserved
Illegal
Peripheral Frame 1 (PF1)
Peripheral Frame 2 (PF2)
Reserved
Illegal
Global-Memory Allocation
Register
Interrupt Flag Register
Emulation Registers
and Reserved
Illegal
System Configuration and
Control Registers
Watchdog Timer Registers
ADC Control Registers
Reserved
SCI
Illegal
External-Interrupt Registers
Illegal
Digital-I/O Control Registers
Illegal
Reserved
Illegal
0005
0006
0007
005F
7000–700F
7010–701F
7020–702F
7030–703F
7040–704F
7050–705F
7060–706F
7070–707F
7080–708F
7090–709F
70A0–70FF
7100–722F
7230–73FF
12
FFFF
Reserved/
Illegal
Capture & QEP Registers
Interrupt Mask, Vector and
Figure 2. Peripheral Memory Map for ’C242
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General-Purpose
Timer Registers
Compare, PWM, and
Deadband Registers
Flag Registers
Reserved
7400–7408
7411–7419
7420–7429
742C–7431
7432–743F
TMS320C242
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
digital I/O and shared pin functions
The ’C242 has a total of 26 general-purpose, bidirectional, digital I/O (GPIO) pins –most of which are shared
between primary functions and I/O. Twenty (20) I/O pins of the ’C242 are shared with other functions. The digital
I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O
and shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
D Output Control Registers — used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
D Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins
The control structure for shared I/O pins is shown in Figure 3, where each pin has three bits that define its
operation:
D Mux control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
D I/O direction bit — if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
D I/O data bit — if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
IOP Data Bit
(Read/Write)
In Out
IOP DIR Bit
0 = Input
1 = Output
Primary
Function
or I/O Pin
Primary
Function
01
Pin
Note:
When the MUX control bit = 1, the primary
function is selected in all cases except
for the following pins:
1. XF/IOPC0 (0 = Primary Function)
/IOPC1 (0 = Primary Function)
2. BIO
3. CLKOUT/IOPD0 (0 = Primary Function)
MUX Control Bit
0 = I/O Function
1 = Primary Function
Figure 3. Shared Pin Configuration
A summary of shared pin configurations and associated bits is shown in Table 3.
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TMS320C242
MUX CONTROL
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
description of shared I/O pins (continued)
68-PIN
PLCC
56
57
58
59
10
†
Valid only if the I/O function is selected on the pin
‡
If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
§
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
¶
Dedicated I/O pins
Table 3. Shared Pin Configurations
PIN NO.
64-PIN
QFP
54 43 OCRA.0 SCITXD IOPA0 PADATDIR 0 8
55 44 OCRA.1 SCIRXD IOPA1 PADATDIR 1 9
66 55 OCRA.2 XINT1 IOPA2 PADATDIR 2 10
15 8 OCRA.3 CAP1/QEP0 IOPA3 PADATDIR 3 11
14 7 OCRA.4 CAP2/QEP1 IOPA4 PADATDIR 4 12
13 6 OCRA.5 CAP3 IOPA5 PADATDIR 5 13
7 64 OCRA.6 PWM1 IOPA6 PADATDIR 6 14
6 63 OCRA.7 PWM2 IOPA7 PADATDIR 7 15
5 62 OCRA.8 PWM3 IOPB0 PBDATDIR 0 8
4 61 OCRA.9 PWM4 IOPB1 PBDATDIR 1 9
3 60 OCRA.10 PWM5 IOPB2 PBDATDIR 2 10
2 59 OCRA.11 PWM6 IOPB3 PBDATDIR 3 11
19 12 OCRA.12 T1PWM/T1CMP IOPB4 PBDATDIR 4 12
18 11 OCRA.13 T2PWM/T2CMP IOPB5 PBDATDIR 5 13
67 56 OCRA.14 TDIR IOPB6 PBDATDIR 6 14
68 57 OCRA.15 TCLKIN IOPB7 PBDATDIR 7 15
50 39 OCRB.0 IOPC0 XF PCDATDIR 0 8
53 42 OCRB.1 IOPC1 BIO PCDATDIR 1 9
¶
45
¶
46
¶
47
¶
48
¶
11
12 5 OCRB.8 IOPD0 CLKOUT PDDATDIR 0 8
65 54 OCRB.9 XINT2/ADCSOC IOPD1 PDDATDIR 1 9
4
¶
3
¶
¶
¶
¶
¶
¶
MUX CONTROL
REGISTER
(name.bit #)
OCRB.2 – IOPC2 PCDATDIR 2 10
OCRB.3 – IOPC3 PCDATDIR 3 11
OCRB.4 – IOPC4 PCDATDIR 4 12
OCRB.5 – IOPC5 PCDATDIR 5 13
OCRB.6 – IOPC6 PCDATDIR 6 14
OCRB.7 – IOPC7 PCDATDIR 7 15
PIN FUNCTION SELECTED I/O PORT DATA AND DIRECTION
(OCRx.n = 1) (OCRx.n = 0) REGISTER
PORT A
PORT B
PORT C
PORT D
DATA BIT
‡
NO.
†
DIR BIT
NO.
§
14
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TMS320C242
ADV ANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
digital I/O control registers
Table 4 lists the registers available in the digital I/O module. As with other ’C242 peripherals, the registers are
memory-mapped to the data space.
Table 4. Addresses of Digital I/O Control Registers
ADDRESS REGISTER NAME
7090h OCRA I/O mux control register A
7092h OCRB I/O mux control register B
7098h PADATDIR I/O port A data and direction register
709Ah PBDATDIR I/O port B data and direction register
709Ch PCDATDIR I/O port C data and direction register
709Eh PDDATDIR I/O port D data and direction register
device reset and interrupts
The TMS320x24x software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The ’C242 recognizes three types of
interrupt sources:
D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The ’C242 device has two sources of reset: an external reset pin and a watchdog timer timeout (reset).
D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
–
External interrupts
XINT2, PDPINT , and NMI. The first three can be masked both by dedicated enable bits and by the C PU’s
interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. NMI, which
is not maskable, takes priority over peripheral interrupts and software-generated interrupts. It can be
locked out only by an already executing NMI
Peripheral interrupts
–
SCI, WD, and ADC. They can be masked both by enable bits for each eve nt in each perip heral and by the
CPU’s IMR, which can mask each maskable interrupt line at the DSP core.
are generated by one of four external pins corresponding to the interrupts XINT1,
or a reset.
are initiated internally by these on-chip peripheral modules: the event manager,
D Software-generated interrupts for the ’C242 include:
The INTR instruction.
–
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
–
The NMI instruction.
used for the nonmaskable hardware interrupt NMI. NMI can be initiated by driving the NMI
executing an NMI instruction. This instruction globally disables maskable interrupts.
–
The TRAP instruction.
TRAP instruction does
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
This instruction allows initialization of any ’C242 interrupt with software. Its
This instruction forces a branch to interrupt vector location 24h, the same location
pin low or by
This instruction forces the CPU to branch to interrupt vector location 22h. The
not
disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
–
An emulator trap.
This interrupt can be generated with either an INTR instruction or a TRAP instruction.
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15
TMS320C242
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
reset
The reset operation ensures an orderly startup sequence for the device. There are two possible causes of a
reset, as shown in Figure 4.
Reset
Watchdog Timer Reset
External Reset (RS) Pin Active
Figure 4. Reset Signals
The two possible reset signals are generated as follows:
D Watchdog timer reset. A watchdog-timer-generated reset occurs if the watchdog timer overflows or an
improper value is written to either the watchdog key register or the watchdog control register. (Note that
when the device is powered on, the watchdog timer is automatically active.) The watchdog timer reset is
reflected on the external RS
pin also.
D Reset pin active. To generate an external reset pulse on the RS pin, a low-level pulse duration of at least
one CPUCLK cycle is necessary to ensure that the device recognizes the reset signal.
Signal
System Reset
hardware-generated interrupts
Once watchdog reset is activated, the external RS
cycles. This allows the TMS320x24x device to reset external system components.
The occurrence of a reset condition causes the TMS320x24x to terminate program execution and affects
various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are
affected by a reset are initialized to their reset state.
The ’24x CPU supports one nonmaskable interrupt (NMI) and six maskable prioritized interrupt requests. The
’24x devices have many peripherals, and each peripheral is capable of generating one or more interrupts in
response to many events. The ’24x CPU does not have sufficient interrupt requests to handle all these
peripheral interrupt requests; therefore, a centralized interrupt controller is provided to arbitrate the interrupt
requests from all the different sources. Throughout this section, refer to Figure 5 .
pin is driven (active) low for a minimum of eight CPUCLK
16
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hardware-generated interrupts (continued)
ADVANCE
INFORMATION
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
PDPINT
ADCINT
XINT1
XINT2
RXINT
TXINT
CMP1INT
CMP2INT
CMP3INT
TPINT1
TCINT1
TUFINT1
TOFINT1
TPINT2
TCINT2
TUFINT2
TOFINT2
CAPINT1
CAPINT2
CAPINT3
Level 1
IRQ GEN
Level 2
IRQ GEN
Level 3
IRQ GEN
Level 4
IRQ GEN
PIE
IMR
IFR
INT1
INT2
CPU
INT3
INT4
RXINT
TXINT
ADCINT
XINT1
XINT2
Peripheral Interrupt Requests
(PIRQs)
Level 5
IRQ GEN
Level 6
IRQ GEN
PIVR & logic
PIRQR#
PIACK#
Data
Bus
Addr
Bus
INT5
INT6
IACK
Figure 5. Peripheral Interrupt Expansion Block Diagram
interrupt hierarchy
The number of interrupt requests available is expanded by having two levels of hierarchy in the interrupt request
system. There are two levels of hierarchy in both the interrupt request/acknowledge hardware and in the
interrupt service routine software.
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TMS320C242
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
interrupt request structure
1. At the lower level of the hierarchy , the peripheral interrupt requests (PIRQs) from several peripherals to the
interrupt controller are ORed together to generate a request to the CPU. There is an interrupt flag bit and
an interrupt enable bit located in the peripheral for each event that can cause a peripheral interrupt request.
There is also one PIRQ for each event. If an interrupt-causing event occurs in a peripheral, and the
corresponding interrupt enable bit is set, the interrupt request from the peripheral to the interrupt controller
is asserted. This interrupt request simply reflects the status of the peripheral’s interrupt flag gated with the
interrupt enable bit. When the interrupt flag is cleared, the interrupt request is cleared. Some peripherals
have the capability to make either a high-priority or a low-priority interrupt request. If a peripheral has this
capability , the value of its interrupt priority bit is transmitted to the interrupt controller . The interrupt request
continues to be asserted until it is either automatically cleared by an interrupt acknowledge or cleared by
software.
2. At the upper level of the hierarchy, the ORed PIRQs generate interrupt (INT) requests to the CPU. The
request to the ’24x CPU is a low-going pulse of 2 CPU clock cycles. The Peripheral Interrupt Expansion
(PIE) controller generates an INT pulse when any of the PIRQs controlling that INT go active. If any of the
PIRQs capable of asserting that CPU interrupt request are still active in the cycle following an interrupt
acknowledge for that INT, another INT pulse is generated in the PIE. Each INT request is followed by an
interrupt acknowledge from the CPU, which helps to clear the interrupt-causing flag in the PIE. The interrupt
controller defines which CPU interrupt requests get asserted by which peripheral interrupt requests, and
the relative priority of each peripheral interrupt request. Thus, priority is determined by the interrupt
controller and is not part of any of the peripherals. Table 5 lists interrupt source priority and vectors.
18
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interrupt request structure (continued)
INT2
INT3
0008h
000Ah
ADVANCE
INFORMATION
Table 5. ’C242 Interrupt Source Priority and Vectors
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
CPU
INTERRUPT
NAME
Reset 1
Reserved 2
NMI 3
PDPINT 4 0.0 0020h Y EV
ADCINT 5 0.1 0004h Y ADC
XINT1 6 0.2 0001h Y
XINT2 7
Reserved 8
RXINT 9 0.5 0006h Y SCI
TXINT 10 0.6 0007h Y SCI
Reserved 11
Reserved 12
CMP1INT 13 0.9 0021h Y EV Compare 1 interrupt
CMP2INT 14 0.10 0022h Y EV Compare 2 interrupt
CMP3INT 15 0.11 0023h Y EV Compare 3 interrupt
TPINT1 16
TCINT1 17
TUFINT1 18 0.14 0029h Y EV
TOFINT1 19 0.15 002Ah Y EV Timer 1 overflow interrupt
TPINT2 20 1.0 002Bh Y EV Timer 2 period interrupt
TCINT2 21
TUFINT2 22
TOFINT2 23 1.3 002Eh Y EV Timer 2 overflow interrupt
CAPINT1 24
CAPINT2 25
CAPINT3 26
Reserved 27
RXINT 28
TXINT 29
OVERALL
PRIORITY
INTERRUPT
AND
VECTOR
ADDRESS
RSN
0000h
–
0026h
NMI
0024h
INT1
0002h
INT2
0004h
INT3
0006h
INT4
INT5
BIT
POSITION IN
PIRQRx AND
PIACKRx
0.3 0011h Y
0.12 0027h Y EV Timer 1 period interrupt
0.13 0028h Y EV Timer 1 PWM interrupt
1.1 002Ch Y EV Timer 2 PWM interrupt
1.2 002Dh Y EV
1.4 0033h Y EV Capture 1 interrupt
1.5 0034h Y EV Capture 2 interrupt
1.6 0035h Y EV Capture 3 interrupt
1.8 0006h Y SCI
1.9 0007h Y SCI
PERIPHERAL
INTERRUPT
VECTOR
(PIV)
N/A N
N/A N CPU Emulator Trap
N/A N
MASKABLE?
SOURCE
PERIPHERAL
MODULE
RS pin,
Watchdog
Nonmaskable
Interrupt
External
Interrupt Logic
External
Interrupt Logic
Reset from pin, watchdog
timeout
Nonmaskable interrupt
Power device protection
interrupt pin
ADC interrupt in
high-priority mode
External interrupt pins in
high priority
External interrupt pins in
high priority
SCI receiver interrupt in
high-priority mode
SCI transmitter interrupt
in high-priority mode
Timer 1 underflow
interrupt
Timer 2 underflow
interrupt
SCI receiver interrupt
(low-priority mode)
SCI transmitter interrupt
(low-priority mode)
DESCRIPTION
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19
TMS320C242
INT5
000Ch
ADVANCE
INFORMATION
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
interrupt request structure (continued)
Table 5.’C242 Interrupt Source Priority and Vectors (Continued)
†
interrupt acknowledge
CPU
INTERRUPT
NAME
Reserved 30
Reserved 31
ADCINT 32 1.12 0004h Y ADC
XINT1 33
XINT2 34
Reserved 000Eh N/A Y CPU Analysis interrupt
TRAP N/A 0022h N/A N/A CPU TRAP instruction
Phantom
Interrupt
Vector
INT8 through
INT16
INT20 through
INT31
Refer to the
and Peripherals User’s Guide Volume 2
OVERALL
PRIORITY
N/A N/A 0000h N/A CPU
N/A
N/A
TMS320C24x CPU System and Instruction Set, Volume 1
INTERRUPT
AND
VECTOR
ADDRESS
INT5
000Ah
INT6
000Ch
0010h through
0020h
00028h through
0603Fh
(SPRU276) for more information.
BIT
POSITION
IN
PIRQRx
AND
PIACKRx
1.13 0001h Y
1.14 0011h Y
PERIPHERAL
INTERRUPT
VECTOR
(PIV)
N/A N/A CPU
N/A N/A CPU
(SPRU160); and the
MASKABLE?
TMS320F243,F241,C242 DSP Controllers System
SOURCE
PERIPHERAL
MODULE
External
Interrupt Logic
External
Interrupt Logic
DESCRIPTION
ADC interrupt
(low-priority)
External interrupt pins
(low-priority mode)
External interrupt pins
(low-priority mode)
Phantom interrupt
vector
Software
p
Interrupt
†
Vectors
When the CPU asserts its interrupt acknowledge, it simultaneously puts a value on the memory interface
program address bus, which corresponds to the CPU interrupt being acknowledged (it does this because it is
fetching the CPU interrupt vector from program memory , each INT has a vector stored in a dedicated program
memory address). This value is shown in Table 5, column 3, CPU Interrupt and Vector Address. The PIE
controller uses the CPU interrupt acknowledge to generate its internal signals to clear the current interrupt
request.
interrupt vectors
20
When the CPU receives an interrupt request (INT), it does not know which peripheral PIRQ caused the INT
request. T o enable the CPU to distinguish among the PIRQs, a unique interrupt vector is generated in response
to a CPU interrupt acknowledge signal. This vector (PIV) is loaded into the Peripheral Interrupt Vector Register
(PIVR) in the PIE controller. The CPU reads this PIV vector value from PIVR and branches to the respective
Interrupt Service Routine (SISR). The PIVs are all implemented as hard-coded values on the ’C242, according
to Table 5, column 5.
In effect, there are two vector tables: a CPU vector table and a user-specified peripheral vector table. The CPU’s
vector table, which starts at 0000h, is used to get to the General Interrupt Service Routine (GISR) in response
to a CPU interrupt request (INT). A user-specified peripheral vector table is employed to get to the
Event-Specific Interrupt Service Routine (SISR), corresponding to the event which caused the peripheral
interrupt request (PIRQ). The code in the GISR should read the Peripheral Interrupt Vector Register (PIVR) after
saving any necessary context, and use this value PIV to generate a branch to the SISR. There is one SISR for
every interrupt request from a peripheral to the interrupt controller. The SISR performs the actions required in
response to the peripheral interrupt request.
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