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TMS320*2804 Series
Reference Manual
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Texas Instruments TMS320*2801 Series, TMS320*280 Series, TMS320*2804 Series Reference Manual

TMS320x280x, 2801x, 2804x Boot ROM
Reference Guide
Literature Number: SPRU722C
November 2004 – Revised October 2006
2 SPRU722C – November 2004 – Revised October 2006
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Contents
Preface ............................................................................................................................... 7
1.1 Boot ROM Memory Map.......................................................................................... 12
1.2 On-Chip Boot ROM IQ Math Tables ............................................................................ 13
1.3 CPU Vector Table ................................................................................................. 14
2.1 Bootloader Functional Operation ................................................................................ 18
2.2 Bootloader Device Configuration ................................................................................ 19
2.3 PLL Multiplier Selection .......................................................................................... 19
2.4 Watchdog Module ................................................................................................. 19
2.5 Taking an ITRAP Interrupt ....................................................................................... 20
2.6 Internal Pullup Resisters ......................................................................................... 20
2.7 PIE Configuration .................................................................................................. 20
2.8 Reserved Memory ................................................................................................. 20
2.9 Bootloader Modes ................................................................................................. 21
2.10 Bootloader Data Stream Structure .............................................................................. 24
2.11 Basic Transfer Procedure ........................................................................................ 28
2.12 InitBoot Assembly Routine ....................................................................................... 29
2.13 SelectBootMode Function ........................................................................................ 30
2.14 CopyData Function ................................................................................................ 33
2.15 SCI_Boot Function ................................................................................................ 33
2.16 Parallel_Boot Function (GPIO) .................................................................................. 35
2.17 SPI_Boot Function ................................................................................................ 40
2.18 I
2.19 eCAN Boot Function .............................................................................................. 45
2.20 ExitBoot Assembly Routine ...................................................................................... 47
2
C Boot Function .................................................................................................. 42
3.1 The C2000 Hex Utility ............................................................................................ 50
3.2 Example: Preparing a COFF File For eCAN Bootloading ................................................... 51
4.1 Boot ROM Version and Checksum Information ............................................................... 56
4.2 Bootloader Code Revision History .............................................................................. 56
4.3 Bootloader Code Listing (V3.0) .................................................................................. 57
4.4 Bootloader Code Listing (V4.0) .................................................................................. 87
A Revision History ....................................................................................................... 93
SPRU722C – November 2004 – Revised October 2006 Contents 3
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List of Figures
1-1 Memory Map of On-Chip ROM ........................................................................................... 12
1-2 Vector Table Map .......................................................................................................... 14
2-1 Bootloader Flow Diagram ................................................................................................. 18
2-2 Boot ROM Function Overview ............................................................................................ 22
2-3 Jump-to-Flash Flow Diagram ............................................................................................. 22
2-4 Flow Diagram of Jump to M0 SARAM ................................................................................... 23
2-5 Flow Diagram of Jump-to-OTP Memory ................................................................................ 23
2-6 Bootloader Basic Transfer Procedure .................................................................................. 29
2-7 Overview of InitBoot Assembly Function ................................................................................ 30
2-8 Overview of the SelectBootMode Function ............................................................................ 32
2-9 Overview of CopyData Function ......................................................................................... 33
2-10 Overview of SCI Bootloader Operation .................................................................................. 33
2-11 Overview of SCI_Boot Function .......................................................................................... 34
2-12 Overview of SCI_GetWordData Function .............................................................................. 35
2-13 Overview of Parallel GPIO bootloader Operation ...................................................................... 35
2-14 Parallel GPIO bootloader Handshake Protocol ........................................................................ 36
2-15 Parallel GPIO Mode Overview ............................................................................................ 36
2-16 Parallel GPIO Mode - Host Transfer Flow .............................................................................. 37
2-17 16-Bit Parallel GetWord Function ........................................................................................ 38
2-18 8-Bit Parallel GetWord Function .......................................................................................... 39
2-19 SPI Loader .................................................................................................................. 40
2-20 Data Transfer From EEPROM Flow ..................................................................................... 41
2-21 Overview of SPIA_GetWordData Function ............................................................................. 42
2-22 EEPROM Device at Address 0x50 ....................................................................................... 42
2-23 Overview of I2C_Boot Function ......................................................................................... 43
2-24 Random Read .............................................................................................................. 44
2-25 Sequential Read ............................................................................................................ 45
2-26 Overview of eCAN-A bootloader Operation ............................................................................. 45
2-27 ExitBoot Procedure Flow .................................................................................................. 47
4 List of Figures SPRU722C – November 2004 – Revised October 2006
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List of Tables
1-1 Vector Locations ............................................................................................................ 15
2-1 Configuration for Device Modes .......................................................................................... 19
2-2 Boot Mode Selection ....................................................................................................... 21
2-3 General Structure Of Source Program Data Stream In 16-Bit Mode ............................................... 25
2-4 LSB/MSB Loading Sequence in 8-Bit Data Stream ................................................................... 27
2-5 Boot Mode Selection ...................................................................................................... 30
2-6 SPI 8-Bit Data Stream .................................................................................................... 40
2-7 I
2-8 Bit-Rate Values for Different XCLKIN Values .......................................................................... 45
2-9 eCAN 8-Bit Data Stream .................................................................................................. 46
2-10 CPU Register Restored Values .......................................................................................... 48
3-1 Boot-Loader Options ....................................................................................................... 51
4-1 Bootloader Revision and Checksum Information ...................................................................... 56
4-2 Bootloader Revision Per Device.......................................................................................... 56
A-1 Changes for Revision C ................................................................................................... 93
2
C 8-Bit Data Stream ..................................................................................................... 44
SPRU722C – November 2004 – Revised October 2006 List of Tables 5
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List of Tables6 SPRU722C – November 2004 – Revised October 2006
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Preface

SPRU722C – November 2004 – Revised October 2006
Read This First
This reference guide is applicable for the code and data stored in the on-chip boot ROM on the TMS320x280x, TMS320x2801x and TMS320x2804x processors. This includes all flash-based, ROM-based, and RAM-based devices within these families.
The boot ROM is factory programmed with boot-loading software. Boot-mode signals (general purpose I/Os) are used to tell the bootloader software which mode to use on power up. The boot ROM also contains standard math tables, such as SIN/COS waveforms, for use in IQ math related algorithms found in the C28x™ IQMath Library - A Virtual Floating Point Engine (literature number SPRC087).
This guide describes the purpose and features of the bootloader. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h or with a leading 0x. For example, the following number is 40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the related devices and related support tools. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com .
Data Manuals — SPRS230: — TMS320F2809, F2808, F2806, F2802, F2801, F2801x UCD9501, C2802, C2801 DSPs
Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications
for the F280x devices.
SPRS357: — TMS320F28044 Digital Signal Processor Data Manual contains the pinout, signal
descriptions, as well as electrical and timing specifications for the F28044 device.
User's Guides — SPRU051: — TMS320x28xx, 28xxx Serial Communication Interface (SCI) Reference Guide describes the
SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.
SPRU059: — TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI -
a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate.
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Related Documentation From Texas Instruments
SPRU074: — TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) Reference Guide
describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments.
SPRU430: — TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central
processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs.
SPRU513: — TMS320C28x Assembly Language Tools User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device.
SPRU514: — TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device.
SPRU566: — TMS320x28xx, 28xxx Peripheral Reference Guide describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
SPRU608: — The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core.
SPRU625: — TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide
describes development using DSP/BIOS.
SPRU712: — TMS320x28xx, 28xxx System Control and Interrupts Reference Guide describes the
various interrupts and system control features of the 280x digital signal processors (DSPs).
SPRU716: — TMS320x280x, 2801x, 2804x Analog-to-Digital Converter (ADC) Reference Guide
describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
SPRU721: — TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Reference Guide describes the features
and operation of the inter-integrated circuit (I2C) module that is available on the TMS320x280x digital signal processor (DSP).
SPRU790: — TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide
describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems. It includes the module description and registers
SPRU791: — TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide
describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion
SPRU807: — TMS320x28xx, 28xxx Enhanced Capture (eCAP) Module Reference Guide describes the
enhanced capture module. It includes the module description and registers.
SPRU924: — TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) describes the
operation of the high-resolution extension to the pulse width modulator (HRPWM)
Application Reports — SPRAA58: — TMS320x281x to TMS320x280x Migration Overview describes differences between the
Texas Instruments TMS320x281x and TMS320x280x DSPs to assist in application migration from the 281x to the 280x. While the main focus of this document is migration from 281x to 280x, users considering migrating in the reverse direction (280x to 281x) will also find this document useful.
SPRA550: — 3.3 V DSP for Digital Motor Control describes a scenario of a 3.3-V-only motor controller
indicating that for most applications, no significant issue of interfacing between 3.3 V and 5 V exists. On-chip 3.3-V analog-to-digital converter (ADC) versus 5-V ADC is also discussed. Guidelines for component layout and printed circuit board (PCB) design that can reduce system noise and EMI effects are summarized.
8 Read This First SPRU722C – November 2004 – Revised October 2006
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Related Documentation From Texas Instruments
SPRA820: — Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for
online stack overflow detection on the TMS320C28x™ DSP. C-source code is provided that contains functions for implementing the overflow detection on both DSP/BIOS™ and non-DSP/BIOS applications.
SPRA861: — RAMDISK: A Sample User-Defined C I/O Driver provides an easy way to use the
sophisticated buffering of the high-level CIO functions on an arbitrary device. This application report presents a sample implementation of a user-defined device driver.
SPRA873: — Thermo-Electric Cooler Control Using a TMS320F2812 DSP & DRV592 Power Amplifier
presents a thermoelectric cooler system consisting of a Texas Instruments TMS320F2812 digital signal processor (DSP) and DRV592 power amplifier. The DSP implements a digital proportional-integral-derivative feedback controller using an integrated 12-bit analog-to-digital converter to read the thermistor, and direct output of pulse-width-modulated waveforms to the H-bridge DRV592 power amplifier. A complete description of the experimental system, along with software and software operating instructions, is provided.
SPRA876: — Programming Examples for the TMS320F281x eCAN contains several programming
examples to illustrate how the eCAN module is set up for different modes of operation to help you come up to speed quickly in programming the eCAN. All projects and CANalyzer configuration files are included in the attached SPRA876.zip file.
SPRA953: — IC Package Thermal Metrics describes the traditional and new thermal metrics and will put
their application in perspective with respect to system level junction temperature estimation.
SPRA958: — Running an Application from Internal Flash Memory on the TMS320F281x DSP (Rev. B)
covers the requirements needed to properly configure application software for execution from on-chip flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects are presented. Example code projects are included.
SPRA963: — Reliability Data for TMS320LF24x and TMS320F281x Devices describes reliability data for
TMS320LF24x and TMS320F281x devices.
SPRA989: — F2810, F2811, and F2812 ADC Calibration describes a method for improving the absolute
accuracy of the 12-bit analog-to-digital converter (ADC) found on the F2810/F2811/F2812 devices. This application note is accompanied by an example program (ADCcalibration.zip) that executes from RAM on the F2812 eZdsp.
SPRA991: — Simulation Fulfills its Promise for Enhancing Debug and Analysis - A White Paper describes
simulation enhancements that enable developers to speed up the development cycle by allowing them to evaluate system alternatives more effectively.
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Related Documentation From Texas Instruments
Read This First10 SPRU722C – November 2004 – Revised October 2006
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SPRU722C – November 2004 – Revised October 2006

Boot ROM Overview

The boot ROM is a block of read-only memory that is factory programmed.
Topic .................................................................................................. Page
1.1 Boot ROM Memory Map ............................................................. 12
1.2 On-Chip Boot ROM IQ Math Tables ............................................. 13
1.3 CPU Vector Table ...................................................................... 14
Chapter 1
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Sin/Cos
(644 x 16)
Data space Prog space
Normalized inverse
(528 x 16)
Normalized square root
(274 x 16)
Normalized Arctan
(452 x 16)
(360 x 16)
Rounding and saturation
Bootloader functions
ROM version
ROM checksum
Reset vector
CPU vector table
(64 x 16)
On-chip boot ROM
Section start
address
0x3F F000
0x3F F502
0x3F F712
0x3F F9E8
0x3F FB50
0x3F F834
0x3F FFC0
0x3F FFFF
Boot ROM Memory Map

1.1 Boot ROM Memory Map

The boot ROM is a 4K x 16 block of read-only memory located at addresses 0x3F F000 - 0x3F FFF. The on-chip boot ROM is factory programmed with boot-load routines and math tables for use with the
C28x™ IQMath Library - A Virtual Floating Point Engine (literature number SPRC087). Chapter 4 contains the code for each of the following items:
• Bootloader functions
• Version number, release date and checksum
• Reset vector
• CPU vector table (Used for test purposes only)
• IQmath Tables
Figure 1-1 shows the memory map of the on-chip boot ROM. The memory block is 4Kx16 in size and is
located at 0x3F F000 - 0x3F FFFF in both program and data space.
Figure 1-1. Memory Map of On-Chip ROM
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1.2 On-Chip Boot ROM IQ Math Tables

3K x 16 words of the boot ROM memory is reserved for IQ math tables. These math tables are provided to help improve performance and save RAM space.
The math tables included in the boot ROM are used by the Texas Instruments™ C28x™ IQMath Library - A Virtual Floating Point Engine (literature number SPRC087). The 28x IQmath Library is a collection of highly optimized and high precision mathematical functions for C/C++ programmers to seamlessly port a floating-point algorithm into fixed-point code on TMS320C28x devices.
These routines are typically used in computational-intensive real-time applications where optimal execution speed and high accuracy is critical. By using these routines you can achieve execution speeds that are considerably faster than equivalent code written in standard ANSI C language. In addition, by providing ready-to-use high precision functions, the TI IQmath Library can shorten significantly your DSP application development time. The C28x™ IQMath Library - A Virtual Floating Point Engine (literature number SPRC087) can be downloaded from the TI website.
The following math tables are included in the Boot ROM:
• Sine/Cosine Table
– Table size: 1282 words – Q format: Q30 – Contents: 32-bit samples for one and a quarter period sine wave This is useful for accurate sine wave generation and 32-bit FFTs. This can also be used for 16-bit
math, just skip over every second value.
• Normalized Inverse Table
– Table size: 528 words – Q format: Q29 – Contents: 32-bit normalized inverse samples plus saturation limits This table is used as an initial estimate in the Newton-Raphson inverse algorithm. By using a more
accurate estimate the convergence is quicker and hence cycle time is faster.
• Normalized Square Root Table
– Table size: 274 words – Q format: Q30 – Contents: 32-bit normalized inverse square root samples plus saturation This table is used as an initial estimate in the Newton-Raphson square-root algorithm. By using a more
accurate estimate the convergence is quicker and hence cycle time is faster.
• Normalized Arctan Table
– Table size: 452 words – Q format: Q30 – Contents 32-bit second order coefficients for line of best fit plus normalization table This table is used as an initial estimate in the Arctan iterative algorithm. By using a more accurate
estimate the convergence is quicker and hence cycle time is faster.
• Rounding and Saturation Table
– Table size: 360 words – Q format: Q30 – Contents: 32-bit rounding and saturation limits for various Q values
On-Chip Boot ROM IQ Math Tables
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Math tables
and functions
Bootloader
functions
Reset vector
CPU vector table
64 x 16
0x3F F000
0x3F FB50
0x3F FFFF
0x3F FFC0
Reset fetched from here when VMAP=1 Other vectors fetched from here when VMAP=1, ENPIE=0
CPU Vector Table

1.3 CPU Vector Table

A CPU vector table resides in boot ROM memory from address 0x3F FFC0 - 0x3F FFFF. This vector table is active after reset when VMAP = 1, ENPIE = 0 (PIE vector table disabled).
Figure 1-2. Vector Table Map
A The VMAP bit is located in Status Register 1 (ST1). VMAP is always 1 on reset. It can be changed after reset by
software, however the normal operating mode will be to leave VMAP = 1.
B The ENPIE bit is located in the PIECTRL register. The default state of this bit at reset is 0, which disables the
Peripheral Interrupt Expansion block (PIE).
The only vector that will normally be handled from the internal boot ROM memory is the reset vector located at 0x3F FFC0. The reset vector is factory programmed to point to the InitBoot function stored in the boot ROM. This function starts the boot load process. A series of checking operations is performed on General Purpose I/O (GPIO I/O) pins to determine which boot mode to use. This boot mode selection is described in Section 2.9 of this document.
The remaining vectors in the boot ROM are not used during normal operation. After the boot process is complete, you should initialize the Peripheral Interrupt Expansion (PIE) vector table and enable the PIE block. From that point on, all vectors, except reset, will be fetched from the PIE module and not the CPU vector table shown in Table 1-1 .
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CPU Vector Table
For TI silicon debug and test purposes the vectors located in the boot ROM memory point to locations in the M0 SARAM block as described in Table 1-1 . During silicon debug, you can program the specified locations in M0 with branch instructions to catch any vectors fetched from boot ROM. This is not required for normal device operation.
Table 1-1. Vector Locations
Vector Boot ROM (i.e., points to) Vector Boot ROM (i.e., points to)
RESET 0x3F FFC0 InitBoot (0x3F FB50) RTOSINT 0x3F FFE0 0x00 0060 INT1 0x3F FFC2 0x00 0042 Reserved 0x3F FFE2 0x00 0062 INT2 0x3F FFC4 0x00 0044 NMI 0x3F FFE4 0x00 0064 INT3 0x3F FFC6 0x00 0046 ILLEGAL INT4 0x3F FFC8 0x00 0048 USER1 0x3F FFE8 0x00 0068 INT5 0x3F FFCA 0x00 004A USER2 0x3F FFEA 0x00 006A INT6 0x3F FFCC 0x00 004C USER3 0x3F FFEC 0x00 006C INT7 0x3F FFCE 0x00 004E USER4 0x3F FFEE 0x00 006E INT8 0x3F FFD0 0x00 0050 USER5 0x3F FFF0 0x00 0070 INT9 0x3F FFD2 0x00 0052 USER6 0x3F FFF2 0x00 0072 INT10 0x3F FFD4 0x00 0054 USER7 0x3F FFF4 0x00 0074 INT11 0x3F FFD6 0x00 0056 USER8 0x3F FFF6 0x00 0076 INT12 0x3F FFD8 0x00 0058 USER9 0x3F FFF8 0x00 0078 INT13 0x3F FFDA 0x00 005A USER10 0x3F FFFA 0x00 007A INT14 0x3F FFDC 0x00 005C USER11 0x3F FFFC 0x00 007C DLOGINT 0x3F FFDE 0x00 005E USER12 0x3F FFFE 0x00 007E
Location in Contents Location in Contents
(1)
0x3F FFE6 0x00 0066 or ITRAPIsr
(1)
As of version 4 of the boot ROM code, this vector points to a ITRAP interrupt service routine, ITRAPIsr(), within the boot ROM. This ISR attempts to enable the watchdog and loops until the watchdog resets the part. On previous revisions, this vector points to location 0x66 in M0 SARAM. Refer to Section 4.1 to determine the version of the boot ROM code on a particular device.
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CPU Vector Table
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SPRU722C – November 2004 – Revised October 2006

Bootloader Features

This section describes in detail the boot mode selection process, as well as the specifics of the bootloader operation.
Topic .................................................................................................. Page
2.1 Bootloader Functional Operation ................................................ 18
2.2 Bootloader Device Configuration ................................................ 19
2.3 PLL Multiplier Selection ............................................................. 19
2.4 Watchdog Module ..................................................................... 19
2.5 Taking an ITRAP Interrupt .......................................................... 20
2.6 Internal Pullup Resisters ............................................................ 20
2.7 PIE Configuration ...................................................................... 20
2.8 Reserved Memory ..................................................................... 20
2.9 Bootloader Modes ..................................................................... 21
2.10 Bootloader Data Stream Structure ............................................... 24
2.11 Basic Transfer Procedure .......................................................... 28
2.12 InitBoot Assembly Routine ......................................................... 29
2.13 SelectBootMode Function .......................................................... 30
2.14 CopyData Function.................................................................... 33
2.15 SCI_Boot Function .................................................................... 33
2.16 Parallel_Boot Function (GPIO) .................................................... 35
2.17 SPI_Boot Function .................................................................... 40
2.18 I
2.19 eCAN Boot Function .................................................................. 45
2.20 ExitBoot Assembly Routine ........................................................ 47
2
C Boot Function ...................................................................... 42
Chapter 2
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Boot ROM
Reset vector fetched from boot ROM
address 0x3F FFC0
Jump to InitBoot function to start
boot process
Boot determined by the state of I/O pins
SelectBootMode function
Begin execution at Entry Point as
determined by selected boot mode
PIE disabled (ENPIE−0)
VMAP=1
OBJMODE=0
AMODE=0
MOM1MAP=1
Reset
(power-on reset or warm reset)
Silicon sets the following:
Bootloader Functional Operation

2.1 Bootloader Functional Operation

The bootloader is the program located in the on-chip boot ROM that is executed following a reset. The bootloader is used to transfer code from an external source into internal memory following power up.
This allows code to reside in slow non-volatile memory externally, and be transferred to high-speed memory to be executed.
The bootloader provides a variety of different ways to download code to accommodate different system requirements. The bootloader uses various GPIO signals to determine which boot mode to use. The boot mode selection process as well as the specifics of each bootloader are described in the remainder of this document. Figure 2-1 shows the basic bootloader flow.
Figure 2-1. Bootloader Flow Diagram
The reset vector in boot ROM redirects program execution to the InitBoot function. After performing device initialization the bootloader will check the state of GPIO pins to determine which boot mode you want to execute. Options include: jump to flash, jump to SARAM, jump to OTP, or call one of the on-chip boot loading routines.
After the selection process and if the required boot loading is complete, the processor will continue execution at an entry point determined by the boot mode selected. If a bootloader was called, then the input stream loaded by the peripheral determines this entry address. This data stream is described in
Section 2.10 . If, instead, you choose to boot directly to flash, OTP, or SARAM, the entry address is
predefined for each of these memory blocks. The following sections discuss in detail the different boot modes available and the process used for
loading data code into the device.
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2.2 Bootloader Device Configuration

At reset, any 28x™ CPU-based device is in 27x™ object-compatible mode. It is up to the application to place the device in the proper operating mode before execution proceeds.
On the 28x devices, when booting from the internal boot ROM, the device is configured for 28x operating mode by the boot ROM software. You are responsible for any additional configuration required.
For example, if your application includes C2xLP™ source, then you are responsible for configuring the device for C2xLP source compatibility prior to execution of code generated from C2xLP source.
The configuration required for each operating mode is summarized in Table 2-1 .
Bootloader Device Configuration
Table 2-1. Configuration for Device Modes
C27x Mode (Reset) 28x Mode Compatible Mode
OBJMODE 0 1 1 AMODE 0 0 1 PAGE0 0 0 0 M0M1MAP Other Settings SXM = 1, C = 1, SPM = 0
(1)
(1)
Normally for C27x compatibility, the M0M1MAP would be 0. On these devices, however, it is tied off high internally; therefore, at reset, M0M1MAP is always configured for 28x mode.
1 1 1
C2xLP Source

2.3 PLL Multiplier Selection

The boot ROM does not change the state of the PLL. Note that the PLL multiplier is not affected by a reset from the debugger. Therefore, a boot that is initialized from a reset from Code Composer Studio™ may be at a different speed than booting by pulling the external reset line ( XRS) low.

2.4 Watchdog Module

When branching directly to flash, M0 single-access RAM (SARAM), or one-time-programmable (OTP) memory, the watchdog is not touched. In the other boot modes, the watchdog is disabled before booting and then re-enabled and cleared before branching to the final destination address.
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Taking an ITRAP Interrupt

2.5 Taking an ITRAP Interrupt

If an illegal opcode is fetched, the 28x will take an ITRAP (illegal trap) interrupt. During the boot process, the interrupt vector used by the ITRAP is within the CPU vector table of the boot ROM. As of version 4 of the boot ROM code, the ITRAP vector points to an interrupt service routine (ISR) within the boot ROM named ITRAPIsr(). This interrupt service routine attempts to enable the watchdog and then loops forever until the processor is reset. This ISR will be used for any ITRAP until the user's application initializes and enables the peripheral interrupt expansion (PIE) block. Once the PIE is enabled, the ITRAP vector located within the PIE vector table will be used. Prior to boot ROM code version 4, the ITRAP interrupt vector in the CPU vector table pointed to a RAM location in M0 memory. Refer to Section 4.1 to determine the boot ROM code version of a particular device.

2.6 Internal Pullup Resisters

Each GPIO pin has an internal pullup resistor that can be enabled or disabled in software. The pins that are read by the boot mode selection code to determine the boot mode selection have pull-ups enabled after reset by default. In noisy conditions it is still recommended that you configure each of the three boot mode selection pins externally.
The individual bootloaders SCI, SPI, eCAN, and parallel boot all enable the pullup resistors for the pins that are used for control and data transfer. The bootloader leaves the resistors enabled for these pins when it exits. For example, the SCI-A bootloader enables the pullup resistors on the SCITXA and SCIRXA pins. It is your responsibility to disable them, if desired, after the bootloader exits.

2.7 PIE Configuration

The boot modes do not enable the PIE. It is left in its default state, which is disabled.

2.8 Reserved Memory

The first 80 words of the M1 memory block (address 0x400 - 0x44F) are reserved for the stack and .ebss code sections during the boot-load process. If code is bootloaded into this region there is no error checking to prevent it from corrupting the boot ROM stack.
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2.9 Bootloader Modes

To accommodate different system requirements, the boot ROM offers a variety of different boot modes. This section describes the different boot modes and gives brief summary of their functional operation. The states of three GPIO pins are used to determine the desired boot mode as shown in Table 2-2 .
Boot to Flash
SCI-A Boot Load a data stream from SCI-A. 1 1 0 SPI-A Boot Load from an external serial SPI EEPROM on SPI-A. 1 0 1 I2C Boot Load data from an external EEPROM at address 0x50 on the 1 0 0
eCAN-A Boot Boot to M0 SARAM Boot to OTP Parallel I/O Boot Load data from GPIO0 - GPIO15. 0 0 0
(1)
You must take extra care because of any effect toggling SPICLKA to select a boot mode may have on external logic.
(2)
When booting directly to flash, it is assumed that you have previously programmed a branch statement at 0x3F 7FF6 to redirect program flow as desired.
(3)
On devices that do not have an eCAN-A module this configuration is reserved. If it is selected, then the eCAN-A bootloader will run and will loop forever waiting for an incoming message.
(4)
When booting directly to OTP or M0 SARAM, it is assumed that you have previously programmed or loaded code starting at the entry point location.
Bootloader Modes
Table 2-2. Boot Mode Selection
Mode Description GPIO18 GPIO29 GPIO34
SPICLKA
SCITXDB
(2)
Jump to flash address 0x3F 7FF6. You must have programmed 1 1 1 a branch instruction here prior to reset to redirect code execution as desired.
I2C bus.
(3)
(4)
Call CAN_Boot to load from eCAN-A mailbox 1. 0 1 1
(4)
Jump to M0 SARAM address 0x00 0000. 0 1 0 Jump to OTP address 0x3D 7800. 0 0 1
(1)
SCITXDA
SPRU722C – November 2004 – Revised October 2006 Bootloader Features 21
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Reset
InitBoot
Call
SelectBootMode
Read the state
of I/O pins to
determine what
boot mode is
desired
Call
Boot Loader
?
No
Yes
EntryPoint determined
directly from state of
I/O pins
Call
boot loader,
SCI, SPI,
I2C, eCAN, or
parallel I/O
EntryPoint
and load
data/code
Read
Call
ExitBoot
Begin execution
at EntryPoint
Reset InitBoot
SelectBootMode
Select jump
to flash
ExitBoot
Jump to
0x3F 7FF6
User
programmed
branch to
desired
location
Bootloader Modes
Figure 2-2 shows an overview of the boot process. Each step is described in greater detail in following
sections.
Figure 2-2. Boot ROM Function Overview
The following boot modes do not call a bootloader. Instead, they jump to a predefined location in memory:
• Jump to branch instruction in flash memory
• Jump to M0 SARAM
22 Bootloader Features SPRU722C – November 2004 – Revised October 2006
In this mode, the boot ROM software will configure the device for 28x operation and then branch directly to location 0x3F 7FF6 in flash memory. This location is just before the 128-bit code security module (CSM) password locations. You are required to have previously programmed a branch instruction at location 0x3F 7FF6 that will redirect code execution to either a custom boot-loader or the application code.
On RAM-only devices, the boot-to-flash option jumps to reserved memory and should not be used. On ROM-only devices, the boot-to-flash option jumps to the location 0x3F7FF6 in ROM.
Figure 2-3. Jump-to-Flash Flow Diagram
In this mode, the boot ROM software will configure the device for 28x operation and then branch directly to 0x00 0000; the first address in the M0 SARAM memory block
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Reset InitBoot
SelectBootMode
Select jump
to M0 SARAM
ExitBoot
Jump to
0x00 0000
Execution continues
Reset InitBoot
SelectBootMode
Select jump
to OTP
ExitBoot
Jump to
0x3D 7800
Execute
preprogrammed
OTP code
Bootloader Modes
Figure 2-4. Flow Diagram of Jump to M0 SARAM
• Jump to OTP memory
In this mode, the boot ROM software will configure the device for 28x operation and then branch directly to at 0x3D 7800; the first address in the OTP memory block.
On ROM devices, the boot-to-OTP option jumps to address 0x3D 7800 in ROM. On RAM devices, the boot-to-OTP option jumps to reserved memory and should not be used.
Figure 2-5. Flow Diagram of Jump-to-OTP Memory
The following boot modes call a boot load routine that loads a data stream from the peripheral into memory:
• Standard serial boot mode (SCI-A)
In this mode, the boot ROM will load code to be executed into on-chip memory via the SCI-A port.
• SPI EEPROM boot mode (SPI-A)
In this mode, the boot ROM will load code and data into on-chip memory from an external EEPROM via the SPI-A port.
• I2C-A boot mode (I2C-A)
In this mode, the boot ROM will load code and data into on-chip memory from an external EEPROM at address 0x50 on the I2C-A bus. The EEPROM must adhere to conventional I2C EEPROM protocol with a 16-bit base address architecture.
• eCAN Boot Mode (eCAN-A)
In this mode, the eCAN-A peripheral is used to transfer data and code into the on-chip memory using eCAN-A mailbox 1. The transfer is an 8-bit data stream with two 8-bit values being transferred during each communication. On devices that do not have an eCAN-A peripheral, this mode is reserved and should not be used.
• Boot from GPIO Port (Parallel Boot from GPIO0-GPIO15)
In this mode, the boot ROM uses GPIO port A pins GPIO0-GPIO15 to load code and data from an external source. This mode supports both 8-bit and 16-bit data streams. Since this mode requires a number of GPIO pins, it is typically used to download code for flash programming when the device is connected to a platform explicitly for flash programming and not a target board.
SPRU722C – November 2004 – Revised October 2006 Bootloader Features 23
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Bootloader Data Stream Structure

2.10 Bootloader Data Stream Structure

The following two tables and associated examples show the structure of the data stream incoming to the bootloader. The basic structure is the same for all the bootloaders and is based on the C54x source data stream generated by the C54x hex utility. The C28x hex utility (hex2000.exe) has been updated to support this structure. The hex2000.exe utility is included with the C2000 code generation tools. All values in the data stream structure are in hex.
The first 16-bit word in the data stream is known as the key value. The key value is used to tell the bootloader the width of the incoming stream: 8 or 16 bits. Note that not all bootloaders will accept both 8 and 16-bit streams. Please refer to the detailed information on each loader for the valid data stream width. For an 8-bit data stream, the key value is 0x08AA and for a 16-bit stream it is 0x10AA. If a bootloader receives an invalid key value, then the load is aborted. In this case, the entry point for the flash memory (0x3F 7FF6) will be used.
The next 8 words are used to initialize register values or otherwise enhance the bootloader by passing values to it. If a bootloader does not use these values then they are reserved for future use and the bootloader simply reads the value and then discards it. Currently only the SPI and I2C bootloaders use these words to initialize registers.
The tenth and eleventh words comprise the 22-bit entry point address. This address is used to initialize the PC after the boot load is complete. This address is most likely the entry point of the program downloaded by the bootloader.
The twelfth word in the data stream is the size of the first data block to be transferred. The size of the block is defined for both 8-bit and 16-bit data stream formats as the number of 16-bit words in the block. For example, to transfer a block of 20 8-bit data values from an 8-bit data stream, the block size would be 0x000A to indicate 10 16-bit words.
The next two words tell the loader the destination address of the block of data. Following the size and address will be the 16-bit words that makeup that block of data.
This pattern of block size/destination address repeats for each block of data to be transferred. Once all the blocks have been transferred, a block size of 0x0000 signals to the loader that the transfer is complete. At this point the loader will return the entry point address to the calling routine which in turn will cleanup and exit. Execution will then continue at the entry point address as determined by the input data stream contents.
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Bootloader Data Stream Structure
Table 2-3. General Structure Of Source Program Data Stream In 16-Bit Mode
Word Contents
1 10AA (KeyValue for memory width = 16bits) 2 Register initialization value or reserved for future use 3 Register initialization value or reserved for future use 4 Register initialization value or reserved for future use 5 Register initialization value or reserved for future use 6 Register initialization value or reserved for future use 7 Register initialization value or reserved for future use 8 Register initialization value or reserved for future use
9 Register initialization value or reserved for future use 10 Entry point PC[22:16] 11 Entry point PC[15:0] 12 Block size (number of words) of the first block of data to load. If the block size is 0, this indicates the end
13 Destination address of first block Addr[31:16] 14 Destination address of first block Addr[15:0] 15 First word of the first block in the source being loaded
... ...
... ...
. Last word of the first block of the source being loaded . Block size of the 2nd block to load. . Destination address of second block Addr[31:16] . Destination address of second block Addr[15:0] . First word of the second block in the source being loaded . … . Last word of the second block of the source being loaded . Block size of the last block to load . Destination address of last block Addr[31:16] . Destination address of last block Addr[15:0] . First word of the last block in the source being loaded
... ...
... ...
n Last word of the last block of the source being loaded
n+1 Block size of 0000h - indicates end of the source program
of the source program. Otherwise another section follows.
SPRU722C – November 2004 – Revised October 2006 Bootloader Features 25
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Bootloader Data Stream Structure
Example 2-1. Data Stream Structure 16-bit
10AA ; 0x10AA 16-bit key value 0000 ; 8 reserved words
0000 0000 0000 0000 0000 0000 0000 003F ; 0x003F8000 EntryAddr, starting point after boot load completes 8000 0005 ; 0x0005 - First block consists of 5 16-bit words 003F ; 0x003F9010 - First block will be loaded starting at 0x3F9010 9010 0001 ; Data loaded = 0x0001 0x0002 0x0003 0x0004 0x0005 0002 0003 0004 0005 0002 ; 0x0002 - 2nd block consists of 2 16-bit words 003F ; 0x003F8000 - 2nd block will be loaded starting at 0x3F8000 8000 7700 ; Data loaded = 0x7700 0x7625 7625 0000 ; 0x0000 - Size of 0 indicates end of data stream
After load has completed the following memory values will have been initialized as follows:
Location Value 0x3F9010 0x0001 0x3F9011 0x0002 0x3F9012 0x0003 0x3F9013 0x0004 0x3F9014 0x0005 0x3F8000 0x7700 0x3F8001 0x7625 PC Begins execution at 0x3F8000
26 Bootloader Features SPRU722C – November 2004 – Revised October 2006
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Bootloader Data Stream Structure
In 8-bit mode, the least significant byte (LSB) of the word is sent first followed by the most significant byte (MSB). For 32-bit values, such as a destination address, the most significant word (MSW) is loaded first, followed by the least significant word (LSW). The bootloaders take this into account when loading an 8-bit data stream.
Table 2-4. LSB/MSB Loading Sequence in 8-Bit Data Stream
Byte Contents
LSB (First Byte of 2) MSB (Second Byte of 2)
1 2 LSB: AA (KeyValue for memory width = 8 bits) MSB: 08h (KeyValue for memory width = 8 bits) 3 4 LSB: Register initialization value or reserved MSB: Register initialization value or reserved 5 6 LSB: Register initialization value or reserved MSB: Register initialization value or reserved 7 8 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
... ... ... ...
... ... ... ...
17 18 LSB: Register initialization value or reserved MSB: Register initialization value or reserved 19 20 LSB: Upper half of Entry point PC[23:16] MSB: Upper half of entry point PC[31:24] (Always 0x00) 21 22 LSB: Lower half of Entry point PC[7:0] MSB: Lower half of Entry point PC[15:8] 23 24 LSB: Block size in words of the first block to load. If the MSB: block size
25 26 LSB: MSW destination address, first block Addr[23:16] MSB: MSW destination address, first block Addr[31:24] 27 28 LSB: LSW destination address, first block Addr[7:0] MSB: LSW destination address, first block Addr[15:8] 29 30 LSB: First word of the first block being loaded MSB: First word of the first block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the first block to load MSB: Last word of the first block to load . . LSB: Block size of the second block MSB: Block size of the second block . . LSB: MSW destination address, second block Addr[23:16] MSB: MSW destination address, second block
. . LSB: LSW destination address, second block Addr[7:0] MSB: LSW destination address, second block Addr[15:8] . . LSB: First word of the second block being loaded MSB: First word of the second block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the second block MSB: Last word of the second block . . LSB: Block size of the last block MSB: Block size of the last block . . LSB: MSW of destination address of last block Addr[23:16] MSB: MSW destination address, last block Addr[31:24] . . LSB: LSW destination address, last block Addr[7:0] MSB: LSW destination address, last block Addr[15:8] . . LSB: First word of the last block being loaded MSB: First word of the last block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the last block MSB: Last word of the last block
n n+1 LSB: 00h MSB: 00h - indicates the end of the source
block size is 0, this indicates the end of the source program. Otherwise another block follows. For example, a block size of 0x000A would indicate 10 words or 20 bytes in the block.
Addr[31:24]
SPRU722C – November 2004 – Revised October 2006 Bootloader Features 27
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Basic Transfer Procedure
Example 2-2. Data Stream Structure 8-bit
AA 08 ; 0x08AA 8-bit key value 00 00 00 00 ; 8 reserved words 00 00 00 00 00 00 00 00 00 00 00 00 3F 00 00 80 ; 0x003F8000 EntryAddr, starting point after boot load completes 05 00 ; 0x0005 - First block consists of 5 16-bit words 3F 00 10 90 ; 0x003F9010 - First block will be loaded starting at 0x3F9010 01 00 ; Data loaded = 0x0001 0x0002 0x0003 0x0004 0x0005 02 00 03 00 04 00 05 00 02 00 ; 0x0002 - 2nd block consists of 2 16-bit words 3F 00 00 80 ; 0x003F8000 - 2nd block will be loaded starting at 0x3F8000 00 77 ; Data loaded = 0x7700 0x7625 25 76 00 00 ; 0x0000 - Size of 0 indicates end of data stream
After load has completed the following memory values will have been initialized as follows:
Location Value 0x3F9010 0x0001 0x3F9011 0x0002 0x3F9012 0x0003 0x3F9013 0x0004 0x3F9014 0x0005 0x3F8000 0x7700 0x3F8001 0x7625 PC Begins execution at 0x3F8000

2.11 Basic Transfer Procedure

Figure 2-6 illustrates the basic process a bootloader uses to determine whether 8-bit or 16-bit data stream
has been selected, transfer that data, and start program execution. This process occurs after the bootloader finds the valid boot mode selected by the state of GPIO pins.
The loader first compares the first value sent by the host against the 16-bit key value of 0x10AA. If the value fetched does not match then the loader will read a second value. This value will be combined with the first value to form a word. This will then be checked against the 8-bit key value of 0x08AA. If the loader finds that the header does not match either the 8-bit or 16-bit key value, or if the value is not valid for the given boot mode then the load will abort. In this case the loader will return the entry point address for the flash to the calling routine.
28 Bootloader Features SPRU722C – November 2004 – Revised October 2006
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Read first word (W1)
W1=
0x10AA
?
No
16-bit data size
Yes
Read EntryPoint address
Read second word
(W2) and discard
upper 8-bits
?
0x08AA
W2:W1=
Yes
No
8-bit
DataSize
Data format error
Return
FLASH_ENTRY_POINT
Read BlockSize (R)
?
R=0
No
Yes
Return
EntryPoint
Read BlockAddress
Transfer R words of
data from source to
destination
Figure 2-6. Bootloader Basic Transfer Procedure
InitBoot Assembly Routine
A 8-bit and 16-bit transfers are not valid for all boot modes. See the info specific to a particular bootloader for any
limitations.
B In 8-bit mode, the LSB of the 16-bit word is read first followed by the MSB.

2.12 InitBoot Assembly Routine

The first routine called after reset is the InitBoot assembly routine. This routine initializes the device for operation in C28x object mode. InitBoot also performs a dummy read of the Code Security Module (CSM) password locations. If the CSM passwords are erased (all 0xFFFFs) then this has the effect of unlocking the CSM. Otherwise the CSM will remain locked and this dummy read of the password locations will have no effect. This can be useful if you have a new device that you want to boot load.
After the dummy read of the CSM password locations, the InitBoot routine calls the SelectBootMode function. This function determines the type of boot mode desired by the state of certain GPIO pins. This process is described in Section 2.13 . Once the boot is complete, the SelectBootMode function passes back the entry point address (EntryAddr) to the InitBoot function. EntryAddr is the location where code execution will begin after the bootloader exits. InitBoot then calls the ExitBoot routine that then restores CPU registers to their reset state and exits to the EntryAddr that was determined by the boot mode.
SPRU722C – November 2004 – Revised October 2006 Bootloader Features 29
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