TEXAS INSTRUMENTS TMS29LF800T, TMS29LF800B Technical data

查询TMS29LF800B供应商

D

Single Power Supply Supports 2.7-V and

3.6-V Read/Write Operation

D

Organization
1048576 By 8 Bits
524288 By 16 Bits

D

Array-Blocking Architecture
– One 16K-Byte/One 8K-Word Boot Sector
– Two 8K-Byte/4K-Word Parameter Sectors
– One 32K-Byte/16K-Word Sector
– Fifteen 64K-Byte/32K-Word Sectors
– Any Combination of Sectors Can Be

Erased. Supports Full-Chip Erase

– Any Combination of Sectors Can Be

Marked as Read-Only

D

Boot-Code Sector Architecture
– T = Top Sector
– B = Bottom Sector

D

Sector Protection
– Hardware Protection Method That

Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment

D

Embedded Program/Erase Algorithms
– Automatically Pre-Programs and Erases

Any Sector

– Automatically Programs and Verifies the

Program Data at Specified Address

D

JEDEC Standards
– Compatible With JEDEC Byte Pinouts
– Compatible With JEDEC EEPROM

Command Set

D

Fully Automated On-Chip Erase and
Program Operations

D

100 000 Program/Erase Cycles

D

Low Power Dissipation
– 20-mA Typical Active Read for Byte Mode
– 28-mA Typical Active Read for Word

Mode

– 30-mA Typical Program/Erase Current
– Less Than 60-µA Standby Current
– 5 µA in Deep Power-Down Mode

D

All Inputs/Outputs TTL-Compatible

TMS29LF800T, TMS29LF800B

1048576 BY 8-BIT/524288 BY 16-BIT

FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

D

Erase Suspend/Resume
– Supports Reading Data From, or

Programming Data to, a Sector Not
Being Erased

D

Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation

D

Package Options
– 44-Pin Plastic Small-Outline Package

(PSOP) (DBJ Suffix)

– 48-Pin Thin Small-Outline Package

(TSOP) (DCD Suffix)

D

Detection Of Program/Erase Operation
– Data Polling and Toggle Bit Feature of

Program/Erase Cycle Completion

– Hardware Method for Detection of

Program/Erase Cycle Completion
Through Ready/Busy (RY/BY

D

High-Speed Data Access at 3.3-V
V

"

10% at Three Temperature Ranges

CC

– 90 ns Commercial ...0°C to 70°C
– 100 ns Extended...–40°C to 85°C
– 120 ns Automotive ...–40°C to 125°C

PIN NOMENCLATURE

A[0:18] Address Inputs
BYTE
DQ[0:14] Data In/Data out
DQ15/A

–1

CE
OE
NC No Internal Connection
RESET
RY/BY
V

CC

V

SS

WE

Byte/Word Enable

Data In/Out (Word-Wide mode)
Low-Order Address (Byte-Wide mode)
Chip Enable
Output Enable

Reset/Deep Power Down
Ready/Busy Output
Power Supply
Ground
Write Enable

) Output Pin

PRODUCT PREVIEW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Copyright  1997, Texas Instruments Incorporated

1

TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

44-PIN PSOP

DBJ PACKAGE

(TOP VIEW)

description

RY/BY

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE

V

SS

OE
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET
WE
A8
A9
A10
A1 1
A12
A13
A14
A15
A16
BYTE
V

SS

DQ15/A
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

–1

The TMS29LF800T/B is a 1048576 by 8-bit/524288 by 16-bit (8388608-bit), 3-V single-supply , programmable
read-only memory device that can be electrically erased and reprogrammed. This device is organized as 1024K
by 8 bits or 512K by 16 bits, divided into 19 sectors:

– One 16K-byte/8K-word boot sector

PRODUCT PREVIEW

– Two 8K-byte/4K-word sectors
– One 32K-byte/16K-word sector

– Fifteen 64K-byte/32K-word sectors
Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported.
Sector data protection is afforded by methods that can disable any combination of sectors from write or read

operations using standard programming equipment. An on-chip state machine provides an on-board algorithm
that automatically pre-programs and erases any sector before it automatically programs and verifies program
data at any specified address. The command set is compatible with that of the Joint Electronic Device
Engineering Council (JEDEC) standards and is compatible with the JEDEC 8M-bit electrically erasable,
programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to
unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible.
Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector
that is not being erased.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

48-PIN TSOP

DCD PACKAGE

(TOP VIEW)

TMS29LF800T, TMS29LF800B

1048576 BY 8-BIT/524288 BY 16-BIT

FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

A15
A14
A13
A12

A1 1

A10

A9

A8
NC
NC

WE

RESET

NC
NC

RY/BY

A18
A17

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE
V

SS

DQ15/A
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V

SS

CE
A0

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PRODUCT PREVIEW

3

TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

description (continued)

Device operations are selected by writing JEDEC-standard commands into the command register using
standard microprocessor write timings. The command register acts as an input to an internal-state machine
which interprets the commands, controls the erase and programming operations, outputs the status of the
device, outputs the data stored in the device, and outputs the device algorithm-selection code. On initial power
up, the device defaults to the read mode. A hardware-reset pin initializes the internal-state machine to the read
operation.

The device has low power dissipation with a 20-mA active read for the byte mode, 28-mA active read for the
word mode, 30-mA typical program/erase current mode, and less than 60-mA standby current with a 5-mA
deep-power-down mode. These devices are offered with 90-, 100-, and 120-ns access times. Table 1 and
T able 2 show the sector-address ranges. The TMS29LF800T/B is offered in a 48-pin thin small-outline package
(TSOP ) (DCD suffix) and a 44-pin plastic small-outline package (PSOP) (DBJ suffix).

device symbol nomenclature

T –90TMS29LF800

C

PRODUCT PREVIEW

DCD

L

Temperature Range

L = Commercial (0°C to 70°C)
E = Extended (–40°C to 85°C)
Q = Automotive (–40°C to 125°C)

Package Designator

DCD = 48-Pin Thin Small-Outline Package
DBJ = 44-Pin Plastic Small-Outline Package

Program/Erase Endurance

C = 100000 Cycles
B = 10000 Cycles

Speed Option

90 = 90 ns
100 = 100 ns
120 = 120 ns

Boot Code Selection Architecture

T = Top Sector
B = Bottom Sector

Device Number/Description

8M Bits

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS29LF800T, TMS29LF800B

1048576 BY 8-BIT/524288 BY 16-BIT

FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

logic symbol for 44-pin package

RY/BY
RESET

†

A0
A1
A2
A3
A4
A5
A6
A7
A8

A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

BYTE

CE

OE

WE

11
10
9
8
7
6
5
4
42
41
40
39
38
37
36
35
34
3
2

1
44
33
12

14
43

0

18

G1
[PWR DWN]
G2 EN (READ)
G3
(WRITE)

FLASH

MEMORY

524288 × 16

A

524287

0

A, 3D
∇ 4

15

DQ0

17

DQ1

19

DQ2

21

DQ3

24

DQ4

26

DQ5

28

DQ6

30

DQ7

16

DQ8

18

DQ9

DQ11

–1

20
22
25
27
29
31

DQ10

DQ12
DQ13
DQ14

DQ15/A

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DBJ package.

A, Z4

PRODUCT PREVIEW

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

5

TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

logic symbol for 48-pin package

RY/BY
RESET

†

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10

A11
A12
A13
A14
A15
A16
A17
A18

BYTE

CE

OE

WE

25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16

15
12
47
26

28
11

0

18

G1
[PWR DWN]
G2 EN (READ)
G3 1, 2 (WRITE)

FLASH

MEMORY

524288 × 16

A

524287

0

A, 3D
∇ 4

29

DQ0

31

DQ1

33

DQ2

35

DQ3

38

DQ4

40

PRODUCT PREVIEW

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DCD package.

DQ5
DQ6
DQ7
DQ8
DQ9

DQ10

DQ11
DQ12
DQ13
DQ14

DQ15/A

–1

42
44
30
32
34
36
39
41
43
45

A, Z4

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

block diagram

V

CC

V

SS

RY/BY

Buffer

TMS29LF800T, TMS29LF800B

1048576 BY 8-BIT/524288 BY 16-BIT

FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

DQ0–DQ15

RY/BY

Erase Voltage

Generator

Input/Output Buffers

WE

BYTE

RESET

A0–A18

CE

OE

State Control

Command Registers

VCC Detector

PGM Voltage

Generator

Timer

STB

STB

Chip-Enable

Output-Enable

Logic

A
d
d

r
e
s
s

Y-Decoder

X-Decoder

Data Latch

Y-Gating

Cell Matrix

PRODUCT PREVIEW

A

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

L

a

t
c

h

7

TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

operation

See Table 1 and Table 2 for the sector-address ranges of the TMS29LF800T/B.

Table 1. Top-Boot Sector-Address Ranges

A18 A17 A16 A15 A14 A13 A12 SECTOR SIZE (x8) ADDRESS RANGE (x16) ADDRESS RANGE

SA18 1 1 1 1 1 1 X 16K-Byte FC000H–FFFFFH 7E000H–7FFFFH
SA17 1 1 1 1 1 0 1 8K-Byte FA000H–FBFFFH 7D000H–7DFFFH
SA16 1 1 1 1 1 0 0 8K-Byte F8000H–F9FFFH 7C000H–7CFFFH
SA15 1 1 1 1 0 X X 32K-Byte F0000H–F7FFFH 78000H–7BFFFH
SA14 1 1 1 0 X X X 64K-Byte E0000H–EFFFFH 70000H–77FFFH
SA13 1 1 0 1 X X X 64K-Byte D0000H–DFFFFH 68000H–6FFFFH
SA12 1 1 0 0 X X X 64K-Byte C0000H–CFFFFH 60000H–67FFFH
SA11 1 0 1 1 X X X 64K-Byte B0000H–BFFFFH 58000H–5FFFFH
SA10 1 0 1 0 X X X 64K-Byte A0000H–AFFFFH 50000H–57FFFH

SA9 1 0 0 1 X X X 64K-Byte 90000H–9FFFFH 48000H–4FFFFH
SA8 1 0 0 0 X X X 64K-Byte 80000H–8FFFFH 40000H–47FFFH
SA7 0 1 1 1 X X X 64K-Byte 70000H–7FFFFH 38000H–3FFFFH
SA6 0 1 1 0 X X X 64K-Byte 60000H–6FFFFH 30000H–37FFFH
SA5 0 1 0 1 X X X 64K-Byte 50000H–5FFFFH 28000H–2FFFFH
SA4 0 1 0 0 X X X 64K-Byte 40000H–4FFFFH 20000H–27FFFH
SA3 0 0 1 1 X X X 64K-Byte 30000H–3FFFFH 18000H–1FFFFH
SA2 0 0 1 0 X X X 64K-Byte 20000H–2FFFFH 10000H–17FFFH
SA1 0 0 0 1 X X X 64K-Byte 10000H–1FFFFH 08000H–0FFFFH
SA0 0 0 0 0 X X X 64K-Byte 00000H–0FFFFH 00000H–07FFFH

†

The address range is A–1–A18 in byte mode.
The address range is A0–A18 in word mode.

†

PRODUCT PREVIEW

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation (continued)

TMS29LF800T, TMS29LF800B

1048576 BY 8-BIT/524288 BY 16-BIT

FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

Table 2. Bottom-Boot Sector-Address Ranges

A18 A17 A16 A15 A14 A13 A12 SECTOR SIZE (x8) ADDRESS RANGE (x16) ADDRESS RANGE

SA18 1 1 1 1 X X X 64K-Byte F0000H–FFFFFH 78000H–7FFFFH
SA17 1 1 1 0 X X X 64K-Byte E0000H–EFFFFH 70000H–77FFFH
SA16 1 1 0 1 X X X 64K-Byte D0000H–DFFFFH 68000H–6FFFFH
SA15 1 1 0 0 X X X 64K-Byte C0000H–CFFFFH 60000H–67FFFH
SA14 1 0 1 1 X X X 64K-Byte B0000H–BFFFFH 58000H–5FFFFH
SA13 1 0 1 0 X X X 64K-Byte A0000H–AFFFFH 50000H–57FFFH
SA12 1 0 0 1 X X X 64K-Byte 90000H–9FFFFH 48000H–4FFFFH
SA11 1 0 0 0 X X X 64K-Byte 80000H–8FFFFH 40000H–47FFFH
SA10 0 1 1 1 X X X 64K-Byte 70000H–7FFFFH 38000H–3FFFFH

SA9 0 1 1 0 X X X 64K-Byte 60000H–6FFFFH 30000H–37FFFH
SA8 0 1 0 1 X X X 64K-Byte 50000H–5FFFFH 28000H–2FFFFH
SA7 0 1 0 0 X X X 64K-Byte 40000H–4FFFFH 20000H–27FFFH
SA6 0 0 1 1 X X X 64K-Byte 30000H–3FFFFH 18000H–1FFFFH
SA5 0 0 1 0 X X X 64K-Byte 20000H–2FFFFH 10000H–17FFFH
SA4 0 0 0 1 X X X 64K-Byte 10000H–1FFFFH 08000H–0FFFFH
SA3 0 0 0 0 1 X X 32K-Byte 08000H–0FFFFH 04000H–07FFFH
SA2 0 0 0 0 0 1 1 8K-Byte 06000H–07FFFH 03000H–03FFFH
SA1 0 0 0 0 0 1 0 8K-Byte 04000H–05FFFH 02000H–02FFFH
SA0 0 0 0 0 0 0 X 16K-Byte 00000H–03FFFH 00000H–01FFFH

†

The address range is A–1–A18 in byte mode.
The address range is A0–A18 in word mode.

†

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PRODUCT PREVIEW

9

TMS29LF800T, TMS29LF800B

MODE

DQ0–DQ7

3-V power suppl

MODE

DQ0–DQ15

3-V power suppl

1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

operation (continued)

See Table 3 and Table 4 for the operation modes of the TMS29LF800T/B.

Table 3. Byte-Operation Mode (BYTE

FUNCTIONS

CE OE WE A0 A1 A6 A9 RESET

Algorithm-selection mode V

p

Read V
Output disable VILVIHV
Standby and write inhibit V
Write‡ VILVIHV
Temporary sector unprotect X X X X X X X V
Verify sector protect V
Hardware reset X X X X X X X V

Legend:
VIL = Logic 0
VIH = Logic 1
VID = 12.0 ± 0.5 V

†

X can be VIL or VIH.

‡

See Table 6 for valid address and data during write.

pp

y

ILVILVIHVILVILVILVID

VILVILVIHVIHVILVILV

VILVILVIHVIHVILVILV

ILVILVIH

X X X X X X V

IH

ILVILVIHVILVIHVILVID

A0 A1 A6 A9 V

X X X X V

IH

A0 A1 A6 A9 V

IL

†

Table 4. Word-Operation Mode (BYTE =VIH)

FUNCTIONS

CE OE WE A0 A1 A6 A9 RESET

V

VILV

Algorithm-selection mode

PRODUCT PREVIEW

p

Read V
Output disable V
Standby and write inhibit V
Write‡ V
Temporary sector unprotect X X X X X X X V
Verify sector protect V
Hardware reset X X X X X X X V

Legend:
VIL = Logic 0
VIH = Logic 1
VID = 12.0 ± 0.5 V

†

X can be VIL or VIH.

‡

See Table 6 for valid address and data during write.

pp

y

IL

V

VILV

IL

V

VILV

IL

VILV

IL
ILVIHVIH

IH

ILVIHVIL

VILV

IL

IHVILVILVILVID

IHVIHVILVILVID

IHVIHVILVILVID

A0 A1 A6 A9 V

IH

X X X X V

X X X X X X V

A0 A1 A6 A9 V

IHVILVIHVILVID

†

= VIL)

Manufacturer-Equivalent Code 01h

V

IH

(TMS29LF800T/B – Byte)
Device-Equivalent Code DAh

V

ID

ID

IH

(TMS29LF800T – Byte)
Device-Equivalent Code 5Bh

V

IH

(TMS29LF800B – Byte)
Data out

IH

Hi-Z

IH

Hi-Z

IH

Data in

IH

X

ID

V

Data out

IH

Hi-Z

IL

V

Manufacturer-Equivalent Code 01h

IH

(TMS29LF800T/B – Word)

V

Device-Equivalent Code 22DAh

IH

(TMS29LF800T – Word)

V

Device-Equivalent Code 225Bh

IH

(TMS29LF800B – Word)
Data out

IH

Hi-Z

IH

Hi-Z

IH

Data in

IH

X

ID

V

Data out

IH

Hi-Z

IL

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

read mode

TMS29LF800T, TMS29LF800B

1048576 BY 8-BIT/524288 BY 16-BIT

FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

A logic-low signal applied to the CE

and OE pins allows the output of the TMS29LF800T/B to be read. When
two or more ’29LF800T/B devices are connected in parallel, the output of any one device can be read without
interference. The CE

pin is for power control and is used for device selection. The OE pin is for output control,

and is used to gate the data output onto the bus from the selected device.
The address-access time (t

access time (t
access time (t

) is the delay from CE low and stable addresses to valid output data. The output-enable

ELQV

) is the delay from OE low to valid output data when CE equals logic low and addresses are

GLQV

stable for at least the duration of t

) is the delay from stable address to valid output data. The chip-enable (CE)

AVQV

AVQV–tGLQV

.

standby mode

I

supply current is reduced by applying a logic-high level on CE and RESET to enter the standby mode. In

CC

the standby mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on
CE

and RESET reduces the current to 60 µA. Applying a TTL logic-high level on CE and RESET reduces the
current to 1 mA. If the ’29LF800T/B is deselected during erasure or programming, the device continues to draw
active current until the operation is complete.

output disable

When OE

equals VIH or CE equals VIH, output from the device is disabled and the output pins (DQ0–DQ15) are

placed in the high-impedance state.

automatic-sleep mode

The ’29LF800T/B has a built-in feature called automatic-sleep mode to minimize device energy consumption
which is independent of CE

, WE, and OE, and is enabled when addresses remain stable for 300 ns. Typical
sleep-mode current is 60 µA. Sleep mode does not affect output data, which remains latched and available to
the system.

algorithm selection

The algorithm-selection mode provides access to a binary code that matches the device with its proper
programming and erase command operations. This mode is activated when V
address pin A9. Address pins A1 and A6 must be logic low. T wo bytes of code are accessed by toggling address
pin A0 from V

to VIH. Address pins other than A0, A1, and A6 can be at logic low or at logic high.

IL

The algorithm-selection mode can also be read by using the command register, which is useful when V
available to be placed on address pin A9. Table 5 shows the binary algorithm-selection codes.

Table 5. Algorithm-Selection Codes (3-V Single Power Supply)

CODE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Manufacturer­equivalent code

TMS29LF800T ­Byte

TMS29LF800B­Byte

TMS29LF800T 22DAH 0 0 1 0 0 0 1 0 1 1 0 1 1 0 1 0
TMS29LF800B 225BH 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1
Sector protection 01H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

†

A1 = VIL, A6 = VIL, CE = VIL, OE = V

01H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

DAH A

5BH A

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 0 1 1 0 1 0

–1

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 1 0 1 1 0 1 1

–1

IL

(1 1.5 V to 12.5 V) is placed on

ID

ID

†

PRODUCT PREVIEW

is not

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

11

TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

erasure and programming

Erasure and programming of the ’29LF800 are accomplished by writing a sequence of commands using
standard microprocessor write timing. The commands are written to a command register and input to the
command-state machine (CSM). The CSM interprets the command entered and initiates program, erase,
suspend, and resume operations as instructed. The CSM acts as the interface between the write-state machine
(WSM) and external-chip operations. The WSM controls all voltage generation, pulse generation,
preconditioning, and verification of memory contents. Program and block-/chip-erase functions are fully
automatic. Once the end of a program or erase operation has been reached, the device resets internally to the
read mode. If V
aborted and subsequent writes are ignored until the V
logically correct to prevent unintentional command writes, programming, or erasing.

command definitions

Device operating modes are selected by writing specific address and data sequences into the command
register. Table 6 defines the valid command sequences. Writing incorrect address and data values or writing
them in the incorrect sequence causes the device to reset to the read mode. The command register does not
occupy an addressable memory location. The register is used to store the command sequence along with the
address and data needed by the memory array. Commands are written by setting CE
bringing WE
on the rising edge of WE
characteristics of the write/erase/program-operations section for specific timing information.

drops below the low-voltage-detect level (V

CC

from logic high to logic low. Addresses are latched on the falling edge of WE and data is latched

. Holding WE = VIL and toggling CE is an alternative method. See the switching

level is greater than V

CC

), any programming or erase operation is

LKO

. The control pins must be

LKO

= VIL, OE = VIH, and

PRODUCT PREVIEW

12

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

command definitions (continued)

COMMAND

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

go

Á

3

Á

555H

Á

AAH

Á

2AAH

Á

55H

Á

555H

Á

90H

Á

01H

Á

Á

Á

g

Á

3

Á

2AAH

Á

AAH

Á

555H

Á

55H

Á

2AAH

Á

90H

Á

01H

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

TMS29LF800T, TMS29LF800B

1048576 BY 8-BIT/524288 BY 16-BIT

FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

Table 6. Command Definitions

Read/reset
(word)

Read/reset
(byte)

ÁÁÁ

Read/reset
(word)

Read/reset
(byte)

ÁÁÁ

Algorithm
selection (word)

ÁÁÁ

BUS

CYCLES

1

1

ÁÁ

3

3

ÁÁ

ÁÁ

1ST CYCLE

ADDR

xxxxH

xxx

Á

555H

2AAH

Á

Á

DATA

xxF0H

F0H

Á

xxAAH

AAH

Á

xx

Á

2ND CYCLE

ADDR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

2AAH

555H

Á

Á

Algorithm
selection (byte)

ÁÁÁ

Program (word)
Program (byte)

Chip erase

ÁÁÁ

(word)

Chip erase
(byte)

Sector erase

ÁÁÁ

(word)
Sector erase

(byte)

ÁÁÁ

Sector-erase

ÁÁÁ

suspend (word)
Sector-erase

suspend (byte)

ÁÁÁ

Sector-erase
resume (word)

Sector-erase
resume (byte)

ÁÁÁ

ÁÁ

4
4

6

ÁÁ

6

6

ÁÁ

6

ÁÁ

1

ÁÁ

1

ÁÁ

1

1

ÁÁ

Á

555H

2AAH

555H

Á

2AAH

555H

Á

2AAH

Á

XXXXH

Á

XXX

Á

XXXXH

XXX

Á

Á

xxAAH

AAH

xxAAH

Á

AAH

xxAAH

Á

AAH

Á

xxB0H

Á

B0H

Á

xx30H

30H

Á

Á

2AAH

555H

2AAH

Á

555H

2AAH

Á

555H

Á

Erase suspend valid during sector-erase operation

ББББББББББББББББББББ

Erase suspend valid during sector-erase operation

ББББББББББББББББББББ

Erase resume valid only after erase-suspend operation

Erase resume valid only after erase-suspend operation

ББББББББББББББББББББ

LEGEND:

RA = Address of the location to be read
PA = Address of the location to be programmed
SA = Address of the sector to be erased

Addresses A12—A18 select 1 to 19 sectors.
RD = Data to be read at selected address location
PD = Data to be programmed at selected address location

DATA

xx55H

55H

Á

xx

Á

Á

xx55H

55H

xx55H

Á

55H

xx55H

Á

55H

Á

3RD CYCLE

ADDR

555H

2AAH

ÁÁ

ÁÁ

ÁÁ

555H

2AAH

555H

ÁÁ

2AAH

555H

ÁÁ

2AAH

ÁÁ

DATA

xxF0H

F0H

Á

xx

Á

Á

xxA0H

A0H

xx80H

Á

80H

xx80H

Á

80H

Á

4TH CYCLE

ADDR

RA

RA

Á

Á

Á

PA
PA

555H

Á

2AAH

555H

Á

2AAH

Á

DATA

RD

RD

Á

22DAH

T

225BH

B

Á

DAH

T

5BH

B

Á

PD
PD

xxAAH

Á

AAH

xxAAH

Á

AAH

Á

5TH CYCLE

ADDR

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

2AAH

Á

555H

2AAH

Á

555H

Á

DATA

xx55H

Á

55H

xx55H

Á

55H

Á

6TH CYCLE

ADDR

555H

Á

2AAH

SA

Á

SA

Á

Á

Á

Á

DATA

xx10H

10H

xx30H

30H

PRODUCT PREVIEW

read/reset command

The read or reset mode is activated by writing either of the two read/reset command sequences into the
command register. The device remains in this mode until another valid command sequence is input in the
command register. Memory data is available in the read mode and can be read with standard microprocessor
read-cycle timing.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

13

TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

read/reset command (continued)

On power up, the device defaults to the read/reset mode. A read/reset command sequence is not required and
memory data is available.

algorithm-selection command

The algorithm-selection command allows access to a binary code that matches the device with the proper
programming and erase command operations. After writing the three-bus-cycle command sequence, the first
byte/word of the algorithm-selection code can be read from address XX00h. The second byte/word of the code
can be read from address XX01h (see Table 6). This mode remains in effect until another valid command
sequence is written to the device.

program command

Programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the
program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the
device. The addresses are latched on the falling edge of WE
in the fourth bus cycle. The rising edge of WE starts the program operation. The embedded programming
function automatically provides needed voltage and timing to program and verify the cell margin. Any further
commands written to the device during the program operation are ignored.

Programming can be performed at any address location in any sequence. When erased, all bits are in a
logic-high state. Logic lows are programmed into the device and only an erase operation can change bits from
logic lows to logic highs. Attempting to program a 1 into a bit that has been programmed previously to a 0 causes
the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (DQ5) to
a logic-high state. The automatic-programming operation is complete when the data on DQ7 is equivalent to
the data written to DQ5, at which time the device returns to the read mode and addresses are no longer latched.
Figure 9 shows a flowchart of the typical device-programming operation.

and the data is latched on the rising edge of WE

chip-erase command

Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup
state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command. This
command sequence is required to ensure that the memory contents are not erased accidentally . The rising edge
of WE

starts the chip-erase operation. Any further commands written to the device during the chip-erase

operation are ignored.

PRODUCT PREVIEW

The embedded chip-erase function automatically provides voltage and timing needed to program and to verify
all the memory cells prior to electrical erase. It then erases and verifies the cell margin automatically without
programming the memory cells prior to erase.

Figure 12 shows a flowchart of the typical chip-erase operation.

sector-erase command

Sector-erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the
erase-setup state. The next two bus cycles unlock the erase mode and then the sixth bus cycle loads the
sector-erase command and the sector-address location to be erased. Any address location within the desired
sector can be used. The addresses are latched on the falling edge of WE
is latched on the rising edge of WE
sector-erase operation begins on the selected sector(s).

Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For
each additional sector to be selected for erase, another bus cycle is issued. The bus cycle loads the next
sector-address location and the sector-erase command. The time between the end of the previous bus cycle
and the start of the next bus cycle must be less than 100 µs; otherwise, the new sector location is not loaded.
A time delay of 100 µs from the rising edge of the last WE
edge of WE

within the 100 µs time delay, the timer is reset.

and the sector-erase command (30h)

in the sixth bus cycle. After a delay of 80 µs from the rising edge of WE, the

starts the sector-erase operation. If there is a falling

14

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS29LF800T, TMS29LF800B

1048576 BY 8-BIT/524288 BY 16-BIT

FLASH MEMORIES

SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997

sector-erase command (continued)

One to nineteen sector-address locations can be loaded in any sequence. The state of the delay timer can be
monitored using the sector-erase delay indicator (DQ3). If DQ3 is at logic low, the time delay has not expired.
See the operation status section for a description.

Any command other than erase suspend (B0h) or sector erase (30h) written to the device during the
sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s)
selected for erase are no longer valid. To complete the sector-erase operation, reissue the sector-erase
command sequence.

The embedded sector-erase function automatically provides needed voltage and timing to program and to verify
all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically.
Programming the memory cells prior to erase is not required.

See the operation status section for a full description. Figure 14 shows a flowchart of the typical sector-erase
operation.

erase-suspend command

The erase-suspend command (B0h) allows interruption of a sector-erase operation to read data from unaltered
sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be V
erase-suspend command (B0h) is latched on the rising edge of WE
progress, the erase-suspend command requests the internal write-state machine to halt operation at
predetermined breakpoints. The erase-suspend command is valid only during the sector-erase operation and
is invalid during programming and chip-erase operations. The sector-erase delay timer expires immediately if
the erase-suspend command is issued while the delay is active.

. Once the sector-erase operation is in

or VIH and the

IL

After the erase-suspend command is issued, the device takes between 0.1 µs and 15 µs to suspend the
operation. The toggle bit must be monitored to determine when the suspend has been executed. When the
toggle bit stops toggling, data can be read from sectors that are not selected for erase. Reading from a sector
selected for erase can result in invalid data. See the operation status section for a full description.

Once the sector-erase operation is suspended, reading from or programing to a sector that is not being erased
can be performed. This command is applicable only during sector-erase operation. Any other command written
during erase-suspend mode to the suspended sector is ignored.

erase-resume command

The erase-resume command (30h) restarts a suspended sector-erase operation from the point where it was
halted. Erase resume is a one-bus-cycle command. The addresses can be V
command (30h) is latched on the rising edge of WE
combination is written, the internal-pulse counter (exceed timing limit) is reset. The erase-resume command
is valid only in the erase-suspend state. After the erase-resume command is executed, the device returns to
the valid sector-erase state and further writes of the erase-resume command are ignored. After the device has
resumed the sector-erase operation, another erase-suspend command can be issued to the device.

. When an erase-suspend/erase-resume command

or VIH and the erase-resume

IL

operation status

The status of the device during an automatic-programming algorithm, chip-erase, or automatic-erase algorithm
can be determined in three ways:

D

DQ7: Data polling

D

DQ6: Toggle bit

PRODUCT PREVIEW

D

RY/BY: Ready/busy bit

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

15